| Jiafei Pan | 46367ad | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <bl_common.h> |
| 9 | #include <desc_image_load.h> |
| 10 | #include "ls_16550.h" |
| 11 | #include "plat_ls.h" |
| 12 | #include "ls_def.h" |
| 13 | |
| 14 | /* Data structure which holds the extents of the trusted SRAM for BL2 */ |
| 15 | static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); |
| 16 | |
| 17 | /******************************************************************************* |
| 18 | * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 |
| 19 | * in x0. This memory layout is sitting at the base of the free trusted SRAM. |
| 20 | * Copy it to a safe location before its reclaimed by later BL2 functionality. |
| 21 | ******************************************************************************/ |
| 22 | void ls_bl2_early_platform_setup(meminfo_t *mem_layout) |
| 23 | { |
| 24 | static console_ls_16550_t console; |
| 25 | |
| 26 | /* Initialize the console to provide early debug support */ |
| 27 | console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK, |
| 28 | LS_TF_UART_BAUDRATE, &console); |
| 29 | |
| 30 | /* Setup the BL2 memory layout */ |
| 31 | bl2_tzram_layout = *mem_layout; |
| 32 | |
| 33 | /* Initialise the IO layer and register platform IO devices */ |
| 34 | plat_ls_io_setup(); |
| 35 | } |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * Perform the very early platform specific architectural setup here. At the |
| 39 | * moment this is only initializes the mmu in a quick and dirty way. |
| 40 | ******************************************************************************/ |
| 41 | void ls_bl2_plat_arch_setup(void) |
| 42 | { |
| 43 | ls_setup_page_tables(bl2_tzram_layout.total_base, |
| 44 | bl2_tzram_layout.total_size, |
| 45 | BL_CODE_BASE, |
| 46 | BL_CODE_END, |
| 47 | BL_RO_DATA_BASE, |
| 48 | BL_RO_DATA_END |
| 49 | #if USE_COHERENT_MEM |
| 50 | , BL_COHERENT_RAM_BASE, |
| 51 | BL_COHERENT_RAM_END |
| 52 | #endif |
| 53 | ); |
| 54 | |
| 55 | #ifdef AARCH32 |
| 56 | enable_mmu_secure(0); |
| 57 | #else |
| 58 | enable_mmu_el1(0); |
| 59 | #endif |
| 60 | } |
| 61 | |
| 62 | void bl2_plat_arch_setup(void) |
| 63 | { |
| 64 | ls_bl2_plat_arch_setup(); |
| 65 | } |
| 66 | |
| 67 | int ls_bl2_handle_post_image_load(unsigned int image_id) |
| 68 | { |
| 69 | int err = 0; |
| 70 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
| 71 | |
| 72 | assert(bl_mem_params); |
| 73 | |
| 74 | switch (image_id) { |
| 75 | #ifdef AARCH64 |
| 76 | case BL32_IMAGE_ID: |
| 77 | bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry(); |
| 78 | break; |
| 79 | #endif |
| 80 | |
| 81 | case BL33_IMAGE_ID: |
| 82 | /* BL33 expects to receive the primary CPU MPID (through r0) */ |
| 83 | bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); |
| 84 | bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry(); |
| 85 | break; |
| 86 | } |
| 87 | |
| 88 | return err; |
| 89 | } |
| 90 | |
| 91 | /******************************************************************************* |
| 92 | * This function can be used by the platforms to update/use image |
| 93 | * information for given `image_id`. |
| 94 | ******************************************************************************/ |
| 95 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 96 | { |
| 97 | return ls_bl2_handle_post_image_load(image_id); |
| 98 | } |