Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 1 | /* |
Chandni Cherukuri | c873efc | 2023-02-16 20:22:32 +0530 | [diff] [blame] | 2 | * Copyright (c) 2020-2023, Arm Limited. All rights reserved. |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MORELLO_DEF_H |
| 8 | #define MORELLO_DEF_H |
| 9 | |
| 10 | /* Non-secure SRAM MMU mapping */ |
| 11 | #define MORELLO_NS_SRAM_BASE UL(0x06000000) |
| 12 | #define MORELLO_NS_SRAM_SIZE UL(0x00010000) |
| 13 | #define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \ |
| 14 | MORELLO_NS_SRAM_BASE, \ |
| 15 | MORELLO_NS_SRAM_SIZE, \ |
| 16 | MT_DEVICE | MT_RW | MT_SECURE) |
| 17 | |
Werner Lewis | cb5e71a | 2023-08-17 12:06:52 +0100 | [diff] [blame] | 18 | /* SDS Firmware version defines */ |
| 19 | #define MORELLO_SDS_FIRMWARE_VERSION_STRUCT_ID U(2) |
| 20 | #define MORELLO_SDS_FIRMWARE_VERSION_OFFSET U(0) |
| 21 | #ifdef TARGET_PLATFORM_FVP |
| 22 | # define MORELLO_SDS_FIRMWARE_VERSION_SIZE U(8) |
| 23 | #else |
| 24 | # define MORELLO_SDS_FIRMWARE_VERSION_SIZE U(16) |
| 25 | #endif |
| 26 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 27 | /* SDS Platform information defines */ |
| 28 | #define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8) |
| 29 | #define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0) |
sah01 | 3c5bb04 | 2021-12-02 06:37:04 +0000 | [diff] [blame] | 30 | #ifdef TARGET_PLATFORM_FVP |
| 31 | # define MORELLO_SDS_PLATFORM_INFO_SIZE U(8) |
| 32 | #else |
Chandni Cherukuri | c873efc | 2023-02-16 20:22:32 +0530 | [diff] [blame] | 33 | # define MORELLO_SDS_PLATFORM_INFO_SIZE U(26) |
sah01 | 3c5bb04 | 2021-12-02 06:37:04 +0000 | [diff] [blame] | 34 | #endif |
Manoj Kumar | 4ca42b8 | 2021-01-20 17:57:31 +0530 | [diff] [blame] | 35 | #define MORELLO_MAX_DDR_CAPACITY U(0x1000000000) |
sah01 | 3c5bb04 | 2021-12-02 06:37:04 +0000 | [diff] [blame] | 36 | #define MORELLO_MAX_REMOTE_CHIP_COUNT U(16) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 37 | |
Chandni Cherukuri | dff7f6c | 2021-11-30 20:35:35 +0530 | [diff] [blame] | 38 | #define MORELLO_SCC_SERVER_MODE U(0) |
| 39 | #define MORELLO_SCC_CLIENT_MODE_MASK U(1) |
| 40 | #define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4) |
| 41 | #define MORELLO_SCC_C2_TAG_CACHE_EN_MASK U(8) |
| 42 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 43 | /* Base address of non-secure SRAM where Platform information will be filled */ |
Manoj Kumar | 4ca42b8 | 2021-01-20 17:57:31 +0530 | [diff] [blame] | 44 | #define MORELLO_PLATFORM_INFO_BASE UL(0x06000000) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 45 | |
Manoj Kumar | b19e62a | 2021-08-26 10:49:02 +0530 | [diff] [blame] | 46 | /* DMC memory status registers */ |
Chandni Cherukuri | dff7f6c | 2021-11-30 20:35:35 +0530 | [diff] [blame] | 47 | #define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000) |
| 48 | #define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000) |
Manoj Kumar | b19e62a | 2021-08-26 10:49:02 +0530 | [diff] [blame] | 49 | |
| 50 | #define MORELLO_DMC_MEMC_STATUS_MASK U(7) |
| 51 | |
| 52 | /* DMC memory command registers */ |
Chandni Cherukuri | dff7f6c | 2021-11-30 20:35:35 +0530 | [diff] [blame] | 53 | #define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008) |
| 54 | #define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008) |
| 55 | |
| 56 | /* DMC capability control register */ |
| 57 | #define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00) |
| 58 | #define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00) |
| 59 | |
| 60 | /* DMC tag cache control register */ |
| 61 | #define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04) |
| 62 | #define MORELLO_DMC1_TAG_CACHE_CTL UL(0x4E100D04) |
| 63 | |
| 64 | /* DMC tag cache config register */ |
| 65 | #define MORELLO_DMC0_TAG_CACHE_CFG UL(0x4E000D08) |
| 66 | #define MORELLO_DMC1_TAG_CACHE_CFG UL(0x4E100D08) |
| 67 | |
| 68 | /* DMC memory access control register */ |
| 69 | #define MORELLO_DMC0_MEM_ACCESS_CTL UL(0x4E000D0C) |
| 70 | #define MORELLO_DMC1_MEM_ACCESS_CTL UL(0x4E100D0C) |
| 71 | |
| 72 | #define MORELLO_DMC_MEM_ACCESS_DIS (1UL << 16) |
| 73 | |
| 74 | /* DMC memory address control register */ |
| 75 | #define MORELLO_DMC0_MEM_ADDR_CTL UL(0x4E000D10) |
| 76 | #define MORELLO_DMC1_MEM_ADDR_CTL UL(0x4E100D10) |
| 77 | |
| 78 | /* DMC memory address control 2 register */ |
| 79 | #define MORELLO_DMC0_MEM_ADDR_CTL2 UL(0x4E000D14) |
| 80 | #define MORELLO_DMC1_MEM_ADDR_CTL2 UL(0x4E100D14) |
| 81 | |
| 82 | /* DMC special control register */ |
| 83 | #define MORELLO_DMC0_SPL_CTL_REG UL(0x4E000D18) |
| 84 | #define MORELLO_DMC1_SPL_CTL_REG UL(0x4E100D18) |
Manoj Kumar | b19e62a | 2021-08-26 10:49:02 +0530 | [diff] [blame] | 85 | |
| 86 | /* DMC ERR0CTLR0 registers */ |
Chandni Cherukuri | dff7f6c | 2021-11-30 20:35:35 +0530 | [diff] [blame] | 87 | #define MORELLO_DMC0_ERR0CTLR0_REG UL(0x4E000708) |
| 88 | #define MORELLO_DMC1_ERR0CTLR0_REG UL(0x4E100708) |
Manoj Kumar | b19e62a | 2021-08-26 10:49:02 +0530 | [diff] [blame] | 89 | |
| 90 | /* DMC ECC in ERR0CTLR0 register */ |
| 91 | #define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9) |
| 92 | |
| 93 | /* DMC ERR2STATUS register */ |
Chandni Cherukuri | dff7f6c | 2021-11-30 20:35:35 +0530 | [diff] [blame] | 94 | #define MORELLO_DMC0_ERR2STATUS_REG UL(0x4E000790) |
| 95 | #define MORELLO_DMC1_ERR2STATUS_REG UL(0x4E100790) |
Manoj Kumar | b19e62a | 2021-08-26 10:49:02 +0530 | [diff] [blame] | 96 | |
| 97 | /* DMC memory commands */ |
| 98 | #define MORELLO_DMC_MEMC_CMD_CONFIG U(0) |
| 99 | #define MORELLO_DMC_MEMC_CMD_READY U(3) |
| 100 | |
Werner Lewis | d72ac0d | 2023-03-22 10:20:53 +0000 | [diff] [blame] | 101 | /* SDS Platform information struct definition */ |
| 102 | #ifdef TARGET_PLATFORM_FVP |
| 103 | /* |
| 104 | * Platform information structure stored in SDS. |
| 105 | * This structure holds information about platform's DDR |
| 106 | * size |
| 107 | * - Local DDR size in bytes, DDR memory in main board |
| 108 | */ |
| 109 | struct morello_plat_info { |
| 110 | uint64_t local_ddr_size; |
| 111 | } __packed; |
| 112 | #else |
| 113 | /* |
| 114 | * Platform information structure stored in SDS. |
| 115 | * This structure holds information about platform's DDR |
| 116 | * size which is an information about multichip setup |
| 117 | * - Local DDR size in bytes, DDR memory in main board |
| 118 | * - Remote DDR size in bytes, DDR memory in remote board |
| 119 | * - remote_chip_count |
| 120 | * - multichip mode |
| 121 | * - scc configuration |
| 122 | * - silicon revision |
| 123 | */ |
| 124 | struct morello_plat_info { |
| 125 | uint64_t local_ddr_size; |
| 126 | uint64_t remote_ddr_size; |
| 127 | uint8_t remote_chip_count; |
| 128 | bool multichip_mode; |
| 129 | uint32_t scc_config; |
| 130 | uint32_t silicon_revision; |
| 131 | } __packed; |
| 132 | #endif |
| 133 | |
Werner Lewis | cb5e71a | 2023-08-17 12:06:52 +0100 | [diff] [blame] | 134 | /* SDS Firmware revision struct definition */ |
| 135 | #ifdef TARGET_PLATFORM_FVP |
| 136 | /* |
| 137 | * Firmware revision structure stored in SDS. |
| 138 | * This structure holds information about firmware versions. |
| 139 | * - SCP firmware version |
| 140 | * - SCP firmware commit |
| 141 | */ |
| 142 | struct morello_firmware_version { |
| 143 | uint32_t scp_fw_ver; |
| 144 | uint32_t scp_fw_commit; |
| 145 | } __packed; |
| 146 | #else |
| 147 | /* |
| 148 | * Firmware revision structure stored in SDS. |
| 149 | * This structure holds information about firmware versions. |
| 150 | * - SCP firmware version |
| 151 | * - SCP firmware commit |
| 152 | * - MCC firmware version |
| 153 | * - PCC firmware version |
| 154 | */ |
| 155 | struct morello_firmware_version { |
| 156 | uint32_t scp_fw_ver; |
| 157 | uint32_t scp_fw_commit; |
| 158 | uint32_t mcc_fw_ver; |
| 159 | uint32_t pcc_fw_ver; |
| 160 | } __packed; |
| 161 | #endif |
| 162 | |
| 163 | /* Compile time assertions to ensure the size of structures are of the required bytes */ |
Werner Lewis | d72ac0d | 2023-03-22 10:20:53 +0000 | [diff] [blame] | 164 | CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, |
| 165 | assert_invalid_plat_info_size); |
| 166 | |
Werner Lewis | cb5e71a | 2023-08-17 12:06:52 +0100 | [diff] [blame] | 167 | CASSERT(sizeof(struct morello_firmware_version) == MORELLO_SDS_FIRMWARE_VERSION_SIZE, |
| 168 | assert_invalid_firmware_version_size); |
| 169 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 170 | #endif /* MORELLO_DEF_H */ |