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Dan Handleyed6ff952014-05-14 17:44:19 +01001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __FVP_DEF_H__
32#define __FVP_DEF_H__
33
34#include <platform_def.h> /* for TZROM_SIZE */
35
36
37/* Firmware Image Package */
38#define FIP_IMAGE_NAME "fip.bin"
39
40/* Constants for accessing platform configuration */
41#define CONFIG_GICD_ADDR 0
42#define CONFIG_GICC_ADDR 1
43#define CONFIG_GICH_ADDR 2
44#define CONFIG_GICV_ADDR 3
45#define CONFIG_MAX_AFF0 4
46#define CONFIG_MAX_AFF1 5
47/* Indicate whether the CPUECTLR SMP bit should be enabled. */
48#define CONFIG_CPU_SETUP 6
49#define CONFIG_BASE_MMAP 7
50/* Indicates whether CCI should be enabled on the platform. */
51#define CONFIG_HAS_CCI 8
52#define CONFIG_HAS_TZC 9
53#define CONFIG_LIMIT 10
54
55/*******************************************************************************
56 * FVP memory map related constants
57 ******************************************************************************/
58
59#define FLASH0_BASE 0x08000000
60#define FLASH0_SIZE TZROM_SIZE
61
62#define FLASH1_BASE 0x0c000000
63#define FLASH1_SIZE 0x04000000
64
65#define PSRAM_BASE 0x14000000
66#define PSRAM_SIZE 0x04000000
67
68#define VRAM_BASE 0x18000000
69#define VRAM_SIZE 0x02000000
70
71/* Aggregate of all devices in the first GB */
72#define DEVICE0_BASE 0x1a000000
73#define DEVICE0_SIZE 0x12200000
74
75#define DEVICE1_BASE 0x2f000000
76#define DEVICE1_SIZE 0x200000
77
78#define NSRAM_BASE 0x2e000000
79#define NSRAM_SIZE 0x10000
80
81#define MBOX_OFF 0x1000
82
83/* Base address where parameters to BL31 are stored */
84#define PARAMS_BASE TZDRAM_BASE
85
86#define DRAM1_BASE 0x80000000ull
87#define DRAM1_SIZE 0x80000000ull
88#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
89#define DRAM1_SEC_SIZE 0x01000000ull
90
91#define DRAM_BASE DRAM1_BASE
92#define DRAM_SIZE DRAM1_SIZE
93
94#define DRAM2_BASE 0x880000000ull
95#define DRAM2_SIZE 0x780000000ull
96#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
97
98#define PCIE_EXP_BASE 0x40000000
99#define TZRNG_BASE 0x7fe60000
100#define TZNVCTR_BASE 0x7fe70000
101#define TZROOTKEY_BASE 0x7fe80000
102
103/* Memory mapped Generic timer interfaces */
104#define SYS_CNTCTL_BASE 0x2a430000
105#define SYS_CNTREAD_BASE 0x2a800000
106#define SYS_TIMCTL_BASE 0x2a810000
107
108/* V2M motherboard system registers & offsets */
109#define VE_SYSREGS_BASE 0x1c010000
110#define V2M_SYS_ID 0x0
111#define V2M_SYS_LED 0x8
112#define V2M_SYS_CFGDATA 0xa0
113#define V2M_SYS_CFGCTRL 0xa4
114
115/* Load address of BL33 in the FVP port */
116#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
117
Andrew Thoelkea55566d2014-05-28 22:22:55 +0100118/* Special value used to verify platform parameters from BL2 to BL3-1 */
119#define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
120
Dan Handleyed6ff952014-05-14 17:44:19 +0100121/*
122 * V2M sysled bit definitions. The values written to this
123 * register are defined in arch.h & runtime_svc.h. Only
124 * used by the primary cpu to diagnose any cold boot issues.
125 *
126 * SYS_LED[0] - Security state (S=0/NS=1)
127 * SYS_LED[2:1] - Exception Level (EL3-EL0)
128 * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
129 *
130 */
131#define SYS_LED_SS_SHIFT 0x0
132#define SYS_LED_EL_SHIFT 0x1
133#define SYS_LED_EC_SHIFT 0x3
134
135#define SYS_LED_SS_MASK 0x1
136#define SYS_LED_EL_MASK 0x3
137#define SYS_LED_EC_MASK 0x1f
138
139/* V2M sysid register bits */
140#define SYS_ID_REV_SHIFT 27
141#define SYS_ID_HBI_SHIFT 16
142#define SYS_ID_BLD_SHIFT 12
143#define SYS_ID_ARCH_SHIFT 8
144#define SYS_ID_FPGA_SHIFT 0
145
146#define SYS_ID_REV_MASK 0xf
147#define SYS_ID_HBI_MASK 0xfff
148#define SYS_ID_BLD_MASK 0xf
149#define SYS_ID_ARCH_MASK 0xf
150#define SYS_ID_FPGA_MASK 0xff
151
152#define SYS_ID_BLD_LENGTH 4
153
154#define REV_FVP 0x0
155#define HBI_FVP_BASE 0x020
156#define HBI_FOUNDATION 0x010
157
158#define BLD_GIC_VE_MMAP 0x0
159#define BLD_GIC_A53A57_MMAP 0x1
160
161#define ARCH_MODEL 0x1
162
163/* FVP Power controller base address*/
164#define PWRC_BASE 0x1c100000
165
166
167/*******************************************************************************
168 * CCI-400 related constants
169 ******************************************************************************/
170#define CCI400_BASE 0x2c090000
171#define CCI400_SL_IFACE_CLUSTER0 3
172#define CCI400_SL_IFACE_CLUSTER1 4
173#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
174 CCI400_SL_IFACE_CLUSTER1 : \
175 CCI400_SL_IFACE_CLUSTER0)
176
177/*******************************************************************************
178 * GIC-400 & interrupt handling related constants
179 ******************************************************************************/
180/* VE compatible GIC memory map */
181#define VE_GICD_BASE 0x2c001000
182#define VE_GICC_BASE 0x2c002000
183#define VE_GICH_BASE 0x2c004000
184#define VE_GICV_BASE 0x2c006000
185
186/* Base FVP compatible GIC memory map */
187#define BASE_GICD_BASE 0x2f000000
188#define BASE_GICR_BASE 0x2f100000
189#define BASE_GICC_BASE 0x2c000000
190#define BASE_GICH_BASE 0x2c010000
191#define BASE_GICV_BASE 0x2c02f000
192
193#define IRQ_TZ_WDOG 56
194#define IRQ_SEC_PHY_TIMER 29
195#define IRQ_SEC_SGI_0 8
196#define IRQ_SEC_SGI_1 9
197#define IRQ_SEC_SGI_2 10
198#define IRQ_SEC_SGI_3 11
199#define IRQ_SEC_SGI_4 12
200#define IRQ_SEC_SGI_5 13
201#define IRQ_SEC_SGI_6 14
202#define IRQ_SEC_SGI_7 15
203#define IRQ_SEC_SGI_8 16
204
205/*******************************************************************************
206 * PL011 related constants
207 ******************************************************************************/
208#define PL011_UART0_BASE 0x1c090000
209#define PL011_UART1_BASE 0x1c0a0000
210#define PL011_UART2_BASE 0x1c0b0000
211#define PL011_UART3_BASE 0x1c0c0000
212
213/*******************************************************************************
214 * TrustZone address space controller related constants
215 ******************************************************************************/
216#define TZC400_BASE 0x2a4a0000
217
218/*
219 * The NSAIDs for this platform as used to program the TZC400.
220 */
221
222/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
223#define FVP_AID_WIDTH 4
224
225/* NSAIDs used by devices in TZC filter 0 on FVP */
226#define FVP_NSAID_DEFAULT 0
227#define FVP_NSAID_PCI 1
228#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
229#define FVP_NSAID_AP 9 /* Application Processors */
230#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
231
232/* NSAIDs used by devices in TZC filter 2 on FVP */
233#define FVP_NSAID_HDLCD0 2
234#define FVP_NSAID_CLCD 7
235
236
237#endif /* __FVP_DEF_H__ */