blob: 63f6c3dd7d53c5a38762aa73758887c647b8f321 [file] [log] [blame]
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "platform_def.h"
#include "tc_vers.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc_fvp.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
/ {
compatible = "arm,tc";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &os_uart;
};
chosen {
stdout-path = STDOUT_PATH;
/*
* Add some dummy entropy for Linux so it
* doesn't delay the boot waiting for it.
*/
rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 >;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
core8 {
cpu = <&CPU8>;
};
core9 {
cpu = <&CPU9>;
};
core10 {
cpu = <&CPU10>;
};
core11 {
cpu = <&CPU11>;
};
core12 {
cpu = <&CPU12>;
};
core13 {
cpu = <&CPU13>;
};
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
};
/*
* The timings below are just to demonstrate working cpuidle.
* These values may be inaccurate.
*/
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
amus {
amu: amu-0 {
#address-cells = <1>;
#size-cells = <0>;
mpmm_gear0: counter@0 {
reg = <0>;
enable-at-el3;
};
mpmm_gear1: counter@1 {
reg = <1>;
enable-at-el3;
};
mpmm_gear2: counter@2 {
reg = <2>;
enable-at-el3;
};
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <LIT_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU1:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x100>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <LIT_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU2:cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
#if TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 0>;
capacity-dmips-mhz = <LIT_CAPACITY>;
#elif TARGET_PLATFORM == 3
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
CPU3:cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x300>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
#if TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 0>;
capacity-dmips-mhz = <LIT_CAPACITY>;
#elif TARGET_PLATFORM == 3
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
CPU4:cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x400>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU5:cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x500>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU6:cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x600>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
#if TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#elif TARGET_PLATFORM == 3
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
CPU7:cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x700>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#else
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
amu = <&amu>;
supports-mpmm;
};
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
CPU8:cpu@800 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x800>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU9:cpu@900 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x900>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG2_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU10:cpu@A00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xA00>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG2_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU11:cpu@B00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xB00>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG2_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU12:cpu@C00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xC00>;
enable-method = "psci";
clocks = <&scmi_dvfs 3>;
capacity-dmips-mhz = <BIG_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU13:cpu@D00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xD00>;
enable-method = "psci";
clocks = <&scmi_dvfs 3>;
capacity-dmips-mhz = <BIG_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
linux,cma-default;
};
optee {
compatible = "restricted-dma-pool";
reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
};
fwu_mm {
reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>;
no-map;
};
};
memory {
device_type = "memory";
reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
<&CPU12>, <&CPU13>
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
;
};
sram: sram@6000000 {
compatible = "mmio-sram";
reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>;
cpu_scp_scmi_mem: scp-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
};
mbox_db_rx: mhu@MHU_RX_ADDR() {
compatible = "arm,mhuv2-rx","arm,primecell";
reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_rx";
mhu-protocol = "doorbell";
arm,mhuv2-protocols = <0 1>;
};
mbox_db_tx: mhu@MHU_TX_ADDR() {
compatible = "arm,mhuv2-tx","arm,primecell";
reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
mhu-protocol = "doorbell";
arm,mhuv2-protocols = <0 1>;
};
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
#address-cells = <1>;
#size-cells = <0>;
#if TC_SCMI_PD_CTRL_EN
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
#endif /* TC_SCMI_PD_CTRL_EN */
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
compatible = "arm,gic-v3";
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
<0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc_refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-output-names = "apb_pclk";
};
soc_refclk60mhz: refclk60mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "iofpga_clk";
};
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <UARTCLK_FREQ>;
clock-output-names = "uartclk";
};
/* soc_uart0 on FPGA, ap_ns_uart on FVP */
os_uart: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_uartclk>, <&soc_refclk>;
clock-names = "uartclk", "apb_pclk";
status = "okay";
};
vencoder {
compatible = "drm,virtual-encoder";
port {
vencoder_in: endpoint {
remote-endpoint = <&dp_pl0_out0>;
};
};
display-timings {
timing-panel {
VENCODER_TIMING;
};
};
};
ethernet@18000000 {
compatible = ETH_COMPATIBLE;
reg = <0x0 0x18000000 0x0 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
/* FPGA only but will work on FVP. Keep for simplicity */
phy-mode = "mii";
reg-io-width = <2>;
smsc,irq-push-pull;
};
bp_clock24mhz: clock24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "bp:clock24mhz";
};
sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x0 0x001c010000 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
fixed_3v3: v2m-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mmci@1c050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
MMC_REMOVABLE;
wp-gpios = <&sysreg 1 0>;
bus-width = <4>;
max-frequency = <25000000>;
vmmc-supply = <&fixed_3v3>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "mclk", "apb_pclk";
};
gpu_clk: gpu_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
};
gpu_core_clk: gpu_core_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
};
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&gpu_core_clk>;
clock-names = "shadercores";
#if TC_SCMI_PD_CTRL_EN
power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
scmi-perf-domain = <3>;
#endif /* TC_SCMI_PD_CTRL_EN */
#if TC_IOMMU_EN
iommus = <&smmu_700 0x200>;
#endif /* TC_IOMMU_EN */
};
power_model_simple {
/*
* Numbers used are irrelevant to Titan,
* it helps suppressing the kernel warnings.
*/
compatible = "arm,mali-simple-power-model";
static-coefficient = <2427750>;
dynamic-coefficient = <4687>;
ts = <20000 2000 (-20) 2>;
thermal-zone = "";
};
#if TC_IOMMU_EN
smmu_700: iommu@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <0x0 0x3f000000 0x0 0x5000000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
};
#endif /* TC_IOMMU_EN */
dp0: display@DPU_ADDR() {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>;
interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DPU";
DPU_CLK_ATTR1;
#if TC_IOMMU_EN
iommus = <&smmu_700 0x100>;
#endif /* TC_IOMMU_EN */
#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
pl0: pipeline@0 {
reg = <0>;
DPU_CLK_ATTR2;
pl_id = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_pl0_out0: endpoint {
remote-endpoint = <&vencoder_in>;
};
};
};
};
pl1: pipeline@1 {
reg = <1>;
DPU_CLK_ATTR3;
pl_id = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
};
};
};
/*
* L3 cache in the DSU is the Memory System Component (MSC)
* The MPAM registers are accessed through utility bus in the DSU
*/
msc0 {
compatible = "arm,mpam-msc";
reg = <MPAM_ADDR 0x0 0x2000>;
};
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU0>;
};
ete1 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU1>;
};
ete2 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU2>;
};
ete3 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU3>;
};
ete4 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU4>;
};
ete5 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU5>;
};
ete6 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU6>;
};
ete7 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU7>;
};
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
ete8 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU8>;
};
ete9 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU9>;
};
ete10 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU10>;
};
ete11 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU11>;
};
ete12 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU12>;
};
ete13 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU13>;
};
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
};
trusty {
#size-cells = <0x02>;
#address-cells = <0x02>;
ranges = <0x00>;
compatible = "android,trusty-v1";
virtio {
compatible = "android,trusty-virtio-v1";
};
test {
compatible = "android,trusty-test-v1";
};
log {
compatible = "android,trusty-log-v1";
};
irq {
ipi-range = <0x08 0x0f 0x08>;
interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>;
interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>;
compatible = "android,trusty-irq-v1";
};
};
/* used in U-boot, Linux doesn't care */
arm_ffa {
compatible = "arm,ffa";
method = "smc";
};
};