refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant
The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if there were some LOOPBACK_REG1
register or something, which there is not.
Rename the constant to COMPHY_DIG_LOOPBACK_EN.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie88bdd864e2c9ab7e8de70ed7f3a13ee8f08ff79
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 0695645..1fdb484 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -315,7 +315,7 @@
RXD_INVERT_BIT);
/* 1. Select 40-bit data width width */
- offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
+ offset = COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET;
comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
SEL_DATA_WIDTH_MASK);
@@ -352,7 +352,7 @@
/* Polling status */
mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
- COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
+ COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET);
ret = polling_with_timeout(comphy_indir_regs +
COMPHY_LANE2_INDIR_DATA_OFFSET,
@@ -477,7 +477,8 @@
*/
data = DATA_WIDTH_10BIT;
mask = SEL_DATA_WIDTH_MASK;
- reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask);
+ reg_set16(SGMIIPHY_ADDR(COMPHY_DIG_LOOPBACK_EN, sd_ip_addr),
+ data, mask);
/*
* 12. As long as DFE function needs to be enabled in any mode,
@@ -737,7 +738,7 @@
/*
* 11. Set 20-bit data width
*/
- usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
+ usb3_reg_set(reg_base, COMPHY_DIG_LOOPBACK_EN, DATA_WIDTH_20BIT,
REG_16_BIT_MASK);
/*
@@ -1025,7 +1026,7 @@
/* Polling status */
mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
- COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
+ COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET);
addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET;
data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT,
COMPHY_PLL_TIMEOUT, REG_32BIT);
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 42d4a80..df89da9 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -75,8 +75,9 @@
#define COMPHY_RESERVED_REG 0x0E
#define PHYCTRL_FRM_PIN_BIT BIT(13)
-#define COMPHY_LOOPBACK_REG0 0x23
-#define DIG_LB_EN_ADDR(unit) (COMPHY_LOOPBACK_REG0 * PHY_SHFT(unit))
+#define COMPHY_DIG_LOOPBACK_EN 0x23
+#define DIG_LOOPBACK_EN_ADDR(unit) (COMPHY_DIG_LOOPBACK_EN * \
+ PHY_SHFT(unit))
#define SEL_DATA_WIDTH_OFFSET 10
#define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET)
#define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET)