Merge "fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32" into integration
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index e96156d..301c60c 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -149,11 +149,9 @@
trf_init_el3();
}
- /*
- * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure
- * state execution. This does not affect lower NS ELs.
- */
- pmuv3_init_el3();
+ if (read_feat_pmuv3_id_field() >= 3U) {
+ pmuv3_init_el3();
+ }
#endif /* IMAGE_BL32 */
}
diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c
index effb7e0..456a48e 100644
--- a/lib/extensions/pmuv3/aarch32/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch32/pmuv3.c
@@ -25,10 +25,6 @@
return sdcr;
}
-/*
- * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and
- * to not clash with platforms which reuse the PMU name
- */
void pmuv3_init_el3(void)
{
u_register_t sdcr = read_sdcr();