Merge "fix(allwinner): enable dtb modifications for CPU idle states to the rich OS" into integration
diff --git a/.editorconfig b/.editorconfig
index 12f786d..1b29c88 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -70,3 +70,6 @@
# [PEP8] Maximum Line Length
# "Limit all lines to a maximum of 79 characters."
max_line_length = 79
+
+[.git/COMMIT_EDITMSG]
+max_line_length = 72
diff --git a/Makefile b/Makefile
index a2ff9ce..4f3f261 100644
--- a/Makefile
+++ b/Makefile
@@ -43,17 +43,6 @@
# Configure the toolchains used to build TF-A and its tools
################################################################################
-#
-# The clean and check targets do not behave correctly if the user's environment
-# does not appropriately configure a toolchain. While we try to find a permanent
-# solution to this, do not try to detect any toolchains if we are building
-# exclusively with targets which do not use any toolchain tools.
-#
-
-ifeq ($(filter-out check% %clean doc %tool,$(or $(MAKECMDGOALS),all)),)
- toolchains :=
-endif
-
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
# Assertions enabled for DEBUG builds by default
@@ -608,19 +597,11 @@
################################################################################
# FEAT_RME
ifeq (${ENABLE_RME},1)
- # RME doesn't support BRBE
- ENABLE_BRBE_FOR_NS := 0
-
# RME doesn't support PIE
ifneq (${ENABLE_PIE},0)
$(error ENABLE_RME does not support PIE)
endif
- # RME doesn't support BRBE
- ifneq (${ENABLE_BRBE_FOR_NS},0)
- $(error ENABLE_RME does not support BRBE.)
- endif
-
# RME requires AARCH64
ifneq (${ARCH},aarch64)
$(error ENABLE_RME requires AArch64)
@@ -1188,6 +1169,7 @@
HW_ASSISTED_COHERENCY \
MEASURED_BOOT \
DICE_PROTECTION_ENVIRONMENT \
+ RMMD_ENABLE_EL3_TOKEN_SIGN \
DRTM_SUPPORT \
NS_TIMER_SWITCH \
OVERRIDE_LIBC \
@@ -1274,11 +1256,13 @@
ENABLE_FEAT_RNG_TRAP \
ENABLE_FEAT_SEL2 \
ENABLE_FEAT_TCR2 \
+ ENABLE_FEAT_THE \
ENABLE_FEAT_SB \
ENABLE_FEAT_S2PIE \
ENABLE_FEAT_S1PIE \
ENABLE_FEAT_S2POE \
ENABLE_FEAT_S1POE \
+ ENABLE_FEAT_SCTLR2 \
ENABLE_FEAT_GCS \
ENABLE_FEAT_VHE \
ENABLE_FEAT_MPAM \
@@ -1342,6 +1326,7 @@
ENABLE_PMF \
ENABLE_PSCI_STAT \
ENABLE_RME \
+ RMMD_ENABLE_EL3_TOKEN_SIGN \
ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SME_FOR_NS \
ENABLE_SME2_FOR_NS \
@@ -1430,10 +1415,12 @@
ENABLE_FEAT_CSV2_3 \
ENABLE_FEAT_PAN \
ENABLE_FEAT_TCR2 \
+ ENABLE_FEAT_THE \
ENABLE_FEAT_S2PIE \
ENABLE_FEAT_S1PIE \
ENABLE_FEAT_S2POE \
ENABLE_FEAT_S1POE \
+ ENABLE_FEAT_SCTLR2 \
ENABLE_FEAT_GCS \
ENABLE_FEAT_MTE2 \
FEATURE_DETECTION \
@@ -1500,7 +1487,7 @@
# Build targets
################################################################################
-.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip sp fwu_fip certtool dtbs memmap doc enctool
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip sp tl fwu_fip certtool dtbs memmap doc enctool
.SUFFIXES:
all: msg_start
@@ -1727,7 +1714,7 @@
${FIPTOOL}: FORCE
ifdef UNIX_MK
- $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
+ $(q)${MAKE} PLAT=${PLAT} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
@@ -1746,6 +1733,11 @@
${PYTHON} -m memory.memmap -sr ${BUILD_PLAT}
endif
+tl: ${BUILD_PLAT}/tl.bin
+${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
+ $(if $(host-poetry),$(q)poetry -q install)
+ $(q)$(if $(host-poetry),poetry run )tlc create --fdt $< -s ${FW_HANDOFF_SIZE} $@
+
doc:
$(s)echo " BUILD DOCUMENTATION"
$(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index db0eafc..a8a0061 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -19,7 +19,8 @@
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
- lib/el3_runtime/aarch64/context.S
+ lib/el3_runtime/aarch64/context.S \
+ lib/cpus/errata_common.c
endif
ifeq (${TRUSTED_BOARD_BOOT},1)
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index e47b082..7423805 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -229,7 +229,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
handle_sync_exception
end_vector_entry sync_exception_aarch64
@@ -237,7 +236,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry irq_aarch64
@@ -245,7 +243,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry fiq_aarch64
@@ -258,7 +255,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_lower_el_async_ea
#else
b report_unhandled_exception
@@ -279,7 +275,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
handle_sync_exception
end_vector_entry sync_exception_aarch32
@@ -287,7 +282,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry irq_aarch32
@@ -295,7 +289,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry fiq_aarch32
@@ -308,7 +301,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_lower_el_async_ea
#else
b report_unhandled_exception
diff --git a/changelog.yaml b/changelog.yaml
index d073a84..3591f02 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -272,6 +272,13 @@
- title: Corstone-1000
scope: corstone-1000
+ - title: Automotive RD
+ scope: automotive_rd
+
+ subsections:
+ - title: RD-1 AE
+ scope: rd1ae
+
- title: Aspeed
scope: aspeed
@@ -893,6 +900,9 @@
- title: Console
scope: console
+ - title: Delay Timer
+ scope: delay-timer
+
- title: Generic Clock
scope: clk
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 783b660..b213ffa 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,19 @@
return 0;
}
+uint64_t fdt_read_uint64_default(const void *dtb, int node,
+ const char *prop_name, uint64_t dflt_value)
+{
+ uint64_t ret = dflt_value;
+ int err = fdt_read_uint64(dtb, node, prop_name, &ret);
+
+ if (err < 0) {
+ return dflt_value;
+ }
+
+ return ret;
+}
+
/*
* Read bytes from a given property of the given node. Any number of
* bytes of the property can be read. The fdt pointer is updated.
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 9b9f7b4..e63eec4 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -257,6 +257,18 @@
}
+static unsigned int read_feat_the_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT,
+ ID_AA64PFR1_EL1_THE_MASK);
+}
+
+static unsigned int read_feat_sctlr2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT,
+ ID_AA64MMFR3_EL1_SCTLR2_MASK);
+}
+
/***********************************************************************************
* TF-A supports many Arm architectural features starting from arch version
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
@@ -365,6 +377,10 @@
"CSV2_3", 3, 3);
check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(),
"DEBUGV8P9", 11, 11);
+ check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(),
+ "THE", 1, 1);
+ check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(),
+ "SCTLR2", 1, 1);
/* v9.0 features */
check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 8bb12ab..03526a6 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -49,12 +49,14 @@
:|G|: `laurenw-arm`_
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
:|G|: `madhukar-Arm`_
-:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|M|: Raghu Krishnamurthy <raghuoss@raghushome.com>
:|G|: `raghuncstate`_
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
:|G|: `ManishVB-Arm`_
:|M|: Yann Gautier <yann.gautier@st.com>
:|G|: `Yann-lms`_
+:|M|: Govindraj Raja <govindraj.raja@arm.com>
+:|G|: `govindraj-arm`_
LTS Maintainers
---------------
@@ -594,6 +596,16 @@
:|G|: `rupsin01`_
:|F|: plat/arm/board/tc
+Arm Automotive RD platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Diego Sueiro <diego.sueiro@arm.com>
+:|G|: `diego-sueiro`_
+:|M|: Peter Hoyes <peter.hoyes@arm.com>
+:|G|: `hoyes`_
+:|M|: Divin Raj <divin.raj@arm.com>
+:|G|: `divin-raj`_
+:|F|: plat/arm/board/automotive_rd
+
Aspeed platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
@@ -1006,7 +1018,7 @@
:|G|: `sandrine-bailleux-arm`_
:|M|: Joanna Farley <joanna.farley@arm.com>
:|G|: `joannafarley-arm`_
-:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|M|: Raghu Krishnamurthy <raghuoss@raghushome.com>
:|G|: `raghuncstate`_
:|M|: Varun Wadekar <vwadekar@nvidia.com>
:|G|: `vwadekar`_
@@ -1041,12 +1053,16 @@
.. _CJKay: https://github.com/cjkay
.. _danh-arm: https://github.com/danh-arm
.. _davidvincze: https://github.com/davidvincze
+.. _diego-sueiro: https://github.com/diego-sueiro
+.. _divin-raj: https://github.com/divin-raj
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
+.. _govindraj-arm: https://github.com/govindraj-arm
.. _gprocopciucnxp: https://github.com/gprocopciucnxp
.. _grandpaul: https://github.com/grandpaul
.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
+.. _hoyes: https://github.com/hoyes
.. _hzhuang1: https://github.com/hzhuang1
.. _hugues-kambampiana-arm: https://github.com/hugueskamba
.. _JackyBai: https://github.com/JackyBai
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 7fafe03..253b18d 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -70,6 +70,10 @@
+-----------------+---------------------------+------------------------------+
| v2.11 | 4th week of May '24 | 2nd week of May '24 |
+-----------------+---------------------------+------------------------------+
+| v2.12 | 4th week of Nov '24 | 2nd week of Nov '24 |
++-----------------+---------------------------+------------------------------+
+| v2.13 | 4th week of May '25 | 2nd week of May '25 |
++-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
--------------------------------
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
index c5dad14..2b6382b 100644
--- a/docs/components/ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst
@@ -122,7 +122,7 @@
- managed-exit-virq
- value type: <empty>
- Indicates if the partition needs managed exit, if supported, to be signaled
- through vFIQ signal.
+ through vIRQ signal.
- ns-interrupts-action [mandatory]
- value type: <u32>
@@ -143,12 +143,6 @@
- 0x0: Other-Secure interrupt is queued
- 0x1: Other-Secure interrupt is signaled
-- runtime-model
- - value type: <u32>
- - Indicates whether the SP execution can be preempted.
- - This field is deprecated in favor of other-s-interrupts-action and
- ns-interrupts-action fields in the FF-A v1.1 spec.
-
- has-primary-scheduler
- value type: <empty>
- Presence of this field indicates that the partition implements the primary
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index e6ca542..fda43dc 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -840,6 +840,12 @@
- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+
+- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 203bf0f..7776f5b 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -455,6 +455,22 @@
the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Default value is ``0``.
+- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE
+ (Translation Hardening Extension) at EL2 and below, setting the bit
+ SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1
+ registers and context switch them.
+ Its an optional architectural feature and is available from v8.8 and upwards.
+ This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
+ mechanism. Default value is ``0``.
+
+- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2
+ (Extension to SCTLR_ELx) at EL2 and below, setting the bit
+ SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and
+ context switch them. This feature is OPTIONAL from Armv8.0 implementations
+ and mandatory in Armv8.9 implementations.
+ This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
+ mechanism. Default value is ``0``.
+
- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
support in GCC for TF-A. This option is currently only supported for
AArch64. Default is 0.
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 6a0241f..de2da2f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -27,11 +27,11 @@
Program Min supported version
======================== =====================
Arm Compiler 6.18
-Arm GNU Compiler 13.2
+Arm GNU Compiler 13.3
Clang/LLVM 11.0.0
Device Tree Compiler 1.4.7
GNU make 3.81
-mbed TLS\ [#f1]_ 3.6.0
+mbed TLS\ [#f1]_ 3.6.1
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry [#f2]_ 1.3.2
@@ -51,7 +51,7 @@
AArch64 builds, the respective targets required are ``arm-none-eabi`` and
``aarch64-none-elf``.
-Testing has been performed with version 13.2.Rel1 (gcc 13.2) of the Arm
+Testing has been performed with version 13.3.Rel1 (gcc 13.3) of the Arm
GNU compiler, which can be installed from the `Arm Developer website`_.
In addition, a native compiler is required to build supporting tools.
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index e1b3ef0..afbb157 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -16,6 +16,12 @@
should match the frame used by the Non-Secure image (normally the Linux
kernel). Default is true (access to the frame is allowed).
+- ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of
+ FW_CONFIG device trees from the Firmware Image Package (FIP). When enabled,
+ BL2 calls the platform specific function `arm_bl2_el3_plat_config_load`.
+ This function is responsible for loading, parsing, and validating the
+ FW_CONFIG device trees from the FIP. The option depends on RESET_TO_BL2.
+
- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
By default, Arm platforms use a watchdog to trigger a system reset in case
an error is encountered during the boot process (for example, when an image
diff --git a/docs/plat/arm/automotive_rd/index.rst b/docs/plat/arm/automotive_rd/index.rst
new file mode 100644
index 0000000..d0db6ac
--- /dev/null
+++ b/docs/plat/arm/automotive_rd/index.rst
@@ -0,0 +1,50 @@
+RD-1 AE (Kronos) Platform
+=========================
+
+Some of the features of the RD-1 AE platform referenced in TF-A include:
+
+- Neoverse-V3AE, Arm9.2-A application processor (64-bit mode)
+- A GICv4-compatible GIC-720AE
+
+Further information on RD1-AE is available at `rd1ae`_
+
+Boot Sequence
+-------------
+
+BL2 –> BL31 –> BL33
+
+The boot process starts from RSE (Runtime Security Engine) that loads the BL2 image
+and signals the System Control Processor (SCP) to power up the Application Processor (AP).
+The AP then runs BL2, which loads the rest of the images, including the runtime firmware
+BL31, and proceeds to execute it. Finally, it passes control to the non-secure world
+BL33 (u-boot).
+
+BL2 performs the actions described in the `Trusted Board Boot (TBB)`_ document.
+
+Build Procedure (TF-A only)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to
+ point to the toolchain folder.
+
+- Build TF-A:
+
+ .. code:: shell
+
+ make \
+ PLAT=rd1ae \
+ MBEDTLS_DIR=<mbedtls_dir> \
+ ARCH=aarch64 \
+ CREATE_KEYS=1 \
+ GENERATE_COT=1 \
+ TRUSTED_BOARD_BOOT=1 \
+ COT=tbbr \
+ ARM_ROTPK_LOCATION=devel_rsa \
+ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+ BL33=<path to u-boot binary> \
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*
+
+.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
+.. _rd1ae: https://developer.arm.com/Tools%20and%20Software/Arm%20Reference%20Design-1%20AE
+.. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index 2f68522..35c0c59 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst
@@ -14,6 +14,7 @@
arm-build-options
morello/index
corstone1000/index
+ automotive_rd/index
This chapter holds documentation related to Arm's development platforms,
including both software models (FVPs) and hardware development boards
@@ -21,4 +22,4 @@
--------------
-*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 85c97e5..a8e0c8d 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -72,8 +72,8 @@
+----------------+----------------+--------------------+--------------------+
| Platform | Vendor | Deprecated version | Deleted version |
+================+================+====================+====================+
-| None at this | | | |
-| time. | | | |
+| TC2 | Arm | 2.12 | TBD |
+| | | | |
+----------------+----------------+--------------------+--------------------+
--------------
diff --git a/docs/plat/s32g274a.rst b/docs/plat/s32g274a.rst
index 3aa858e..d3f31ca 100644
--- a/docs/plat/s32g274a.rst
+++ b/docs/plat/s32g274a.rst
@@ -95,5 +95,17 @@
-d "${BOOT_IMAGE}" \
fip.s32
+SoC Errata Workarounds
+----------------------
+
+The S32G274A port of the TF-A includes compilation flags that can be used to
+control the workaround for the SoC. These flags are used similarly to how the
+:ref:`arm_cpu_macros_errata_workarounds` are used. The list of workarounds
+includes the following switches:
+
+- ``ERRATA_S32_051700``: This applies erratum ERR051700 workaround to
+ SoCs part of the S32 Common Chassis family, and therefore it needs to
+ be enabled for the S32G and S32R devices.
+
.. _s32g2: https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g2-processors-for-vehicle-networking:S32G2
.. _s32g274ardb2: https://www.nxp.com/design/design-center/designs/s32g2-vehicle-networking-reference-design:S32G-VNP-RDB2
diff --git a/drivers/arm/dcc/dcc_console.c b/drivers/arm/dcc/dcc_console.c
index 19c3450..841c1fd 100644
--- a/drivers/arm/dcc/dcc_console.c
+++ b/drivers/arm/dcc/dcc_console.c
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2021, Xilinx Inc.
+ * Copyright (c) 2015-2022, Xilinx Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
* Written by Michal Simek.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -45,7 +46,7 @@
#define TIMEOUT_COUNT_US U(0x10624)
struct dcc_console {
- struct console console;
+ console_t console;
};
static inline uint32_t __dcc_getstatus(void)
@@ -147,13 +148,14 @@
},
};
-int console_dcc_register(void)
+int console_dcc_register(console_t *console)
{
- return console_register(&dcc_console.console);
+ memcpy(console, &dcc_console.console, sizeof(console_t));
+ return console_register(console);
}
-void console_dcc_unregister(void)
+void console_dcc_unregister(console_t *console)
{
- dcc_console_flush(&dcc_console.console);
- (void)console_unregister(&dcc_console.console);
+ dcc_console_flush(console);
+ (void)console_unregister(console);
}
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index e925e14..765491e 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -66,7 +66,6 @@
)
ifeq (${PSA_CRYPTO},1)
-LIBMBEDTLS_CFLAGS += -Wno-error=unused-but-set-variable
LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \
psa_crypto.c \
psa_crypto_client.c \
@@ -74,6 +73,8 @@
psa_crypto_rsa.c \
psa_crypto_ecp.c \
psa_crypto_slot_management.c \
+ psa_crypto_aead.c \
+ psa_crypto_cipher.c \
psa_util.c \
)
endif
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 53f8adf..f2ccf15 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -9,13 +9,11 @@
#include <string.h>
/* mbed TLS headers */
-#include <mbedtls/gcm.h>
#include <mbedtls/md.h>
#include <mbedtls/memory_buffer_alloc.h>
#include <mbedtls/oid.h>
#include <mbedtls/platform.h>
#include <mbedtls/psa_util.h>
-#include <mbedtls/version.h>
#include <mbedtls/x509.h>
#include <psa/crypto.h>
#include <psa/crypto_platform.h>
@@ -433,78 +431,61 @@
unsigned int iv_len, const void *tag,
unsigned int tag_len)
{
- mbedtls_gcm_context ctx;
- mbedtls_cipher_id_t cipher = MBEDTLS_CIPHER_ID_AES;
+ mbedtls_svc_key_id_t key_id = MBEDTLS_SVC_KEY_ID_INIT;
+ psa_aead_operation_t operation = PSA_AEAD_OPERATION_INIT;
+ psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT;
+ psa_status_t psa_status = PSA_ERROR_GENERIC_ERROR;
unsigned char buf[DEC_OP_BUF_SIZE];
- unsigned char tag_buf[CRYPTO_MAX_TAG_SIZE];
unsigned char *pt = data_ptr;
size_t dec_len;
- int diff, i, rc;
- size_t output_length __unused;
+ size_t output_length;
- mbedtls_gcm_init(&ctx);
+ /* Load the key into the PSA key store. */
+ psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT);
+ psa_set_key_algorithm(&attributes, PSA_ALG_GCM);
+ psa_set_key_type(&attributes, PSA_KEY_TYPE_AES);
- rc = mbedtls_gcm_setkey(&ctx, cipher, key, key_len * 8);
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ psa_status = psa_import_key(&attributes, key, key_len, &key_id);
+ if (psa_status != PSA_SUCCESS) {
+ return CRYPTO_ERR_DECRYPTION;
}
-#if (MBEDTLS_VERSION_MAJOR < 3)
- rc = mbedtls_gcm_starts(&ctx, MBEDTLS_GCM_DECRYPT, iv, iv_len, NULL, 0);
-#else
- rc = mbedtls_gcm_starts(&ctx, MBEDTLS_GCM_DECRYPT, iv, iv_len);
-#endif
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ /* Perform the decryption. */
+ psa_status = psa_aead_decrypt_setup(&operation, key_id, PSA_ALG_GCM);
+ if (psa_status != PSA_SUCCESS) {
+ goto err;
+ }
+
+ psa_status = psa_aead_set_nonce(&operation, iv, iv_len);
+ if (psa_status != PSA_SUCCESS) {
+ goto err;
}
while (len > 0) {
dec_len = MIN(sizeof(buf), len);
-#if (MBEDTLS_VERSION_MAJOR < 3)
- rc = mbedtls_gcm_update(&ctx, dec_len, pt, buf);
-#else
- rc = mbedtls_gcm_update(&ctx, pt, dec_len, buf, sizeof(buf), &output_length);
-#endif
-
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ psa_status = psa_aead_update(&operation, pt, dec_len, buf,
+ sizeof(buf), &output_length);
+ if (psa_status != PSA_SUCCESS) {
+ goto err;
}
- memcpy(pt, buf, dec_len);
- pt += dec_len;
+ memcpy(pt, buf, output_length);
+ pt += output_length;
len -= dec_len;
}
-#if (MBEDTLS_VERSION_MAJOR < 3)
- rc = mbedtls_gcm_finish(&ctx, tag_buf, sizeof(tag_buf));
-#else
- rc = mbedtls_gcm_finish(&ctx, NULL, 0, &output_length, tag_buf, sizeof(tag_buf));
-#endif
-
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
- }
-
- /* Check tag in "constant-time" */
- for (diff = 0, i = 0; i < tag_len; i++)
- diff |= ((const unsigned char *)tag)[i] ^ tag_buf[i];
-
- if (diff != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ /* Verify the tag. */
+ psa_status = psa_aead_verify(&operation, NULL, 0, &output_length, tag, tag_len);
+ if (psa_status == PSA_SUCCESS) {
+ psa_destroy_key(key_id);
+ return CRYPTO_SUCCESS;
}
- /* GCM decryption success */
- rc = CRYPTO_SUCCESS;
-
-exit_gcm:
- mbedtls_gcm_free(&ctx);
- return rc;
+err:
+ psa_aead_abort(&operation);
+ psa_destroy_key(key_id);
+ return CRYPTO_ERR_DECRYPTION;
}
/*
diff --git a/drivers/delay_timer/delay_timer.c b/drivers/delay_timer/delay_timer.c
index a3fd7bf..bdbbbf6 100644
--- a/drivers/delay_timer/delay_timer.c
+++ b/drivers/delay_timer/delay_timer.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -80,3 +80,25 @@
timer_ops = ops_ptr;
}
+
+/***********************************************************
+ * Initialize the timer in us
+ ***********************************************************/
+uint64_t timeout_init_us(uint32_t usec)
+{
+ assert(timer_ops != NULL);
+ assert(timer_ops->timeout_init_us != NULL);
+
+ return timer_ops->timeout_init_us(usec);
+}
+
+/***********************************************************
+ * check the given timeout elapsed or not.
+ ***********************************************************/
+bool timeout_elapsed(uint64_t cnt)
+{
+ assert(timer_ops != NULL);
+ assert(timer_ops->timeout_elapsed != NULL);
+
+ return timer_ops->timeout_elapsed(cnt);
+}
diff --git a/drivers/delay_timer/generic_delay_timer.c b/drivers/delay_timer/generic_delay_timer.c
index ca522e0..0407e38 100644
--- a/drivers/delay_timer/generic_delay_timer.c
+++ b/drivers/delay_timer/generic_delay_timer.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -18,7 +18,26 @@
static timer_ops_t ops;
-static uint32_t get_timer_value(void)
+static uint64_t timeout_cnt_us2cnt(uint32_t us)
+{
+ return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL;
+}
+
+static uint64_t generic_delay_timeout_init_us(uint32_t us)
+{
+ uint64_t cnt = timeout_cnt_us2cnt(us);
+
+ cnt += read_cntpct_el0();
+
+ return cnt;
+}
+
+static bool generic_delay_timeout_elapsed(uint64_t expire_cnt)
+{
+ return read_cntpct_el0() > expire_cnt;
+}
+
+static uint32_t generic_delay_get_timer_value(void)
{
/*
* Generic delay timer implementation expects the timer to be a down
@@ -31,9 +50,11 @@
void generic_delay_timer_init_args(uint32_t mult, uint32_t div)
{
- ops.get_timer_value = get_timer_value;
+ ops.get_timer_value = generic_delay_get_timer_value;
ops.clk_mult = mult;
ops.clk_div = div;
+ ops.timeout_init_us = generic_delay_timeout_init_us;
+ ops.timeout_elapsed = generic_delay_timeout_elapsed;
timer_init(&ops);
@@ -59,4 +80,3 @@
generic_delay_timer_init_args(mult, div);
}
-
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
index 84e76f7..e54d581 100644
--- a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
+++ b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
@@ -13,6 +13,11 @@
#define ARM_DFS_BASE_ADDR (0x40054000UL)
#define CGM0_BASE_ADDR (0x40030000UL)
#define CGM1_BASE_ADDR (0x40034000UL)
+#define DDRPLL_BASE_ADDR (0x40044000UL)
+#define MC_ME_BASE_ADDR (0x40088000UL)
+#define MC_RGM_BASE_ADDR (0x40078000UL)
+#define RDC_BASE_ADDR (0x40080000UL)
+#define MC_CGM5_BASE_ADDR (0x40068000UL)
/* FXOSC */
#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-mc-me.h b/drivers/nxp/clk/s32cc/include/s32cc-mc-me.h
new file mode 100644
index 0000000..8249fc5
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/include/s32cc-mc-me.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021, 2023-2024 NXP
+ */
+#ifndef S32CC_MC_ME_H
+#define S32CC_MC_ME_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+int mc_me_enable_partition(uintptr_t mc_me, uintptr_t mc_rgm, uintptr_t rdc,
+ uint32_t part);
+void mc_me_enable_part_cofb(uintptr_t mc_me, uint32_t partition_n, uint32_t block,
+ bool check_status);
+
+#endif /* S32CC_MC_ME_H */
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
new file mode 100644
index 0000000..d6234da
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021, 2023-2024 NXP
+ */
+#ifndef S32CC_MC_RGM_H
+#define S32CC_MC_RGM_H
+
+#include <stdint.h>
+
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value);
+void mc_rgm_release_part(uintptr_t rgm, uint32_t part);
+void mc_rgm_wait_part_deassert(uintptr_t rgm, uint32_t part);
+
+#endif /* MC_RGM_H */
diff --git a/drivers/nxp/clk/s32cc/mc_me.c b/drivers/nxp/clk/s32cc/mc_me.c
new file mode 100644
index 0000000..04d0425
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/mc_me.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <s32cc-mc-me.h>
+#include <s32cc-mc-rgm.h>
+
+#define MC_ME_MAX_PARTITIONS (4U)
+
+#define MC_ME_CTL_KEY(MC_ME) ((MC_ME) + 0x0UL)
+#define MC_ME_CTL_KEY_KEY (0x5AF0U)
+#define MC_ME_CTL_KEY_INVERTEDKEY (0xA50FU)
+
+#define MC_ME_PRTN_N(MC_ME, PART) ((MC_ME) + 0x100UL + ((PART) * 0x200UL))
+#define MC_ME_PRTN_N_PCONF(MC_ME, PART) (MC_ME_PRTN_N(MC_ME, PART))
+#define MC_ME_PRTN_N_PCE BIT_32(0)
+#define MC_ME_PRTN_N_OSSE BIT_32(2)
+#define MC_ME_PRTN_N_PUPD(MC_ME, PART) (MC_ME_PRTN_N(MC_ME, PART) + 0x4UL)
+#define MC_ME_PRTN_N_PCUD BIT_32(0)
+#define MC_ME_PRTN_N_OSSUD BIT_32(2)
+#define MC_ME_PRTN_N_STAT(MC_ME, PART) (MC_ME_PRTN_N(MC_ME, PART) + 0x8UL)
+#define MC_ME_PRTN_N_PCS BIT_32(0)
+#define MC_ME_PRTN_N_COFB0_STAT(MC_ME, PART) \
+ (MC_ME_PRTN_N(MC_ME, PART) + 0x10UL)
+#define MC_ME_PRTN_N_COFB0_CLKEN(MC_ME, PART) \
+ (MC_ME_PRTN_N(MC_ME, PART) + 0x30UL)
+#define MC_ME_PRTN_N_REQ(PART) BIT_32(PART)
+
+#define RDC_RD_CTRL(RDC, PART) ((RDC) + ((PART) * 0x4UL))
+#define RDC_CTRL_UNLOCK BIT_32(31)
+#define RDC_RD_INTERCONNECT_DISABLE BIT_32(3)
+
+#define RDC_RD_N_STATUS(RDC, PART) ((RDC) + ((PART) * 0x4UL) + 0x80UL)
+#define RDC_RD_INTERCONNECT_DISABLE_STAT \
+ BIT_32(4)
+
+static bool is_interconnect_disabled(uintptr_t rdc, uint32_t part)
+{
+ return ((mmio_read_32(RDC_RD_N_STATUS(rdc, part)) &
+ RDC_RD_INTERCONNECT_DISABLE_STAT) != 0U);
+}
+
+static void enable_interconnect(uintptr_t rdc, uint32_t part)
+{
+ /* Unlock RDC register write */
+ mmio_setbits_32(RDC_RD_CTRL(rdc, part), RDC_CTRL_UNLOCK);
+
+ /* Clear corresponding RDC_RD_INTERCONNECT bit */
+ mmio_clrbits_32(RDC_RD_CTRL(rdc, part), RDC_RD_INTERCONNECT_DISABLE);
+
+ /* Wait until the interface gets enabled */
+ while (is_interconnect_disabled(rdc, part)) {
+ }
+
+ /* Lock RDC register write */
+ mmio_clrbits_32(RDC_RD_CTRL(rdc, part), RDC_CTRL_UNLOCK);
+}
+
+static int mc_me_check_partition_nb_valid(uint32_t part)
+{
+ if (part >= MC_ME_MAX_PARTITIONS) {
+ ERROR("Invalid partition %" PRIu32 "\n", part);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void part_pconf_write_pce(uintptr_t mc_me, uint32_t pce_bit,
+ uint32_t part)
+{
+ mmio_clrsetbits_32(MC_ME_PRTN_N_PCONF(mc_me, part), MC_ME_PRTN_N_PCE,
+ pce_bit & MC_ME_PRTN_N_PCE);
+}
+
+static void mc_me_apply_hw_changes(uintptr_t mc_me)
+{
+ mmio_write_32(MC_ME_CTL_KEY(mc_me), MC_ME_CTL_KEY_KEY);
+ mmio_write_32(MC_ME_CTL_KEY(mc_me), MC_ME_CTL_KEY_INVERTEDKEY);
+}
+
+static void part_pupd_update_and_wait(uintptr_t mc_me, uint32_t part,
+ uint32_t mask)
+{
+ uint32_t pconf, stat;
+
+ mmio_setbits_32(MC_ME_PRTN_N_PUPD(mc_me, part), mask);
+
+ mc_me_apply_hw_changes(mc_me);
+
+ /* wait for the updates to apply */
+ pconf = mmio_read_32(MC_ME_PRTN_N_PCONF(mc_me, part));
+ do {
+ stat = mmio_read_32(MC_ME_PRTN_N_STAT(mc_me, part));
+ } while ((stat & mask) != (pconf & mask));
+}
+
+static void part_pconf_write_osse(uintptr_t mc_me, uint32_t osse_bit,
+ uint32_t part)
+{
+ mmio_clrsetbits_32(MC_ME_PRTN_N_PCONF(mc_me, part), MC_ME_PRTN_N_OSSE,
+ (osse_bit & MC_ME_PRTN_N_OSSE));
+}
+
+int mc_me_enable_partition(uintptr_t mc_me, uintptr_t mc_rgm, uintptr_t rdc,
+ uint32_t part)
+{
+ uint32_t part_stat;
+ int ret;
+
+ /* Partition 0 is already enabled by BootROM */
+ if (part == 0U) {
+ return 0;
+ }
+
+ ret = mc_me_check_partition_nb_valid(part);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Enable a partition only if it's disabled */
+ part_stat = mmio_read_32(MC_ME_PRTN_N_STAT(mc_me, part));
+ if ((MC_ME_PRTN_N_PCS & part_stat) != 0U) {
+ return 0;
+ }
+
+ part_pconf_write_pce(mc_me, MC_ME_PRTN_N_PCE, part);
+ part_pupd_update_and_wait(mc_me, part, MC_ME_PRTN_N_PCUD);
+
+ enable_interconnect(rdc, part);
+
+ /* Release partition reset */
+ mc_rgm_release_part(mc_rgm, part);
+
+ /* Clear OSSE bit */
+ part_pconf_write_osse(mc_me, 0, part);
+
+ part_pupd_update_and_wait(mc_me, part, MC_ME_PRTN_N_OSSUD);
+
+ mc_rgm_wait_part_deassert(mc_rgm, part);
+
+ return 0;
+}
+
+void mc_me_enable_part_cofb(uintptr_t mc_me, uint32_t partition_n, uint32_t block,
+ bool check_status)
+{
+ uint32_t block_mask = MC_ME_PRTN_N_REQ(block);
+ uintptr_t cofb_stat_addr;
+
+ mmio_setbits_32(MC_ME_PRTN_N_COFB0_CLKEN(mc_me, partition_n),
+ block_mask);
+
+ mmio_setbits_32(MC_ME_PRTN_N_PCONF(mc_me, partition_n),
+ MC_ME_PRTN_N_PCE);
+
+ part_pupd_update_and_wait(mc_me, partition_n, MC_ME_PRTN_N_PCUD);
+
+ cofb_stat_addr = MC_ME_PRTN_N_COFB0_STAT(mc_me, partition_n);
+ if (check_status) {
+ while ((mmio_read_32(cofb_stat_addr) & block_mask) == 0U) {
+ }
+ }
+}
diff --git a/drivers/nxp/clk/s32cc/mc_rgm.c b/drivers/nxp/clk/s32cc/mc_rgm.c
new file mode 100644
index 0000000..c66b013
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/mc_rgm.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <s32cc-mc-rgm.h>
+
+#define MC_RGM_PRST(RGM, PER) ((RGM) + 0x40UL + ((PER) * 0x8UL))
+#define MC_RGM_PRST_PERIPH_N_RST(PER) BIT_32(PER)
+#define MC_RGM_PSTAT(RGM, PER) ((RGM) + 0x140UL + ((PER) * 0x8UL))
+#define MC_RGM_PSTAT_PERIPH(PER) BIT_32(PER)
+
+/* ERR051700
+ * Releasing more than one Software Resettable Domain (SRD)
+ * from reset simultaneously, by clearing the corresponding
+ * peripheral MC_RGM_PRSTn[PERIPH_x_RST] reset control may
+ * cause a false setting of the Fault Collection and
+ * Control Unit (FCCU) Non-Critical Fault (NCF) flag
+ * corresponding to a Memory-Test-Repair (MTR) Error
+ */
+#if (ERRATA_S32_051700 == 1)
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
+{
+ uint32_t current_bit_checked, i;
+ uint32_t current_regs, mask;
+ int bit_index;
+
+ current_regs = mmio_read_32(MC_RGM_PRST(rgm, part));
+ /* Create a mask with all changed bits */
+ mask = current_regs ^ value;
+
+ while (mask != 0U) {
+ bit_index = __builtin_ffs(mask);
+ if (bit_index < 1) {
+ break;
+ }
+
+ i = (uint32_t)bit_index - 1U;
+ current_bit_checked = BIT_32(i);
+
+ /* Check if we assert or de-assert.
+ * Also wait for completion.
+ */
+ if ((value & current_bit_checked) != 0U) {
+ mmio_setbits_32(MC_RGM_PRST(rgm, part),
+ current_bit_checked);
+ while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
+ current_bit_checked) == 0U)
+ ;
+ } else {
+ mmio_clrbits_32(MC_RGM_PRST(rgm, part),
+ current_bit_checked);
+ while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
+ current_bit_checked) != 0U)
+ ;
+ }
+
+ mask &= ~current_bit_checked;
+ }
+}
+#else /* ERRATA_S32_051700 */
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
+{
+ mmio_write_32(MC_RGM_PRST(rgm, part), value);
+}
+#endif /* ERRATA_S32_051700 */
+
+void mc_rgm_release_part(uintptr_t rgm, uint32_t part)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(MC_RGM_PRST(rgm, part));
+ reg &= ~MC_RGM_PRST_PERIPH_N_RST(0);
+ mc_rgm_periph_reset(rgm, part, reg);
+}
+
+void mc_rgm_wait_part_deassert(uintptr_t rgm, uint32_t part)
+{
+ while ((mmio_read_32(MC_RGM_PSTAT(rgm, part)) &
+ MC_RGM_PSTAT_PERIPH(0)) != 0U) {
+ }
+}
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
index 7a65ea6..602179e 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk.mk
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -9,6 +9,8 @@
-I${PLAT_DRIVERS_PATH}/clk/s32cc/include \
CLK_SOURCES := \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_rgm.c \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_me.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_modules.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_utils.c \
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index fed16a7..9b57607 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -4,17 +4,16 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
-
-#include <s32cc-clk-regs.h>
-
#include <common/debug.h>
#include <drivers/clk.h>
#include <lib/mmio.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-modules.h>
+#include <s32cc-clk-regs.h>
#include <s32cc-clk-utils.h>
+#include <s32cc-mc-me.h>
-#define MAX_STACK_DEPTH (15U)
+#define MAX_STACK_DEPTH (40U)
/* This is used for floating-point precision calculations. */
#define FP_PRECISION (100000000UL)
@@ -26,6 +25,11 @@
uintptr_t armdfs_base;
uintptr_t cgm0_base;
uintptr_t cgm1_base;
+ uintptr_t cgm5_base;
+ uintptr_t ddrpll_base;
+ uintptr_t mc_me;
+ uintptr_t mc_rgm;
+ uintptr_t rdc;
};
static int update_stack_depth(unsigned int *depth)
@@ -47,38 +51,33 @@
.armdfs_base = ARM_DFS_BASE_ADDR,
.cgm0_base = CGM0_BASE_ADDR,
.cgm1_base = CGM1_BASE_ADDR,
+ .cgm5_base = MC_CGM5_BASE_ADDR,
+ .ddrpll_base = DDRPLL_BASE_ADDR,
+ .mc_me = MC_ME_BASE_ADDR,
+ .mc_rgm = MC_RGM_BASE_ADDR,
+ .rdc = RDC_BASE_ADDR,
};
return &driver;
}
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth);
+static int enable_module(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
-static int enable_clk_module(const struct s32cc_clk_obj *module,
- const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module)
{
const struct s32cc_clk *clk = s32cc_obj2clk(module);
- int ret;
-
- ret = update_stack_depth(depth);
- if (ret != 0) {
- return ret;
- }
-
- if (clk == NULL) {
- return -EINVAL;
- }
if (clk->module != NULL) {
- return enable_module(clk->module, depth);
+ return clk->module;
}
if (clk->pclock != NULL) {
- return enable_clk_module(&clk->pclock->desc, drv, depth);
+ return &clk->pclock->desc;
}
- return -EINVAL;
+ return NULL;
}
static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
@@ -96,6 +95,9 @@
case S32CC_PERIPH_PLL:
*base = drv->periphpll_base;
break;
+ case S32CC_DDR_PLL:
+ *base = drv->ddrpll_base;
+ break;
case S32CC_ARM_DFS:
*base = drv->armdfs_base;
break;
@@ -105,6 +107,9 @@
case S32CC_CGM1:
*base = drv->cgm1_base;
break;
+ case S32CC_CGM5:
+ *base = drv->cgm5_base;
+ break;
case S32CC_FIRC:
break;
case S32CC_SIRC:
@@ -145,14 +150,15 @@
}
}
-static int enable_osc(const struct s32cc_clk_obj *module,
+static int enable_osc(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_osc *osc = s32cc_obj2osc(module);
+ unsigned int ldepth = depth;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -175,6 +181,17 @@
return ret;
}
+static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_pll *pll = s32cc_obj2pll(module);
+
+ if (pll->source == NULL) {
+ ERROR("Failed to identify PLL's parent\n");
+ }
+
+ return pll->source;
+}
+
static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq,
uint32_t *mfi, uint32_t *mfn)
@@ -313,18 +330,19 @@
return ret;
}
-static int enable_pll(const struct s32cc_clk_obj *module,
+static int enable_pll(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_pll *pll = s32cc_obj2pll(module);
const struct s32cc_clkmux *mux;
uintptr_t pll_addr = UL(0x0);
+ unsigned int ldepth = depth;
unsigned long sclk_freq;
uint32_t sclk_id;
int ret;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -403,17 +421,29 @@
enable_odiv(pll_addr, div_index);
}
-static int enable_pll_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+
+ if (pdiv->parent == NULL) {
+ ERROR("Failed to identify PLL DIV's parent\n");
+ }
+
+ return pdiv->parent;
+}
+
+static int enable_pll_div(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
uintptr_t pll_addr = 0x0ULL;
+ unsigned int ldepth = depth;
const struct s32cc_pll *pll;
uint32_t dc;
int ret;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -526,15 +556,35 @@
mux_hw_clk, false);
}
+static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ struct s32cc_clk *clk;
+
+ if (mux == NULL) {
+ return NULL;
+ }
+
+ clk = s32cc_get_arch_clk(mux->source_id);
+ if (clk == NULL) {
+ ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n",
+ mux->source_id, mux->index);
+ return NULL;
+ }
+
+ return &clk->desc;
+}
+
-static int enable_mux(const struct s32cc_clk_obj *module,
+static int enable_mux(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ unsigned int ldepth = depth;
const struct s32cc_clk *clk;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -553,6 +603,8 @@
switch (mux->module) {
/* PLL mux will be enabled by PLL setup */
case S32CC_ARM_PLL:
+ case S32CC_PERIPH_PLL:
+ case S32CC_DDR_PLL:
break;
case S32CC_CGM1:
ret = enable_cgm_mux(mux, drv);
@@ -560,6 +612,9 @@
case S32CC_CGM0:
ret = enable_cgm_mux(mux, drv);
break;
+ case S32CC_CGM5:
+ ret = enable_cgm_mux(mux, drv);
+ break;
default:
ERROR("Unknown mux parent type: %d\n", mux->module);
ret = -EINVAL;
@@ -569,13 +624,25 @@
return ret;
}
-static int enable_dfs(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_dfs *dfs = s32cc_obj2dfs(module);
+
+ if (dfs->parent == NULL) {
+ ERROR("Failed to identify DFS's parent\n");
+ }
+
+ return dfs->parent;
+}
+
+static int enable_dfs(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
+ unsigned int ldepth = depth;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -722,18 +789,31 @@
return 0;
}
+static struct s32cc_clk_obj *
+get_dfs_div_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+
+ if (dfs_div->parent == NULL) {
+ ERROR("Failed to identify DFS divider's parent\n");
+ }
+
+ return dfs_div->parent;
+}
+
-static int enable_dfs_div(const struct s32cc_clk_obj *module,
+static int enable_dfs_div(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+ unsigned int ldepth = depth;
const struct s32cc_pll *pll;
const struct s32cc_dfs *dfs;
uintptr_t dfs_addr = 0UL;
uint32_t mfi, mfn;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
@@ -762,67 +842,211 @@
return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
}
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
+typedef int (*enable_clk_t)(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
+
+static int enable_part(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
{
- const struct s32cc_clk_drv *drv = get_drv();
+ const struct s32cc_part *part = s32cc_obj2part(module);
+ uint32_t part_no = part->partition_id;
+
+ if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) {
+ return -EINVAL;
+ }
+
+ return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no);
+}
+
+static int enable_part_block(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ const struct s32cc_part_block *block = s32cc_obj2partblock(module);
+ const struct s32cc_part *part = block->part;
+ uint32_t part_no = part->partition_id;
+ unsigned int ldepth = depth;
+ uint32_t cofb;
+ int ret;
+
+ ret = update_stack_depth(&ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if ((block->block >= s32cc_part_block0) &&
+ (block->block <= s32cc_part_block15)) {
+ cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0;
+ mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status);
+ } else {
+ ERROR("Unknown partition block type: %d\n", block->block);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct s32cc_clk_obj *
+get_part_block_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_part_block *block = s32cc_obj2partblock(module);
+
+ return &block->part->desc;
+}
+
+static int enable_module_with_refcount(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
+
+static int enable_part_block_link(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module);
+ struct s32cc_part_block *block = link->block;
+ unsigned int ldepth = depth;
+ int ret;
+
+ ret = update_stack_depth(&ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Move the enablement algorithm to partition tree */
+ return enable_module_with_refcount(&block->desc, drv, ldepth);
+}
+
+static struct s32cc_clk_obj *
+get_part_block_link_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module);
+
+ return link->parent;
+}
+
+static int no_enable(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ return 0;
+}
+
+static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod,
+ const struct s32cc_clk_drv *drv, bool leaf_node,
+ unsigned int depth)
+{
+ unsigned int ldepth = depth;
int ret = 0;
- ret = update_stack_depth(depth);
+ if (mod == NULL) {
+ return 0;
+ }
+
+ ret = update_stack_depth(&ldepth);
if (ret != 0) {
return ret;
}
+ /* Refcount will be updated as part of the recursivity */
+ if (leaf_node) {
+ return en_cb(mod, drv, ldepth);
+ }
+
+ if (mod->refcount == 0U) {
+ ret = en_cb(mod, drv, ldepth);
+ }
+
+ if (ret == 0) {
+ mod->refcount++;
+ }
+
+ return ret;
+}
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module);
+
+static int enable_module(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ struct s32cc_clk_obj *parent = get_module_parent(module);
+ static const enable_clk_t enable_clbs[12] = {
+ [s32cc_clk_t] = no_enable,
+ [s32cc_osc_t] = enable_osc,
+ [s32cc_pll_t] = enable_pll,
+ [s32cc_pll_out_div_t] = enable_pll_div,
+ [s32cc_clkmux_t] = enable_mux,
+ [s32cc_shared_clkmux_t] = enable_mux,
+ [s32cc_dfs_t] = enable_dfs,
+ [s32cc_dfs_div_t] = enable_dfs_div,
+ [s32cc_part_t] = enable_part,
+ [s32cc_part_block_t] = enable_part_block,
+ [s32cc_part_block_link_t] = enable_part_block_link,
+ };
+ unsigned int ldepth = depth;
+ uint32_t index;
+ int ret = 0;
+
+ ret = update_stack_depth(&ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
if (drv == NULL) {
return -EINVAL;
}
- switch (module->type) {
- case s32cc_osc_t:
- ret = enable_osc(module, drv, depth);
- break;
- case s32cc_clk_t:
- ret = enable_clk_module(module, drv, depth);
- break;
- case s32cc_pll_t:
- ret = enable_pll(module, drv, depth);
- break;
- case s32cc_pll_out_div_t:
- ret = enable_pll_div(module, drv, depth);
- break;
- case s32cc_clkmux_t:
- ret = enable_mux(module, drv, depth);
- break;
- case s32cc_shared_clkmux_t:
- ret = enable_mux(module, drv, depth);
- break;
- case s32cc_fixed_div_t:
- ret = -ENOTSUP;
- break;
- case s32cc_dfs_t:
- ret = enable_dfs(module, drv, depth);
- break;
- case s32cc_dfs_div_t:
- ret = enable_dfs_div(module, drv, depth);
- break;
- default:
- ret = -EINVAL;
- break;
+ index = (uint32_t)module->type;
+
+ if (index >= ARRAY_SIZE(enable_clbs)) {
+ ERROR("Undefined module type: %d\n", module->type);
+ return -EINVAL;
}
+ if (enable_clbs[index] == NULL) {
+ ERROR("Undefined callback for the clock type: %d\n",
+ module->type);
+ return -EINVAL;
+ }
+
+ parent = get_module_parent(module);
+
+ ret = exec_cb_with_refcount(enable_module, parent, drv,
+ false, ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = exec_cb_with_refcount(enable_clbs[index], module, drv,
+ true, ldepth);
+ if (ret != 0) {
+ return ret;
+ }
+
return ret;
}
+static int enable_module_with_refcount(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ return exec_cb_with_refcount(enable_module, module, drv, false, depth);
+}
+
static int s32cc_clk_enable(unsigned long id)
{
+ const struct s32cc_clk_drv *drv = get_drv();
unsigned int depth = MAX_STACK_DEPTH;
- const struct s32cc_clk *clk;
+ struct s32cc_clk *clk;
clk = s32cc_get_arch_clk(id);
if (clk == NULL) {
return -EINVAL;
}
- return enable_module(&clk->desc, &depth);
+ return enable_module_with_refcount(&clk->desc, drv, depth);
}
static void s32cc_clk_disable(unsigned long id)
@@ -1115,9 +1339,82 @@
return ret;
}
+static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module)
+{
+ return NULL;
+}
+
+typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj);
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
+{
+ static const get_parent_clb_t parents_clbs[12] = {
+ [s32cc_clk_t] = get_clk_parent,
+ [s32cc_osc_t] = get_no_parent,
+ [s32cc_pll_t] = get_pll_parent,
+ [s32cc_pll_out_div_t] = get_pll_div_parent,
+ [s32cc_clkmux_t] = get_mux_parent,
+ [s32cc_shared_clkmux_t] = get_mux_parent,
+ [s32cc_dfs_t] = get_dfs_parent,
+ [s32cc_dfs_div_t] = get_dfs_div_parent,
+ [s32cc_part_t] = get_no_parent,
+ [s32cc_part_block_t] = get_part_block_parent,
+ [s32cc_part_block_link_t] = get_part_block_link_parent,
+ };
+ uint32_t index;
+
+ if (module == NULL) {
+ return NULL;
+ }
+
+ index = (uint32_t)module->type;
+
+ if (index >= ARRAY_SIZE(parents_clbs)) {
+ ERROR("Undefined module type: %d\n", module->type);
+ return NULL;
+ }
+
+ if (parents_clbs[index] == NULL) {
+ ERROR("Undefined parent getter for type: %d\n", module->type);
+ return NULL;
+ }
+
+ return parents_clbs[index](module);
+}
+
static int s32cc_clk_get_parent(unsigned long id)
{
- return -ENOTSUP;
+ struct s32cc_clk *parent_clk;
+ const struct s32cc_clk_obj *parent;
+ const struct s32cc_clk *clk;
+ unsigned long parent_id;
+ int ret;
+
+ clk = s32cc_get_arch_clk(id);
+ if (clk == NULL) {
+ return -EINVAL;
+ }
+
+ parent = get_module_parent(clk->module);
+ if (parent == NULL) {
+ return -EINVAL;
+ }
+
+ parent_clk = s32cc_obj2clk(parent);
+ if (parent_clk == NULL) {
+ return -EINVAL;
+ }
+
+ ret = s32cc_get_clk_id(parent_clk, &parent_id);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (parent_id > (unsigned long)INT_MAX) {
+ return -E2BIG;
+ }
+
+ return (int)parent_id;
}
static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index 45e2070..71055ab 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -10,6 +10,9 @@
#define S32CC_A53_MIN_FREQ (48UL * MHZ)
#define S32CC_A53_MAX_FREQ (1000UL * MHZ)
+/* Partitions */
+static struct s32cc_part part0 = S32CC_PART(0);
+
/* Oscillators */
static struct s32cc_osc fxosc =
S32CC_OSC_INIT(S32CC_FXOSC);
@@ -139,7 +142,40 @@
static struct s32cc_clk periph_pll_phi3_clk =
S32CC_FREQ_MODULE_CLK(periph_pll_phi3_div, 0, 133333333);
+/* DDR PLL */
+static struct s32cc_clkmux ddr_pll_mux =
+ S32CC_CLKMUX_INIT(S32CC_DDR_PLL, 0, 2,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_FXOSC, 0, 0, 0);
+static struct s32cc_clk ddr_pll_mux_clk =
+ S32CC_MODULE_CLK(ddr_pll_mux);
+static struct s32cc_pll ddrpll =
+ S32CC_PLL_INIT(ddr_pll_mux_clk, S32CC_DDR_PLL, 1);
+static struct s32cc_clk ddr_pll_vco_clk =
+ S32CC_FREQ_MODULE_CLK(ddrpll, 1300 * MHZ, 1600 * MHZ);
+
+static struct s32cc_pll_out_div ddr_pll_phi0_div =
+ S32CC_PLL_OUT_DIV_INIT(ddrpll, 0);
+static struct s32cc_clk ddr_pll_phi0_clk =
+ S32CC_FREQ_MODULE_CLK(ddr_pll_phi0_div, 0, 800 * MHZ);
+
-static struct s32cc_clk *s32cc_hw_clk_list[22] = {
+/* MC_CGM5 */
+static struct s32cc_clkmux cgm5_mux0 =
+ S32CC_SHARED_CLKMUX_INIT(S32CC_CGM5, 0, 2,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_DDR_PLL_PHI0,
+ 0, 0, 0);
+static struct s32cc_clk cgm5_mux0_clk = S32CC_MODULE_CLK(cgm5_mux0);
+
+/* DDR clock */
+static struct s32cc_part_block part0_block1 =
+ S32CC_PART_BLOCK(&part0, s32cc_part_block1);
+static struct s32cc_part_block_link ddr_block_link =
+ S32CC_PART_BLOCK_LINK(cgm5_mux0_clk, &part0_block1);
+static struct s32cc_clk ddr_clk =
+ S32CC_FREQ_MODULE_CLK(ddr_block_link, 0, 800 * MHZ);
+
+static struct s32cc_clk *s32cc_hw_clk_list[37] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
[S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
@@ -150,6 +186,8 @@
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_DFS1)] = &arm_dfs1_clk,
/* PERIPH PLL */
[S32CC_CLK_ID(S32CC_CLK_PERIPH_PLL_PHI3)] = &periph_pll_phi3_clk,
+ /* DDR PLL */
+ [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_PHI0)] = &ddr_pll_phi0_clk,
};
static struct s32cc_clk_array s32cc_hw_clocks = {
@@ -158,7 +196,7 @@
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
-static struct s32cc_clk *s32cc_arch_clk_list[18] = {
+static struct s32cc_clk *s32cc_arch_clk_list[22] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
@@ -184,6 +222,13 @@
/* Linflex */
[S32CC_CLK_ID(S32CC_CLK_LINFLEX)] = &linflex_clk,
[S32CC_CLK_ID(S32CC_CLK_LINFLEX_BAUD)] = &linflex_baud_clk,
+ /* DDR PLL */
+ [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_MUX)] = &ddr_pll_mux_clk,
+ [S32CC_CLK_ID(S32CC_CLK_DDR_PLL_VCO)] = &ddr_pll_vco_clk,
+ /* MC_CGM5 */
+ [S32CC_CLK_ID(S32CC_CLK_MC_CGM5_MUX0)] = &cgm5_mux0_clk,
+ /* DDR */
+ [S32CC_CLK_ID(S32CC_CLK_DDR)] = &ddr_clk,
};
static struct s32cc_clk_array s32cc_arch_clocks = {
@@ -192,12 +237,21 @@
.n_clks = ARRAY_SIZE(s32cc_arch_clk_list),
};
+static const struct s32cc_clk_array *s32cc_clk_table[2] = {
+ &s32cc_hw_clocks,
+ &s32cc_arch_clocks,
+};
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id)
{
- static const struct s32cc_clk_array *clk_table[2] = {
- &s32cc_hw_clocks,
- &s32cc_arch_clocks,
- };
+ return s32cc_get_clk_from_table(s32cc_clk_table,
+ ARRAY_SIZE(s32cc_clk_table),
+ id);
+}
- return s32cc_get_clk_from_table(clk_table, ARRAY_SIZE(clk_table), id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id)
+{
+ return s32cc_get_id_from_table(s32cc_clk_table,
+ ARRAY_SIZE(s32cc_clk_table),
+ clk, id);
}
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_utils.c b/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
index 14ab674..0e75054 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
@@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-utils.h>
@@ -42,3 +43,23 @@
return NULL;
}
+
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+ size_t size, const struct s32cc_clk *clk,
+ unsigned long *clk_index)
+{
+ size_t i, j;
+
+ for (i = 0; i < size; i++) {
+ for (j = 0; j < clk_arr[i]->n_clks; j++) {
+ if (clk_arr[i]->clks[j] != clk) {
+ continue;
+ }
+
+ *clk_index = S32CC_CLK(clk_arr[i]->type_mask, j);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 8c4a9e8..02b9df9 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -16,8 +16,10 @@
#define S32CC_XBAR_2X_FREQ (800U * MHZ)
#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
+#define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
+#define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
-static int enable_fxosc_clk(void)
+static int setup_fxosc(void)
{
int ret;
@@ -26,15 +28,10 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_FXOSC);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
-static int enable_arm_pll(void)
+static int setup_arm_pll(void)
{
int ret;
@@ -53,20 +50,10 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
- if (ret != 0) {
- return ret;
- }
-
- ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
-static int enable_periph_pll(void)
+static int setup_periph_pll(void)
{
int ret;
@@ -85,16 +72,6 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
- if (ret != 0) {
- return ret;
- }
-
- ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
@@ -164,23 +141,57 @@
return ret;
}
-int s32cc_init_early_clks(void)
+static int setup_ddr_pll(void)
{
int ret;
- s32cc_clk_register_drv();
+ ret = clk_set_parent(S32CC_CLK_DDR_PLL_MUX, S32CC_CLK_FXOSC);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_DDR_PLL_VCO, S32CC_DDR_PLL_VCO_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+static int enable_ddr_clk(void)
+{
+ int ret;
+
+ ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0);
+ if (ret != 0) {
+ return ret;
+ }
- ret = enable_fxosc_clk();
+ ret = clk_enable(S32CC_CLK_DDR);
if (ret != 0) {
return ret;
}
+ return ret;
+}
+
+int s32cc_init_early_clks(void)
+{
+ int ret;
+
+ s32cc_clk_register_drv();
+
- ret = enable_arm_pll();
+ ret = setup_fxosc();
if (ret != 0) {
return ret;
}
- ret = enable_periph_pll();
+ ret = setup_arm_pll();
if (ret != 0) {
return ret;
}
@@ -195,10 +206,25 @@
return ret;
}
+ ret = setup_periph_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
ret = enable_uart_clk();
if (ret != 0) {
return ret;
}
+ ret = setup_ddr_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = enable_ddr_clk();
+ if (ret != 0) {
+ return ret;
+ }
+
return ret;
}
diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c
index e92f980..bd49324 100644
--- a/drivers/st/crypto/stm32_hash.c
+++ b/drivers/st/crypto/stm32_hash.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <common/sha_common_macros.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_hash.h>
@@ -62,15 +63,6 @@
#define HASH_STR_NBLW_MASK GENMASK(4, 0)
#define HASH_STR_DCAL BIT(8)
-#define MD5_DIGEST_SIZE 16U
-#define SHA1_DIGEST_SIZE 20U
-#define SHA224_DIGEST_SIZE 28U
-#define SHA256_DIGEST_SIZE 32U
-#define SHA384_DIGEST_SIZE 48U
-#define SHA512_224_DIGEST_SIZE 28U
-#define SHA512_256_DIGEST_SIZE 32U
-#define SHA512_DIGEST_SIZE 64U
-
#define RESET_TIMEOUT_US_1MS 1000U
#define HASH_TIMEOUT_US 10000U
diff --git a/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr3.h b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr3.h
new file mode 100644
index 0000000..936b73c
--- /dev/null
+++ b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr3.h
@@ -0,0 +1,935 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MNPMUSRAMMSGBLOCK_DDR3_H
+#define MNPMUSRAMMSGBLOCK_DDR3_H
+
+/*
+ * DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+struct pmu_smb_ddr_1d {
+ uint8_t reserved00; /*
+ * Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ * reserved00[0:4] RFU, must be zero
+ *
+ * reserved00[5] = Train vrefDAC0 During Read Deskew
+ * 0x1 = Read Deskew will begin by enabling and roughly
+ * training the phy's per-lane reference voltages.
+ * Training the vrefDACs CSRs will increase the maximum 1D
+ * training time by around half a millisecond, but will
+ * improve 1D training accuracy on systems with
+ * significant voltage-offsets between lane read eyes.
+ * 0x0 = Read Deskew will assume the messageblock's
+ * phyVref setting will work for all lanes.
+ *
+ * reserved00[6] = Enable High Effort WrDQ1D
+ * 0x1 = WrDQ1D will conditionally retry training at
+ * several extra RxClkDly Timings. This will increase the
+ * maximum 1D training time by up to 4 extra iterations of
+ * WrDQ1D. This is only required in systems that suffer
+ * from very large, asymmetric eye-collapse when receiving
+ * PRBS patterns.
+ * 0x0 = WrDQ1D assume rxClkDly values found by SI
+ * Friendly RdDqs1D will work for receiving PRBS patterns
+ *
+ * reserved00[7] = Optimize for the special hard macros in
+ * TSMC28.
+ * 0x1 = set if the phy being trained was manufactured in
+ * any TSMC28 process node.
+ * 0x0 = otherwise, when not training a TSMC28 phy, leave
+ * this field as 0.
+ */
+ uint8_t msgmisc; /*
+ * Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ * Contains various global options for training.
+ *
+ * Bit fields:
+ *
+ * msgmisc[0] = MTESTEnable
+ * 0x1 = Pulse primary digital test output bump at the end
+ * of each major training stage. This enables observation
+ * of training stage completion by observing the digital
+ * test output.
+ * 0x0 = Do not pulse primary digital test output bump
+ *
+ * msgmisc[1] = SimulationOnlyReset
+ * 0x1 = Verilog only simulation option to shorten
+ * duration of DRAM reset pulse length to 1ns.
+ * Must never be set to 1 in silicon.
+ * 0x0 = Use reset pulse length specified by JEDEC
+ * standard.
+ *
+ * msgmisc[2] = SimulationOnlyTraining
+ * 0x1 = Verilog only simulation option to shorten the
+ * duration of the training steps by performing fewer
+ * iterations.
+ * Must never be set to 1 in silicon.
+ * 0x0 = Use standard training duration.
+ *
+ * msgmisc[3] = RFU, must be zero
+ *
+ * msgmisc[4] = Suppress streaming messages, including
+ * assertions, regardless of hdtctrl setting.
+ * Stage Completion messages, as well as training completion
+ * and error messages are still sent depending on hdtctrl
+ * setting.
+ *
+ * msgmisc[5] = PerByteMaxRdLat
+ * 0x1 = Each DBYTE will return dfi_rddata_valid at the
+ * lowest possible latency. This may result in unaligned
+ * data between bytes to be returned to the DFI.
+ * 0x0 = Every DBYTE will return dfi_rddata_valid
+ * simultaneously. This will ensure that data bytes will
+ * return aligned accesses to the DFI.
+ *
+ * msgmisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only,
+ * otherwise RFU, must be zero)
+ * 0x1 = Support rank populated with a subset of byte, but
+ * where even-odd pair of rank support all the byte
+ * 0x0 = All rank populated with all the byte (tyical
+ * configuration)
+ *
+ * msgmisc[7] RFU, must be zero
+ *
+ * Notes:
+ *
+ * - SimulationOnlyReset and SimulationOnlyTraining can be
+ * used to speed up simulation run times, and must never
+ * be used in real silicon. Some VIPs may have checks on
+ * DRAM reset parameters that may need to be disabled when
+ * using SimulationOnlyReset.
+ */
+ uint16_t pmurevision; /*
+ * Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ * PMU firmware revision ID
+ * After training is run, this address will contain the
+ * revision ID of the firmware.
+ * Please reference this revision ID when filing support
+ * cases.
+ */
+ uint8_t pstate; /*
+ * Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ * Must be set to the target pstate to be trained
+ * 0x0 = pstate 0
+ * 0x1 = pstate 1
+ * 0x2 = pstate 2
+ * 0x3 = pstate 3
+ * All other encodings are reserved
+ */
+ uint8_t pllbypassen; /*
+ * Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ * Set according to whether target pstate uses PHY PLL
+ * bypass
+ * 0x0 = PHY PLL is enabled for target pstate
+ * 0x1 = PHY PLL is bypassed for target pstate
+ */
+ uint16_t dramfreq; /*
+ * Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ * DDR data rate for the target pstate in units of MT/s.
+ * For example enter 0x0640 for DDR1600.
+ */
+ uint8_t dfifreqratio; /*
+ * Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ * Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ * 0x1 = 1:1
+ * 0x2 = 1:2
+ * 0x4 = 1:4
+ */
+ uint8_t bpznresval; /*
+ * Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ * Overwrite the value of precision resistor connected to
+ * Phy BP_ZN
+ * 0x00 = Do not program. Use current CSR value.
+ * 0xf0 = 240 Ohm
+ * 0x78 = 120 Ohm
+ * 0x28 = 40 Ohm
+ * All other values are reserved.
+ * It is recommended to set this to 0x00.
+ */
+ uint8_t phyodtimpedance; /*
+ * Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ * Must be programmed to the termination impedance in ohms
+ * used by PHY during reads.
+ *
+ * 0x0 = Firmware skips programming (must be manually
+ * programmed by user prior to training start)
+ *
+ * See PHY databook for legal termination impedance values.
+ *
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must determine the correct value
+ * through SI simulation or other methods.
+ */
+ uint8_t phydrvimpedance; /*
+ * Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ * Must be programmed to the driver impedance in ohms used
+ * by PHY during writes for all DBYTE drivers
+ * (DQ/DM/DBI/DQS).
+ *
+ * 0x0 = Firmware skips programming (must be manually
+ * programmed by user prior to training start)
+ *
+ * See PHY databook for legal R_on driver impedance values.
+ *
+ * For digital simulation, any value can be used that is not
+ * Hi-Z. For silicon, the users must determine the correct
+ * value through SI simulation or other methods.
+ */
+ uint8_t phyvref; /*
+ * Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ * Must be programmed with the Vref level to be used by the
+ * PHY during reads
+ *
+ * The units of this field are a percentage of VDDQ
+ * according to the following equation:
+ *
+ * Receiver Vref = VDDQ*phyvref[6:0]/128
+ *
+ * For example to set Vref at 0.75*VDDQ, set this field to
+ * 0x60.
+ *
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must calculate the analytical Vref by
+ * using the impedances, terminations, and series resistance
+ * present in the system.
+ */
+ uint8_t dramtype; /*
+ * Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ * Module Type:
+ * 0x01 = DDR3 unbuffered
+ * 0x02 = Reserved
+ * 0x03 = Reserved
+ * 0x04 = Reserved
+ * 0x05 = Reserved
+ */
+ uint8_t disableddbyte; /*
+ * Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ * Bitmap to indicate which Dbyte are not connected (for
+ * DByte 0 to 7):
+ * Set disableddbyte[i] to 1 only to specify that DByte is
+ * not need to be trained (DByte 8 can be disabled via
+ * enableddqs setting)
+ */
+ uint8_t enableddqs; /*
+ * Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ * Total number of DQ bits enabled in PHY
+ */
+ uint8_t cspresent; /*
+ * Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ * Indicates presence of DRAM at each chip select for PHY.
+ * Each bit corresponds to a logical CS.
+ *
+ * If the bit is set to 1, the CS is connected to DRAM.
+ * If the bit is set to 0, the CS is not connected to DRAM.
+ *
+ * cspresent[0] = CS0 is populated with DRAM
+ * cspresent[1] = CS1 is populated with DRAM
+ * cspresent[2] = CS2 is populated with DRAM
+ * cspresent[3] = CS3 is populated with DRAM
+ * cspresent[7:4] = Reserved (must be programmed to 0)
+ */
+ uint8_t cspresentd0; /*
+ * Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ * The CS signals from field cspresent that are routed to
+ * DIMM connector 0
+ */
+ uint8_t cspresentd1; /*
+ * Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ * The CS signals from field cspresent that are routed to
+ * DIMM connector 1
+ */
+ uint8_t addrmirror; /*
+ * Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ * Corresponds to CS[3:0]
+ * 1 = Address Mirror.
+ * 0 = No Address Mirror.
+ */
+ uint8_t cstestfail; /*
+ * Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ * This field will be set if training fails on any rank.
+ * 0x0 = No failures
+ * non-zero = one or more ranks failed training
+ */
+ uint8_t phycfg; /*
+ * Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ * Additional mode bits.
+ *
+ * Bit fields:
+ * [0] SlowAccessMode:
+ * 1 = 2T Address Timing.
+ * 0 = 1T Address Timing.
+ * [7-1] RFU, must be zero
+ *
+ * WARNING: In case of DDR4 Geardown Mode (mr3[A3] == 1),
+ * phycfg[0] must be 0.
+ */
+ uint16_t sequencectrl; /*
+ * Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ * Controls the training steps to be run. Each bit
+ * corresponds to a training step.
+ *
+ * If the bit is set to 1, the training step will run.
+ * If the bit is set to 0, the training step will be
+ * skipped.
+ *
+ * Training step to bit mapping:
+ * sequencectrl[0] = Run DevInit - Device/phy
+ * initialization. Should always be set.
+ * sequencectrl[1] = Run WrLvl - Write leveling
+ * sequencectrl[2] = Run RxEn - Read gate training
+ * sequencectrl[3] = Run RdDQS1D - 1d read dqs training
+ * sequencectrl[4] = Run WrDQ1D - 1d write dq training
+ * sequencectrl[5] = RFU, must be zero
+ * sequencectrl[6] = RFU, must be zero
+ * sequencectrl[7] = RFU, must be zero
+ * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew
+ * training
+ * sequencectrl[9] = Run MxRdLat - Max read latency training
+ * sequencectrl[10] = RFU, must be zero
+ * sequencectrl[11] = RFU, must be zero
+ * sequencectrl[12] = RFU, must be zero
+ * sequencectrl[13] = RFU, must be zero
+ * sequencectrl[15-14] = RFU, must be zero
+ */
+ uint8_t hdtctrl; /*
+ * Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ * To control the total number of debug messages, a
+ * verbosity subfield (hdtctrl, Hardware Debug Trace
+ * Control) exists in the message block. Every message has a
+ * verbosity level associated with it, and as the hdtctrl
+ * value is increased, less important s messages stop being
+ * sent through the mailboxes. The meanings of several major
+ * hdtctrl thresholds are explained below:
+ *
+ * 0x04 = Maximal debug messages (e.g., Eye contours)
+ * 0x05 = Detailed debug messages (e.g. Eye delays)
+ * 0x0A = Coarse debug messages (e.g. rank information)
+ * 0xC8 = Stage completion
+ * 0xC9 = Assertion messages
+ * 0xFF = Firmware completion messages only
+ */
+ uint8_t reserved19; /* Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A */
+ uint8_t reserved1a; /* Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A */
+ uint8_t share2dvrefresult; /*
+ * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ * Bitmap that designates the phy's vref source for every
+ * pstate
+ * If share2dvrefresult[x] = 0, then after 2D training,
+ * pstate x will continue using the phyVref provided in
+ * pstate x's 1D messageblock.
+ * If share2dvrefresult[x] = 1, then after 2D training,
+ * pstate x will use the per-lane VrefDAC0/1 CSRs trained by
+ * 2d training.
+ */
+ uint8_t reserved1c; /* Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A */
+ uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */
+ uint8_t reserved1e; /*
+ * Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ * Input for constraining the range of vref(DQ) values
+ * training will collect data for, usually reducing training
+ * time. However, too large of a voltage range may cause
+ * longer 2D training times while too small of a voltage
+ * range may truncate passing regions. When in doubt, leave
+ * this field set to 0.
+ * Used by 2D training in: Rd2D, Wr2D
+ *
+ * reserved1E[0-3]: Rd2D Voltage Range
+ * 0 = Training will search all phy vref(DQ) settings
+ * 1 = limit to +/-2 %VDDQ from phyVref
+ * 2 = limit to +/-4 %VDDQ from phyVref
+ * . . .
+ * 15 = limit to +/-30% VDDQ from phyVref
+ *
+ * reserved1E[4-7]: Wr2D Voltage Range
+ * 0 = Training will search all dram vref(DQ) settings
+ * 1 = limit to +/-2 %VDDQ from mr6
+ * 2 = limit to +/-4 %VDDQ from mr6
+ * . . .
+ * 15 = limit to +/-30% VDDQ from mr6
+ */
+ uint8_t reserved1f; /*
+ * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ * Extended training option:
+ *
+ * reserved1F[1:0]: Configured RxClkDly offset try during
+ * WrDq1D high-effort (i.e., when reserved00[6] is set)
+ * 0: -8, +8, -16, +16
+ * 1: -4, +4, -8, +8, -12, +12, -16, +16
+ * 2: -2, +2, -4, +4, -6, +6, -8, +8
+ * 3: -2, +2, -4, +4, -6, +6, -8, +8, -10, +10, -12, +12,
+ * -14, +14, -16, +16
+ *
+ * reserved1F[2]: When set, execute again WrDq1D after
+ * RdDqs1D PRBS
+ *
+ * reserved1F[3]: When set redo RdDeskew with PRBS after
+ * (first) WrDqs1D
+ *
+ * reserved1F[7:4]: This field is reserved and must be
+ * programmed to 0x00.
+ */
+ uint8_t reserved20; /*
+ * Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ * This field is reserved and must be programmed to 0x00,
+ * excepted for Reserved:
+ * Reserved MREP assume raising edge is found when
+ * reserved20[3:0]+3 consecutive 1 are received during MREP
+ * fine delay swept; reserved20[6:0] thus permits to
+ * increase tolerance for noisy system. And if reserved20[7]
+ * is set, MREP training is failing if no raising edge is
+ * found (otherwise the raising edge is assume close to
+ * delay 0).
+ */
+ uint8_t reserved21; /*
+ * Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ * This field is reserved and must be programmed to 0x00,
+ * excepted for Reserved:
+ * Reserved DWL assume raising edge is found when
+ * reserved21[3:0]+3 consecutive 1 are received during DWL
+ * fine delay swept; reserved21[6:0] thus permits to
+ * increase tolerance for noisy system. And if reserved21[7]
+ * is set, DWL training is failing if no raising edge is
+ * found (otherwise the raising edge is assume close to
+ * delay 0).
+ */
+ uint16_t phyconfigoverride; /*
+ * Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ * Override PhyConfig csr.
+ * 0x0: Use hardware csr value for PhyConfing
+ * (recommended)
+ * Other values: Use value for PhyConfig instead of
+ * Hardware value.
+ */
+ uint8_t dfimrlmargin; /*
+ * Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ * Margin added to smallest passing trained DFI Max Read
+ * Latency value, in units of DFI clocks. Recommended to be
+ * >= 1.
+ */
+ int8_t cdd_rr_3_2; /*
+ * Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 3 to cs 2.
+ */
+ int8_t cdd_rr_3_1; /*
+ * Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 3 to cs 1.
+ */
+ int8_t cdd_rr_3_0; /*
+ * Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 3 to cs 0.
+ */
+ int8_t cdd_rr_2_3; /*
+ * Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 2 to cs 3.
+ */
+ int8_t cdd_rr_2_1; /*
+ * Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 2 to cs 1.
+ */
+ int8_t cdd_rr_2_0; /*
+ * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 2 to cs 0.
+ */
+ int8_t cdd_rr_1_3; /*
+ * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 3.
+ */
+ int8_t cdd_rr_1_2; /*
+ * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 2.
+ */
+ int8_t cdd_rr_1_0; /*
+ * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 0.
+ */
+ int8_t cdd_rr_0_3; /*
+ * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 3.
+ */
+ int8_t cdd_rr_0_2; /*
+ * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 2.
+ */
+ int8_t cdd_rr_0_1; /*
+ * Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 1.
+ */
+ int8_t cdd_ww_3_2; /*
+ * Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 3 to cs
+ * 2.
+ */
+ int8_t cdd_ww_3_1; /*
+ * Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 3 to cs
+ * 1.
+ */
+ int8_t cdd_ww_3_0; /*
+ * Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 3 to cs
+ * 0.
+ */
+ int8_t cdd_ww_2_3; /*
+ * Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 2 to cs
+ * 3.
+ */
+ int8_t cdd_ww_2_1; /*
+ * Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 2 to cs
+ * 1.
+ */
+ int8_t cdd_ww_2_0; /*
+ * Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 2 to cs
+ * 0.
+ */
+ int8_t cdd_ww_1_3; /*
+ * Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 3.
+ */
+ int8_t cdd_ww_1_2; /*
+ * Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 2.
+ */
+ int8_t cdd_ww_1_0; /*
+ * Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 0.
+ */
+ int8_t cdd_ww_0_3; /*
+ * Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 3.
+ */
+ int8_t cdd_ww_0_2; /*
+ * Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 2.
+ */
+ int8_t cdd_ww_0_1; /*
+ * Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 1.
+ */
+ int8_t cdd_rw_3_3; /*
+ * Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 3.
+ */
+ int8_t cdd_rw_3_2; /*
+ * Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 2.
+ */
+ int8_t cdd_rw_3_1; /*
+ * Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 1.
+ */
+ int8_t cdd_rw_3_0; /*
+ * Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 0.
+ */
+ int8_t cdd_rw_2_3; /*
+ * Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 3.
+ */
+ int8_t cdd_rw_2_2; /*
+ * Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 2.
+ */
+ int8_t cdd_rw_2_1; /*
+ * Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 1.
+ */
+ int8_t cdd_rw_2_0; /*
+ * Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 0.
+ */
+ int8_t cdd_rw_1_3; /*
+ * Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 3.
+ */
+ int8_t cdd_rw_1_2; /*
+ * Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 2.
+ */
+ int8_t cdd_rw_1_1; /*
+ * Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 1.
+ */
+ int8_t cdd_rw_1_0; /*
+ * Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 0.
+ */
+ int8_t cdd_rw_0_3; /*
+ * Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 3.
+ */
+ int8_t cdd_rw_0_2; /*
+ * Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 2.
+ */
+ int8_t cdd_rw_0_1; /*
+ * Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 1.
+ */
+ int8_t cdd_rw_0_0; /*
+ * Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 0.
+ */
+ int8_t cdd_wr_3_3; /*
+ * Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 3.
+ */
+ int8_t cdd_wr_3_2; /*
+ * Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 2.
+ */
+ int8_t cdd_wr_3_1; /*
+ * Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 1.
+ */
+ int8_t cdd_wr_3_0; /*
+ * Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 0.
+ */
+ int8_t cdd_wr_2_3; /*
+ * Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 3.
+ */
+ int8_t cdd_wr_2_2; /*
+ * Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 2.
+ */
+ int8_t cdd_wr_2_1; /*
+ * Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 1.
+ */
+ int8_t cdd_wr_2_0; /*
+ * Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 0.
+ */
+ int8_t cdd_wr_1_3; /*
+ * Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 3.
+ */
+ int8_t cdd_wr_1_2; /*
+ * Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 2.
+ */
+ int8_t cdd_wr_1_1; /*
+ * Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 1.
+ */
+ int8_t cdd_wr_1_0; /*
+ * Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 0.
+ */
+ int8_t cdd_wr_0_3; /*
+ * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 3.
+ */
+ int8_t cdd_wr_0_2; /*
+ * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 2.
+ */
+ int8_t cdd_wr_0_1; /*
+ * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 1.
+ */
+ int8_t cdd_wr_0_0; /*
+ * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 0.
+ */
+ uint8_t reserved5d; /*
+ * Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ * This field is reserved and must be programmed to 0x00,
+ * excepted for DDR4:
+ * By default, if this parameter is 0, the offset applied at
+ * the end of DDR4 RxEn training resulting in the trained
+ * RxEnDly is 3/8 of the RX preamble width; if reserved5D is
+ * non zero, this offset is used instead (in fine step).
+ */
+ uint16_t mr0; /*
+ * Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ * Value of DDR mode register mr0 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr1; /*
+ * Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ * Value of DDR mode register mr1 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr2; /*
+ * Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ * Value of DDR mode register mr2 for all ranks for current
+ * pstate.
+ */
+ uint8_t reserved64; /*
+ * Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ * Reserved64[0] = protect memory reset
+ * 0x0 = dfi_reset_n cannot control CP_MEMRESET_L to
+ * devices after training. (Default value)
+ * 0x1 = dfi_reset_n can control CP_MEMRESET_L to
+ * devices after training.
+ *
+ * Reserved64[7:1] RFU, must be zero
+ */
+ uint8_t reserved65; /*
+ * Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved66; /*
+ * Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved67; /*
+ * Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved68; /*
+ * Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved69; /*
+ * Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved6a; /*
+ * Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved6b; /*
+ * Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved6c; /*
+ * Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved6d; /*
+ * Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved6e; /*
+ * Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved6f; /*
+ * Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved70; /*
+ * Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved71; /*
+ * Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved72; /*
+ * Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved73; /*
+ * Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t acsmodtctrl0; /*
+ * Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ * Odt pattern for accesses targeting rank 0. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl1; /*
+ * Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ * Odt pattern for accesses targeting rank 1. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl2; /*
+ * Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ * Odt pattern for accesses targeting rank 2. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl3; /*
+ * Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ * Odt pattern for accesses targeting rank 3. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl4; /*
+ * Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t acsmodtctrl5; /*
+ * Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t acsmodtctrl6; /*
+ * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t acsmodtctrl7; /*
+ * Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved7c; /*
+ * Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved7d; /*
+ * Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved7e; /*
+ * Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved7f; /*
+ * Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved80; /*
+ * Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved81; /*
+ * Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved82; /*
+ * Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved83; /*
+ * Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ * This field is reserved and must be programmed to 0x00.
+ */
+ uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */
+ uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */
+ uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */
+ uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */
+ uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */
+ uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */
+ uint8_t reserved8a; /* Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A */
+ uint8_t reserved8b; /* Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A */
+ uint8_t reserved8c; /* Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A */
+ uint8_t reserved8d; /* Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A */
+ uint8_t reserved8e; /* Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A */
+ uint8_t reserved8f; /* Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A */
+ uint8_t reserved90; /* Byte offset 0x90, CSR Addr 0x54048, Direction=N/A */
+ uint8_t reserved91; /* Byte offset 0x91, CSR Addr 0x54048, Direction=N/A */
+ uint8_t reserved92; /* Byte offset 0x92, CSR Addr 0x54049, Direction=N/A */
+ uint8_t reserved93; /* Byte offset 0x93, CSR Addr 0x54049, Direction=N/A */
+ uint8_t reserved94; /* Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A */
+ uint8_t reserved95; /* Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A */
+ uint8_t reserved96; /* Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A */
+ uint8_t reserved97; /* Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A */
+ uint8_t reserved98; /* Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A */
+ uint8_t reserved99; /* Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A */
+ uint8_t reserved9a; /* Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A */
+ uint8_t reserved9b; /* Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A */
+ uint8_t reserved9c; /* Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A */
+ uint8_t reserved9d; /* Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A */
+ uint8_t reserved9e; /* Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A */
+ uint8_t reserved9f; /* Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A */
+ uint8_t reserveda0; /* Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A */
+ uint8_t reserveda1; /* Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A */
+ uint8_t reserveda2; /* Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A */
+ uint8_t reserveda3; /* Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A */
+} __packed __aligned(2);
+
+#endif /* MNPMUSRAMMSGBLOCK_DDR3_H */
diff --git a/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr4.h b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr4.h
new file mode 100644
index 0000000..384650e
--- /dev/null
+++ b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr4.h
@@ -0,0 +1,2203 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MNPMUSRAMMSGBLOCK_DDR4_H
+#define MNPMUSRAMMSGBLOCK_DDR4_H
+
+/* DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+struct pmu_smb_ddr_1d {
+ uint8_t reserved00; /*
+ * Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ * reserved00[0:4] RFU, must be zero
+ *
+ * reserved00[5] = Train vrefDAC0 During Read Deskew
+ * 0x1 = Read Deskew will begin by enabling and roughly
+ * training the phy's per-lane reference voltages.
+ * Training the vrefDACs CSRs will increase the maximum 1D
+ * training time by around half a millisecond, but will
+ * improve 1D training accuracy on systems with
+ * significant voltage-offsets between lane read eyes.
+ * 0x0 = Read Deskew will assume the messageblock's
+ * phyVref setting will work for all lanes.
+ *
+ * reserved00[6] = Enable High Effort WrDQ1D
+ * 0x1 = WrDQ1D will conditionally retry training at
+ * several extra RxClkDly Timings. This will increase the
+ * maximum 1D training time by up to 4 extra iterations of
+ * WrDQ1D. This is only required in systems that suffer
+ * from very large, asymmetric eye-collapse when receiving
+ * PRBS patterns.
+ * 0x0 = WrDQ1D assume rxClkDly values found by SI
+ * Friendly RdDqs1D will work for receiving PRBS patterns
+ *
+ * reserved00[7] = Optimize for the special hard macros in
+ * TSMC28.
+ * 0x1 = set if the phy being trained was manufactured in
+ * any TSMC28 process node.
+ * 0x0 = otherwise, when not training a TSMC28 phy, leave
+ * this field as 0.
+ */
+ uint8_t msgmisc; /*
+ * Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ * Contains various global options for training.
+ *
+ * Bit fields:
+ *
+ * msgmisc[0] = MTESTEnable
+ * 0x1 = Pulse primary digital test output bump at the end
+ * of each major training stage. This enables observation
+ * of training stage completion by observing the digital
+ * test output.
+ * 0x0 = Do not pulse primary digital test output bump
+ *
+ * msgmisc[1] = SimulationOnlyReset
+ * 0x1 = Verilog only simulation option to shorten
+ * duration of DRAM reset pulse length to 1ns.
+ * Must never be set to 1 in silicon.
+ * 0x0 = Use reset pulse length specified by JEDEC
+ * standard.
+ *
+ * msgmisc[2] = SimulationOnlyTraining
+ * 0x1 = Verilog only simulation option to shorten the
+ * duration of the training steps by performing fewer
+ * iterations.
+ * Must never be set to 1 in silicon.
+ * 0x0 = Use standard training duration.
+ *
+ * msgmisc[3] = RFU, must be zero
+ * 0x1 = Program user characterized Vref DQ values per
+ * DDR4 DRAM device. The message block vrefdqr*nib* fields
+ * must be populated with the desired per device Vref DQs
+ * when using this option. Note: this option is not
+ * applicable in 2D training because these values are
+ * explicitly trained in 2D.
+ * 0x0 = Program Vref DQ for all DDR4 devices with the
+ * single value provided in mr6 message block field
+ *
+ * msgmisc[4] = Suppress streaming messages, including
+ * assertions, regardless of hdtctrl setting.
+ * Stage Completion messages, as well as training completion
+ * and error messages are still sent depending on hdtctrl
+ * setting.
+ *
+ * msgmisc[5] = PerByteMaxRdLat
+ * 0x1 = Each DBYTE will return dfi_rddata_valid at the
+ * lowest possible latency. This may result in unaligned
+ * data between bytes to be returned to the DFI.
+ * 0x0 = Every DBYTE will return dfi_rddata_valid
+ * simultaneously. This will ensure that data bytes will
+ * return aligned accesses to the DFI.
+ *
+ * msgmisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only,
+ * otherwise RFU, must be zero)
+ * 0x1 = Support rank populated with a subset of byte, but
+ * where even-odd pair of rank support all the byte
+ * 0x0 = All rank populated with all the byte (tyical
+ * configuration)
+ *
+ * msgmisc[7] RFU, must be zero
+ *
+ * Notes:
+ *
+ * - SimulationOnlyReset and SimulationOnlyTraining can be
+ * used to speed up simulation run times, and must never
+ * be used in real silicon. Some VIPs may have checks on
+ * DRAM reset parameters that may need to be disabled when
+ * using SimulationOnlyReset.
+ */
+ uint16_t pmurevision; /*
+ * Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ * PMU firmware revision ID
+ * After training is run, this address will contain the
+ * revision ID of the firmware.
+ * Please reference this revision ID when filing support
+ * cases.
+ */
+ uint8_t pstate; /*
+ * Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ * Must be set to the target pstate to be trained
+ * 0x0 = pstate 0
+ * 0x1 = pstate 1
+ * 0x2 = pstate 2
+ * 0x3 = pstate 3
+ * All other encodings are reserved
+ */
+ uint8_t pllbypassen; /*
+ * Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ * Set according to whether target pstate uses PHY PLL
+ * bypass
+ * 0x0 = PHY PLL is enabled for target pstate
+ * 0x1 = PHY PLL is bypassed for target pstate
+ */
+ uint16_t dramfreq; /*
+ * Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ * DDR data rate for the target pstate in units of MT/s.
+ * For example enter 0x0640 for DDR1600.
+ */
+ uint8_t dfifreqratio; /*
+ * Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ * Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ * 0x1 = 1:1
+ * 0x2 = 1:2
+ * 0x4 = 1:4
+ */
+ uint8_t bpznresval; /*
+ * Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ * Overwrite the value of precision resistor connected to
+ * Phy BP_ZN
+ * 0x00 = Do not program. Use current CSR value.
+ * 0xf0 = 240 Ohm
+ * 0x78 = 120 Ohm
+ * 0x28 = 40 Ohm
+ * All other values are reserved.
+ * It is recommended to set this to 0x00.
+ */
+ uint8_t phyodtimpedance; /*
+ * Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ * Must be programmed to the termination impedance in ohms
+ * used by PHY during reads.
+ *
+ * 0x0 = Firmware skips programming (must be manually
+ * programmed by user prior to training start)
+ *
+ * See PHY databook for legal termination impedance values.
+ *
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must determine the correct value
+ * through SI simulation or other methods.
+ */
+ uint8_t phydrvimpedance; /*
+ * Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ * Must be programmed to the driver impedance in ohms used
+ * by PHY during writes for all DBYTE drivers
+ * (DQ/DM/DBI/DQS).
+ *
+ * 0x0 = Firmware skips programming (must be manually
+ * programmed by user prior to training start)
+ *
+ * See PHY databook for legal R_on driver impedance values.
+ *
+ * For digital simulation, any value can be used that is not
+ * Hi-Z. For silicon, the users must determine the correct
+ * value through SI simulation or other methods.
+ */
+ uint8_t phyvref; /*
+ * Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ * Must be programmed with the Vref level to be used by the
+ * PHY during reads
+ *
+ * The units of this field are a percentage of VDDQ
+ * according to the following equation:
+ *
+ * Receiver Vref = VDDQ*phyvref[6:0]/128
+ *
+ * For example to set Vref at 0.75*VDDQ, set this field to
+ * 0x60.
+ *
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must calculate the analytical Vref by
+ * using the impedances, terminations, and series resistance
+ * present in the system.
+ */
+ uint8_t dramtype; /*
+ * Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ * Module Type:
+ * 0x01 = Reserved
+ * 0x02 = DDR4 unbuffered
+ * 0x03 = Reserved
+ * 0x04 = Reserved
+ * 0x05 = Reserved
+ */
+ uint8_t disableddbyte; /*
+ * Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ * Bitmap to indicate which Dbyte are not connected (for
+ * DByte 0 to 7):
+ * Set disableddbyte[i] to 1 only to specify that DByte is
+ * not need to be trained (DByte 8 can be disabled via
+ * enableddqs setting)
+ */
+ uint8_t enableddqs; /*
+ * Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ * Total number of DQ bits enabled in PHY
+ */
+ uint8_t cspresent; /*
+ * Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ * Indicates presence of DRAM at each chip select for PHY.
+ * Each bit corresponds to a logical CS.
+ *
+ * If the bit is set to 1, the CS is connected to DRAM.
+ * If the bit is set to 0, the CS is not connected to DRAM.
+ *
+ * cspresent[0] = CS0 is populated with DRAM
+ * cspresent[1] = CS1 is populated with DRAM
+ * cspresent[2] = CS2 is populated with DRAM
+ * cspresent[3] = CS3 is populated with DRAM
+ * cspresent[7:4] = Reserved (must be programmed to 0)
+ */
+ uint8_t cspresentd0; /*
+ * Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ * The CS signals from field cspresent that are routed to
+ * DIMM connector 0
+ */
+ uint8_t cspresentd1; /*
+ * Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ * The CS signals from field cspresent that are routed to
+ * DIMM connector 1
+ */
+ uint8_t addrmirror; /*
+ * Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ * Corresponds to CS[3:0]
+ * 1 = Address Mirror.
+ * 0 = No Address Mirror.
+ */
+ uint8_t cstestfail; /*
+ * Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ * This field will be set if training fails on any rank.
+ * 0x0 = No failures
+ * non-zero = one or more ranks failed training
+ */
+ uint8_t phycfg; /*
+ * Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ * Additional mode bits.
+ *
+ * Bit fields:
+ * [0] SlowAccessMode:
+ * 1 = 2T Address Timing.
+ * 0 = 1T Address Timing.
+ * [7-1] RFU, must be zero
+ *
+ * WARNING: In case of DDR4 Geardown Mode (mr3[A3] == 1),
+ * phycfg[0] must be 0.
+ */
+ uint16_t sequencectrl; /*
+ * Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ * Controls the training steps to be run. Each bit
+ * corresponds to a training step.
+ *
+ * If the bit is set to 1, the training step will run.
+ * If the bit is set to 0, the training step will be
+ * skipped.
+ *
+ * Training step to bit mapping:
+ * sequencectrl[0] = Run DevInit - Device/phy
+ * initialization. Should always be set.
+ * sequencectrl[1] = Run WrLvl - Write leveling
+ * sequencectrl[2] = Run RxEn - Read gate training
+ * sequencectrl[3] = Run RdDQS1D - 1d read dqs training
+ * sequencectrl[4] = Run WrDQ1D - 1d write dq training
+ * sequencectrl[5] = RFU, must be zero
+ * sequencectrl[6] = RFU, must be zero
+ * sequencectrl[7] = RFU, must be zero
+ * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew
+ * training
+ * sequencectrl[9] = Run MxRdLat - Max read latency training
+ * sequencectrl[10] = Run Reserved
+ * sequencectrl[11] = Run Reserved
+ * sequencectrl[12] = Run Reserved
+ * sequencectrl[13] = Run Reserved
+ * sequencectrl[15-14] = RFU, must be zero
+ */
+ uint8_t hdtctrl; /*
+ * Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ * To control the total number of debug messages, a
+ * verbosity subfield (hdtctrl, Hardware Debug Trace
+ * Control) exists in the message block. Every message has a
+ * verbosity level associated with it, and as the hdtctrl
+ * value is increased, less important s messages stop being
+ * sent through the mailboxes. The meanings of several major
+ * hdtctrl thresholds are explained below:
+ *
+ * 0x04 = Maximal debug messages (e.g., Eye contours)
+ * 0x05 = Detailed debug messages (e.g. Eye delays)
+ * 0x0A = Coarse debug messages (e.g. rank information)
+ * 0xC8 = Stage completion
+ * 0xC9 = Assertion messages
+ * 0xFF = Firmware completion messages only
+ */
+ uint8_t reserved19; /* Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A */
+ uint8_t reserved1a; /* Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A */
+ uint8_t share2dvrefresult; /*
+ * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ * Bitmap that designates the phy's vref source for every
+ * pstate
+ * If share2dvrefresult[x] = 0, then after 2D training,
+ * pstate x will continue using the phyVref provided in
+ * pstate x's 1D messageblock.
+ * If share2dvrefresult[x] = 1, then after 2D training,
+ * pstate x will use the per-lane VrefDAC0/1 CSRs trained by
+ * 2d training.
+ */
+ uint8_t reserved1c; /* Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A */
+ uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */
+ uint8_t reserved1e; /*
+ * Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ * Input for constraining the range of vref(DQ) values
+ * training will collect data for, usually reducing training
+ * time. However, too large of a voltage range may cause
+ * longer 2D training times while too small of a voltage
+ * range may truncate passing regions. When in doubt, leave
+ * this field set to 0.
+ * Used by 2D training in: Rd2D, Wr2D
+ *
+ * reserved1E[0-3]: Rd2D Voltage Range
+ * 0 = Training will search all phy vref(DQ) settings
+ * 1 = limit to +/-2 %VDDQ from phyVref
+ * 2 = limit to +/-4 %VDDQ from phyVref
+ * . . .
+ * 15 = limit to +/-30% VDDQ from phyVref
+ *
+ * reserved1E[4-7]: Wr2D Voltage Range
+ * 0 = Training will search all dram vref(DQ) settings
+ * 1 = limit to +/-2 %VDDQ from mr6
+ * 2 = limit to +/-4 %VDDQ from mr6
+ * . . .
+ * 15 = limit to +/-30% VDDQ from mr6
+ */
+ uint8_t reserved1f; /*
+ * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ * Extended training option:
+ *
+ * reserved1F[1:0]: Configured RxClkDly offset try during
+ * WrDq1D high-effort (i.e., when reserved00[6] is set)
+ * 0: -8, +8, -16, +16
+ * 1: -4, +4, -8, +8, -12, +12, -16, +16
+ * 2: -2, +2, -4, +4, -6, +6, -8, +8
+ * 3: -2, +2, -4, +4, -6, +6, -8, +8, -10, +10, -12, +12,
+ * -14, +14, -16, +16
+ *
+ * reserved1F[2]: When set, execute again WrDq1D after
+ * RdDqs1D PRBS
+ * reserved1F[3]: When set redo RdDeskew with PRBS after
+ * (first) WrDqs1D
+ * reserved1F[7:4]: This field is reserved and must be
+ * programmed to 0x00.
+ */
+ uint8_t reserved20; /*
+ * Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ * This field is reserved and must be programmed to 0x00,
+ * excepted for Reserved:
+ * Reserved MREP assume raising edge is found when
+ * reserved20[3:0]+3 consecutive 1 are received during MREP
+ * fine delay swept; reserved20[6:0] thus permits to
+ * increase tolerance for noisy system. And if reserved20[7]
+ * is set, MREP training is failing if no raising edge is
+ * found (otherwise the raising edge is assume close to
+ * delay 0).
+ */
+ uint8_t reserved21; /*
+ * Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ * This field is reserved and must be programmed to 0x00,
+ * excepted for Reserved:
+ * Reserved DWL assume raising edge is found when
+ * reserved21[3:0]+3 consecutive 1 are received during DWL
+ * fine delay swept; reserved21[6:0] thus permits to
+ * increase tolerance for noisy system. And if reserved21[7]
+ * is set, DWL training is failing if no raising edge is
+ * found (otherwise the raising edge is assume close to
+ * delay 0).
+ */
+ uint16_t phyconfigoverride; /*
+ * Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ * Override PhyConfig csr.
+ * 0x0: Use hardware csr value for PhyConfing
+ * (recommended)
+ * Other values: Use value for PhyConfig instead of
+ * Hardware value.
+ */
+ uint8_t dfimrlmargin; /*
+ * Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ * Margin added to smallest passing trained DFI Max Read
+ * Latency value, in units of DFI clocks. Recommended to be
+ * >= 1.
+ */
+ int8_t cdd_rr_3_2; /*
+ * Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 3 to cs 2.
+ */
+ int8_t cdd_rr_3_1; /*
+ * Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 3 to cs 1.
+ */
+ int8_t cdd_rr_3_0; /*
+ * Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 3 to cs 0.
+ */
+ int8_t cdd_rr_2_3; /*
+ * Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 2 to cs 3.
+ */
+ int8_t cdd_rr_2_1; /*
+ * Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 2 to cs 1.
+ */
+ int8_t cdd_rr_2_0; /*
+ * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 2 to cs 0.
+ */
+ int8_t cdd_rr_1_3; /*
+ * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 3.
+ */
+ int8_t cdd_rr_1_2; /*
+ * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 2.
+ */
+ int8_t cdd_rr_1_0; /*
+ * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 0.
+ */
+ int8_t cdd_rr_0_3; /*
+ * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 3.
+ */
+ int8_t cdd_rr_0_2; /*
+ * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 2.
+ */
+ int8_t cdd_rr_0_1; /*
+ * Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 1.
+ */
+ int8_t cdd_ww_3_2; /*
+ * Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 3 to cs
+ * 2.
+ */
+ int8_t cdd_ww_3_1; /*
+ * Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 3 to cs
+ * 1.
+ */
+ int8_t cdd_ww_3_0; /*
+ * Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 3 to cs
+ * 0.
+ */
+ int8_t cdd_ww_2_3; /*
+ * Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 2 to cs
+ * 3.
+ */
+ int8_t cdd_ww_2_1; /*
+ * Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 2 to cs
+ * 1.
+ */
+ int8_t cdd_ww_2_0; /*
+ * Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 2 to cs
+ * 0.
+ */
+ int8_t cdd_ww_1_3; /*
+ * Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 3.
+ */
+ int8_t cdd_ww_1_2; /*
+ * Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 2.
+ */
+ int8_t cdd_ww_1_0; /*
+ * Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 0.
+ */
+ int8_t cdd_ww_0_3; /*
+ * Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 3.
+ */
+ int8_t cdd_ww_0_2; /*
+ * Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 2.
+ */
+ int8_t cdd_ww_0_1; /*
+ * Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 1.
+ */
+ int8_t cdd_rw_3_3; /*
+ * Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 3.
+ */
+ int8_t cdd_rw_3_2; /*
+ * Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 2.
+ */
+ int8_t cdd_rw_3_1; /*
+ * Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 1.
+ */
+ int8_t cdd_rw_3_0; /*
+ * Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 3 to
+ * cs 0.
+ */
+ int8_t cdd_rw_2_3; /*
+ * Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 3.
+ */
+ int8_t cdd_rw_2_2; /*
+ * Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 2.
+ */
+ int8_t cdd_rw_2_1; /*
+ * Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 1.
+ */
+ int8_t cdd_rw_2_0; /*
+ * Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 2 to
+ * cs 0.
+ */
+ int8_t cdd_rw_1_3; /*
+ * Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 3.
+ */
+ int8_t cdd_rw_1_2; /*
+ * Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 2.
+ */
+ int8_t cdd_rw_1_1; /*
+ * Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 1.
+ */
+ int8_t cdd_rw_1_0; /*
+ * Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to
+ * cs 0.
+ */
+ int8_t cdd_rw_0_3; /*
+ * Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 3.
+ */
+ int8_t cdd_rw_0_2; /*
+ * Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 2.
+ */
+ int8_t cdd_rw_0_1; /*
+ * Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 1.
+ */
+ int8_t cdd_rw_0_0; /*
+ * Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to
+ * cs 0.
+ */
+ int8_t cdd_wr_3_3; /*
+ * Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 3.
+ */
+ int8_t cdd_wr_3_2; /*
+ * Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 2.
+ */
+ int8_t cdd_wr_3_1; /*
+ * Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 1.
+ */
+ int8_t cdd_wr_3_0; /*
+ * Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 3 to
+ * cs 0.
+ */
+ int8_t cdd_wr_2_3; /*
+ * Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 3.
+ */
+ int8_t cdd_wr_2_2; /*
+ * Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 2.
+ */
+ int8_t cdd_wr_2_1; /*
+ * Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 1.
+ */
+ int8_t cdd_wr_2_0; /*
+ * Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 2 to
+ * cs 0.
+ */
+ int8_t cdd_wr_1_3; /*
+ * Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 3.
+ */
+ int8_t cdd_wr_1_2; /*
+ * Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 2.
+ */
+ int8_t cdd_wr_1_1; /*
+ * Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 1.
+ */
+ int8_t cdd_wr_1_0; /*
+ * Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to
+ * cs 0.
+ */
+ int8_t cdd_wr_0_3; /*
+ * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 3.
+ */
+ int8_t cdd_wr_0_2; /*
+ * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 2.
+ */
+ int8_t cdd_wr_0_1; /*
+ * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 1.
+ */
+ int8_t cdd_wr_0_0; /*
+ * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to
+ * cs 0.
+ */
+ uint8_t reserved5d; /*
+ * Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ * This field is reserved and must be programmed to 0x00,
+ * excepted for DDR4:
+ * By default, if this parameter is 0, the offset applied at
+ * the end of DDR4 RxEn training resulting in the trained
+ * RxEnDly is 3/8 of the RX preamble width; if reserved5D is
+ * non zero, this offset is used instead (in fine step).
+ */
+ uint16_t mr0; /*
+ * Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ * Value of DDR mode register mr0 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr1; /*
+ * Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ * Value of DDR mode register mr1 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr2; /*
+ * Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ * Value of DDR mode register mr2 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr3; /*
+ * Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ * Value of DDR mode register mr3 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr4; /*
+ * Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ * Value of DDR mode register mr4 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr5; /*
+ * Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ * Value of DDR mode register mr5 for all ranks for current
+ * pstate.
+ */
+ uint16_t mr6; /*
+ * Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ * Value of DDR mode register mr6 for all ranks for current
+ * pstate. Note: The initial VrefDq value and range must be
+ * set in A6:A0.
+ */
+ uint8_t x16present; /*
+ * Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ * X16 device map. Corresponds to CS[3:0].
+ * x16present[0] = CS0 is populated with X16 devices
+ * x16present[1] = CS1 is populated with X16 devices
+ * x16present[2] = CS2 is populated with X16 devices
+ * x16present[3] = CS3 is populated with X16 devices
+ * x16present[7:4] = Reserved (must be programmed to 0)
+ *
+ * Ranks may not contain mixed device types.
+ */
+ uint8_t cssetupgddec; /*
+ * Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ * controls timing of chip select signals when DDR4
+ * gear-down mode is active
+ * 0 - Leave delay of chip select timing group signal
+ * the same both before and after gear-down sync occurs
+ * 1 - Add 1UI of delay to chip select timing group
+ * signals when geardown-mode is active. This allows CS
+ * signals to have equal setup and hold time in gear-down
+ * mode
+ */
+ uint16_t rtt_nom_wr_park0; /*
+ * Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0
+ * DRAM:
+ * rtt_nom_wr_park0[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park0[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 0
+ * rtt_nom_wr_park0[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 0
+ * rtt_nom_wr_park0[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 0
+ */
+ uint16_t rtt_nom_wr_park1; /*
+ * Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1
+ * DRAM:
+ * rtt_nom_wr_park1[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park1[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 1
+ * rtt_nom_wr_park1[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 1
+ * rtt_nom_wr_park1[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 1
+ */
+ uint16_t rtt_nom_wr_park2; /*
+ * Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2
+ * DRAM:
+ * rtt_nom_wr_park2[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park2[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 2
+ * rtt_nom_wr_park2[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 2
+ * rtt_nom_wr_park2[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 2
+ */
+ uint16_t rtt_nom_wr_park3; /*
+ * Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3
+ * DRAM:
+ * rtt_nom_wr_park3[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park3[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 3
+ * rtt_nom_wr_park3[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 3
+ * rtt_nom_wr_park3[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 3
+ */
+ uint16_t rtt_nom_wr_park4; /*
+ * Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4
+ * DRAM:
+ * rtt_nom_wr_park4[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park4[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 4
+ * rtt_nom_wr_park4[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 4
+ * rtt_nom_wr_park4[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 4
+ */
+ uint16_t rtt_nom_wr_park5; /*
+ * Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5
+ * DRAM:
+ * rtt_nom_wr_park5[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park5[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 5
+ * rtt_nom_wr_park5[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 5
+ * rtt_nom_wr_park5[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 5
+ */
+ uint16_t rtt_nom_wr_park6; /*
+ * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6
+ * DRAM:
+ * rtt_nom_wr_park6[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park6[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 6
+ * rtt_nom_wr_park6[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 6
+ * rtt_nom_wr_park6[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 6
+ */
+ uint16_t rtt_nom_wr_park7; /*
+ * Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7
+ * DRAM:
+ * rtt_nom_wr_park7[0] = 1: Option is enable (otherwise,
+ * remaining bit fields are don't care)
+ * rtt_nom_wr_park7[5:3]: Optional RTT_NOM value to be used
+ * in mr1[10:8] for rank 7
+ * rtt_nom_wr_park7[11:9]: Optional RTT_WR value to be used
+ * in mr2[11:9] for rank 7
+ * rtt_nom_wr_park7[8:6]: Optional RTT_PARK value to be used
+ * in mr5[8:6] for rank 7
+ */
+ uint8_t acsmodtctrl0; /*
+ * Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ * Odt pattern for accesses targeting rank 0. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl1; /*
+ * Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ * Odt pattern for accesses targeting rank 1. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl2; /*
+ * Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ * Odt pattern for accesses targeting rank 2. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl3; /*
+ * Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ * Odt pattern for accesses targeting rank 3. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl4; /*
+ * Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ * Odt pattern for accesses targeting rank 4. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl5; /*
+ * Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ * Odt pattern for accesses targeting rank 5. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl6; /*
+ * Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ * Odt pattern for accesses targeting rank 6. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t acsmodtctrl7; /*
+ * Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ * Odt pattern for accesses targeting rank 7. [3:0] is used
+ * for write ODT [7:4] is used for read ODT
+ */
+ uint8_t vrefdqr0nib0; /*
+ * Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ * VrefDq for rank 0 nibble 0. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr0nib1; /*
+ * Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ * VrefDq for rank 0 nibble 1. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib0 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr0nib2; /*
+ * Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ * VrefDq for rank 0 nibble 2. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib0 for x16 devices.
+ */
+ uint8_t vrefdqr0nib3; /*
+ * Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ * VrefDq for rank 0 nibble 3. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib0 for x16 devices, or
+ * vrefdqr0nib2 for x8 devices.
+ */
+ uint8_t vrefdqr0nib4; /*
+ * Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ * VrefDq for rank 0 nibble 4. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr0nib5; /*
+ * Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ * VrefDq for rank 0 nibble 5. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib4 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr0nib6; /*
+ * Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ * VrefDq for rank 0 nibble 6. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib4 for x16 devices.
+ */
+ uint8_t vrefdqr0nib7; /*
+ * Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ * VrefDq for rank 0 nibble 7. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib4 for x16 devices,
+ * or vrefdqr0nib6 for x8 devices.
+ */
+ uint8_t vrefdqr0nib8; /*
+ * Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ * VrefDq for rank 0 nibble 8. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr0nib9; /*
+ * Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ * VrefDq for rank 0 nibble 9. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib8 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr0nib10; /*
+ * Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ * VrefDq for rank 0 nibble 10. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib8 for x16 devices.
+ */
+ uint8_t vrefdqr0nib11; /*
+ * Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ * VrefDq for rank 0 nibble 11. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib8 for x16 devices,
+ * or vrefdqr0nib10 for x8 devices.
+ */
+ uint8_t vrefdqr0nib12; /*
+ * Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ * VrefDq for rank 0 nibble 12. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr0nib13; /*
+ * Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ * VrefDq for rank 0 nibble 13. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib12 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr0nib14; /*
+ * Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ * VrefDq for rank 0 nibble 14. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib12 for x16 devices.
+ */
+ uint8_t vrefdqr0nib15; /*
+ * Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ * VrefDq for rank 0 nibble 15. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib12 for x16 devices,
+ * or vrefdqr0nib14 for x8 devices.
+ */
+ uint8_t vrefdqr0nib16; /*
+ * Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ * VrefDq for rank 0 nibble 16. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr0nib17; /*
+ * Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ * VrefDq for rank 0 nibble 17. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib16 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr0nib18; /*
+ * Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ * VrefDq for rank 0 nibble 18. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib16 for x16 devices.
+ */
+ uint8_t vrefdqr0nib19; /*
+ * Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ * VrefDq for rank 0 nibble 19. Specifies mr6[6:0].
+ * Identical to vrefdqr0nib16 for x16 devices,
+ * or vrefdqr0nib18 for x8 devices.
+ */
+ uint8_t vrefdqr1nib0; /*
+ * Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ * VrefDq for rank 1 nibble 0. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr1nib1; /*
+ * Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ * VrefDq for rank 1 nibble 1. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib0 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr1nib2; /*
+ * Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ * VrefDq for rank 1 nibble 2. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib0 for x16 devices.
+ */
+ uint8_t vrefdqr1nib3; /*
+ * Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ * VrefDq for rank 1 nibble 3. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib0 for x16 devices,
+ * or vrefdqr1nib2 for x8 devices.
+ */
+ uint8_t vrefdqr1nib4; /*
+ * Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ * VrefDq for rank 1 nibble 4. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr1nib5; /*
+ * Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ * VrefDq for rank 1 nibble 5. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib4 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr1nib6; /*
+ * Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ * VrefDq for rank 1 nibble 6. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib4 for x16 devices.
+ */
+ uint8_t vrefdqr1nib7; /*
+ * Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ * VrefDq for rank 1 nibble 7. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib4 for x16 devices,
+ * or vrefdqr1nib6 for x8 devices.
+ */
+ uint8_t vrefdqr1nib8; /*
+ * Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ * VrefDq for rank 1 nibble 8. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr1nib9; /*
+ * Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ * VrefDq for rank 1 nibble 9. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib8 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr1nib10; /*
+ * Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ * VrefDq for rank 1 nibble 10. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib8 for x16 devices.
+ */
+ uint8_t vrefdqr1nib11; /*
+ * Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ * VrefDq for rank 1 nibble 11. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib8 for x16 devices,
+ * or vrefdqr1nib10 for x8 devices.
+ */
+ uint8_t vrefdqr1nib12; /*
+ * Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ * VrefDq for rank 1 nibble 12. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr1nib13; /*
+ * Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ * VrefDq for rank 1 nibble 13. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib12 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr1nib14; /*
+ * Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ * VrefDq for rank 1 nibble 14. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib12 for x16 devices.
+ */
+ uint8_t vrefdqr1nib15; /*
+ * Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ * VrefDq for rank 1 nibble 15. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib12 for x16 devices,
+ * or vrefdqr1nib14 for x8 devices.
+ */
+ uint8_t vrefdqr1nib16; /*
+ * Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ * VrefDq for rank 1 nibble 16. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr1nib17; /*
+ * Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ * VrefDq for rank 1 nibble 17. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib16 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr1nib18; /*
+ * Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ * VrefDq for rank 1 nibble 18. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib16 for x16 devices.
+ */
+ uint8_t vrefdqr1nib19; /*
+ * Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ * VrefDq for rank 1 nibble 19. Specifies mr6[6:0].
+ * Identical to vrefdqr1nib16 for x16 devices,
+ * or vrefdqr1nib18 for x8 devices.
+ */
+ uint8_t vrefdqr2nib0; /*
+ * Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ * VrefDq for rank 2 nibble 0. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr2nib1; /*
+ * Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ * VrefDq for rank 2 nibble 1. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib0 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr2nib2; /*
+ * Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ * VrefDq for rank 2 nibble 2. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib0 for x16 devices.
+ */
+ uint8_t vrefdqr2nib3; /*
+ * Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ * VrefDq for rank 2 nibble 3. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib0 for x16 devices,
+ * or vrefdqr2nib2 for x8 devices.
+ */
+ uint8_t vrefdqr2nib4; /*
+ * Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ * VrefDq for rank 2 nibble 4. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr2nib5; /*
+ * Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ * VrefDq for rank 2 nibble 5. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib4 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr2nib6; /*
+ * Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ * VrefDq for rank 2 nibble 6. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib4 for x16 devices.
+ */
+ uint8_t vrefdqr2nib7; /*
+ * Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ * VrefDq for rank 2 nibble 7. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib4 for x16 devices,
+ * or vrefdqr2nib6 for x8 devices.
+ */
+ uint8_t vrefdqr2nib8; /*
+ * Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ * VrefDq for rank 2 nibble 8. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr2nib9; /*
+ * Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ * VrefDq for rank 2 nibble 9. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib8 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr2nib10; /*
+ * Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ * VrefDq for rank 2 nibble 10. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib8 for x16 devices.
+ */
+ uint8_t vrefdqr2nib11; /*
+ * Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ * VrefDq for rank 2 nibble 11. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib8 for x16 devices,
+ * or vrefdqr2nib10 for x8 devices.
+ */
+ uint8_t vrefdqr2nib12; /*
+ * Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ * VrefDq for rank 2 nibble 12. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr2nib13; /*
+ * Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ * VrefDq for rank 2 nibble 13. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib12 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr2nib14; /*
+ * Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ * VrefDq for rank 2 nibble 14. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib12 for x16 devices.
+ */
+ uint8_t vrefdqr2nib15; /*
+ * Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ * VrefDq for rank 2 nibble 15. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib12 for x16 devices,
+ * or vrefdqr2nib14 for x8 devices.
+ */
+ uint8_t vrefdqr2nib16; /*
+ * Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ * VrefDq for rank 2 nibble 16. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr2nib17; /*
+ * Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ * VrefDq for rank 2 nibble 17. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib16 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr2nib18; /*
+ * Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ * VrefDq for rank 2 nibble 18. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib16 for x16 devices.
+ */
+ uint8_t vrefdqr2nib19; /*
+ * Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ * VrefDq for rank 2 nibble 19. Specifies mr6[6:0].
+ * Identical to vrefdqr2nib16 for x16 devices,
+ * or vrefdqr2nib18 for x8 devices.
+ */
+ uint8_t vrefdqr3nib0; /*
+ * Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ * VrefDq for rank 3 nibble 0. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr3nib1; /*
+ * Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ * VrefDq for rank 3 nibble 1. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib0 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr3nib2; /*
+ * Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ * VrefDq for rank 3 nibble 2. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib0 for x16 devices.
+ */
+ uint8_t vrefdqr3nib3; /*
+ * Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ * VrefDq for rank 3 nibble 3. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib0 for x16 devices,
+ * or vrefdqr3nib2 for x8 devices.
+ */
+ uint8_t vrefdqr3nib4; /*
+ * Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ * VrefDq for rank 3 nibble 4. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr3nib5; /*
+ * Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ * VrefDq for rank 3 nibble 5. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib4 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr3nib6; /*
+ * Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ * VrefDq for rank 3 nibble 6. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib4 for x16 devices.
+ */
+ uint8_t vrefdqr3nib7; /*
+ * Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ * VrefDq for rank 3 nibble 7. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib4 for x16 devices,
+ * or vrefdqr3nib6 for x8 devices.
+ */
+ uint8_t vrefdqr3nib8; /*
+ * Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ * VrefDq for rank 3 nibble 8. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr3nib9; /*
+ * Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ * VrefDq for rank 3 nibble 9. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib8 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr3nib10; /*
+ * Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ * VrefDq for rank 3 nibble 10. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib8 for x16 devices.
+ */
+ uint8_t vrefdqr3nib11; /*
+ * Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ * VrefDq for rank 3 nibble 11. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib8 for x16 devices,
+ * or vrefdqr3nib10 for x8 devices.
+ */
+ uint8_t vrefdqr3nib12; /*
+ * Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ * VrefDq for rank 3 nibble 12. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr3nib13; /*
+ * Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ * VrefDq for rank 3 nibble 13. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib12 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr3nib14; /*
+ * Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ * VrefDq for rank 3 nibble 14. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib12 for x16 devices.
+ */
+ uint8_t vrefdqr3nib15; /*
+ * Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ * VrefDq for rank 3 nibble 15. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib12 for x16 devices,
+ * or vrefdqr3nib14 for x8 devices.
+ */
+ uint8_t vrefdqr3nib16; /*
+ * Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ * VrefDq for rank 3 nibble 16. Specifies mr6[6:0]
+ */
+ uint8_t vrefdqr3nib17; /*
+ * Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ * VrefDq for rank 3 nibble 17. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib16 for x8 or x16 devices.
+ */
+ uint8_t vrefdqr3nib18; /*
+ * Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ * VrefDq for rank 3 nibble 18. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib16 for x16 devices.
+ */
+ uint8_t vrefdqr3nib19; /*
+ * Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ * VrefDq for rank 3 nibble 19. Specifies mr6[6:0].
+ * Identical to vrefdqr3nib16 for x16 devices,
+ * or vrefdqr3nib18 for x8 devices.
+ */
+ uint8_t reservedd6; /* Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A */
+ uint8_t reservedd7; /* Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A */
+ uint8_t reservedd8; /* Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A */
+ uint8_t reservedd9; /* Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A */
+ uint8_t reservedda; /* Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A */
+ uint8_t reserveddb; /* Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A */
+ uint8_t reserveddc; /* Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A */
+ uint8_t reserveddd; /* Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A */
+ uint8_t reservedde; /* Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A */
+ uint8_t reserveddf; /* Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A */
+ uint8_t reservede0; /* Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A */
+ uint8_t reservede1; /* Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A */
+ uint8_t reservede2; /* Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A */
+ uint8_t reservede3; /* Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A */
+ uint8_t reservede4; /* Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A */
+ uint8_t reservede5; /* Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A */
+ uint8_t reservede6; /* Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A */
+ uint8_t reservede7; /* Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A */
+ uint8_t reservede8; /* Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A */
+ uint8_t reservede9; /* Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A */
+ uint8_t reservedea; /* Byte offset 0xea, CSR Addr 0x54075, Direction=N/A */
+ uint8_t reservedeb; /* Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A */
+ uint8_t reservedec; /* Byte offset 0xec, CSR Addr 0x54076, Direction=N/A */
+ uint8_t reserveded; /* Byte offset 0xed, CSR Addr 0x54076, Direction=N/A */
+ uint8_t reservedee; /* Byte offset 0xee, CSR Addr 0x54077, Direction=N/A */
+ uint8_t reservedef; /* Byte offset 0xef, CSR Addr 0x54077, Direction=N/A */
+ uint8_t reservedf0; /* Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A */
+ uint8_t reservedf1; /* Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A */
+ uint8_t reservedf2; /* Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A */
+ uint8_t reservedf3; /* Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A */
+ uint8_t reservedf4; /* Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A */
+ uint8_t reservedf5; /* Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A */
+ uint8_t reservedf6; /* Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A */
+ uint8_t reservedf7; /* Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A */
+ uint8_t reservedf8; /* Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A */
+ uint8_t reservedf9; /* Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A */
+ uint8_t reservedfa; /* Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A */
+ uint8_t reservedfb; /* Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A */
+ uint8_t reservedfc; /* Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A */
+ uint8_t reservedfd; /* Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A */
+ uint8_t reservedfe; /* Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A */
+ uint8_t reservedff; /* Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A */
+ uint8_t reserved100; /* Byte offset 0x100, CSR Addr 0x54080, Direction=N/A */
+ uint8_t reserved101; /* Byte offset 0x101, CSR Addr 0x54080, Direction=N/A */
+ uint8_t reserved102; /* Byte offset 0x102, CSR Addr 0x54081, Direction=N/A */
+ uint8_t reserved103; /* Byte offset 0x103, CSR Addr 0x54081, Direction=N/A */
+ uint8_t reserved104; /* Byte offset 0x104, CSR Addr 0x54082, Direction=N/A */
+ uint8_t reserved105; /* Byte offset 0x105, CSR Addr 0x54082, Direction=N/A */
+ uint8_t reserved106; /* Byte offset 0x106, CSR Addr 0x54083, Direction=N/A */
+ uint8_t reserved107; /* Byte offset 0x107, CSR Addr 0x54083, Direction=N/A */
+ uint8_t reserved108; /* Byte offset 0x108, CSR Addr 0x54084, Direction=N/A */
+ uint8_t reserved109; /* Byte offset 0x109, CSR Addr 0x54084, Direction=N/A */
+ uint8_t reserved10a; /* Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A */
+ uint8_t reserved10b; /* Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A */
+ uint8_t reserved10c; /* Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A */
+ uint8_t reserved10d; /* Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A */
+ uint8_t reserved10e; /* Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A */
+ uint8_t reserved10f; /* Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A */
+ uint8_t reserved110; /* Byte offset 0x110, CSR Addr 0x54088, Direction=N/A */
+ uint8_t reserved111; /* Byte offset 0x111, CSR Addr 0x54088, Direction=N/A */
+ uint8_t reserved112; /* Byte offset 0x112, CSR Addr 0x54089, Direction=N/A */
+ uint8_t reserved113; /* Byte offset 0x113, CSR Addr 0x54089, Direction=N/A */
+ uint8_t reserved114; /* Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A */
+ uint8_t reserved115; /* Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A */
+ uint8_t reserved116; /* Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A */
+ uint8_t reserved117; /* Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A */
+ uint8_t reserved118; /* Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A */
+ uint8_t reserved119; /* Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A */
+ uint8_t reserved11a; /* Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A */
+ uint8_t reserved11b; /* Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A */
+ uint8_t reserved11c; /* Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A */
+ uint8_t reserved11d; /* Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A */
+ uint8_t reserved11e; /* Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A */
+ uint8_t reserved11f; /* Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A */
+ uint8_t reserved120; /* Byte offset 0x120, CSR Addr 0x54090, Direction=N/A */
+ uint8_t reserved121; /* Byte offset 0x121, CSR Addr 0x54090, Direction=N/A */
+ uint8_t reserved122; /* Byte offset 0x122, CSR Addr 0x54091, Direction=N/A */
+ uint8_t reserved123; /* Byte offset 0x123, CSR Addr 0x54091, Direction=N/A */
+ uint8_t reserved124; /* Byte offset 0x124, CSR Addr 0x54092, Direction=N/A */
+ uint8_t reserved125; /* Byte offset 0x125, CSR Addr 0x54092, Direction=N/A */
+ uint8_t reserved126; /* Byte offset 0x126, CSR Addr 0x54093, Direction=N/A */
+ uint8_t reserved127; /* Byte offset 0x127, CSR Addr 0x54093, Direction=N/A */
+ uint8_t reserved128; /* Byte offset 0x128, CSR Addr 0x54094, Direction=N/A */
+ uint8_t reserved129; /* Byte offset 0x129, CSR Addr 0x54094, Direction=N/A */
+ uint8_t reserved12a; /* Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A */
+ uint8_t reserved12b; /* Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A */
+ uint8_t reserved12c; /* Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A */
+ uint8_t reserved12d; /* Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A */
+ uint8_t reserved12e; /* Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A */
+ uint8_t reserved12f; /* Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A */
+ uint8_t reserved130; /* Byte offset 0x130, CSR Addr 0x54098, Direction=N/A */
+ uint8_t reserved131; /* Byte offset 0x131, CSR Addr 0x54098, Direction=N/A */
+ uint8_t reserved132; /* Byte offset 0x132, CSR Addr 0x54099, Direction=N/A */
+ uint8_t reserved133; /* Byte offset 0x133, CSR Addr 0x54099, Direction=N/A */
+ uint8_t reserved134; /* Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A */
+ uint8_t reserved135; /* Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A */
+ uint8_t reserved136; /* Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A */
+ uint8_t reserved137; /* Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A */
+ uint8_t reserved138; /* Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A */
+ uint8_t reserved139; /* Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A */
+ uint8_t reserved13a; /* Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A */
+ uint8_t reserved13b; /* Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A */
+ uint8_t reserved13c; /* Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A */
+ uint8_t reserved13d; /* Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A */
+ uint8_t reserved13e; /* Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A */
+ uint8_t reserved13f; /* Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A */
+ uint8_t reserved140; /* Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A */
+ uint8_t reserved141; /* Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A */
+ uint8_t reserved142; /* Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A */
+ uint8_t reserved143; /* Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A */
+ uint8_t reserved144; /* Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A */
+ uint8_t reserved145; /* Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A */
+ uint8_t reserved146; /* Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A */
+ uint8_t reserved147; /* Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A */
+ uint8_t reserved148; /* Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A */
+ uint8_t reserved149; /* Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A */
+ uint8_t reserved14a; /* Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A */
+ uint8_t reserved14b; /* Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A */
+ uint8_t reserved14c; /* Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A */
+ uint8_t reserved14d; /* Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A */
+ uint8_t reserved14e; /* Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A */
+ uint8_t reserved14f; /* Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A */
+ uint8_t reserved150; /* Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A */
+ uint8_t reserved151; /* Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A */
+ uint8_t reserved152; /* Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A */
+ uint8_t reserved153; /* Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A */
+ uint8_t reserved154; /* Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A */
+ uint8_t reserved155; /* Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A */
+ uint8_t reserved156; /* Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A */
+ uint8_t reserved157; /* Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A */
+ uint8_t reserved158; /* Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A */
+ uint8_t reserved159; /* Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A */
+ uint8_t reserved15a; /* Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A */
+ uint8_t reserved15b; /* Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A */
+ uint8_t reserved15c; /* Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A */
+ uint8_t reserved15d; /* Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A */
+ uint8_t reserved15e; /* Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A */
+ uint8_t reserved15f; /* Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A */
+ uint8_t reserved160; /* Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A */
+ uint8_t reserved161; /* Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A */
+ uint8_t reserved162; /* Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A */
+ uint8_t reserved163; /* Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A */
+ uint8_t reserved164; /* Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A */
+ uint8_t reserved165; /* Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A */
+ uint8_t reserved166; /* Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A */
+ uint8_t reserved167; /* Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A */
+ uint8_t reserved168; /* Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A */
+ uint8_t reserved169; /* Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A */
+ uint8_t reserved16a; /* Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A */
+ uint8_t reserved16b; /* Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A */
+ uint8_t reserved16c; /* Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A */
+ uint8_t reserved16d; /* Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A */
+ uint8_t reserved16e; /* Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A */
+ uint8_t reserved16f; /* Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A */
+ uint8_t reserved170; /* Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A */
+ uint8_t reserved171; /* Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A */
+ uint8_t reserved172; /* Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A */
+ uint8_t reserved173; /* Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A */
+ uint8_t reserved174; /* Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A */
+ uint8_t reserved175; /* Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A */
+ uint8_t reserved176; /* Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A */
+ uint8_t reserved177; /* Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A */
+ uint8_t reserved178; /* Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A */
+ uint8_t reserved179; /* Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A */
+ uint8_t reserved17a; /* Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A */
+ uint8_t reserved17b; /* Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A */
+ uint8_t reserved17c; /* Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A */
+ uint8_t reserved17d; /* Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A */
+ uint8_t reserved17e; /* Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A */
+ uint8_t reserved17f; /* Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A */
+ uint8_t reserved180; /* Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A */
+ uint8_t reserved181; /* Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A */
+ uint8_t reserved182; /* Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A */
+ uint8_t reserved183; /* Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A */
+ uint8_t reserved184; /* Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A */
+ uint8_t reserved185; /* Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A */
+ uint8_t reserved186; /* Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A */
+ uint8_t reserved187; /* Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A */
+ uint8_t reserved188; /* Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A */
+ uint8_t reserved189; /* Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A */
+ uint8_t reserved18a; /* Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A */
+ uint8_t reserved18b; /* Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A */
+ uint8_t reserved18c; /* Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A */
+ uint8_t reserved18d; /* Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A */
+ uint8_t reserved18e; /* Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A */
+ uint8_t reserved18f; /* Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A */
+ uint8_t reserved190; /* Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A */
+ uint8_t reserved191; /* Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A */
+ uint8_t reserved192; /* Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A */
+ uint8_t reserved193; /* Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A */
+ uint8_t reserved194; /* Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A */
+ uint8_t reserved195; /* Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A */
+ uint8_t reserved196; /* Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A */
+ uint8_t reserved197; /* Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A */
+ uint8_t reserved198; /* Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A */
+ uint8_t reserved199; /* Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A */
+ uint8_t reserved19a; /* Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A */
+ uint8_t reserved19b; /* Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A */
+ uint8_t reserved19c; /* Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A */
+ uint8_t reserved19d; /* Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A */
+ uint8_t reserved19e; /* Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A */
+ uint8_t reserved19f; /* Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A */
+ uint8_t reserved1a0; /* Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A */
+ uint8_t reserved1a1; /* Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A */
+ uint8_t reserved1a2; /* Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A */
+ uint8_t reserved1a3; /* Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A */
+ uint8_t reserved1a4; /* Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A */
+ uint8_t reserved1a5; /* Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A */
+ uint8_t reserved1a6; /* Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A */
+ uint8_t reserved1a7; /* Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A */
+ uint8_t reserved1a8; /* Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A */
+ uint8_t reserved1a9; /* Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A */
+ uint8_t reserved1aa; /* Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A */
+ uint8_t reserved1ab; /* Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A */
+ uint8_t reserved1ac; /* Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A */
+ uint8_t reserved1ad; /* Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A */
+ uint8_t reserved1ae; /* Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A */
+ uint8_t reserved1af; /* Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A */
+ uint8_t reserved1b0; /* Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A */
+ uint8_t reserved1b1; /* Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A */
+ uint8_t reserved1b2; /* Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A */
+ uint8_t reserved1b3; /* Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A */
+ uint8_t reserved1b4; /* Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A */
+ uint8_t reserved1b5; /* Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A */
+ uint8_t reserved1b6; /* Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A */
+ uint8_t reserved1b7; /* Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A */
+ uint8_t reserved1b8; /* Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A */
+ uint8_t reserved1b9; /* Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A */
+ uint8_t reserved1ba; /* Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A */
+ uint8_t reserved1bb; /* Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A */
+ uint8_t reserved1bc; /* Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A */
+ uint8_t reserved1bd; /* Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A */
+ uint8_t reserved1be; /* Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A */
+ uint8_t reserved1bf; /* Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A */
+ uint8_t reserved1c0; /* Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A */
+ uint8_t reserved1c1; /* Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A */
+ uint8_t reserved1c2; /* Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A */
+ uint8_t reserved1c3; /* Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A */
+ uint8_t reserved1c4; /* Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A */
+ uint8_t reserved1c5; /* Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A */
+ uint8_t reserved1c6; /* Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A */
+ uint8_t reserved1c7; /* Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A */
+ uint8_t reserved1c8; /* Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A */
+ uint8_t reserved1c9; /* Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A */
+ uint8_t reserved1ca; /* Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A */
+ uint8_t reserved1cb; /* Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A */
+ uint8_t reserved1cc; /* Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A */
+ uint8_t reserved1cd; /* Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A */
+ uint8_t reserved1ce; /* Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A */
+ uint8_t reserved1cf; /* Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A */
+ uint8_t reserved1d0; /* Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A */
+ uint8_t reserved1d1; /* Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A */
+ uint8_t reserved1d2; /* Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A */
+ uint8_t reserved1d3; /* Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A */
+ uint8_t reserved1d4; /* Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A */
+ uint8_t reserved1d5; /* Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A */
+ uint8_t reserved1d6; /* Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A */
+ uint8_t reserved1d7; /* Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A */
+ uint8_t reserved1d8; /* Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A */
+ uint8_t reserved1d9; /* Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A */
+ uint8_t reserved1da; /* Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A */
+ uint8_t reserved1db; /* Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A */
+ uint8_t reserved1dc; /* Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A */
+ uint8_t reserved1dd; /* Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A */
+ uint8_t reserved1de; /* Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A */
+ uint8_t reserved1df; /* Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A */
+ uint8_t reserved1e0; /* Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A */
+ uint8_t reserved1e1; /* Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A */
+ uint8_t reserved1e2; /* Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A */
+ uint8_t reserved1e3; /* Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A */
+ uint8_t reserved1e4; /* Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A */
+ uint8_t reserved1e5; /* Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A */
+ uint8_t reserved1e6; /* Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A */
+ uint8_t reserved1e7; /* Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A */
+ uint8_t reserved1e8; /* Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A */
+ uint8_t reserved1e9; /* Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A */
+ uint8_t reserved1ea; /* Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A */
+ uint8_t reserved1eb; /* Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A */
+ uint8_t reserved1ec; /* Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A */
+ uint8_t reserved1ed; /* Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A */
+ uint8_t reserved1ee; /* Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A */
+ uint8_t reserved1ef; /* Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A */
+ uint8_t reserved1f0; /* Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A */
+ uint8_t reserved1f1; /* Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A */
+ uint8_t reserved1f2; /* Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A */
+ uint8_t reserved1f3; /* Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A */
+ uint8_t reserved1f4; /* Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A */
+ uint8_t reserved1f5; /* Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A */
+ uint8_t reserved1f6; /* Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A */
+ uint8_t reserved1f7; /* Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A */
+ uint8_t reserved1f8; /* Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A */
+ uint8_t reserved1f9; /* Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A */
+ uint8_t reserved1fa; /* Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A */
+ uint8_t reserved1fb; /* Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A */
+ uint8_t reserved1fc; /* Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A */
+ uint8_t reserved1fd; /* Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A */
+ uint8_t reserved1fe; /* Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A */
+ uint8_t reserved1ff; /* Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A */
+ uint8_t reserved200; /* Byte offset 0x200, CSR Addr 0x54100, Direction=N/A */
+ uint8_t reserved201; /* Byte offset 0x201, CSR Addr 0x54100, Direction=N/A */
+ uint8_t reserved202; /* Byte offset 0x202, CSR Addr 0x54101, Direction=N/A */
+ uint8_t reserved203; /* Byte offset 0x203, CSR Addr 0x54101, Direction=N/A */
+ uint8_t reserved204; /* Byte offset 0x204, CSR Addr 0x54102, Direction=N/A */
+ uint8_t reserved205; /* Byte offset 0x205, CSR Addr 0x54102, Direction=N/A */
+ uint8_t reserved206; /* Byte offset 0x206, CSR Addr 0x54103, Direction=N/A */
+ uint8_t reserved207; /* Byte offset 0x207, CSR Addr 0x54103, Direction=N/A */
+ uint8_t reserved208; /* Byte offset 0x208, CSR Addr 0x54104, Direction=N/A */
+ uint8_t reserved209; /* Byte offset 0x209, CSR Addr 0x54104, Direction=N/A */
+ uint8_t reserved20a; /* Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A */
+ uint8_t reserved20b; /* Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A */
+ uint8_t reserved20c; /* Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A */
+ uint8_t reserved20d; /* Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A */
+ uint8_t reserved20e; /* Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A */
+ uint8_t reserved20f; /* Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A */
+ uint8_t reserved210; /* Byte offset 0x210, CSR Addr 0x54108, Direction=N/A */
+ uint8_t reserved211; /* Byte offset 0x211, CSR Addr 0x54108, Direction=N/A */
+ uint8_t reserved212; /* Byte offset 0x212, CSR Addr 0x54109, Direction=N/A */
+ uint8_t reserved213; /* Byte offset 0x213, CSR Addr 0x54109, Direction=N/A */
+ uint8_t reserved214; /* Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A */
+ uint8_t reserved215; /* Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A */
+ uint8_t reserved216; /* Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A */
+ uint8_t reserved217; /* Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A */
+ uint8_t reserved218; /* Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A */
+ uint8_t reserved219; /* Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A */
+ uint8_t reserved21a; /* Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A */
+ uint8_t reserved21b; /* Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A */
+ uint8_t reserved21c; /* Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A */
+ uint8_t reserved21d; /* Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A */
+ uint8_t reserved21e; /* Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A */
+ uint8_t reserved21f; /* Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A */
+ uint8_t reserved220; /* Byte offset 0x220, CSR Addr 0x54110, Direction=N/A */
+ uint8_t reserved221; /* Byte offset 0x221, CSR Addr 0x54110, Direction=N/A */
+ uint8_t reserved222; /* Byte offset 0x222, CSR Addr 0x54111, Direction=N/A */
+ uint8_t reserved223; /* Byte offset 0x223, CSR Addr 0x54111, Direction=N/A */
+ uint8_t reserved224; /* Byte offset 0x224, CSR Addr 0x54112, Direction=N/A */
+ uint8_t reserved225; /* Byte offset 0x225, CSR Addr 0x54112, Direction=N/A */
+ uint8_t reserved226; /* Byte offset 0x226, CSR Addr 0x54113, Direction=N/A */
+ uint8_t reserved227; /* Byte offset 0x227, CSR Addr 0x54113, Direction=N/A */
+ uint8_t reserved228; /* Byte offset 0x228, CSR Addr 0x54114, Direction=N/A */
+ uint8_t reserved229; /* Byte offset 0x229, CSR Addr 0x54114, Direction=N/A */
+ uint8_t reserved22a; /* Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A */
+ uint8_t reserved22b; /* Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A */
+ uint8_t reserved22c; /* Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A */
+ uint8_t reserved22d; /* Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A */
+ uint8_t reserved22e; /* Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A */
+ uint8_t reserved22f; /* Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A */
+ uint8_t reserved230; /* Byte offset 0x230, CSR Addr 0x54118, Direction=N/A */
+ uint8_t reserved231; /* Byte offset 0x231, CSR Addr 0x54118, Direction=N/A */
+ uint8_t reserved232; /* Byte offset 0x232, CSR Addr 0x54119, Direction=N/A */
+ uint8_t reserved233; /* Byte offset 0x233, CSR Addr 0x54119, Direction=N/A */
+ uint8_t reserved234; /* Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A */
+ uint8_t reserved235; /* Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A */
+ uint8_t reserved236; /* Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A */
+ uint8_t reserved237; /* Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A */
+ uint8_t reserved238; /* Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A */
+ uint8_t reserved239; /* Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A */
+ uint8_t reserved23a; /* Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A */
+ uint8_t reserved23b; /* Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A */
+ uint8_t reserved23c; /* Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A */
+ uint8_t reserved23d; /* Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A */
+ uint8_t reserved23e; /* Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A */
+ uint8_t reserved23f; /* Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A */
+ uint8_t reserved240; /* Byte offset 0x240, CSR Addr 0x54120, Direction=N/A */
+ uint8_t reserved241; /* Byte offset 0x241, CSR Addr 0x54120, Direction=N/A */
+ uint8_t reserved242; /* Byte offset 0x242, CSR Addr 0x54121, Direction=N/A */
+ uint8_t reserved243; /* Byte offset 0x243, CSR Addr 0x54121, Direction=N/A */
+ uint8_t reserved244; /* Byte offset 0x244, CSR Addr 0x54122, Direction=N/A */
+ uint8_t reserved245; /* Byte offset 0x245, CSR Addr 0x54122, Direction=N/A */
+ uint8_t reserved246; /* Byte offset 0x246, CSR Addr 0x54123, Direction=N/A */
+ uint8_t reserved247; /* Byte offset 0x247, CSR Addr 0x54123, Direction=N/A */
+ uint8_t reserved248; /* Byte offset 0x248, CSR Addr 0x54124, Direction=N/A */
+ uint8_t reserved249; /* Byte offset 0x249, CSR Addr 0x54124, Direction=N/A */
+ uint8_t reserved24a; /* Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A */
+ uint8_t reserved24b; /* Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A */
+ uint8_t reserved24c; /* Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A */
+ uint8_t reserved24d; /* Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A */
+ uint8_t reserved24e; /* Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A */
+ uint8_t reserved24f; /* Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A */
+ uint8_t reserved250; /* Byte offset 0x250, CSR Addr 0x54128, Direction=N/A */
+ uint8_t reserved251; /* Byte offset 0x251, CSR Addr 0x54128, Direction=N/A */
+ uint8_t reserved252; /* Byte offset 0x252, CSR Addr 0x54129, Direction=N/A */
+ uint8_t reserved253; /* Byte offset 0x253, CSR Addr 0x54129, Direction=N/A */
+ uint8_t reserved254; /* Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A */
+ uint8_t reserved255; /* Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A */
+ uint8_t reserved256; /* Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A */
+ uint8_t reserved257; /* Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A */
+ uint8_t reserved258; /* Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A */
+ uint8_t reserved259; /* Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A */
+ uint8_t reserved25a; /* Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A */
+ uint8_t reserved25b; /* Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A */
+ uint8_t reserved25c; /* Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A */
+ uint8_t reserved25d; /* Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A */
+ uint8_t reserved25e; /* Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A */
+ uint8_t reserved25f; /* Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A */
+ uint8_t reserved260; /* Byte offset 0x260, CSR Addr 0x54130, Direction=N/A */
+ uint8_t reserved261; /* Byte offset 0x261, CSR Addr 0x54130, Direction=N/A */
+ uint8_t reserved262; /* Byte offset 0x262, CSR Addr 0x54131, Direction=N/A */
+ uint8_t reserved263; /* Byte offset 0x263, CSR Addr 0x54131, Direction=N/A */
+ uint8_t reserved264; /* Byte offset 0x264, CSR Addr 0x54132, Direction=N/A */
+ uint8_t reserved265; /* Byte offset 0x265, CSR Addr 0x54132, Direction=N/A */
+ uint8_t reserved266; /* Byte offset 0x266, CSR Addr 0x54133, Direction=N/A */
+ uint8_t reserved267; /* Byte offset 0x267, CSR Addr 0x54133, Direction=N/A */
+ uint8_t reserved268; /* Byte offset 0x268, CSR Addr 0x54134, Direction=N/A */
+ uint8_t reserved269; /* Byte offset 0x269, CSR Addr 0x54134, Direction=N/A */
+ uint8_t reserved26a; /* Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A */
+ uint8_t reserved26b; /* Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A */
+ uint8_t reserved26c; /* Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A */
+ uint8_t reserved26d; /* Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A */
+ uint8_t reserved26e; /* Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A */
+ uint8_t reserved26f; /* Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A */
+ uint8_t reserved270; /* Byte offset 0x270, CSR Addr 0x54138, Direction=N/A */
+ uint8_t reserved271; /* Byte offset 0x271, CSR Addr 0x54138, Direction=N/A */
+ uint8_t reserved272; /* Byte offset 0x272, CSR Addr 0x54139, Direction=N/A */
+ uint8_t reserved273; /* Byte offset 0x273, CSR Addr 0x54139, Direction=N/A */
+ uint8_t reserved274; /* Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A */
+ uint8_t reserved275; /* Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A */
+ uint8_t reserved276; /* Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A */
+ uint8_t reserved277; /* Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A */
+ uint8_t reserved278; /* Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A */
+ uint8_t reserved279; /* Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A */
+ uint8_t reserved27a; /* Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A */
+ uint8_t reserved27b; /* Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A */
+ uint8_t reserved27c; /* Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A */
+ uint8_t reserved27d; /* Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A */
+ uint8_t reserved27e; /* Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A */
+ uint8_t reserved27f; /* Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A */
+ uint8_t reserved280; /* Byte offset 0x280, CSR Addr 0x54140, Direction=N/A */
+ uint8_t reserved281; /* Byte offset 0x281, CSR Addr 0x54140, Direction=N/A */
+ uint8_t reserved282; /* Byte offset 0x282, CSR Addr 0x54141, Direction=N/A */
+ uint8_t reserved283; /* Byte offset 0x283, CSR Addr 0x54141, Direction=N/A */
+ uint8_t reserved284; /* Byte offset 0x284, CSR Addr 0x54142, Direction=N/A */
+ uint8_t reserved285; /* Byte offset 0x285, CSR Addr 0x54142, Direction=N/A */
+ uint8_t reserved286; /* Byte offset 0x286, CSR Addr 0x54143, Direction=N/A */
+ uint8_t reserved287; /* Byte offset 0x287, CSR Addr 0x54143, Direction=N/A */
+ uint8_t reserved288; /* Byte offset 0x288, CSR Addr 0x54144, Direction=N/A */
+ uint8_t reserved289; /* Byte offset 0x289, CSR Addr 0x54144, Direction=N/A */
+ uint8_t reserved28a; /* Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A */
+ uint8_t reserved28b; /* Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A */
+ uint8_t reserved28c; /* Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A */
+ uint8_t reserved28d; /* Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A */
+ uint8_t reserved28e; /* Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A */
+ uint8_t reserved28f; /* Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A */
+ uint8_t reserved290; /* Byte offset 0x290, CSR Addr 0x54148, Direction=N/A */
+ uint8_t reserved291; /* Byte offset 0x291, CSR Addr 0x54148, Direction=N/A */
+ uint8_t reserved292; /* Byte offset 0x292, CSR Addr 0x54149, Direction=N/A */
+ uint8_t reserved293; /* Byte offset 0x293, CSR Addr 0x54149, Direction=N/A */
+ uint8_t reserved294; /* Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A */
+ uint8_t reserved295; /* Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A */
+ uint8_t reserved296; /* Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A */
+ uint8_t reserved297; /* Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A */
+ uint8_t reserved298; /* Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A */
+ uint8_t reserved299; /* Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A */
+ uint8_t reserved29a; /* Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A */
+ uint8_t reserved29b; /* Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A */
+ uint8_t reserved29c; /* Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A */
+ uint8_t reserved29d; /* Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A */
+ uint8_t reserved29e; /* Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A */
+ uint8_t reserved29f; /* Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A */
+ uint8_t reserved2a0; /* Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A */
+ uint8_t reserved2a1; /* Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A */
+ uint8_t reserved2a2; /* Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A */
+ uint8_t reserved2a3; /* Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A */
+ uint8_t reserved2a4; /* Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A */
+ uint8_t reserved2a5; /* Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A */
+ uint8_t reserved2a6; /* Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A */
+ uint8_t reserved2a7; /* Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A */
+ uint8_t reserved2a8; /* Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A */
+ uint8_t reserved2a9; /* Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A */
+ uint8_t reserved2aa; /* Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A */
+ uint8_t reserved2ab; /* Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A */
+ uint8_t reserved2ac; /* Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A */
+ uint8_t reserved2ad; /* Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A */
+ uint8_t reserved2ae; /* Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A */
+ uint8_t reserved2af; /* Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A */
+ uint8_t reserved2b0; /* Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A */
+ uint8_t reserved2b1; /* Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A */
+ uint8_t reserved2b2; /* Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A */
+ uint8_t reserved2b3; /* Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A */
+ uint8_t reserved2b4; /* Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A */
+ uint8_t reserved2b5; /* Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A */
+ uint8_t reserved2b6; /* Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A */
+ uint8_t reserved2b7; /* Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A */
+ uint8_t reserved2b8; /* Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A */
+ uint8_t reserved2b9; /* Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A */
+ uint8_t reserved2ba; /* Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A */
+ uint8_t reserved2bb; /* Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A */
+ uint8_t reserved2bc; /* Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A */
+ uint8_t reserved2bd; /* Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A */
+ uint8_t reserved2be; /* Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A */
+ uint8_t reserved2bf; /* Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A */
+ uint8_t reserved2c0; /* Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A */
+ uint8_t reserved2c1; /* Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A */
+ uint8_t reserved2c2; /* Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A */
+ uint8_t reserved2c3; /* Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A */
+ uint8_t reserved2c4; /* Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A */
+ uint8_t reserved2c5; /* Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A */
+ uint8_t reserved2c6; /* Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A */
+ uint8_t reserved2c7; /* Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A */
+ uint8_t reserved2c8; /* Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A */
+ uint8_t reserved2c9; /* Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A */
+ uint8_t reserved2ca; /* Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A */
+ uint8_t reserved2cb; /* Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A */
+ uint8_t reserved2cc; /* Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A */
+ uint8_t reserved2cd; /* Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A */
+ uint8_t reserved2ce; /* Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A */
+ uint8_t reserved2cf; /* Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A */
+ uint8_t reserved2d0; /* Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A */
+ uint8_t reserved2d1; /* Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A */
+ uint8_t reserved2d2; /* Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A */
+ uint8_t reserved2d3; /* Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A */
+ uint8_t reserved2d4; /* Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A */
+ uint8_t reserved2d5; /* Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A */
+ uint8_t reserved2d6; /* Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A */
+ uint8_t reserved2d7; /* Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A */
+ uint8_t reserved2d8; /* Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A */
+ uint8_t reserved2d9; /* Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A */
+ uint8_t reserved2da; /* Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A */
+ uint8_t reserved2db; /* Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A */
+ uint8_t reserved2dc; /* Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A */
+ uint8_t reserved2dd; /* Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A */
+ uint8_t reserved2de; /* Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A */
+ uint8_t reserved2df; /* Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A */
+ uint8_t reserved2e0; /* Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A */
+ uint8_t reserved2e1; /* Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A */
+ uint8_t reserved2e2; /* Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A */
+ uint8_t reserved2e3; /* Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A */
+ uint8_t reserved2e4; /* Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A */
+ uint8_t reserved2e5; /* Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A */
+ uint8_t reserved2e6; /* Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A */
+ uint8_t reserved2e7; /* Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A */
+ uint8_t reserved2e8; /* Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A */
+ uint8_t reserved2e9; /* Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A */
+ uint8_t reserved2ea; /* Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A */
+ uint8_t reserved2eb; /* Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A */
+ uint8_t reserved2ec; /* Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A */
+ uint8_t reserved2ed; /* Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A */
+ uint8_t reserved2ee; /* Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A */
+ uint8_t reserved2ef; /* Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A */
+ uint8_t reserved2f0; /* Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A */
+ uint8_t reserved2f1; /* Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A */
+ uint8_t reserved2f2; /* Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A */
+ uint8_t reserved2f3; /* Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A */
+ uint8_t reserved2f4; /* Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A */
+ uint8_t reserved2f5; /* Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A */
+ uint8_t reserved2f6; /* Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A */
+ uint8_t reserved2f7; /* Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A */
+ uint8_t reserved2f8; /* Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A */
+ uint8_t reserved2f9; /* Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A */
+ uint8_t reserved2fa; /* Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A */
+ uint8_t reserved2fb; /* Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A */
+ uint8_t reserved2fc; /* Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A */
+ uint8_t reserved2fd; /* Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A */
+ uint8_t reserved2fe; /* Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A */
+ uint8_t reserved2ff; /* Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A */
+ uint8_t reserved300; /* Byte offset 0x300, CSR Addr 0x54180, Direction=N/A */
+ uint8_t reserved301; /* Byte offset 0x301, CSR Addr 0x54180, Direction=N/A */
+ uint8_t reserved302; /* Byte offset 0x302, CSR Addr 0x54181, Direction=N/A */
+ uint8_t reserved303; /* Byte offset 0x303, CSR Addr 0x54181, Direction=N/A */
+ uint8_t reserved304; /* Byte offset 0x304, CSR Addr 0x54182, Direction=N/A */
+ uint8_t reserved305; /* Byte offset 0x305, CSR Addr 0x54182, Direction=N/A */
+ uint8_t reserved306; /* Byte offset 0x306, CSR Addr 0x54183, Direction=N/A */
+ uint8_t reserved307; /* Byte offset 0x307, CSR Addr 0x54183, Direction=N/A */
+ uint8_t reserved308; /* Byte offset 0x308, CSR Addr 0x54184, Direction=N/A */
+ uint8_t reserved309; /* Byte offset 0x309, CSR Addr 0x54184, Direction=N/A */
+ uint8_t reserved30a; /* Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A */
+ uint8_t reserved30b; /* Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A */
+ uint8_t reserved30c; /* Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A */
+ uint8_t reserved30d; /* Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A */
+ uint8_t reserved30e; /* Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A */
+ uint8_t reserved30f; /* Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A */
+ uint8_t reserved310; /* Byte offset 0x310, CSR Addr 0x54188, Direction=N/A */
+ uint8_t reserved311; /* Byte offset 0x311, CSR Addr 0x54188, Direction=N/A */
+ uint8_t reserved312; /* Byte offset 0x312, CSR Addr 0x54189, Direction=N/A */
+ uint8_t reserved313; /* Byte offset 0x313, CSR Addr 0x54189, Direction=N/A */
+ uint8_t reserved314; /* Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A */
+ uint8_t reserved315; /* Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A */
+ uint8_t reserved316; /* Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A */
+ uint8_t reserved317; /* Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A */
+ uint8_t reserved318; /* Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A */
+ uint8_t reserved319; /* Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A */
+ uint8_t reserved31a; /* Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A */
+ uint8_t reserved31b; /* Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A */
+ uint8_t reserved31c; /* Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A */
+ uint8_t reserved31d; /* Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A */
+ uint8_t reserved31e; /* Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A */
+ uint8_t reserved31f; /* Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A */
+ uint8_t reserved320; /* Byte offset 0x320, CSR Addr 0x54190, Direction=N/A */
+ uint8_t reserved321; /* Byte offset 0x321, CSR Addr 0x54190, Direction=N/A */
+ uint8_t reserved322; /* Byte offset 0x322, CSR Addr 0x54191, Direction=N/A */
+ uint8_t reserved323; /* Byte offset 0x323, CSR Addr 0x54191, Direction=N/A */
+ uint8_t reserved324; /* Byte offset 0x324, CSR Addr 0x54192, Direction=N/A */
+ uint8_t reserved325; /* Byte offset 0x325, CSR Addr 0x54192, Direction=N/A */
+ uint8_t reserved326; /* Byte offset 0x326, CSR Addr 0x54193, Direction=N/A */
+ uint8_t reserved327; /* Byte offset 0x327, CSR Addr 0x54193, Direction=N/A */
+ uint8_t reserved328; /* Byte offset 0x328, CSR Addr 0x54194, Direction=N/A */
+ uint8_t reserved329; /* Byte offset 0x329, CSR Addr 0x54194, Direction=N/A */
+ uint8_t reserved32a; /* Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A */
+ uint8_t reserved32b; /* Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A */
+ uint8_t reserved32c; /* Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A */
+ uint8_t reserved32d; /* Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A */
+ uint8_t reserved32e; /* Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A */
+ uint8_t reserved32f; /* Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A */
+ uint8_t reserved330; /* Byte offset 0x330, CSR Addr 0x54198, Direction=N/A */
+ uint8_t reserved331; /* Byte offset 0x331, CSR Addr 0x54198, Direction=N/A */
+ uint8_t reserved332; /* Byte offset 0x332, CSR Addr 0x54199, Direction=N/A */
+ uint8_t reserved333; /* Byte offset 0x333, CSR Addr 0x54199, Direction=N/A */
+ uint8_t reserved334; /* Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A */
+ uint8_t reserved335; /* Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A */
+ uint8_t reserved336; /* Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A */
+ uint8_t reserved337; /* Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A */
+ uint8_t reserved338; /* Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A */
+ uint8_t reserved339; /* Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A */
+ uint8_t reserved33a; /* Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A */
+ uint8_t reserved33b; /* Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A */
+ uint8_t reserved33c; /* Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A */
+ uint8_t reserved33d; /* Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A */
+ uint8_t reserved33e; /* Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A */
+ uint8_t reserved33f; /* Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A */
+ uint8_t reserved340; /* Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A */
+ uint8_t reserved341; /* Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A */
+ uint8_t reserved342; /* Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A */
+ uint8_t reserved343; /* Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A */
+ uint8_t reserved344; /* Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A */
+ uint8_t reserved345; /* Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A */
+ uint8_t reserved346; /* Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A */
+ uint8_t reserved347; /* Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A */
+ uint8_t reserved348; /* Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A */
+ uint8_t reserved349; /* Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A */
+ uint8_t reserved34a; /* Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A */
+ uint8_t reserved34b; /* Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A */
+ uint8_t reserved34c; /* Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A */
+ uint8_t reserved34d; /* Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A */
+ uint8_t reserved34e; /* Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A */
+ uint8_t reserved34f; /* Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A */
+ uint8_t reserved350; /* Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A */
+ uint8_t reserved351; /* Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A */
+ uint8_t reserved352; /* Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A */
+ uint8_t reserved353; /* Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A */
+ uint8_t reserved354; /* Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A */
+ uint8_t reserved355; /* Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A */
+ uint8_t reserved356; /* Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A */
+ uint8_t reserved357; /* Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A */
+ uint8_t reserved358; /* Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A */
+ uint8_t reserved359; /* Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A */
+ uint8_t reserved35a; /* Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A */
+ uint8_t reserved35b; /* Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A */
+ uint8_t reserved35c; /* Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A */
+ uint8_t reserved35d; /* Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A */
+ uint8_t reserved35e; /* Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A */
+ uint8_t reserved35f; /* Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A */
+ uint8_t reserved360; /* Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A */
+ uint8_t reserved361; /* Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A */
+ uint8_t reserved362; /* Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A */
+ uint8_t reserved363; /* Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A */
+ uint8_t reserved364; /* Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A */
+ uint8_t reserved365; /* Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A */
+ uint8_t reserved366; /* Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A */
+ uint8_t reserved367; /* Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A */
+ uint8_t reserved368; /* Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A */
+ uint8_t reserved369; /* Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A */
+ uint8_t reserved36a; /* Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A */
+ uint8_t reserved36b; /* Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A */
+ uint8_t reserved36c; /* Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A */
+ uint8_t reserved36d; /* Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A */
+ uint8_t reserved36e; /* Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A */
+ uint8_t reserved36f; /* Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A */
+ uint8_t reserved370; /* Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A */
+ uint8_t reserved371; /* Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A */
+ uint8_t reserved372; /* Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A */
+ uint8_t reserved373; /* Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A */
+ uint8_t reserved374; /* Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A */
+ uint8_t reserved375; /* Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A */
+ uint8_t reserved376; /* Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A */
+ uint8_t reserved377; /* Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A */
+ uint8_t reserved378; /* Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A */
+ uint8_t reserved379; /* Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A */
+ uint8_t reserved37a; /* Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A */
+ uint8_t reserved37b; /* Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A */
+ uint8_t reserved37c; /* Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A */
+ uint8_t reserved37d; /* Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A */
+ uint8_t reserved37e; /* Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A */
+ uint8_t reserved37f; /* Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A */
+ uint8_t reserved380; /* Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A */
+ uint8_t reserved381; /* Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A */
+ uint8_t reserved382; /* Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A */
+ uint8_t reserved383; /* Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A */
+ uint8_t reserved384; /* Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A */
+ uint8_t reserved385; /* Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A */
+ uint8_t reserved386; /* Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A */
+ uint8_t reserved387; /* Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A */
+ uint8_t reserved388; /* Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A */
+ uint8_t reserved389; /* Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A */
+ uint8_t reserved38a; /* Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A */
+ uint8_t reserved38b; /* Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A */
+ uint8_t reserved38c; /* Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A */
+ uint8_t reserved38d; /* Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A */
+ uint8_t reserved38e; /* Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A */
+ uint8_t reserved38f; /* Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A */
+ uint8_t reserved390; /* Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A */
+ uint8_t reserved391; /* Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A */
+ uint8_t reserved392; /* Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A */
+ uint8_t reserved393; /* Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A */
+ uint8_t reserved394; /* Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A */
+ uint8_t reserved395; /* Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A */
+ uint8_t reserved396; /* Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A */
+ uint8_t reserved397; /* Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A */
+ uint8_t reserved398; /* Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A */
+ uint8_t reserved399; /* Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A */
+ uint8_t reserved39a; /* Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A */
+ uint8_t reserved39b; /* Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A */
+ uint8_t reserved39c; /* Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A */
+ uint8_t reserved39d; /* Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A */
+ uint8_t reserved39e; /* Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A */
+ uint8_t reserved39f; /* Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A */
+ uint8_t reserved3a0; /* Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A */
+ uint8_t reserved3a1; /* Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A */
+ uint8_t reserved3a2; /* Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A */
+ uint8_t reserved3a3; /* Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A */
+ uint8_t reserved3a4; /* Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A */
+ uint8_t reserved3a5; /* Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A */
+ uint8_t reserved3a6; /* Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A */
+ uint8_t reserved3a7; /* Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A */
+ uint8_t reserved3a8; /* Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A */
+ uint8_t reserved3a9; /* Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A */
+ uint8_t reserved3aa; /* Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A */
+ uint8_t reserved3ab; /* Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A */
+ uint8_t reserved3ac; /* Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A */
+ uint8_t reserved3ad; /* Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A */
+ uint8_t reserved3ae; /* Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A */
+ uint8_t reserved3af; /* Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A */
+ uint8_t reserved3b0; /* Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A */
+ uint8_t reserved3b1; /* Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A */
+ uint8_t reserved3b2; /* Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A */
+ uint8_t reserved3b3; /* Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A */
+ uint8_t reserved3b4; /* Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A */
+ uint8_t reserved3b5; /* Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A */
+ uint8_t reserved3b6; /* Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A */
+ uint8_t reserved3b7; /* Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A */
+ uint8_t reserved3b8; /* Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A */
+ uint8_t reserved3b9; /* Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A */
+ uint8_t reserved3ba; /* Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A */
+ uint8_t reserved3bb; /* Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A */
+ uint8_t reserved3bc; /* Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A */
+ uint8_t reserved3bd; /* Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A */
+ uint8_t reserved3be; /* Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A */
+ uint8_t reserved3bf; /* Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A */
+ uint8_t reserved3c0; /* Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A */
+ uint8_t reserved3c1; /* Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A */
+ uint8_t reserved3c2; /* Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A */
+ uint8_t reserved3c3; /* Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A */
+ uint8_t reserved3c4; /* Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A */
+ uint8_t reserved3c5; /* Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A */
+ uint8_t reserved3c6; /* Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A */
+ uint8_t reserved3c7; /* Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A */
+ uint8_t reserved3c8; /* Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A */
+ uint8_t reserved3c9; /* Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A */
+ uint8_t reserved3ca; /* Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A */
+ uint8_t reserved3cb; /* Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A */
+ uint8_t reserved3cc; /* Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A */
+ uint8_t reserved3cd; /* Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A */
+ uint8_t reserved3ce; /* Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A */
+ uint8_t reserved3cf; /* Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A */
+ uint8_t reserved3d0; /* Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A */
+ uint8_t reserved3d1; /* Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A */
+ uint8_t reserved3d2; /* Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A */
+ uint8_t reserved3d3; /* Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A */
+ uint8_t reserved3d4; /* Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A */
+ uint8_t reserved3d5; /* Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A */
+ uint8_t reserved3d6; /* Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A */
+ uint8_t reserved3d7; /* Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A */
+ uint8_t reserved3d8; /* Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A */
+ uint8_t reserved3d9; /* Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A */
+ uint8_t reserved3da; /* Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A */
+ uint8_t reserved3db; /* Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A */
+ uint8_t reserved3dc; /* Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A */
+ uint8_t reserved3dd; /* Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A */
+ uint8_t reserved3de; /* Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A */
+ uint8_t reserved3df; /* Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A */
+ uint8_t reserved3e0; /* Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A */
+ uint8_t reserved3e1; /* Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A */
+ uint8_t reserved3e2; /* Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A */
+ uint8_t reserved3e3; /* Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A */
+ uint8_t reserved3e4; /* Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A */
+ uint8_t reserved3e5; /* Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A */
+ uint8_t reserved3e6; /* Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A */
+ uint8_t reserved3e7; /* Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A */
+ uint8_t reserved3e8; /* Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A */
+ uint8_t reserved3e9; /* Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A */
+ uint8_t reserved3ea; /* Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A */
+ uint8_t reserved3eb; /* Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A */
+ uint8_t reserved3ec; /* Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A */
+ uint8_t reserved3ed; /* Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A */
+ uint8_t reserved3ee; /* Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A */
+ uint8_t reserved3ef; /* Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A */
+ uint8_t reserved3f0; /* Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A */
+ uint8_t reserved3f1; /* Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A */
+ uint8_t reserved3f2; /* Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A */
+ uint8_t reserved3f3; /* Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A */
+ uint8_t reserved3f4; /* Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A */
+ uint8_t reserved3f5; /* Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A */
+ uint16_t alt_cas_l; /*
+ * Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ * This field must be populated if RdDBI is enabled
+ * (applicable when mr5[A12] == 1).
+ * RdDBI is dynamically disabled in certain training steps,
+ * and so the [RdDBI disabled] CAS Latency must be provided
+ * in this field.
+ * The required encoding is as follows:
+ * alt_cas_l[0] == 0: use value in mr0
+ * alt_cas_l[0] == 1: use value in alt_cas_l, i.e.,
+ * mr0{A[12],A[6],A[5],A[4],A[2]} = alt_cas_l[12,6,5,4,2]
+ * Other bits are ignored
+ */
+ uint8_t alt_wcas_l; /*
+ * Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ * This field must be populated if 2tCK write preambles are
+ * enabled (applicable when mr4[A12] == 1).
+ * 2tCK write prambles are dynamically disabled in certain
+ * training steps, and so the [1tCK write preamble] WCAS
+ * Latency must be provided in this field.
+ * The required encoding is as follows:
+ * alt_wcas_l[0] == 0: use value in mr2
+ * alt_wcas_l[0] == 1: use value in alt_wcas_l, i.e.,
+ * mr2{A[5],A[4],A[3]} = alt_wcas_l[5,4,3]
+ * Other bits are ignored
+ */
+ uint8_t d4misc; /*
+ * Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ * Contains various options for training DDR4 Devices.
+ *
+ * Bit fields:
+ *
+ * d4misc[7:5,2,1] RFU, must be zero
+ *
+ * d4misc[0] = protect memory reset
+ * 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to
+ * devices after training.
+ * 0x0 = dfi_resert_n can control BP_MEMRESERT_L to
+ * devices after training
+ *
+ * d4misc[3]: reserved
+ *
+ * d4misc[4]: DRAM reset mode
+ * 0x1 = Do not reset DRAM during devinit
+ * 0x0 = Reset DRAM during devinit
+ */
+} __packed __aligned(2);
+
+#endif /* MNPMUSRAMMSGBLOCK_DDR4_H */
diff --git a/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_lpddr4.h b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_lpddr4.h
new file mode 100644
index 0000000..fb1cd58
--- /dev/null
+++ b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_lpddr4.h
@@ -0,0 +1,925 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MNPMUSRAMMSGBLOCK_LPDDR4_H
+#define MNPMUSRAMMSGBLOCK_LPDDR4_H
+
+/* LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+struct pmu_smb_ddr_1d {
+ uint8_t reserved00; /*
+ * Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ * reserved00[0:4] RFU, must be zero
+ *
+ * reserved00[5] = Quick Rd2D during 1D Training
+ * 0x1 = Read Deskew will begin by enabling and quickly
+ * training the phy's per-lane reference voltages.
+ * Training the vrefDACs CSRs will increase the maximum 1D
+ * training time by around half a millisecond, but will
+ * improve 1D training accuracy on systems with
+ * significant voltage-offsets between lane read eyes.
+ * 0x0 = Read Deskew will assume the messageblock's
+ * phyVref setting is optimal for all lanes.
+ *
+ * reserved00[6] = Enable High Effort WrDQ1D
+ * 0x1 = WrDQ1D will conditionally retry training at
+ * several extra RxClkDly Timings. This will increase the
+ * maximum 1D training time by up to 4 extra iterations of
+ * WrDQ1D. This is only required in systems that suffer
+ * from very large, asymmetric eye-collapse when receiving
+ * PRBS patterns.
+ * 0x0 = WrDQ1D assume rxClkDly values found by SI
+ * Friendly RdDqs1D will work for receiving PRBS patterns
+ *
+ * reserved00[7] = Optimize for the special hard macros in
+ * TSMC28.
+ * 0x1 = set if the phy being trained was manufactured in
+ * any TSMC28 process node.
+ * 0x0 = otherwise, when not training a TSMC28 phy, leave
+ * this field as 0.
+ */
+ uint8_t msgmisc; /*
+ * Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ * Contains various global options for training.
+ *
+ * Bit fields:
+ *
+ * msgmisc[0] MTESTEnable
+ * 0x1 = Pulse primary digital test output bump at the end
+ * of each major training stage. This enables observation
+ * of training stage completion by observing the digital
+ * test output.
+ * 0x0 = Do not pulse primary digital test output bump
+ *
+ * msgmisc[1] SimulationOnlyReset
+ * 0x1 = Verilog only simulation option to shorten
+ * duration of DRAM reset pulse length to 1ns.
+ * Must never be set to 1 in silicon.
+ * 0x0 = Use reset pulse length specified by JEDEC
+ * standard.
+ *
+ * msgmisc[2] SimulationOnlyTraining
+ * 0x1 = Verilog only simulation option to shorten the
+ * duration of the training steps by performing fewer
+ * iterations.
+ * Must never be set to 1 in silicon.
+ * 0x0 = Use standard training duration.
+ *
+ * msgmisc[3] Disable Boot Clock
+ * 0x1 = Disable boot frequency clock when initializing
+ * DRAM. (not recommended)
+ * 0x0 = Use Boot Frequency Clock
+ *
+ * msgmisc[4] Suppress streaming messages, including
+ * assertions, regardless of hdtctrl setting.
+ * Stage Completion messages, as well as training completion
+ * and error messages are still sent depending on hdtctrl
+ * setting.
+ *
+ * msgmisc[5] PerByteMaxRdLat
+ * 0x1 = Each DBYTE will return dfi_rddata_valid at the
+ * lowest possible latency. This may result in unaligned
+ * data between bytes to be returned to the DFI.
+ * 0x0 = Every DBYTE will return dfi_rddata_valid
+ * simultaneously. This will ensure that data bytes will
+ * return aligned accesses to the DFI.
+ *
+ * msgmisc[7-6] RFU, must be zero
+ *
+ * Notes:
+ *
+ * - SimulationOnlyReset and SimulationOnlyTraining can be
+ * used to speed up simulation run times, and must never
+ * be used in real silicon. Some VIPs may have checks on
+ * DRAM reset parameters that may need to be disabled when
+ * using SimulationOnlyReset.
+ */
+ uint16_t pmurevision; /*
+ * Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ * PMU firmware revision ID
+ * After training is run, this address will contain the
+ * revision ID of the firmware
+ */
+ uint8_t pstate; /*
+ * Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ * Must be set to the target pstate to be trained
+ * 0x0 = pstate 0
+ * 0x1 = pstate 1
+ * 0x2 = pstate 2
+ * 0x3 = pstate 3
+ * All other encodings are reserved
+ */
+ uint8_t pllbypassen; /*
+ * Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ * Set according to whether target pstate uses PHY PLL
+ * bypass
+ * 0x0 = PHY PLL is enabled for target pstate
+ * 0x1 = PHY PLL is bypassed for target pstate
+ */
+ uint16_t dramfreq; /*
+ * Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ * DDR data rate for the target pstate in units of MT/s.
+ * For example enter 0x0640 for DDR1600.
+ */
+ uint8_t dfifreqratio; /*
+ * Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ * Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ * 0x1 = 1:1
+ * 0x2 = 1:2
+ * 0x4 = 1:4
+ */
+ uint8_t bpznresval; /*
+ * Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ * Overwrite the value of precision resistor connected to
+ * Phy BP_ZN
+ * 0x00 = Do not program. Use current CSR value.
+ * 0xf0 = 240 Ohm
+ * 0x78 = 120 Ohm
+ * 0x28 = 40 Ohm
+ * All other values are reserved.
+ * It is recommended to set this to 0x00.
+ */
+ uint8_t phyodtimpedance; /*
+ * Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ * Must be programmed to the termination impedance in ohms
+ * used by PHY during reads.
+ *
+ * 0x0 = Firmware skips programming (must be manually
+ * programmed by user prior to training start)
+ *
+ * See PHY databook for legal termination impedance values.
+ *
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must determine the correct value
+ * through SI simulation or other methods.
+ */
+ uint8_t phydrvimpedance; /*
+ * Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ * Must be programmed to the driver impedance in ohms used
+ * by PHY during writes for all DBYTE drivers
+ * (DQ/DM/DBI/DQS).
+ *
+ * 0x0 = Firmware skips programming (must be manually
+ * programmed by user prior to training start)
+ *
+ * See PHY databook for legal R_on driver impedance values.
+ *
+ * For digital simulation, any value can be used that is not
+ * Hi-Z. For silicon, the users must determine the correct
+ * value through SI simulation or other methods.
+ */
+ uint8_t phyvref; /*
+ * Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ * Must be programmed with the Vref level to be used by the
+ * PHY during reads
+ *
+ * The units of this field are a percentage of VDDQ
+ * according to the following equation:
+ *
+ * Receiver Vref = VDDQ*phyvref[6:0]/128
+ *
+ * For example to set Vref at 0.25*VDDQ, set this field to
+ * 0x20.
+ *
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must calculate the analytical Vref by
+ * using the impedances, terminations, and series resistance
+ * present in the system.
+ */
+ uint8_t lp4misc; /*
+ * Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ * Lp4 specific options for training.
+ *
+ * Bit fields:
+ *
+ * lp4misc[0] Enable dfi_reset_n
+ *
+ * 0x0 = (Recommended) PHY internal registers control
+ * memreset during training, and also after training.
+ * dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ *
+ * 0x1 = Enables dfi_reset_n to control memreset after
+ * training. PHY Internal registers control memreset
+ * during training only. To ensure that no glitches occur
+ * on BP_MEMRESET at the end of training, The MC must
+ * drive dfi_reset_n=1'b1 _prior to starting training_
+ *
+ * lp4misc[7-1] RFU, must be zero
+ */
+ uint8_t reserved0e; /*
+ * Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ * Bit Field for enabling optional 2D training features
+ * that impact both Rx2D and Tx2D.
+ *
+ * reserved0E[0:3]: bitTimeControl
+ * input for the amount of data bits 2D writes/reads per DQ
+ * before deciding if any specific voltage and delay setting
+ * passes or fails. Every time this input increases by 1,
+ * the number of 2D data comparisons is doubled. The 2D run
+ * time will increase proportionally to the number of bit
+ * times requested per point.
+ * 0 = 288 bits per point (legacy behavior)
+ * 1 = 576 bits per point
+ * 2 = 1.125 kilobits per point
+ * . . .
+ * 15 = 9 megabits per point
+ *
+ * reserved0E[4]: Exhaustive2D
+ * 0 = 2D optimization assumes the optimal trained point
+ * is near the 1D trained point (legacy behavior)
+ * 1 = 2D optimization searches the entire passing region
+ * at the cost of run time. Recommended for optimal
+ * results any time the optimal trained point is expected
+ * to be near the edges of the eyes instead of near the 1D
+ * trained point.
+ *
+ * reserved0E[5]: Detect Vref Eye Truncation, ignored if
+ * eyeWeight2DControl == 0.
+ * 0 = 2D optimizes for the passing region it can measure.
+ * 1 = For every eye, 2D checks If the legal voltage range
+ * truncated the eye. If the true voltage margin cannot be
+ * measured, 2D will optimize heavily for delay margin
+ * instead of using incomplete voltage margin data. Eyes
+ * that are not truncated will still be optimized using
+ * user programmed weights.
+ *
+ * reserved0E[6]: eyeWeight2DControl
+ * 0 = Use 8 bit weights for Delay_Weight2D and
+ * Voltage_Weight2D and disable TrunkV behavior.
+ * 1 = Use 4 bit weights for Delay_weight2D and
+ * Voltage_Weight2D and enable TrunkV behavior.
+ *
+ * reserved0E[7]: RFU, must be 0
+ */
+ uint8_t cstestfail; /*
+ * Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ * This field will be set if training fails on any rank.
+ * 0x0 = No failures
+ * non-zero = one or more ranks failed training
+ */
+ uint16_t sequencectrl; /*
+ * Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ * Controls the training steps to be run. Each bit
+ * corresponds to a training step.
+ *
+ * If the bit is set to 1, the training step will run.
+ * If the bit is set to 0, the training step will be
+ * skipped.
+ *
+ * Training step to bit mapping:
+ * sequencectrl[0] = Run DevInit - Device/phy
+ * initialization. Should always be set.
+ * sequencectrl[1] = Run WrLvl - Write leveling
+ * sequencectrl[2] = Run RxEn - Read gate training
+ * sequencectrl[3] = Run RdDQS1D - 1d read dqs training
+ * sequencectrl[4] = Run WrDQ1D - 1d write dq training
+ * sequencectrl[5] = RFU, must be zero
+ * sequencectrl[6] = RFU, must be zero
+ * sequencectrl[7] = RFU, must be zero
+ * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew
+ * training
+ * sequencectrl[9] = Run MxRdLat - Max read latency training
+ * sequencectrl[11-10] = RFU, must be zero
+ * sequencectrl[12] = Run LPCA - CA Training
+ * sequencectrl[15-13] = RFU, must be zero
+ */
+ uint8_t hdtctrl; /*
+ * Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ * To control the total number of debug messages, a
+ * verbosity subfield (hdtctrl, Hardware Debug Trace
+ * Control) exists in the message block. Every message has a
+ * verbosity level associated with it, and as the hdtctrl
+ * value is increased, less important s messages stop being
+ * sent through the mailboxes. The meanings of several major
+ * hdtctrl thresholds are explained below:
+ *
+ * 0x04 = Maximal debug messages (e.g., Eye contours)
+ * 0x05 = Detailed debug messages (e.g. Eye delays)
+ * 0x0A = Coarse debug messages (e.g. rank information)
+ * 0xC8 = Stage completion
+ * 0xC9 = Assertion messages
+ * 0xFF = Firmware completion messages only
+ */
+ uint8_t reserved13; /*
+ * Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ *
+ * 0 = Default operation, unchanged.
+ * Others = RD DQ calibration Training steps are completed
+ * with user specified pattern.
+ */
+ uint8_t reserved14; /*
+ * Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ * Configure rd2D search iteration from a starting seed
+ * point:
+ *
+ * reserved14[5:0]: If reserved14[6] is 0, Number of search
+ * iterations (if 0, then default is 20); otherwise if this
+ * value non zero, this value is used as a delta to filter
+ * out points during the averaging: when averaging over a
+ * dimension (delay or voltage), the points having a margin
+ * smaller than the max of the eye in this dimension by at
+ * least this delta value are filtered out.
+ *
+ * reserved14[6]: If set, instead of search, extract center
+ * using an averaging function over the eye surface area,
+ * where some points can be filtered out using
+ * reserved14[5:0]
+ *
+ * reserved14[7]: if set, start search with large step size,
+ * decreasing at each 4 iterations, down to 1 (do not care
+ * if reserved14[6] is set)
+ */
+ uint8_t reserved15; /*
+ * Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ * Configure wr2D search iteration from a starting seed
+ * point:
+ *
+ * reserved15[5:0]: If reserved15[6] is 0, Number of search
+ * iterations (if 0, then default is 20); otherwise if this
+ * value non zero, this value is used as a delta to filter
+ * out points during the averaging: when averaging over a
+ * dimension (delay or voltage), the points having a margin
+ * smaller than the max of the eye in this dimension by at
+ * least this delta value are filtered out.
+ *
+ * reserved15[6]: If set, instead of search, extract center
+ * using an averaging function over the eye surface area,
+ * where some points can be filtered out using
+ * reserved15[5:0]
+ *
+ * reserved15[7]: if set, start search with large step size,
+ * decreasing at each 4 iterations, down to 1 (do not care
+ * if reserved15[6] is set)
+ */
+ uint8_t dfimrlmargin; /*
+ * Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ * Margin added to smallest passing trained DFI Max Read
+ * Latency value, in units of DFI clocks. Recommended to be
+ * >= 1.
+ *
+ * This margin must include the maximum positive drift
+ * expected in tDQSCK over the target temperature and
+ * voltage range of the users system.
+ */
+ uint8_t reserved17; /*
+ * Byte offset 0x17, CSR Addr 0x5400b, Direction=In
+ * Configure DB from which extra info is dump during 2D
+ * training when maximal debug is set:
+ *
+ * reserved17[3:0]: first DB
+ *
+ * reserved17[7:4]: number of DB, including first DB (if 0,
+ * no extra debug per DB is dump)
+ */
+ uint8_t usebroadcastmr; /*
+ * Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ * Training firmware can optionally set per rank mode
+ * register values for DRAM partial array self-refresh
+ * features if desired.
+ *
+ * 0x0 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 for rank 0
+ * channel A
+ * Use mr<1:4, 11:14, 16:17, 22, 24>_b0 for rank 0
+ * channel B
+ * Use mr<1:4, 11:14, 16:17, 22, 24>_a1 for rank 1
+ * channel A
+ * Use mr<1:4, 11:14, 16:17, 22, 24>_b1 for rank 1
+ * channel B
+ *
+ * 0x1 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 setting for
+ * all channels/ranks
+ *
+ * It is recommended in most LPDDR4 system configurations
+ * to set this to 1.
+ * It is recommended in LPDDR4x system configurations to
+ * set this to 0.
+ */
+ uint8_t lp4quickboot; /*
+ * Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ * Enable Quickboot. It must be set to 0x0 since Quickboot
+ * is only supported in dedicated Quickboot firmware.
+ */
+ uint8_t reserved1a; /*
+ * Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ * Input for constraining the range of vref(DQ) values
+ * training will collect data for, usually reducing training
+ * time. However, too large of a voltage range may cause
+ * longer 2D training times while too small of a voltage
+ * range may truncate passing regions. When in doubt, leave
+ * this field set to 0.
+ * Used by 2D stages: Rd2D, Wr2D
+ *
+ * reserved1A[0-3]: Rd2D Voltage Range
+ * 0 = Training will search all phy vref(DQ) settings
+ * 1 = limit to +/-2 %VDDQ from phyVref
+ * 2 = limit to +/-4 %VDDQ from phyVref
+ * . . .
+ * 15 = limit to +/-30% VDDQ from phyVref
+ *
+ * reserved1A[4-7]: Wr2D Voltage Range
+ * 0 = Training will search all dram vref(DQ) settings
+ * 1 = limit to +/-2 %VDDQ from mr14
+ * 2 = limit to +/-4 %VDDQ from mr14
+ * . . .
+ * 15 = limit to +/-30% VDDQ from mr14
+ */
+ uint8_t catrainopt; /*
+ * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ * CA training option bit field
+ * [0] CA VREF Training
+ * 1 = Enable CA VREF Training
+ * 0 = Disable CA VREF Training
+ * WARNING: catrainopt[0] must be set to the same value in
+ * 1D and 2D training.
+ *
+ * [1] Train terminated Rank only
+ * 1 = Only train terminated rank in CA training
+ * 0 = Train all ranks in CA training
+ *
+ * [2-7] RFU must be zero
+ */
+ uint8_t x8mode; /*
+ * Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ * X8 mode configuration:
+ * 0x0 = x16 configuration for all devices
+ * 0xF = x8 configuration for all devices
+ * All other values are RFU
+ */
+ uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */
+ uint8_t reserved1e; /* Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A */
+ uint8_t share2dvrefresult; /*
+ * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ * Bitmap that designates the phy's vref source for every
+ * pstate
+ * If share2dvrefresult[x] = 0, then after 2D training,
+ * pstate x will continue using the phyVref provided in
+ * pstate x's 1D messageblock.
+ * If share2dvrefresult[x] = 1, then after 2D training,
+ * pstate x will use the per-lane VrefDAC0/1 CSRs trained by
+ * 2d training.
+ */
+ uint8_t reserved20; /* Byte offset 0x20, CSR Addr 0x54010, Direction=N/A */
+ uint8_t reserved21; /* Byte offset 0x21, CSR Addr 0x54010, Direction=N/A */
+ uint16_t phyconfigoverride; /*
+ * Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ * Override PhyConfig csr.
+ * 0x0: Use hardware csr value for PhyConfing
+ * (recommended)
+ * Other values: Use value for PhyConfig instead of
+ * Hardware value.
+ *
+ */
+ uint8_t enableddqscha; /*
+ * Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ * Total number of DQ bits enabled in PHY Channel A
+ */
+ uint8_t cspresentcha; /*
+ * Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ * Indicates presence of DRAM at each chip select for PHY
+ * channel A.
+ * 0x1 = CS0 is populated with DRAM
+ * 0x3 = CS0 and CS1 are populated with DRAM
+ *
+ * All other encodings are illegal
+ */
+ int8_t cdd_cha_rr_1_0; /*
+ * Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 0
+ * on Channel A.
+ */
+ int8_t cdd_cha_rr_0_1; /*
+ * Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 1
+ * on Channel A.
+ */
+ int8_t cdd_cha_rw_1_1; /*
+ * Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to cs 1
+ * on Channel A.
+ */
+ int8_t cdd_cha_rw_1_0; /*
+ * Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to cs 0
+ * on Channel A.
+ */
+ int8_t cdd_cha_rw_0_1; /*
+ * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to cs 1
+ * on Channel A.
+ */
+ int8_t cdd_cha_rw_0_0; /*
+ * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs0 to cs 0
+ * on Channel A.
+ */
+ int8_t cdd_cha_wr_1_1; /*
+ * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to cs 1
+ * on Channel A.
+ */
+ int8_t cdd_cha_wr_1_0; /*
+ * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to cs 0
+ * on Channel A.
+ */
+ int8_t cdd_cha_wr_0_1; /*
+ * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to cs 1
+ * on Channel A.
+ */
+ int8_t cdd_cha_wr_0_0; /*
+ * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to cs 0
+ * on Channel A.
+ */
+ int8_t cdd_cha_ww_1_0; /*
+ * Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 0 on Channel A.
+ */
+ int8_t cdd_cha_ww_0_1; /*
+ * Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 1 on Channel A.
+ */
+ uint8_t mr1_a0; /*
+ * Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ * Value to be programmed in DRAM Mode Register 1
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr2_a0; /*
+ * Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ * Value to be programmed in DRAM Mode Register 2
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr3_a0; /*
+ * Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ * Value to be programmed in DRAM Mode Register 3
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr4_a0; /*
+ * Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ * Value to be programmed in DRAM Mode Register 4
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr11_a0; /*
+ * Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ * Value to be programmed in DRAM Mode Register 11
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr12_a0; /*
+ * Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ * Value to be programmed in DRAM Mode Register 12
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr13_a0; /*
+ * Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ * Value to be programmed in DRAM Mode Register 13
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr14_a0; /*
+ * Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ * Value to be programmed in DRAM Mode Register 14
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr16_a0; /*
+ * Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ * Value to be programmed in DRAM Mode Register 16
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr17_a0; /*
+ * Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ * Value to be programmed in DRAM Mode Register 17
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr22_a0; /*
+ * Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ * Value to be programmed in DRAM Mode Register 22
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr24_a0; /*
+ * Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ * Value to be programmed in DRAM Mode Register 24
+ * {Channel A, Rank 0}
+ */
+ uint8_t mr1_a1; /*
+ * Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ * Value to be programmed in DRAM Mode Register 1
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr2_a1; /*
+ * Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ * Value to be programmed in DRAM Mode Register 2
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr3_a1; /*
+ * Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ * Value to be programmed in DRAM Mode Register 3
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr4_a1; /*
+ * Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ * Value to be programmed in DRAM Mode Register 4
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr11_a1; /*
+ * Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ * Value to be programmed in DRAM Mode Register 11
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr12_a1; /*
+ * Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ * Value to be programmed in DRAM Mode Register 12
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr13_a1; /*
+ * Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ * Value to be programmed in DRAM Mode Register 13
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr14_a1; /*
+ * Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ * Value to be programmed in DRAM Mode Register 14
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr16_a1; /*
+ * Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ * Value to be programmed in DRAM Mode Register 16
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr17_a1; /*
+ * Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ * Value to be programmed in DRAM Mode Register 17
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr22_a1; /*
+ * Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ * Value to be programmed in DRAM Mode Register 22
+ * {Channel A, Rank 1}
+ */
+ uint8_t mr24_a1; /*
+ * Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ * Value to be programmed in DRAM Mode Register 24
+ * {Channel A, Rank 1}
+ */
+ uint8_t caterminatingrankcha; /* Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ * Terminating Rank for CA bus on Channel A
+ * 0x0 = Rank 0 is terminating rank
+ * 0x1 = Rank 1 is terminating rank
+ */
+ uint8_t reserved4b; /* Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A */
+ uint8_t reserved4c; /* Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A */
+ uint8_t reserved4d; /* Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A */
+ uint8_t reserved4e; /* Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A */
+ uint8_t reserved4f; /* Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A */
+ uint8_t reserved50; /* Byte offset 0x50, CSR Addr 0x54028, Direction=N/A */
+ uint8_t reserved51; /* Byte offset 0x51, CSR Addr 0x54028, Direction=N/A */
+ uint8_t reserved52; /* Byte offset 0x52, CSR Addr 0x54029, Direction=N/A */
+ uint8_t reserved53; /* Byte offset 0x53, CSR Addr 0x54029, Direction=N/A */
+ uint8_t reserved54; /* Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A */
+ uint8_t reserved55; /* Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A */
+ uint8_t reserved56; /* Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A */
+ uint8_t enableddqschb; /*
+ * Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ * Total number of DQ bits enabled in PHY Channel B
+ */
+ uint8_t cspresentchb; /*
+ * Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ * Indicates presence of DRAM at each chip select for PHY
+ * channel B.
+ * 0x0 = No chip selects are populated with DRAM
+ * 0x1 = CS0 is populated with DRAM
+ * 0x3 = CS0 and CS1 are populated with DRAM
+ *
+ * All other encodings are illegal
+ */
+ int8_t cdd_chb_rr_1_0; /*
+ * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 1 to cs 0
+ * on Channel B.
+ */
+ int8_t cdd_chb_rr_0_1; /*
+ * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ * This is a signed integer value.
+ * Read to read critical delay difference from cs 0 to cs 1
+ * on Channel B.
+ */
+ int8_t cdd_chb_rw_1_1; /*
+ * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to cs 1
+ * on Channel B.
+ */
+ int8_t cdd_chb_rw_1_0; /*
+ * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 1 to cs 0
+ * on Channel B.
+ */
+ int8_t cdd_chb_rw_0_1; /*
+ * Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs 0 to cs 1
+ * on Channel B.
+ */
+ int8_t cdd_chb_rw_0_0; /*
+ * Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ * This is a signed integer value.
+ * Read to write critical delay difference from cs01 to cs 0
+ * on Channel B.
+ */
+ int8_t cdd_chb_wr_1_1; /*
+ * Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to cs 1
+ * on Channel B.
+ */
+ int8_t cdd_chb_wr_1_0; /*
+ * Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 1 to cs 0
+ * on Channel B.
+ */
+ int8_t cdd_chb_wr_0_1; /*
+ * Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to cs 1
+ * on Channel B.
+ */
+ int8_t cdd_chb_wr_0_0; /*
+ * Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ * This is a signed integer value.
+ * Write to read critical delay difference from cs 0 to cs 0
+ * on Channel B.
+ */
+ int8_t cdd_chb_ww_1_0; /*
+ * Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 1 to cs
+ * 0 on Channel B.
+ */
+ int8_t cdd_chb_ww_0_1; /*
+ * Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ * This is a signed integer value.
+ * Write to write critical delay difference from cs 0 to cs
+ * 1 on Channel B.
+ */
+ uint8_t mr1_b0; /*
+ * Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ * Value to be programmed in DRAM Mode Register 1
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr2_b0; /*
+ * Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ * Value to be programmed in DRAM Mode Register 2
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr3_b0; /*
+ * Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ * Value to be programmed in DRAM Mode Register 3
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr4_b0; /*
+ * Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ * Value to be programmed in DRAM Mode Register 4
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr11_b0; /*
+ * Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ * Value to be programmed in DRAM Mode Register 11
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr12_b0; /*
+ * Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ * Value to be programmed in DRAM Mode Register 12
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr13_b0; /*
+ * Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ * Value to be programmed in DRAM Mode Register 13
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr14_b0; /*
+ * Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ * Value to be programmed in DRAM Mode Register 14
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr16_b0; /*
+ * Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ * Value to be programmed in DRAM Mode Register 16
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr17_b0; /*
+ * Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ * Value to be programmed in DRAM Mode Register 17
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr22_b0; /*
+ * Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ * Value to be programmed in DRAM Mode Register 22
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr24_b0; /*
+ * Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ * Value to be programmed in DRAM Mode Register 24
+ * {Channel B, Rank 0}
+ */
+ uint8_t mr1_b1; /*
+ * Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ * Value to be programmed in DRAM Mode Register 1
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr2_b1; /*
+ * Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ * Value to be programmed in DRAM Mode Register 2
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr3_b1; /*
+ * Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ * Value to be programmed in DRAM Mode Register 3
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr4_b1; /*
+ * Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ * Value to be programmed in DRAM Mode Register 4
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr11_b1; /*
+ * Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ * Value to be programmed in DRAM Mode Register 11
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr12_b1; /*
+ * Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ * Value to be programmed in DRAM Mode Register 12
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr13_b1; /*
+ * Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ * Value to be programmed in DRAM Mode Register 13
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr14_b1; /*
+ * Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ * Value to be programmed in DRAM Mode Register 14
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr16_b1; /*
+ * Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ * Value to be programmed in DRAM Mode Register 16
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr17_b1; /*
+ * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ * Value to be programmed in DRAM Mode Register 17
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr22_b1; /*
+ * Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ * Value to be programmed in DRAM Mode Register 22
+ * {Channel B, Rank 1}
+ */
+ uint8_t mr24_b1; /*
+ * Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ * Value to be programmed in DRAM Mode Register 24
+ * {Channel B, Rank 1}
+ */
+ uint8_t caterminatingrankchb; /* Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ * Terminating Rank for CA bus on Channel B
+ * 0x0 = Rank 0 is terminating rank
+ * 0x1 = Rank 1 is terminating rank
+ */
+ uint8_t reserved7e; /* Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A */
+ uint8_t reserved7f; /* Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A */
+ uint8_t reserved80; /* Byte offset 0x80, CSR Addr 0x54040, Direction=N/A */
+ uint8_t reserved81; /* Byte offset 0x81, CSR Addr 0x54040, Direction=N/A */
+ uint8_t reserved82; /* Byte offset 0x82, CSR Addr 0x54041, Direction=N/A */
+ uint8_t reserved83; /* Byte offset 0x83, CSR Addr 0x54041, Direction=N/A */
+ uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */
+ uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */
+ uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */
+ uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */
+ uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */
+ uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */
+} __packed __aligned(2);
+
+#endif /* MNPMUSRAMMSGBLOCK_LPDDR4_H */
diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_csr_all_cdefines.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_csr_all_cdefines.h
new file mode 100644
index 0000000..99a8c4c
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_csr_all_cdefines.h
@@ -0,0 +1,6944 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DDRPHY_PHYINIT_CSR_ALL_DEFINES_H
+#define DDRPHY_PHYINIT_CSR_ALL_DEFINES_H
+
+/* ANIBx register offsets */
+#define CSR_MTESTMUXSEL_ADDR 0x1AU
+#define CSR_AFORCEDRVCONT_ADDR 0x27U
+#define CSR_AFORCETRICONT_ADDR 0x28U
+#define CSR_ATXIMPEDANCE_ADDR 0x43U
+#define CSR_ATESTPRBSERR_ADDR 0x53U
+#define CSR_ATXSLEWRATE_ADDR 0x55U
+#define CSR_ATESTPRBSERRCNT_ADDR 0x56U
+#define CSR_ATXDLY_ADDR 0x80U
+
+/* DBYTEx register offsets */
+#define CSR_DBYTEMISCMODE_ADDR 0x0U
+#define CSR_TSMBYTE0_ADDR 0x1U
+#define CSR_TRAININGPARAM_ADDR 0x2U
+#define CSR_USEDQSENREPLICA_ADDR 0x3U
+#define CSR_RXTRAINPATTERNENABLE_ADDR 0x10U
+#define CSR_TSMBYTE1_ADDR 0x11U
+#define CSR_TSMBYTE2_ADDR 0x12U
+#define CSR_TSMBYTE3_ADDR 0x13U
+#define CSR_TSMBYTE4_ADDR 0x14U
+#define CSR_TESTMODECONFIG_ADDR 0x17U
+#define CSR_TSMBYTE5_ADDR 0x18U
+/* MTESTMUXSEL already defined in ANIBx section */
+#define CSR_DTSMTRAINMODECTRL_ADDR 0x1FU
+#define CSR_DFIMRL_ADDR 0x20U
+#define CSR_ASYNCDBYTEMODE_ADDR 0x24U
+#define CSR_ASYNCDBYTETXEN_ADDR 0x26U
+#define CSR_ASYNCDBYTETXDATA_ADDR 0x28U
+#define CSR_ASYNCDBYTERXDATA_ADDR 0x2AU
+#define CSR_VREFDAC1_ADDR 0x30U
+#define CSR_TRAININGCNTR_ADDR 0x32U
+#define CSR_VREFDAC0_ADDR 0x40U
+#define CSR_TXIMPEDANCECTRL0_ADDR 0x41U
+#define CSR_DQDQSRCVCNTRL_ADDR 0x43U
+#define CSR_TXEQUALIZATIONMODE_ADDR 0x48U
+#define CSR_TXIMPEDANCECTRL1_ADDR 0x49U
+#define CSR_DQDQSRCVCNTRL1_ADDR 0x4AU
+#define CSR_TXIMPEDANCECTRL2_ADDR 0x4BU
+#define CSR_DQDQSRCVCNTRL2_ADDR 0x4CU
+#define CSR_TXODTDRVSTREN_ADDR 0x4DU
+#define CSR_RXFIFOCHECKSTATUS_ADDR 0x56U
+#define CSR_RXFIFOCHECKERRVALUES_ADDR 0x57U
+#define CSR_RXFIFOINFO_ADDR 0x58U
+#define CSR_RXFIFOVISIBILITY_ADDR 0x59U
+#define CSR_RXFIFOCONTENTSDQ3210_ADDR 0x5AU
+#define CSR_RXFIFOCONTENTSDQ7654_ADDR 0x5BU
+#define CSR_RXFIFOCONTENTSDBI_ADDR 0x5CU
+#define CSR_TXSLEWRATE_ADDR 0x5FU
+#define CSR_TRAININGINCDECDTSMEN_ADDR 0x62U
+#define CSR_RXPBDLYTG0_ADDR 0x68U
+#define CSR_RXPBDLYTG1_ADDR 0x69U
+#define CSR_RXPBDLYTG2_ADDR 0x6AU
+#define CSR_RXPBDLYTG3_ADDR 0x6BU
+#define CSR_RXENDLYTG0_ADDR 0x80U
+#define CSR_RXENDLYTG1_ADDR 0x81U
+#define CSR_RXENDLYTG2_ADDR 0x82U
+#define CSR_RXENDLYTG3_ADDR 0x83U
+#define CSR_RXCLKDLYTG0_ADDR 0x8CU
+#define CSR_RXCLKDLYTG1_ADDR 0x8DU
+#define CSR_RXCLKDLYTG2_ADDR 0x8EU
+#define CSR_RXCLKDLYTG3_ADDR 0x8FU
+#define CSR_RXCLKCDLYTG0_ADDR 0x90U
+#define CSR_RXCLKCDLYTG1_ADDR 0x91U
+#define CSR_RXCLKCDLYTG2_ADDR 0x92U
+#define CSR_RXCLKCDLYTG3_ADDR 0x93U
+#define CSR_DQ0LNSEL_ADDR 0xA0U
+#define CSR_DQ1LNSEL_ADDR 0xA1U
+#define CSR_DQ2LNSEL_ADDR 0xA2U
+#define CSR_DQ3LNSEL_ADDR 0xA3U
+#define CSR_DQ4LNSEL_ADDR 0xA4U
+#define CSR_DQ5LNSEL_ADDR 0xA5U
+#define CSR_DQ6LNSEL_ADDR 0xA6U
+#define CSR_DQ7LNSEL_ADDR 0xA7U
+#define CSR_PPTCTLSTATIC_ADDR 0xAAU
+#define CSR_PPTCTLDYN_ADDR 0xABU
+#define CSR_PPTINFO_ADDR 0xACU
+#define CSR_PPTRXENEVNT_ADDR 0xADU
+#define CSR_PPTDQSCNTINVTRNTG0_ADDR 0xAEU
+#define CSR_PPTDQSCNTINVTRNTG1_ADDR 0xAFU
+#define CSR_DTSMBLANKINGCTRL_ADDR 0xB1U
+#define CSR_TSM0_ADDR 0xB2U
+#define CSR_TSM1_ADDR 0xB3U
+#define CSR_TSM2_ADDR 0xB4U
+#define CSR_TSM3_ADDR 0xB5U
+#define CSR_TXCHKDATASELECTS_ADDR 0xB6U
+#define CSR_DTSMUPTHLDXINGIND_ADDR 0xB7U
+#define CSR_DTSMLOTHLDXINGIND_ADDR 0xB8U
+#define CSR_DBYTEALLDTSMCTRL0_ADDR 0xB9U
+#define CSR_DBYTEALLDTSMCTRL1_ADDR 0xBAU
+#define CSR_DBYTEALLDTSMCTRL2_ADDR 0xBBU
+#define CSR_TXDQDLYTG0_ADDR 0xC0U
+#define CSR_TXDQDLYTG1_ADDR 0xC1U
+#define CSR_TXDQDLYTG2_ADDR 0xC2U
+#define CSR_TXDQDLYTG3_ADDR 0xC3U
+#define CSR_TXDQSDLYTG0_ADDR 0xD0U
+#define CSR_TXDQSDLYTG1_ADDR 0xD1U
+#define CSR_TXDQSDLYTG2_ADDR 0xD2U
+#define CSR_TXDQSDLYTG3_ADDR 0xD3U
+#define CSR_DXLCDLSTATUS_ADDR 0xE4U
+
+/* MASTER0 register offsets */
+#define CSR_RXFIFOINIT_ADDR 0x0U
+#define CSR_FORCECLKDISABLE_ADDR 0x1U
+#define CSR_CLOCKINGCTRL_ADDR 0x2U
+#define CSR_FORCEINTERNALUPDATE_ADDR 0x3U
+#define CSR_PHYCONFIG_ADDR 0x4U
+#define CSR_PGCR_ADDR 0x5U
+#define CSR_TESTBUMPCNTRL1_ADDR 0x7U
+#define CSR_CALUCLKINFO_ADDR 0x8U
+#define CSR_TESTBUMPCNTRL_ADDR 0xAU
+#define CSR_SEQ0BDLY0_ADDR 0xBU
+#define CSR_SEQ0BDLY1_ADDR 0xCU
+#define CSR_SEQ0BDLY2_ADDR 0xDU
+#define CSR_SEQ0BDLY3_ADDR 0xEU
+#define CSR_PHYALERTSTATUS_ADDR 0xFU
+#define CSR_PPTTRAINSETUP_ADDR 0x10U
+#define CSR_PPTTRAINSETUP2_ADDR 0x11U
+#define CSR_ATESTMODE_ADDR 0x12U
+#define CSR_TXCALBINP_ADDR 0x14U
+#define CSR_TXCALBINN_ADDR 0x15U
+#define CSR_TXCALPOVR_ADDR 0x16U
+#define CSR_TXCALNOVR_ADDR 0x17U
+#define CSR_DFIMODE_ADDR 0x18U
+#define CSR_TRISTATEMODECA_ADDR 0x19U
+/* MTESTMUXSEL already defined in ANIBx section */
+#define CSR_MTESTPGMINFO_ADDR 0x1BU
+#define CSR_DYNPWRDNUP_ADDR 0x1CU
+#define CSR_PMIENABLE_ADDR 0x1DU
+#define CSR_PHYTID_ADDR 0x1EU
+#define CSR_HWTMRL_ADDR 0x20U
+#define CSR_DFIPHYUPD_ADDR 0x21U
+#define CSR_PDAMRSWRITEMODE_ADDR 0x22U
+#define CSR_DFIGEARDOWNCTL_ADDR 0x23U
+#define CSR_DQSPREAMBLECONTROL_ADDR 0x24U
+#define CSR_MASTERX4CONFIG_ADDR 0x25U
+#define CSR_WRLEVBITS_ADDR 0x26U
+#define CSR_ENABLECSMULTICAST_ADDR 0x27U
+#define CSR_HWTLPCSMULTICAST_ADDR 0x28U
+#define CSR_ACX4ANIBDIS_ADDR 0x2CU
+#define CSR_DMIPINPRESENT_ADDR 0x2DU
+#define CSR_ARDPTRINITVAL_ADDR 0x2EU
+#define CSR_DB0LCDLCALPHDETOUT_ADDR 0x30U
+#define CSR_DB1LCDLCALPHDETOUT_ADDR 0x31U
+#define CSR_DB2LCDLCALPHDETOUT_ADDR 0x32U
+#define CSR_DB3LCDLCALPHDETOUT_ADDR 0x33U
+#define CSR_DB4LCDLCALPHDETOUT_ADDR 0x34U
+#define CSR_DB5LCDLCALPHDETOUT_ADDR 0x35U
+#define CSR_DB6LCDLCALPHDETOUT_ADDR 0x36U
+#define CSR_DB7LCDLCALPHDETOUT_ADDR 0x37U
+#define CSR_DB8LCDLCALPHDETOUT_ADDR 0x38U
+#define CSR_DB9LCDLCALPHDETOUT_ADDR 0x39U
+#define CSR_DBYTEDLLMODECNTRL_ADDR 0x3AU
+#define CSR_DBYTERXENTRAIN_ADDR 0x3BU
+#define CSR_ANLCDLCALPHDETOUT_ADDR 0x3FU
+#define CSR_CALOFFSETS_ADDR 0x45U
+#define CSR_SARINITVALS_ADDR 0x47U
+#define CSR_CALPEXTOVR_ADDR 0x49U
+#define CSR_CALCMPR5OVR_ADDR 0x4AU
+#define CSR_CALNINTOVR_ADDR 0x4BU
+#define CSR_CALDRVSTR0_ADDR 0x50U
+#define CSR_PROCODTCTL_ADDR 0x55U
+#define CSR_PROCODTTIMECTL_ADDR 0x56U
+#define CSR_MEMALERTCONTROL_ADDR 0x5BU
+#define CSR_MEMALERTCONTROL2_ADDR 0x5CU
+#define CSR_MEMRESETL_ADDR 0x60U
+#define CSR_PUBMODE_ADDR 0x6EU
+#define CSR_MISCPHYSTATUS_ADDR 0x6FU
+#define CSR_CORELOOPBACKSEL_ADDR 0x70U
+#define CSR_DLLTRAINPARAM_ADDR 0x71U
+#define CSR_HWTLPCSENA_ADDR 0x72U
+#define CSR_HWTLPCSENB_ADDR 0x73U
+#define CSR_HWTLPCSENBYPASS_ADDR 0x74U
+#define CSR_DFICAMODE_ADDR 0x75U
+#define CSR_HWTCACTL_ADDR 0x76U
+#define CSR_HWTCAMODE_ADDR 0x77U
+#define CSR_DLLCONTROL_ADDR 0x78U
+#define CSR_PULSEDLLUPDATEPHASE_ADDR 0x79U
+#define CSR_HWTCONTROLOVR0_ADDR 0x7AU
+#define CSR_HWTCONTROLOVR1_ADDR 0x7BU
+#define CSR_DLLGAINCTL_ADDR 0x7CU
+#define CSR_DLLLOCKPARAM_ADDR 0x7DU
+#define CSR_HWTCONTROLVAL0_ADDR 0x7EU
+#define CSR_HWTCONTROLVAL1_ADDR 0x7FU
+#define CSR_ACSMGLBLSTART_ADDR 0x81U
+#define CSR_ACSMGLBLSGLSTPCTRL_ADDR 0x82U
+#define CSR_LCDLCALPHASE_ADDR 0x84U
+#define CSR_LCDLCALCTRL_ADDR 0x85U
+#define CSR_CALRATE_ADDR 0x88U
+#define CSR_CALZAP_ADDR 0x89U
+#define CSR_PSTATE_ADDR 0x8BU
+#define CSR_CALPREDRIVEROVERRIDE_ADDR 0x8CU
+#define CSR_PLLOUTGATECONTROL_ADDR 0x8DU
+#define CSR_UCMEMRESETCONTROL_ADDR 0x8FU
+#define CSR_PORCONTROL_ADDR 0x90U
+#define CSR_CALBUSY_ADDR 0x97U
+#define CSR_CALMISC2_ADDR 0x98U
+#define CSR_CALMISC_ADDR 0x9AU
+#define CSR_CALVREFS_ADDR 0x9BU
+#define CSR_CALCMPR5_ADDR 0x9CU
+#define CSR_CALNINT_ADDR 0x9DU
+#define CSR_CALPEXT_ADDR 0x9EU
+#define CSR_CALCMPINVERT_ADDR 0xA8U
+#define CSR_CALCMPANACNTRL_ADDR 0xAEU
+#define CSR_DFIRDDATACSDESTMAP_ADDR 0xB0U
+#define CSR_VREFINGLOBAL_ADDR 0xB2U
+#define CSR_DFIWRDATACSDESTMAP_ADDR 0xB4U
+#define CSR_MASUPDGOODCTR_ADDR 0xB5U
+#define CSR_PHYUPD0GOODCTR_ADDR 0xB6U
+#define CSR_PHYUPD1GOODCTR_ADDR 0xB7U
+#define CSR_CTLUPD0GOODCTR_ADDR 0xB8U
+#define CSR_CTLUPD1GOODCTR_ADDR 0xB9U
+#define CSR_MASUPDFAILCTR_ADDR 0xBAU
+#define CSR_PHYUPD0FAILCTR_ADDR 0xBBU
+#define CSR_PHYUPD1FAILCTR_ADDR 0xBCU
+#define CSR_PHYPERFCTRENABLE_ADDR 0xBDU
+#define CSR_DFIWRRDDATACSCONFIG_ADDR 0xBEU
+#define CSR_PLLPWRDN_ADDR 0xC3U
+#define CSR_PLLRESET_ADDR 0xC4U
+#define CSR_PLLCTRL2_ADDR 0xC5U
+#define CSR_PLLCTRL0_ADDR 0xC6U
+#define CSR_PLLCTRL1_ADDR 0xC7U
+#define CSR_PLLTST_ADDR 0xC8U
+#define CSR_PLLLOCKSTATUS_ADDR 0xC9U
+#define CSR_PLLTESTMODE_ADDR 0xCAU
+#define CSR_PLLCTRL3_ADDR 0xCBU
+#define CSR_PLLCTRL4_ADDR 0xCCU
+#define CSR_PLLENDOFCAL_ADDR 0xCDU
+#define CSR_PLLSTANDBYEFF_ADDR 0xCEU
+#define CSR_PLLDACVALOUT_ADDR 0xCFU
+#define CSR_DLYTESTSEQ_ADDR 0xD0U
+#define CSR_DLYTESTRINGSELDB_ADDR 0xD1U
+#define CSR_DLYTESTRINGSELAC_ADDR 0xD2U
+#define CSR_DLYTESTCNTDFICLKIV_ADDR 0xD3U
+#define CSR_DLYTESTCNTDFICLK_ADDR 0xD4U
+#define CSR_DLYTESTCNTRINGOSCDB0_ADDR 0xD5U
+#define CSR_DLYTESTCNTRINGOSCDB1_ADDR 0xD6U
+#define CSR_DLYTESTCNTRINGOSCDB2_ADDR 0xD7U
+#define CSR_DLYTESTCNTRINGOSCDB3_ADDR 0xD8U
+#define CSR_DLYTESTCNTRINGOSCDB4_ADDR 0xD9U
+#define CSR_DLYTESTCNTRINGOSCDB5_ADDR 0xDAU
+#define CSR_DLYTESTCNTRINGOSCDB6_ADDR 0xDBU
+#define CSR_DLYTESTCNTRINGOSCDB7_ADDR 0xDCU
+#define CSR_DLYTESTCNTRINGOSCDB8_ADDR 0xDDU
+#define CSR_DLYTESTCNTRINGOSCDB9_ADDR 0xDEU
+#define CSR_DLYTESTCNTRINGOSCAC_ADDR 0xDFU
+#define CSR_MSTLCDLDBGCNTL_ADDR 0xE0U
+#define CSR_MSTLCDL0DBGRES_ADDR 0xE1U
+#define CSR_MSTLCDL1DBGRES_ADDR 0xE2U
+#define CSR_LCDLDBGCNTL_ADDR 0xE3U
+#define CSR_ACLCDLSTATUS_ADDR 0xE4U
+#define CSR_CUSTPHYREV_ADDR 0xEDU
+#define CSR_PHYREV_ADDR 0xEEU
+#define CSR_LP3EXITSEQ0BSTARTVECTOR_ADDR 0xEFU
+#define CSR_DFIFREQXLAT0_ADDR 0xF0U
+#define CSR_DFIFREQXLAT1_ADDR 0xF1U
+#define CSR_DFIFREQXLAT2_ADDR 0xF2U
+#define CSR_DFIFREQXLAT3_ADDR 0xF3U
+#define CSR_DFIFREQXLAT4_ADDR 0xF4U
+#define CSR_DFIFREQXLAT5_ADDR 0xF5U
+#define CSR_DFIFREQXLAT6_ADDR 0xF6U
+#define CSR_DFIFREQXLAT7_ADDR 0xF7U
+#define CSR_TXRDPTRINIT_ADDR 0xF8U
+#define CSR_DFIINITCOMPLETE_ADDR 0xF9U
+#define CSR_DFIFREQRATIO_ADDR 0xFAU
+#define CSR_RXFIFOCHECKS_ADDR 0xFBU
+#define CSR_MTESTDTOCTRL_ADDR 0xFFU
+#define CSR_MAPCAA0TODFI_ADDR 0x100U
+#define CSR_MAPCAA1TODFI_ADDR 0x101U
+#define CSR_MAPCAA2TODFI_ADDR 0x102U
+#define CSR_MAPCAA3TODFI_ADDR 0x103U
+#define CSR_MAPCAA4TODFI_ADDR 0x104U
+#define CSR_MAPCAA5TODFI_ADDR 0x105U
+#define CSR_MAPCAA6TODFI_ADDR 0x106U
+#define CSR_MAPCAA7TODFI_ADDR 0x107U
+#define CSR_MAPCAA8TODFI_ADDR 0x108U
+#define CSR_MAPCAA9TODFI_ADDR 0x109U
+#define CSR_MAPCAB0TODFI_ADDR 0x110U
+#define CSR_MAPCAB1TODFI_ADDR 0x111U
+#define CSR_MAPCAB2TODFI_ADDR 0x112U
+#define CSR_MAPCAB3TODFI_ADDR 0x113U
+#define CSR_MAPCAB4TODFI_ADDR 0x114U
+#define CSR_MAPCAB5TODFI_ADDR 0x115U
+#define CSR_MAPCAB6TODFI_ADDR 0x116U
+#define CSR_MAPCAB7TODFI_ADDR 0x117U
+#define CSR_MAPCAB8TODFI_ADDR 0x118U
+#define CSR_MAPCAB9TODFI_ADDR 0x119U
+#define CSR_PHYINTERRUPTENABLE_ADDR 0x11BU
+#define CSR_PHYINTERRUPTFWCONTROL_ADDR 0x11CU
+#define CSR_PHYINTERRUPTMASK_ADDR 0x11DU
+#define CSR_PHYINTERRUPTCLEAR_ADDR 0x11EU
+#define CSR_PHYINTERRUPTSTATUS_ADDR 0x11FU
+#define CSR_HWTSWIZZLEHWTADDRESS0_ADDR 0x120U
+#define CSR_HWTSWIZZLEHWTADDRESS1_ADDR 0x121U
+#define CSR_HWTSWIZZLEHWTADDRESS2_ADDR 0x122U
+#define CSR_HWTSWIZZLEHWTADDRESS3_ADDR 0x123U
+#define CSR_HWTSWIZZLEHWTADDRESS4_ADDR 0x124U
+#define CSR_HWTSWIZZLEHWTADDRESS5_ADDR 0x125U
+#define CSR_HWTSWIZZLEHWTADDRESS6_ADDR 0x126U
+#define CSR_HWTSWIZZLEHWTADDRESS7_ADDR 0x127U
+#define CSR_HWTSWIZZLEHWTADDRESS8_ADDR 0x128U
+#define CSR_HWTSWIZZLEHWTADDRESS9_ADDR 0x129U
+#define CSR_HWTSWIZZLEHWTADDRESS10_ADDR 0x12AU
+#define CSR_HWTSWIZZLEHWTADDRESS11_ADDR 0x12BU
+#define CSR_HWTSWIZZLEHWTADDRESS12_ADDR 0x12CU
+#define CSR_HWTSWIZZLEHWTADDRESS13_ADDR 0x12DU
+#define CSR_HWTSWIZZLEHWTADDRESS14_ADDR 0x12EU
+#define CSR_HWTSWIZZLEHWTADDRESS15_ADDR 0x12FU
+#define CSR_HWTSWIZZLEHWTADDRESS17_ADDR 0x130U
+#define CSR_HWTSWIZZLEHWTACTN_ADDR 0x131U
+#define CSR_HWTSWIZZLEHWTBANK0_ADDR 0x132U
+#define CSR_HWTSWIZZLEHWTBANK1_ADDR 0x133U
+#define CSR_HWTSWIZZLEHWTBANK2_ADDR 0x134U
+#define CSR_HWTSWIZZLEHWTBG0_ADDR 0x135U
+#define CSR_HWTSWIZZLEHWTBG1_ADDR 0x136U
+#define CSR_HWTSWIZZLEHWTCASN_ADDR 0x137U
+#define CSR_HWTSWIZZLEHWTRASN_ADDR 0x138U
+#define CSR_HWTSWIZZLEHWTWEN_ADDR 0x139U
+#define CSR_HWTSWIZZLEHWTPARITYIN_ADDR 0x13AU
+#define CSR_DFIHANDSHAKEDELAYS0_ADDR 0x13CU
+#define CSR_DFIHANDSHAKEDELAYS1_ADDR 0x13DU
+#define CSR_REMOTEIMPCAL_ADDR 0x13EU
+#define CSR_ACLOOPBACKCTL_ADDR 0x13FU
+
+/* ACSM0 register offsets */
+#define CSR_ACSMSEQ0X0_ADDR 0x0U
+#define CSR_ACSMSEQ0X1_ADDR 0x1U
+#define CSR_ACSMSEQ0X2_ADDR 0x2U
+#define CSR_ACSMSEQ0X3_ADDR 0x3U
+#define CSR_ACSMSEQ0X4_ADDR 0x4U
+#define CSR_ACSMSEQ0X5_ADDR 0x5U
+#define CSR_ACSMSEQ0X6_ADDR 0x6U
+#define CSR_ACSMSEQ0X7_ADDR 0x7U
+#define CSR_ACSMSEQ0X8_ADDR 0x8U
+#define CSR_ACSMSEQ0X9_ADDR 0x9U
+#define CSR_ACSMSEQ0X10_ADDR 0xAU
+#define CSR_ACSMSEQ0X11_ADDR 0xBU
+#define CSR_ACSMSEQ0X12_ADDR 0xCU
+#define CSR_ACSMSEQ0X13_ADDR 0xDU
+#define CSR_ACSMSEQ0X14_ADDR 0xEU
+#define CSR_ACSMSEQ0X15_ADDR 0xFU
+#define CSR_ACSMSEQ0X16_ADDR 0x10U
+#define CSR_ACSMSEQ0X17_ADDR 0x11U
+#define CSR_ACSMSEQ0X18_ADDR 0x12U
+#define CSR_ACSMSEQ0X19_ADDR 0x13U
+#define CSR_ACSMSEQ0X20_ADDR 0x14U
+#define CSR_ACSMSEQ0X21_ADDR 0x15U
+#define CSR_ACSMSEQ0X22_ADDR 0x16U
+#define CSR_ACSMSEQ0X23_ADDR 0x17U
+#define CSR_ACSMSEQ0X24_ADDR 0x18U
+#define CSR_ACSMSEQ0X25_ADDR 0x19U
+#define CSR_ACSMSEQ0X26_ADDR 0x1AU
+#define CSR_ACSMSEQ0X27_ADDR 0x1BU
+#define CSR_ACSMSEQ0X28_ADDR 0x1CU
+#define CSR_ACSMSEQ0X29_ADDR 0x1DU
+#define CSR_ACSMSEQ0X30_ADDR 0x1EU
+#define CSR_ACSMSEQ0X31_ADDR 0x1FU
+#define CSR_ACSMSEQ1X0_ADDR 0x20U
+#define CSR_ACSMSEQ1X1_ADDR 0x21U
+#define CSR_ACSMSEQ1X2_ADDR 0x22U
+#define CSR_ACSMSEQ1X3_ADDR 0x23U
+#define CSR_ACSMSEQ1X4_ADDR 0x24U
+#define CSR_ACSMSEQ1X5_ADDR 0x25U
+#define CSR_ACSMSEQ1X6_ADDR 0x26U
+#define CSR_ACSMSEQ1X7_ADDR 0x27U
+#define CSR_ACSMSEQ1X8_ADDR 0x28U
+#define CSR_ACSMSEQ1X9_ADDR 0x29U
+#define CSR_ACSMSEQ1X10_ADDR 0x2AU
+#define CSR_ACSMSEQ1X11_ADDR 0x2BU
+#define CSR_ACSMSEQ1X12_ADDR 0x2CU
+#define CSR_ACSMSEQ1X13_ADDR 0x2DU
+#define CSR_ACSMSEQ1X14_ADDR 0x2EU
+#define CSR_ACSMSEQ1X15_ADDR 0x2FU
+#define CSR_ACSMSEQ1X16_ADDR 0x30U
+#define CSR_ACSMSEQ1X17_ADDR 0x31U
+#define CSR_ACSMSEQ1X18_ADDR 0x32U
+#define CSR_ACSMSEQ1X19_ADDR 0x33U
+#define CSR_ACSMSEQ1X20_ADDR 0x34U
+#define CSR_ACSMSEQ1X21_ADDR 0x35U
+#define CSR_ACSMSEQ1X22_ADDR 0x36U
+#define CSR_ACSMSEQ1X23_ADDR 0x37U
+#define CSR_ACSMSEQ1X24_ADDR 0x38U
+#define CSR_ACSMSEQ1X25_ADDR 0x39U
+#define CSR_ACSMSEQ1X26_ADDR 0x3AU
+#define CSR_ACSMSEQ1X27_ADDR 0x3BU
+#define CSR_ACSMSEQ1X28_ADDR 0x3CU
+#define CSR_ACSMSEQ1X29_ADDR 0x3DU
+#define CSR_ACSMSEQ1X30_ADDR 0x3EU
+#define CSR_ACSMSEQ1X31_ADDR 0x3FU
+#define CSR_ACSMSEQ2X0_ADDR 0x40U
+#define CSR_ACSMSEQ2X1_ADDR 0x41U
+#define CSR_ACSMSEQ2X2_ADDR 0x42U
+#define CSR_ACSMSEQ2X3_ADDR 0x43U
+#define CSR_ACSMSEQ2X4_ADDR 0x44U
+#define CSR_ACSMSEQ2X5_ADDR 0x45U
+#define CSR_ACSMSEQ2X6_ADDR 0x46U
+#define CSR_ACSMSEQ2X7_ADDR 0x47U
+#define CSR_ACSMSEQ2X8_ADDR 0x48U
+#define CSR_ACSMSEQ2X9_ADDR 0x49U
+#define CSR_ACSMSEQ2X10_ADDR 0x4AU
+#define CSR_ACSMSEQ2X11_ADDR 0x4BU
+#define CSR_ACSMSEQ2X12_ADDR 0x4CU
+#define CSR_ACSMSEQ2X13_ADDR 0x4DU
+#define CSR_ACSMSEQ2X14_ADDR 0x4EU
+#define CSR_ACSMSEQ2X15_ADDR 0x4FU
+#define CSR_ACSMSEQ2X16_ADDR 0x50U
+#define CSR_ACSMSEQ2X17_ADDR 0x51U
+#define CSR_ACSMSEQ2X18_ADDR 0x52U
+#define CSR_ACSMSEQ2X19_ADDR 0x53U
+#define CSR_ACSMSEQ2X20_ADDR 0x54U
+#define CSR_ACSMSEQ2X21_ADDR 0x55U
+#define CSR_ACSMSEQ2X22_ADDR 0x56U
+#define CSR_ACSMSEQ2X23_ADDR 0x57U
+#define CSR_ACSMSEQ2X24_ADDR 0x58U
+#define CSR_ACSMSEQ2X25_ADDR 0x59U
+#define CSR_ACSMSEQ2X26_ADDR 0x5AU
+#define CSR_ACSMSEQ2X27_ADDR 0x5BU
+#define CSR_ACSMSEQ2X28_ADDR 0x5CU
+#define CSR_ACSMSEQ2X29_ADDR 0x5DU
+#define CSR_ACSMSEQ2X30_ADDR 0x5EU
+#define CSR_ACSMSEQ2X31_ADDR 0x5FU
+#define CSR_ACSMSEQ3X0_ADDR 0x60U
+#define CSR_ACSMSEQ3X1_ADDR 0x61U
+#define CSR_ACSMSEQ3X2_ADDR 0x62U
+#define CSR_ACSMSEQ3X3_ADDR 0x63U
+#define CSR_ACSMSEQ3X4_ADDR 0x64U
+#define CSR_ACSMSEQ3X5_ADDR 0x65U
+#define CSR_ACSMSEQ3X6_ADDR 0x66U
+#define CSR_ACSMSEQ3X7_ADDR 0x67U
+#define CSR_ACSMSEQ3X8_ADDR 0x68U
+#define CSR_ACSMSEQ3X9_ADDR 0x69U
+#define CSR_ACSMSEQ3X10_ADDR 0x6AU
+#define CSR_ACSMSEQ3X11_ADDR 0x6BU
+#define CSR_ACSMSEQ3X12_ADDR 0x6CU
+#define CSR_ACSMSEQ3X13_ADDR 0x6DU
+#define CSR_ACSMSEQ3X14_ADDR 0x6EU
+#define CSR_ACSMSEQ3X15_ADDR 0x6FU
+#define CSR_ACSMSEQ3X16_ADDR 0x70U
+#define CSR_ACSMSEQ3X17_ADDR 0x71U
+#define CSR_ACSMSEQ3X18_ADDR 0x72U
+#define CSR_ACSMSEQ3X19_ADDR 0x73U
+#define CSR_ACSMSEQ3X20_ADDR 0x74U
+#define CSR_ACSMSEQ3X21_ADDR 0x75U
+#define CSR_ACSMSEQ3X22_ADDR 0x76U
+#define CSR_ACSMSEQ3X23_ADDR 0x77U
+#define CSR_ACSMSEQ3X24_ADDR 0x78U
+#define CSR_ACSMSEQ3X25_ADDR 0x79U
+#define CSR_ACSMSEQ3X26_ADDR 0x7AU
+#define CSR_ACSMSEQ3X27_ADDR 0x7BU
+#define CSR_ACSMSEQ3X28_ADDR 0x7CU
+#define CSR_ACSMSEQ3X29_ADDR 0x7DU
+#define CSR_ACSMSEQ3X30_ADDR 0x7EU
+#define CSR_ACSMSEQ3X31_ADDR 0x7FU
+#define CSR_ACSMPLAYBACK0X0_ADDR 0x80U
+#define CSR_ACSMPLAYBACK1X0_ADDR 0x81U
+#define CSR_ACSMPLAYBACK0X1_ADDR 0x82U
+#define CSR_ACSMPLAYBACK1X1_ADDR 0x83U
+#define CSR_ACSMPLAYBACK0X2_ADDR 0x84U
+#define CSR_ACSMPLAYBACK1X2_ADDR 0x85U
+#define CSR_ACSMPLAYBACK0X3_ADDR 0x86U
+#define CSR_ACSMPLAYBACK1X3_ADDR 0x87U
+#define CSR_ACSMPLAYBACK0X4_ADDR 0x88U
+#define CSR_ACSMPLAYBACK1X4_ADDR 0x89U
+#define CSR_ACSMPLAYBACK0X5_ADDR 0x8AU
+#define CSR_ACSMPLAYBACK1X5_ADDR 0x8BU
+#define CSR_ACSMPLAYBACK0X6_ADDR 0x8CU
+#define CSR_ACSMPLAYBACK1X6_ADDR 0x8DU
+#define CSR_ACSMPLAYBACK0X7_ADDR 0x8EU
+#define CSR_ACSMPLAYBACK1X7_ADDR 0x8FU
+#define CSR_ACSMPSTATEOVREN_ADDR 0x90U
+#define CSR_ACSMPSTATEOVRVAL_ADDR 0x91U
+#define CSR_ACSMCTRL23_ADDR 0xC0U
+#define CSR_ACSMCKEVAL_ADDR 0xC2U
+#define CSR_LOWSPEEDCLOCKDIVIDER_ADDR 0xC8U
+#define CSR_ACSMCSMAPCTRL0_ADDR 0xD0U
+#define CSR_ACSMCSMAPCTRL1_ADDR 0xD1U
+#define CSR_ACSMCSMAPCTRL2_ADDR 0xD2U
+#define CSR_ACSMCSMAPCTRL3_ADDR 0xD3U
+#define CSR_ACSMCSMAPCTRL4_ADDR 0xD4U
+#define CSR_ACSMCSMAPCTRL5_ADDR 0xD5U
+#define CSR_ACSMCSMAPCTRL6_ADDR 0xD6U
+#define CSR_ACSMCSMAPCTRL7_ADDR 0xD7U
+#define CSR_ACSMCSMAPCTRL8_ADDR 0xD8U
+#define CSR_ACSMCSMAPCTRL9_ADDR 0xD9U
+#define CSR_ACSMCSMAPCTRL10_ADDR 0xDAU
+#define CSR_ACSMCSMAPCTRL11_ADDR 0xDBU
+#define CSR_ACSMCSMAPCTRL12_ADDR 0xDCU
+#define CSR_ACSMCSMAPCTRL13_ADDR 0xDDU
+#define CSR_ACSMCSMAPCTRL14_ADDR 0xDEU
+#define CSR_ACSMCSMAPCTRL15_ADDR 0xDFU
+#define CSR_ACSMODTCTRL0_ADDR 0xE0U
+#define CSR_ACSMODTCTRL1_ADDR 0xE1U
+#define CSR_ACSMODTCTRL2_ADDR 0xE2U
+#define CSR_ACSMODTCTRL3_ADDR 0xE3U
+#define CSR_ACSMODTCTRL4_ADDR 0xE4U
+#define CSR_ACSMODTCTRL5_ADDR 0xE5U
+#define CSR_ACSMODTCTRL6_ADDR 0xE6U
+#define CSR_ACSMODTCTRL7_ADDR 0xE7U
+#define CSR_ACSMODTCTRL8_ADDR 0xE8U
+#define CSR_ACSMCTRL16_ADDR 0xE9U
+#define CSR_LOWSPEEDCLOCKSTOPVAL_ADDR 0xEAU
+#define CSR_ACSMCTRL18_ADDR 0xEBU
+#define CSR_ACSMCTRL19_ADDR 0xECU
+#define CSR_ACSMCTRL20_ADDR 0xEDU
+#define CSR_ACSMCTRL21_ADDR 0xEEU
+#define CSR_ACSMCTRL22_ADDR 0xEFU
+#define CSR_ACSMCTRL0_ADDR 0xF0U
+#define CSR_ACSMCTRL1_ADDR 0xF1U
+#define CSR_ACSMCTRL2_ADDR 0xF2U
+#define CSR_ACSMCTRL3_ADDR 0xF3U
+#define CSR_ACSMCTRL4_ADDR 0xF4U
+#define CSR_ACSMCTRL5_ADDR 0xF5U
+#define CSR_ACSMCTRL6_ADDR 0xF6U
+#define CSR_ACSMCTRL7_ADDR 0xF7U
+#define CSR_ACSMCTRL8_ADDR 0xF8U
+#define CSR_ACSMCTRL9_ADDR 0xF9U
+#define CSR_ACSMCTRL10_ADDR 0xFAU
+#define CSR_ACSMCTRL11_ADDR 0xFBU
+#define CSR_ACSMCTRL12_ADDR 0xFCU
+#define CSR_ACSMCTRL13_ADDR 0xFDU
+#define CSR_ACSMCTRL14_ADDR 0xFEU
+#define CSR_ACSMCTRL15_ADDR 0xFFU
+
+/* PPGC0 register offsets */
+#define CSR_PPGCCTRL1_ADDR 0x11U
+#define CSR_PPGCLANE2CRCINMAP0_ADDR 0x15U
+#define CSR_PPGCLANE2CRCINMAP1_ADDR 0x16U
+#define CSR_PRBSTAPDLY0_ADDR 0x24U
+#define CSR_PRBSTAPDLY1_ADDR 0x25U
+#define CSR_PRBSTAPDLY2_ADDR 0x26U
+#define CSR_PRBSTAPDLY3_ADDR 0x27U
+#define CSR_GENPRBSBYTE0_ADDR 0x30U
+#define CSR_GENPRBSBYTE1_ADDR 0x31U
+#define CSR_GENPRBSBYTE2_ADDR 0x32U
+#define CSR_GENPRBSBYTE3_ADDR 0x33U
+#define CSR_GENPRBSBYTE4_ADDR 0x34U
+#define CSR_GENPRBSBYTE5_ADDR 0x35U
+#define CSR_GENPRBSBYTE6_ADDR 0x36U
+#define CSR_GENPRBSBYTE7_ADDR 0x37U
+#define CSR_GENPRBSBYTE8_ADDR 0x38U
+#define CSR_GENPRBSBYTE9_ADDR 0x39U
+#define CSR_GENPRBSBYTE10_ADDR 0x3AU
+#define CSR_GENPRBSBYTE11_ADDR 0x3BU
+#define CSR_GENPRBSBYTE12_ADDR 0x3CU
+#define CSR_GENPRBSBYTE13_ADDR 0x3DU
+#define CSR_GENPRBSBYTE14_ADDR 0x3EU
+#define CSR_GENPRBSBYTE15_ADDR 0x3FU
+#define CSR_PRBSGENCTL_ADDR 0x60U
+#define CSR_PRBSGENSTATELO_ADDR 0x61U
+#define CSR_PRBSGENSTATEHI_ADDR 0x62U
+#define CSR_PRBSCHKSTATELO_ADDR 0x63U
+#define CSR_PRBSCHKSTATEHI_ADDR 0x64U
+#define CSR_PRBSGENCTL1_ADDR 0x65U
+#define CSR_PRBSGENCTL2_ADDR 0x66U
+
+/* INITENG0 register offsets */
+#define CSR_PRESEQUENCEREG0B0S0_ADDR 0x0U
+#define CSR_PRESEQUENCEREG0B0S1_ADDR 0x1U
+#define CSR_PRESEQUENCEREG0B0S2_ADDR 0x2U
+#define CSR_PRESEQUENCEREG0B1S0_ADDR 0x3U
+#define CSR_PRESEQUENCEREG0B1S1_ADDR 0x4U
+#define CSR_PRESEQUENCEREG0B1S2_ADDR 0x5U
+#define CSR_POSTSEQUENCEREG0B0S0_ADDR 0x6U
+#define CSR_POSTSEQUENCEREG0B0S1_ADDR 0x7U
+#define CSR_POSTSEQUENCEREG0B0S2_ADDR 0x8U
+#define CSR_POSTSEQUENCEREG0B1S0_ADDR 0x9U
+#define CSR_POSTSEQUENCEREG0B1S1_ADDR 0xAU
+#define CSR_POSTSEQUENCEREG0B1S2_ADDR 0xBU
+#define CSR_SEQ0BDISABLEFLAG0_ADDR 0xCU
+#define CSR_SEQ0BDISABLEFLAG1_ADDR 0xDU
+#define CSR_SEQ0BDISABLEFLAG2_ADDR 0xEU
+#define CSR_SEQ0BDISABLEFLAG3_ADDR 0xFU
+#define CSR_SEQ0BDISABLEFLAG4_ADDR 0x10U
+#define CSR_SEQ0BDISABLEFLAG5_ADDR 0x11U
+#define CSR_SEQ0BDISABLEFLAG6_ADDR 0x12U
+#define CSR_SEQ0BDISABLEFLAG7_ADDR 0x13U
+#define CSR_STARTVECTOR0B0_ADDR 0x17U
+#define CSR_STARTVECTOR0B1_ADDR 0x18U
+#define CSR_STARTVECTOR0B2_ADDR 0x19U
+#define CSR_STARTVECTOR0B3_ADDR 0x1AU
+#define CSR_STARTVECTOR0B4_ADDR 0x1BU
+#define CSR_STARTVECTOR0B5_ADDR 0x1CU
+#define CSR_STARTVECTOR0B6_ADDR 0x1DU
+#define CSR_STARTVECTOR0B7_ADDR 0x1EU
+#define CSR_STARTVECTOR0B8_ADDR 0x1FU
+#define CSR_STARTVECTOR0B9_ADDR 0x20U
+#define CSR_STARTVECTOR0B10_ADDR 0x21U
+#define CSR_STARTVECTOR0B11_ADDR 0x22U
+#define CSR_STARTVECTOR0B12_ADDR 0x23U
+#define CSR_STARTVECTOR0B13_ADDR 0x24U
+#define CSR_STARTVECTOR0B14_ADDR 0x25U
+#define CSR_STARTVECTOR0B15_ADDR 0x26U
+#define CSR_SEQ0BWAITCONDSEL_ADDR 0x27U
+#define CSR_PHYINLP3_ADDR 0x28U
+#define CSR_SEQUENCEREG0B0S0_ADDR 0x29U
+#define CSR_SEQUENCEREG0B0S1_ADDR 0x2AU
+#define CSR_SEQUENCEREG0B0S2_ADDR 0x2BU
+#define CSR_SEQUENCEREG0B1S0_ADDR 0x2CU
+#define CSR_SEQUENCEREG0B1S1_ADDR 0x2DU
+#define CSR_SEQUENCEREG0B1S2_ADDR 0x2EU
+#define CSR_SEQUENCEREG0B2S0_ADDR 0x2FU
+#define CSR_SEQUENCEREG0B2S1_ADDR 0x30U
+#define CSR_SEQUENCEREG0B2S2_ADDR 0x31U
+#define CSR_SEQUENCEREG0B3S0_ADDR 0x32U
+#define CSR_SEQUENCEREG0B3S1_ADDR 0x33U
+#define CSR_SEQUENCEREG0B3S2_ADDR 0x34U
+#define CSR_SEQUENCEREG0B4S0_ADDR 0x35U
+#define CSR_SEQUENCEREG0B4S1_ADDR 0x36U
+#define CSR_SEQUENCEREG0B4S2_ADDR 0x37U
+#define CSR_SEQUENCEREG0B5S0_ADDR 0x38U
+#define CSR_SEQUENCEREG0B5S1_ADDR 0x39U
+#define CSR_SEQUENCEREG0B5S2_ADDR 0x3AU
+#define CSR_SEQUENCEREG0B6S0_ADDR 0x3BU
+#define CSR_SEQUENCEREG0B6S1_ADDR 0x3CU
+#define CSR_SEQUENCEREG0B6S2_ADDR 0x3DU
+#define CSR_SEQUENCEREG0B7S0_ADDR 0x3EU
+#define CSR_SEQUENCEREG0B7S1_ADDR 0x3FU
+#define CSR_SEQUENCEREG0B7S2_ADDR 0x40U
+#define CSR_SEQUENCEREG0B8S0_ADDR 0x41U
+#define CSR_SEQUENCEREG0B8S1_ADDR 0x42U
+#define CSR_SEQUENCEREG0B8S2_ADDR 0x43U
+#define CSR_SEQUENCEREG0B9S0_ADDR 0x44U
+#define CSR_SEQUENCEREG0B9S1_ADDR 0x45U
+#define CSR_SEQUENCEREG0B9S2_ADDR 0x46U
+#define CSR_SEQUENCEREG0B10S0_ADDR 0x47U
+#define CSR_SEQUENCEREG0B10S1_ADDR 0x48U
+#define CSR_SEQUENCEREG0B10S2_ADDR 0x49U
+#define CSR_SEQUENCEREG0B11S0_ADDR 0x4AU
+#define CSR_SEQUENCEREG0B11S1_ADDR 0x4BU
+#define CSR_SEQUENCEREG0B11S2_ADDR 0x4CU
+#define CSR_SEQUENCEREG0B12S0_ADDR 0x4DU
+#define CSR_SEQUENCEREG0B12S1_ADDR 0x4EU
+#define CSR_SEQUENCEREG0B12S2_ADDR 0x4FU
+#define CSR_SEQUENCEREG0B13S0_ADDR 0x50U
+#define CSR_SEQUENCEREG0B13S1_ADDR 0x51U
+#define CSR_SEQUENCEREG0B13S2_ADDR 0x52U
+#define CSR_SEQUENCEREG0B14S0_ADDR 0x53U
+#define CSR_SEQUENCEREG0B14S1_ADDR 0x54U
+#define CSR_SEQUENCEREG0B14S2_ADDR 0x55U
+#define CSR_SEQUENCEREG0B15S0_ADDR 0x56U
+#define CSR_SEQUENCEREG0B15S1_ADDR 0x57U
+#define CSR_SEQUENCEREG0B15S2_ADDR 0x58U
+#define CSR_SEQUENCEREG0B16S0_ADDR 0x59U
+#define CSR_SEQUENCEREG0B16S1_ADDR 0x5AU
+#define CSR_SEQUENCEREG0B16S2_ADDR 0x5BU
+#define CSR_SEQUENCEREG0B17S0_ADDR 0x5CU
+#define CSR_SEQUENCEREG0B17S1_ADDR 0x5DU
+#define CSR_SEQUENCEREG0B17S2_ADDR 0x5EU
+#define CSR_SEQUENCEREG0B18S0_ADDR 0x5FU
+#define CSR_SEQUENCEREG0B18S1_ADDR 0x60U
+#define CSR_SEQUENCEREG0B18S2_ADDR 0x61U
+#define CSR_SEQUENCEREG0B19S0_ADDR 0x62U
+#define CSR_SEQUENCEREG0B19S1_ADDR 0x63U
+#define CSR_SEQUENCEREG0B19S2_ADDR 0x64U
+#define CSR_SEQUENCEREG0B20S0_ADDR 0x65U
+#define CSR_SEQUENCEREG0B20S1_ADDR 0x66U
+#define CSR_SEQUENCEREG0B20S2_ADDR 0x67U
+#define CSR_SEQUENCEREG0B21S0_ADDR 0x68U
+#define CSR_SEQUENCEREG0B21S1_ADDR 0x69U
+#define CSR_SEQUENCEREG0B21S2_ADDR 0x6AU
+#define CSR_SEQUENCEREG0B22S0_ADDR 0x6BU
+#define CSR_SEQUENCEREG0B22S1_ADDR 0x6CU
+#define CSR_SEQUENCEREG0B22S2_ADDR 0x6DU
+#define CSR_SEQUENCEREG0B23S0_ADDR 0x6EU
+#define CSR_SEQUENCEREG0B23S1_ADDR 0x6FU
+#define CSR_SEQUENCEREG0B23S2_ADDR 0x70U
+#define CSR_SEQUENCEREG0B24S0_ADDR 0x71U
+#define CSR_SEQUENCEREG0B24S1_ADDR 0x72U
+#define CSR_SEQUENCEREG0B24S2_ADDR 0x73U
+#define CSR_SEQUENCEREG0B25S0_ADDR 0x74U
+#define CSR_SEQUENCEREG0B25S1_ADDR 0x75U
+#define CSR_SEQUENCEREG0B25S2_ADDR 0x76U
+#define CSR_SEQUENCEREG0B26S0_ADDR 0x77U
+#define CSR_SEQUENCEREG0B26S1_ADDR 0x78U
+#define CSR_SEQUENCEREG0B26S2_ADDR 0x79U
+#define CSR_SEQUENCEREG0B27S0_ADDR 0x7AU
+#define CSR_SEQUENCEREG0B27S1_ADDR 0x7BU
+#define CSR_SEQUENCEREG0B27S2_ADDR 0x7CU
+#define CSR_SEQUENCEREG0B28S0_ADDR 0x7DU
+#define CSR_SEQUENCEREG0B28S1_ADDR 0x7EU
+#define CSR_SEQUENCEREG0B28S2_ADDR 0x7FU
+#define CSR_SEQUENCEREG0B29S0_ADDR 0x80U
+#define CSR_SEQUENCEREG0B29S1_ADDR 0x81U
+#define CSR_SEQUENCEREG0B29S2_ADDR 0x82U
+#define CSR_SEQUENCEREG0B30S0_ADDR 0x83U
+#define CSR_SEQUENCEREG0B30S1_ADDR 0x84U
+#define CSR_SEQUENCEREG0B30S2_ADDR 0x85U
+#define CSR_SEQUENCEREG0B31S0_ADDR 0x86U
+#define CSR_SEQUENCEREG0B31S1_ADDR 0x87U
+#define CSR_SEQUENCEREG0B31S2_ADDR 0x88U
+#define CSR_SEQUENCEREG0B32S0_ADDR 0x89U
+#define CSR_SEQUENCEREG0B32S1_ADDR 0x8AU
+#define CSR_SEQUENCEREG0B32S2_ADDR 0x8BU
+#define CSR_SEQUENCEREG0B33S0_ADDR 0x8CU
+#define CSR_SEQUENCEREG0B33S1_ADDR 0x8DU
+#define CSR_SEQUENCEREG0B33S2_ADDR 0x8EU
+#define CSR_SEQUENCEREG0B34S0_ADDR 0x8FU
+#define CSR_SEQUENCEREG0B34S1_ADDR 0x90U
+#define CSR_SEQUENCEREG0B34S2_ADDR 0x91U
+#define CSR_SEQUENCEREG0B35S0_ADDR 0x92U
+#define CSR_SEQUENCEREG0B35S1_ADDR 0x93U
+#define CSR_SEQUENCEREG0B35S2_ADDR 0x94U
+#define CSR_SEQUENCEREG0B36S0_ADDR 0x95U
+#define CSR_SEQUENCEREG0B36S1_ADDR 0x96U
+#define CSR_SEQUENCEREG0B36S2_ADDR 0x97U
+#define CSR_SEQUENCEREG0B37S0_ADDR 0x98U
+#define CSR_SEQUENCEREG0B37S1_ADDR 0x99U
+#define CSR_SEQUENCEREG0B37S2_ADDR 0x9AU
+#define CSR_SEQUENCEREG0B38S0_ADDR 0x9BU
+#define CSR_SEQUENCEREG0B38S1_ADDR 0x9CU
+#define CSR_SEQUENCEREG0B38S2_ADDR 0x9DU
+#define CSR_SEQUENCEREG0B39S0_ADDR 0x9EU
+#define CSR_SEQUENCEREG0B39S1_ADDR 0x9FU
+#define CSR_SEQUENCEREG0B39S2_ADDR 0xA0U
+#define CSR_SEQUENCEREG0B40S0_ADDR 0xA1U
+#define CSR_SEQUENCEREG0B40S1_ADDR 0xA2U
+#define CSR_SEQUENCEREG0B40S2_ADDR 0xA3U
+#define CSR_SEQUENCEREG0B41S0_ADDR 0xA4U
+#define CSR_SEQUENCEREG0B41S1_ADDR 0xA5U
+#define CSR_SEQUENCEREG0B41S2_ADDR 0xA6U
+#define CSR_SEQUENCEREG0B42S0_ADDR 0xA7U
+#define CSR_SEQUENCEREG0B42S1_ADDR 0xA8U
+#define CSR_SEQUENCEREG0B42S2_ADDR 0xA9U
+#define CSR_SEQUENCEREG0B43S0_ADDR 0xAAU
+#define CSR_SEQUENCEREG0B43S1_ADDR 0xABU
+#define CSR_SEQUENCEREG0B43S2_ADDR 0xACU
+#define CSR_SEQUENCEREG0B44S0_ADDR 0xADU
+#define CSR_SEQUENCEREG0B44S1_ADDR 0xAEU
+#define CSR_SEQUENCEREG0B44S2_ADDR 0xAFU
+#define CSR_SEQUENCEREG0B45S0_ADDR 0xB0U
+#define CSR_SEQUENCEREG0B45S1_ADDR 0xB1U
+#define CSR_SEQUENCEREG0B45S2_ADDR 0xB2U
+#define CSR_SEQUENCEREG0B46S0_ADDR 0xB3U
+#define CSR_SEQUENCEREG0B46S1_ADDR 0xB4U
+#define CSR_SEQUENCEREG0B46S2_ADDR 0xB5U
+#define CSR_SEQUENCEREG0B47S0_ADDR 0xB6U
+#define CSR_SEQUENCEREG0B47S1_ADDR 0xB7U
+#define CSR_SEQUENCEREG0B47S2_ADDR 0xB8U
+#define CSR_SEQUENCEREG0B48S0_ADDR 0xB9U
+#define CSR_SEQUENCEREG0B48S1_ADDR 0xBAU
+#define CSR_SEQUENCEREG0B48S2_ADDR 0xBBU
+#define CSR_SEQUENCEREG0B49S0_ADDR 0xBCU
+#define CSR_SEQUENCEREG0B49S1_ADDR 0xBDU
+#define CSR_SEQUENCEREG0B49S2_ADDR 0xBEU
+#define CSR_SEQUENCEREG0B50S0_ADDR 0xBFU
+#define CSR_SEQUENCEREG0B50S1_ADDR 0xC0U
+#define CSR_SEQUENCEREG0B50S2_ADDR 0xC1U
+#define CSR_SEQUENCEREG0B51S0_ADDR 0xC2U
+#define CSR_SEQUENCEREG0B51S1_ADDR 0xC3U
+#define CSR_SEQUENCEREG0B51S2_ADDR 0xC4U
+#define CSR_SEQUENCEREG0B52S0_ADDR 0xC5U
+#define CSR_SEQUENCEREG0B52S1_ADDR 0xC6U
+#define CSR_SEQUENCEREG0B52S2_ADDR 0xC7U
+#define CSR_SEQUENCEREG0B53S0_ADDR 0xC8U
+#define CSR_SEQUENCEREG0B53S1_ADDR 0xC9U
+#define CSR_SEQUENCEREG0B53S2_ADDR 0xCAU
+#define CSR_SEQUENCEREG0B54S0_ADDR 0xCBU
+#define CSR_SEQUENCEREG0B54S1_ADDR 0xCCU
+#define CSR_SEQUENCEREG0B54S2_ADDR 0xCDU
+#define CSR_SEQUENCEREG0B55S0_ADDR 0xCEU
+#define CSR_SEQUENCEREG0B55S1_ADDR 0xCFU
+#define CSR_SEQUENCEREG0B55S2_ADDR 0xD0U
+#define CSR_SEQUENCEREG0B56S0_ADDR 0xD1U
+#define CSR_SEQUENCEREG0B56S1_ADDR 0xD2U
+#define CSR_SEQUENCEREG0B56S2_ADDR 0xD3U
+#define CSR_SEQUENCEREG0B57S0_ADDR 0xD4U
+#define CSR_SEQUENCEREG0B57S1_ADDR 0xD5U
+#define CSR_SEQUENCEREG0B57S2_ADDR 0xD6U
+#define CSR_SEQUENCEREG0B58S0_ADDR 0xD7U
+#define CSR_SEQUENCEREG0B58S1_ADDR 0xD8U
+#define CSR_SEQUENCEREG0B58S2_ADDR 0xD9U
+#define CSR_SEQUENCEREG0B59S0_ADDR 0xDAU
+#define CSR_SEQUENCEREG0B59S1_ADDR 0xDBU
+#define CSR_SEQUENCEREG0B59S2_ADDR 0xDCU
+#define CSR_SEQUENCEREG0B60S0_ADDR 0xDDU
+#define CSR_SEQUENCEREG0B60S1_ADDR 0xDEU
+#define CSR_SEQUENCEREG0B60S2_ADDR 0xDFU
+#define CSR_SEQUENCEREG0B61S0_ADDR 0xE0U
+#define CSR_SEQUENCEREG0B61S1_ADDR 0xE1U
+#define CSR_SEQUENCEREG0B61S2_ADDR 0xE2U
+#define CSR_SEQUENCEREG0B62S0_ADDR 0xE3U
+#define CSR_SEQUENCEREG0B62S1_ADDR 0xE4U
+#define CSR_SEQUENCEREG0B62S2_ADDR 0xE5U
+#define CSR_SEQUENCEREG0B63S0_ADDR 0xE6U
+#define CSR_SEQUENCEREG0B63S1_ADDR 0xE7U
+#define CSR_SEQUENCEREG0B63S2_ADDR 0xE8U
+#define CSR_SEQUENCEREG0B64S0_ADDR 0xE9U
+#define CSR_SEQUENCEREG0B64S1_ADDR 0xEAU
+#define CSR_SEQUENCEREG0B64S2_ADDR 0xEBU
+#define CSR_SEQUENCEREG0B65S0_ADDR 0xECU
+#define CSR_SEQUENCEREG0B65S1_ADDR 0xEDU
+#define CSR_SEQUENCEREG0B65S2_ADDR 0xEEU
+#define CSR_SEQUENCEREG0B66S0_ADDR 0xEFU
+#define CSR_SEQUENCEREG0B66S1_ADDR 0xF0U
+#define CSR_SEQUENCEREG0B66S2_ADDR 0xF1U
+#define CSR_SEQUENCEREG0B67S0_ADDR 0xF2U
+#define CSR_SEQUENCEREG0B67S1_ADDR 0xF3U
+#define CSR_SEQUENCEREG0B67S2_ADDR 0xF4U
+#define CSR_SEQUENCEREG0B68S0_ADDR 0xF5U
+#define CSR_SEQUENCEREG0B68S1_ADDR 0xF6U
+#define CSR_SEQUENCEREG0B68S2_ADDR 0xF7U
+#define CSR_SEQUENCEREG0B69S0_ADDR 0xF8U
+#define CSR_SEQUENCEREG0B69S1_ADDR 0xF9U
+#define CSR_SEQUENCEREG0B69S2_ADDR 0xFAU
+#define CSR_SEQUENCEREG0B70S0_ADDR 0xFBU
+#define CSR_SEQUENCEREG0B70S1_ADDR 0xFCU
+#define CSR_SEQUENCEREG0B70S2_ADDR 0xFDU
+#define CSR_SEQUENCEREG0B71S0_ADDR 0xFEU
+#define CSR_SEQUENCEREG0B71S1_ADDR 0xFFU
+#define CSR_SEQUENCEREG0B71S2_ADDR 0x100U
+#define CSR_SEQUENCEREG0B72S0_ADDR 0x101U
+#define CSR_SEQUENCEREG0B72S1_ADDR 0x102U
+#define CSR_SEQUENCEREG0B72S2_ADDR 0x103U
+#define CSR_SEQUENCEREG0B73S0_ADDR 0x104U
+#define CSR_SEQUENCEREG0B73S1_ADDR 0x105U
+#define CSR_SEQUENCEREG0B73S2_ADDR 0x106U
+#define CSR_SEQUENCEREG0B74S0_ADDR 0x107U
+#define CSR_SEQUENCEREG0B74S1_ADDR 0x108U
+#define CSR_SEQUENCEREG0B74S2_ADDR 0x109U
+#define CSR_SEQUENCEREG0B75S0_ADDR 0x10AU
+#define CSR_SEQUENCEREG0B75S1_ADDR 0x10BU
+#define CSR_SEQUENCEREG0B75S2_ADDR 0x10CU
+#define CSR_SEQUENCEREG0B76S0_ADDR 0x10DU
+#define CSR_SEQUENCEREG0B76S1_ADDR 0x10EU
+#define CSR_SEQUENCEREG0B76S2_ADDR 0x10FU
+#define CSR_SEQUENCEREG0B77S0_ADDR 0x110U
+#define CSR_SEQUENCEREG0B77S1_ADDR 0x111U
+#define CSR_SEQUENCEREG0B77S2_ADDR 0x112U
+#define CSR_SEQUENCEREG0B78S0_ADDR 0x113U
+#define CSR_SEQUENCEREG0B78S1_ADDR 0x114U
+#define CSR_SEQUENCEREG0B78S2_ADDR 0x115U
+#define CSR_SEQUENCEREG0B79S0_ADDR 0x116U
+#define CSR_SEQUENCEREG0B79S1_ADDR 0x117U
+#define CSR_SEQUENCEREG0B79S2_ADDR 0x118U
+#define CSR_SEQUENCEREG0B80S0_ADDR 0x119U
+#define CSR_SEQUENCEREG0B80S1_ADDR 0x11AU
+#define CSR_SEQUENCEREG0B80S2_ADDR 0x11BU
+#define CSR_SEQUENCEREG0B81S0_ADDR 0x11CU
+#define CSR_SEQUENCEREG0B81S1_ADDR 0x11DU
+#define CSR_SEQUENCEREG0B81S2_ADDR 0x11EU
+#define CSR_SEQUENCEREG0B82S0_ADDR 0x11FU
+#define CSR_SEQUENCEREG0B82S1_ADDR 0x120U
+#define CSR_SEQUENCEREG0B82S2_ADDR 0x121U
+#define CSR_SEQUENCEREG0B83S0_ADDR 0x122U
+#define CSR_SEQUENCEREG0B83S1_ADDR 0x123U
+#define CSR_SEQUENCEREG0B83S2_ADDR 0x124U
+#define CSR_SEQUENCEREG0B84S0_ADDR 0x125U
+#define CSR_SEQUENCEREG0B84S1_ADDR 0x126U
+#define CSR_SEQUENCEREG0B84S2_ADDR 0x127U
+#define CSR_SEQUENCEREG0B85S0_ADDR 0x128U
+#define CSR_SEQUENCEREG0B85S1_ADDR 0x129U
+#define CSR_SEQUENCEREG0B85S2_ADDR 0x12AU
+#define CSR_SEQUENCEREG0B86S0_ADDR 0x12BU
+#define CSR_SEQUENCEREG0B86S1_ADDR 0x12CU
+#define CSR_SEQUENCEREG0B86S2_ADDR 0x12DU
+#define CSR_SEQUENCEREG0B87S0_ADDR 0x12EU
+#define CSR_SEQUENCEREG0B87S1_ADDR 0x12FU
+#define CSR_SEQUENCEREG0B87S2_ADDR 0x130U
+#define CSR_SEQUENCEREG0B88S0_ADDR 0x131U
+#define CSR_SEQUENCEREG0B88S1_ADDR 0x132U
+#define CSR_SEQUENCEREG0B88S2_ADDR 0x133U
+#define CSR_SEQUENCEREG0B89S0_ADDR 0x134U
+#define CSR_SEQUENCEREG0B89S1_ADDR 0x135U
+#define CSR_SEQUENCEREG0B89S2_ADDR 0x136U
+#define CSR_SEQUENCEREG0B90S0_ADDR 0x137U
+#define CSR_SEQUENCEREG0B90S1_ADDR 0x138U
+#define CSR_SEQUENCEREG0B90S2_ADDR 0x139U
+#define CSR_SEQUENCEREG0B91S0_ADDR 0x13AU
+#define CSR_SEQUENCEREG0B91S1_ADDR 0x13BU
+#define CSR_SEQUENCEREG0B91S2_ADDR 0x13CU
+#define CSR_SEQUENCEREG0B92S0_ADDR 0x13DU
+#define CSR_SEQUENCEREG0B92S1_ADDR 0x13EU
+#define CSR_SEQUENCEREG0B92S2_ADDR 0x13FU
+#define CSR_SEQUENCEREG0B93S0_ADDR 0x140U
+#define CSR_SEQUENCEREG0B93S1_ADDR 0x141U
+#define CSR_SEQUENCEREG0B93S2_ADDR 0x142U
+#define CSR_SEQUENCEREG0B94S0_ADDR 0x143U
+#define CSR_SEQUENCEREG0B94S1_ADDR 0x144U
+#define CSR_SEQUENCEREG0B94S2_ADDR 0x145U
+#define CSR_SEQUENCEREG0B95S0_ADDR 0x146U
+#define CSR_SEQUENCEREG0B95S1_ADDR 0x147U
+#define CSR_SEQUENCEREG0B95S2_ADDR 0x148U
+#define CSR_SEQUENCEREG0B96S0_ADDR 0x149U
+#define CSR_SEQUENCEREG0B96S1_ADDR 0x14AU
+#define CSR_SEQUENCEREG0B96S2_ADDR 0x14BU
+#define CSR_SEQUENCEREG0B97S0_ADDR 0x14CU
+#define CSR_SEQUENCEREG0B97S1_ADDR 0x14DU
+#define CSR_SEQUENCEREG0B97S2_ADDR 0x14EU
+#define CSR_SEQUENCEREG0B98S0_ADDR 0x14FU
+#define CSR_SEQUENCEREG0B98S1_ADDR 0x150U
+#define CSR_SEQUENCEREG0B98S2_ADDR 0x151U
+#define CSR_SEQUENCEREG0B99S0_ADDR 0x152U
+#define CSR_SEQUENCEREG0B99S1_ADDR 0x153U
+#define CSR_SEQUENCEREG0B99S2_ADDR 0x154U
+#define CSR_SEQUENCEREG0B100S0_ADDR 0x155U
+#define CSR_SEQUENCEREG0B100S1_ADDR 0x156U
+#define CSR_SEQUENCEREG0B100S2_ADDR 0x157U
+#define CSR_SEQUENCEREG0B101S0_ADDR 0x158U
+#define CSR_SEQUENCEREG0B101S1_ADDR 0x159U
+#define CSR_SEQUENCEREG0B101S2_ADDR 0x15AU
+#define CSR_SEQUENCEREG0B102S0_ADDR 0x15BU
+#define CSR_SEQUENCEREG0B102S1_ADDR 0x15CU
+#define CSR_SEQUENCEREG0B102S2_ADDR 0x15DU
+#define CSR_SEQUENCEREG0B103S0_ADDR 0x15EU
+#define CSR_SEQUENCEREG0B103S1_ADDR 0x15FU
+#define CSR_SEQUENCEREG0B103S2_ADDR 0x160U
+#define CSR_SEQUENCEREG0B104S0_ADDR 0x161U
+#define CSR_SEQUENCEREG0B104S1_ADDR 0x162U
+#define CSR_SEQUENCEREG0B104S2_ADDR 0x163U
+#define CSR_SEQUENCEREG0B105S0_ADDR 0x164U
+#define CSR_SEQUENCEREG0B105S1_ADDR 0x165U
+#define CSR_SEQUENCEREG0B105S2_ADDR 0x166U
+#define CSR_SEQUENCEREG0B106S0_ADDR 0x167U
+#define CSR_SEQUENCEREG0B106S1_ADDR 0x168U
+#define CSR_SEQUENCEREG0B106S2_ADDR 0x169U
+#define CSR_SEQUENCEREG0B107S0_ADDR 0x16AU
+#define CSR_SEQUENCEREG0B107S1_ADDR 0x16BU
+#define CSR_SEQUENCEREG0B107S2_ADDR 0x16CU
+#define CSR_SEQUENCEREG0B108S0_ADDR 0x16DU
+#define CSR_SEQUENCEREG0B108S1_ADDR 0x16EU
+#define CSR_SEQUENCEREG0B108S2_ADDR 0x16FU
+#define CSR_SEQUENCEREG0B109S0_ADDR 0x170U
+#define CSR_SEQUENCEREG0B109S1_ADDR 0x171U
+#define CSR_SEQUENCEREG0B109S2_ADDR 0x172U
+#define CSR_SEQUENCEREG0B110S0_ADDR 0x173U
+#define CSR_SEQUENCEREG0B110S1_ADDR 0x174U
+#define CSR_SEQUENCEREG0B110S2_ADDR 0x175U
+#define CSR_SEQUENCEREG0B111S0_ADDR 0x176U
+#define CSR_SEQUENCEREG0B111S1_ADDR 0x177U
+#define CSR_SEQUENCEREG0B111S2_ADDR 0x178U
+#define CSR_SEQUENCEREG0B112S0_ADDR 0x179U
+#define CSR_SEQUENCEREG0B112S1_ADDR 0x17AU
+#define CSR_SEQUENCEREG0B112S2_ADDR 0x17BU
+#define CSR_SEQUENCEREG0B113S0_ADDR 0x17CU
+#define CSR_SEQUENCEREG0B113S1_ADDR 0x17DU
+#define CSR_SEQUENCEREG0B113S2_ADDR 0x17EU
+#define CSR_SEQUENCEREG0B114S0_ADDR 0x17FU
+#define CSR_SEQUENCEREG0B114S1_ADDR 0x180U
+#define CSR_SEQUENCEREG0B114S2_ADDR 0x181U
+#define CSR_SEQUENCEREG0B115S0_ADDR 0x182U
+#define CSR_SEQUENCEREG0B115S1_ADDR 0x183U
+#define CSR_SEQUENCEREG0B115S2_ADDR 0x184U
+#define CSR_SEQUENCEREG0B116S0_ADDR 0x185U
+#define CSR_SEQUENCEREG0B116S1_ADDR 0x186U
+#define CSR_SEQUENCEREG0B116S2_ADDR 0x187U
+#define CSR_SEQUENCEREG0B117S0_ADDR 0x188U
+#define CSR_SEQUENCEREG0B117S1_ADDR 0x189U
+#define CSR_SEQUENCEREG0B117S2_ADDR 0x18AU
+#define CSR_SEQUENCEREG0B118S0_ADDR 0x18BU
+#define CSR_SEQUENCEREG0B118S1_ADDR 0x18CU
+#define CSR_SEQUENCEREG0B118S2_ADDR 0x18DU
+#define CSR_SEQUENCEREG0B119S0_ADDR 0x18EU
+#define CSR_SEQUENCEREG0B119S1_ADDR 0x18FU
+#define CSR_SEQUENCEREG0B119S2_ADDR 0x190U
+#define CSR_SEQUENCEREG0B120S0_ADDR 0x191U
+#define CSR_SEQUENCEREG0B120S1_ADDR 0x192U
+#define CSR_SEQUENCEREG0B120S2_ADDR 0x193U
+#define CSR_SEQUENCEREG0B121S0_ADDR 0x194U
+#define CSR_SEQUENCEREG0B121S1_ADDR 0x195U
+#define CSR_SEQUENCEREG0B121S2_ADDR 0x196U
+#define CSR_SEQ0BGPR1_ADDR 0x201U
+#define CSR_SEQ0BGPR2_ADDR 0x202U
+#define CSR_SEQ0BGPR3_ADDR 0x203U
+#define CSR_SEQ0BGPR4_ADDR 0x204U
+#define CSR_SEQ0BGPR5_ADDR 0x205U
+#define CSR_SEQ0BGPR6_ADDR 0x206U
+#define CSR_SEQ0BGPR7_ADDR 0x207U
+#define CSR_SEQ0BGPR8_ADDR 0x208U
+#define CSR_SEQ0BFIXEDADDRBITS_ADDR 0x2FFU
+
+/* DRTUB0 register offsets */
+#define CSR_DCTSHADOWREGS_ADDR 0x4U
+#define CSR_DCTWRITEONLYSHADOW_ADDR 0x30U
+#define CSR_UCTWRITEONLY_ADDR 0x32U
+#define CSR_UCTWRITEPROT_ADDR 0x33U
+#define CSR_UCTDATWRITEONLY_ADDR 0x34U
+#define CSR_UCTDATWRITEPROT_ADDR 0x35U
+#define CSR_UCTLERR_ADDR 0x36U
+#define CSR_UCCLKHCLKENABLES_ADDR 0x80U
+#define CSR_CURPSTATE0B_ADDR 0x81U
+#define CSR_CLRWAKEUPSTICKY_ADDR 0x95U
+#define CSR_WAKEUPMASK_ADDR 0x96U
+#define CSR_CUSTPUBREV_ADDR 0xEDU
+#define CSR_PUBREV_ADDR 0xEEU
+
+/* APBONLY0 register offsets */
+#define CSR_MICROCONTMUXSEL_ADDR 0x0U
+#define CSR_UCTSHADOWREGS_ADDR 0x4U
+#define CSR_DCTWRITEONLY_ADDR 0x30U
+#define CSR_DCTWRITEPROT_ADDR 0x31U
+#define CSR_UCTWRITEONLYSHADOW_ADDR 0x32U
+#define CSR_UCTDATWRITEONLYSHADOW_ADDR 0x34U
+#define CSR_NEVERGATECSRCLOCK_ADDR 0x35U
+#define CSR_DFICFGRDDATAVALIDTICKS_ADDR 0x37U
+#define CSR_MICRORESET_ADDR 0x99U
+#define CSR_SEQUENCEROVERRIDE_ADDR 0xE7U
+#define CSR_DFIINITCOMPLETESHADOW_ADDR 0xFAU
+
+/* ANIBx register bit fields */
+/* CSR_MTESTMUXSEL */
+#define CSR_MTESTMUXSEL_LSB 0
+#define CSR_MTESTMUXSEL_MASK GENMASK_32(5, 0)
+/* CSR_AFORCEDRVCONT */
+#define CSR_AFORCEDRVCONT_LSB 0
+#define CSR_AFORCEDRVCONT_MASK GENMASK_32(3, 0)
+/* CSR_AFORCETRICONT */
+#define CSR_AFORCETRICONT_LSB 0
+#define CSR_AFORCETRICONT_MASK GENMASK_32(3, 0)
+/* CSR_ATXIMPEDANCE */
+#define CSR_ATXIMPEDANCE_LSB 0
+#define CSR_ATXIMPEDANCE_MASK GENMASK_32(9, 0)
+#define CSR_ADRVSTRENP_LSB 0
+#define CSR_ADRVSTRENP_MASK GENMASK_32(4, 0)
+#define CSR_ADRVSTRENN_LSB 5
+#define CSR_ADRVSTRENN_MASK GENMASK_32(9, 5)
+/* CSR_ATESTPRBSERR */
+#define CSR_ATESTPRBSERR_LSB 0
+#define CSR_ATESTPRBSERR_MASK GENMASK_32(3, 0)
+/* CSR_ATXSLEWRATE */
+#define CSR_ATXSLEWRATE_LSB 0
+#define CSR_ATXSLEWRATE_MASK GENMASK_32(10, 0)
+#define CSR_ATXPREP_LSB 0
+#define CSR_ATXPREP_MASK GENMASK_32(3, 0)
+#define CSR_ATXPREN_LSB 4
+#define CSR_ATXPREN_MASK GENMASK_32(7, 4)
+#define CSR_ATXPREDRVMODE_LSB 8
+#define CSR_ATXPREDRVMODE_MASK GENMASK_32(10, 8)
+/* CSR_ATESTPRBSERRCNT */
+#define CSR_ATESTPRBSERRCNT_LSB 0
+#define CSR_ATESTPRBSERRCNT_MASK GENMASK_32(15, 0)
+/* CSR_ATXDLY */
+#define CSR_ATXDLY_LSB 0
+#define CSR_ATXDLY_MASK GENMASK_32(6, 0)
+
+/* DBYTEx register bit fields */
+/* CSR_DBYTEMISCMODE */
+#define CSR_DBYTEMISCMODE_LSB 2
+#define CSR_DBYTEMISCMODE_MASK BIT(2)
+#define CSR_DBYTEDISABLE_LSB 2
+#define CSR_DBYTEDISABLE_MASK BIT(2)
+/* CSR_TSMBYTE0 */
+#define CSR_TSMBYTE0_LSB 0
+#define CSR_TSMBYTE0_MASK GENMASK_32(15, 0)
+#define CSR_PERPHTRAINEN_LSB 0
+#define CSR_PERPHTRAINEN_MASK BIT(0)
+#define CSR_EYEINC_LSB 1
+#define CSR_EYEINC_MASK BIT(1)
+#define CSR_EDGEINC_LSB 2
+#define CSR_EDGEINC_MASK BIT(2)
+#define CSR_EDGEEYEMXSEL_LSB 3
+#define CSR_EDGEEYEMXSEL_MASK BIT(3)
+#define CSR_TSMBYTE0RSVD_LSB 4
+#define CSR_TSMBYTE0RSVD_MASK GENMASK_32(5, 4)
+#define CSR_DIMMBROADINC_LSB 6
+#define CSR_DIMMBROADINC_MASK BIT(6)
+#define CSR_DIMMINC_LSB 7
+#define CSR_DIMMINC_MASK GENMASK_32(8, 7)
+#define CSR_COARSEINC_LSB 9
+#define CSR_COARSEINC_MASK BIT(9)
+#define CSR_DELAYINC_LSB 10
+#define CSR_DELAYINC_MASK BIT(10)
+#define CSR_RXINC_LSB 11
+#define CSR_RXINC_MASK BIT(11)
+#define CSR_RXPERTRAIN_LSB 12
+#define CSR_RXPERTRAIN_MASK BIT(12)
+#define CSR_TXPERTRAIN_LSB 13
+#define CSR_TXPERTRAIN_MASK BIT(13)
+#define CSR_DMTRAIN_LSB 14
+#define CSR_DMTRAIN_MASK BIT(14)
+#define CSR_WRLEVTRAIN_LSB 15
+#define CSR_WRLEVTRAIN_MASK BIT(15)
+/* CSR_TRAININGPARAM */
+#define CSR_TRAININGPARAM_LSB 0
+#define CSR_TRAININGPARAM_MASK GENMASK_32(15, 0)
+#define CSR_ENDYNRATEREDUCTION_LSB 0
+#define CSR_ENDYNRATEREDUCTION_MASK BIT(0)
+#define CSR_TRAININGPARAM01RSVD_LSB 1
+#define CSR_TRAININGPARAM01RSVD_MASK BIT(1)
+#define CSR_TRAINENRXCLK_LSB 2
+#define CSR_TRAINENRXCLK_MASK BIT(2)
+#define CSR_TRAINENRXEN_LSB 3
+#define CSR_TRAINENRXEN_MASK BIT(3)
+#define CSR_TRAINENTXDQS_LSB 4
+#define CSR_TRAINENTXDQS_MASK BIT(4)
+#define CSR_TRAINENTXDQ_LSB 5
+#define CSR_TRAINENTXDQ_MASK BIT(5)
+#define CSR_TRAINENVREFDAC1_LSB 6
+#define CSR_TRAINENVREFDAC1_MASK BIT(6)
+#define CSR_TRAINENVREFDAC0_LSB 7
+#define CSR_TRAINENVREFDAC0_MASK BIT(7)
+#define CSR_TRAINENRXPBD_LSB 8
+#define CSR_TRAINENRXPBD_MASK BIT(8)
+#define CSR_ROLLINTOCOARSE_LSB 9
+#define CSR_ROLLINTOCOARSE_MASK BIT(9)
+#define CSR_TRAINUSINGNATIVEDDLCNTL_LSB 10
+#define CSR_TRAINUSINGNATIVEDDLCNTL_MASK BIT(10)
+#define CSR_TRAININGPARAM11RSVD_LSB 11
+#define CSR_TRAININGPARAM11RSVD_MASK BIT(11)
+#define CSR_TRAININGPARAM12RSVD_LSB 12
+#define CSR_TRAININGPARAM12RSVD_MASK BIT(12)
+#define CSR_INCDECRATE_LSB 13
+#define CSR_INCDECRATE_MASK GENMASK_32(15, 13)
+/* CSR_USEDQSENREPLICA */
+#define CSR_USEDQSENREPLICA_LSB 0
+#define CSR_USEDQSENREPLICA_MASK BIT(0)
+/* CSR_RXTRAINPATTERNENABLE */
+#define CSR_RXTRAINPATTERNENABLE_LSB 0
+#define CSR_RXTRAINPATTERNENABLE_MASK BIT(0)
+/* CSR_TSMBYTE1 */
+#define CSR_TSMBYTE1_LSB 0
+#define CSR_TSMBYTE1_MASK GENMASK_32(15, 0)
+#define CSR_DTSMBDSTP_LSB 0
+#define CSR_DTSMBDSTP_MASK GENMASK_32(7, 0)
+#define CSR_DTSMGDSTP_LSB 8
+#define CSR_DTSMGDSTP_MASK GENMASK_32(15, 8)
+/* CSR_TSMBYTE2 */
+#define CSR_TSMBYTE2_LSB 0
+#define CSR_TSMBYTE2_MASK GENMASK_32(15, 0)
+#define CSR_DTSMGDBAR_LSB 0
+#define CSR_DTSMGDBAR_MASK GENMASK_32(15, 0)
+/* CSR_TSMBYTE3 */
+#define CSR_TSMBYTE3_LSB 0
+#define CSR_TSMBYTE3_MASK GENMASK_32(8, 0)
+#define CSR_DTSMINCDECMODE_LSB 0
+#define CSR_DTSMINCDECMODE_MASK BIT(0)
+#define CSR_DTSMINCDECCTRL_LSB 1
+#define CSR_DTSMINCDECCTRL_MASK BIT(1)
+#define CSR_ENBLRXSAMPFLOPS_LSB 2
+#define CSR_ENBLRXSAMPFLOPS_MASK BIT(2)
+#define CSR_SELRXSAMPFLOPS_LSB 3
+#define CSR_SELRXSAMPFLOPS_MASK BIT(3)
+#define CSR_SELRXBYBASS_LSB 4
+#define CSR_SELRXBYBASS_MASK BIT(4)
+#define CSR_DTSMIGNUPDATEACK_LSB 5
+#define CSR_DTSMIGNUPDATEACK_MASK BIT(5)
+#define CSR_ENABLERXDQASYNC_LSB 6
+#define CSR_ENABLERXDQASYNC_MASK BIT(6)
+#define CSR_DTSMSTATICCMPR_LSB 7
+#define CSR_DTSMSTATICCMPR_MASK BIT(7)
+#define CSR_DTSMSTATICCMPRVAL_LSB 8
+#define CSR_DTSMSTATICCMPRVAL_MASK BIT(8)
+/* CSR_TSMBYTE4 */
+#define CSR_TSMBYTE4_LSB 0
+#define CSR_TSMBYTE4_MASK GENMASK_32(3, 0)
+#define CSR_DTSMINCDECPW_LSB 0
+#define CSR_DTSMINCDECPW_MASK GENMASK_32(3, 0)
+/* CSR_TESTMODECONFIG */
+#define CSR_TESTMODECONFIG_LSB 0
+#define CSR_TESTMODECONFIG_MASK GENMASK_32(9, 0)
+#define CSR_LOOPBACKEN_LSB 0
+#define CSR_LOOPBACKEN_MASK BIT(0)
+#define CSR_RSVDTESTDLLEN_LSB 1
+#define CSR_RSVDTESTDLLEN_MASK BIT(1)
+#define CSR_RSVDTWOTCKTXDQSPRE_LSB 2
+#define CSR_RSVDTWOTCKTXDQSPRE_MASK BIT(2)
+#define CSR_TESTMODERSVD_LSB 3
+#define CSR_TESTMODERSVD_MASK GENMASK_32(7, 3)
+#define CSR_LOOPBACKDISDQSTRI_LSB 8
+#define CSR_LOOPBACKDISDQSTRI_MASK BIT(8)
+#define CSR_RSVDDISTXDQEQPREAMBLE_LSB 9
+#define CSR_RSVDDISTXDQEQPREAMBLE_MASK BIT(9)
+/* CSR_TSMBYTE5 */
+#define CSR_TSMBYTE5_LSB 0
+#define CSR_TSMBYTE5_MASK GENMASK_32(15, 0)
+#define CSR_DTSMBDBAR_LSB 0
+#define CSR_DTSMBDBAR_MASK GENMASK_32(15, 0)
+/* MTESTMUXSEL already defined in ANIBx section */
+/* CSR_DTSMTRAINMODECTRL */
+#define CSR_DTSMTRAINMODECTRL_LSB 0
+#define CSR_DTSMTRAINMODECTRL_MASK GENMASK_32(3, 0)
+#define CSR_DTSMSOELANEMODE_LSB 0
+#define CSR_DTSMSOELANEMODE_MASK GENMASK_32(1, 0)
+#define CSR_DTSMBYTEERRANDMODE_LSB 2
+#define CSR_DTSMBYTEERRANDMODE_MASK BIT(2)
+#define CSR_DTSMNIBERRMODE_LSB 3
+#define CSR_DTSMNIBERRMODE_MASK BIT(3)
+/* CSR_DFIMRL */
+#define CSR_DFIMRL_LSB 0
+#define CSR_DFIMRL_MASK GENMASK_32(4, 0)
+/* CSR_ASYNCDBYTEMODE */
+#define CSR_ASYNCDBYTEMODE_LSB 0
+#define CSR_ASYNCDBYTEMODE_MASK GENMASK_32(8, 0)
+/* CSR_ASYNCDBYTETXEN */
+#define CSR_ASYNCDBYTETXEN_LSB 0
+#define CSR_ASYNCDBYTETXEN_MASK GENMASK_32(11, 0)
+/* CSR_ASYNCDBYTETXDATA */
+#define CSR_ASYNCDBYTETXDATA_LSB 0
+#define CSR_ASYNCDBYTETXDATA_MASK GENMASK_32(11, 0)
+/* CSR_ASYNCDBYTERXDATA */
+#define CSR_ASYNCDBYTERXDATA_LSB 0
+#define CSR_ASYNCDBYTERXDATA_MASK GENMASK_32(11, 0)
+/* CSR_VREFDAC1 */
+#define CSR_VREFDAC1_LSB 0
+#define CSR_VREFDAC1_MASK GENMASK_32(6, 0)
+/* CSR_TRAININGCNTR */
+#define CSR_TRAININGCNTR_LSB 0
+#define CSR_TRAININGCNTR_MASK GENMASK_32(15, 0)
+#define CSR_TRAININGCNTRFINE_LSB 0
+#define CSR_TRAININGCNTRFINE_MASK GENMASK_32(9, 0)
+#define CSR_TRAININGCNTRCOARSE_LSB 10
+#define CSR_TRAININGCNTRCOARSE_MASK GENMASK_32(15, 10)
+/* CSR_VREFDAC0 */
+#define CSR_VREFDAC0_LSB 0
+#define CSR_VREFDAC0_MASK GENMASK_32(6, 0)
+/* CSR_TXIMPEDANCECTRL0 */
+#define CSR_TXIMPEDANCECTRL0_LSB 0
+#define CSR_TXIMPEDANCECTRL0_MASK GENMASK_32(11, 0)
+#define CSR_DRVSTRENDQP_LSB 0
+#define CSR_DRVSTRENDQP_MASK GENMASK_32(5, 0)
+#define CSR_DRVSTRENDQN_LSB 6
+#define CSR_DRVSTRENDQN_MASK GENMASK_32(11, 6)
+/* CSR_DQDQSRCVCNTRL */
+#define CSR_DQDQSRCVCNTRL_LSB 0
+#define CSR_DQDQSRCVCNTRL_MASK GENMASK_32(15, 0)
+#define CSR_SELANALOGVREF_LSB 0
+#define CSR_SELANALOGVREF_MASK BIT(0)
+#define CSR_EXTVREFRANGE_LSB 1
+#define CSR_EXTVREFRANGE_MASK BIT(1)
+#define CSR_DFECTRL_LSB 2
+#define CSR_DFECTRL_MASK GENMASK_32(3, 2)
+#define CSR_MAJORMODEDBYTE_LSB 4
+#define CSR_MAJORMODEDBYTE_MASK GENMASK_32(6, 4)
+#define CSR_GAINCURRADJ_LSB 7
+#define CSR_GAINCURRADJ_MASK GENMASK_32(11, 7)
+#define CSR_RESERVED_LSB 12
+#define CSR_RESERVED_MASK GENMASK_32(15, 12)
+/* CSR_TXEQUALIZATIONMODE */
+#define CSR_TXEQUALIZATIONMODE_LSB 0
+#define CSR_TXEQUALIZATIONMODE_MASK GENMASK_32(1, 0)
+#define CSR_TXEQMODE_LSB 0
+#define CSR_TXEQMODE_MASK GENMASK_32(1, 0)
+/* CSR_TXIMPEDANCECTRL1 */
+#define CSR_TXIMPEDANCECTRL1_LSB 0
+#define CSR_TXIMPEDANCECTRL1_MASK GENMASK_32(11, 0)
+#define CSR_DRVSTRENFSDQP_LSB 0
+#define CSR_DRVSTRENFSDQP_MASK GENMASK_32(5, 0)
+#define CSR_DRVSTRENFSDQN_LSB 6
+#define CSR_DRVSTRENFSDQN_MASK GENMASK_32(11, 6)
+/* CSR_DQDQSRCVCNTRL1 */
+#define CSR_DQDQSRCVCNTRL1_LSB 0
+#define CSR_DQDQSRCVCNTRL1_MASK GENMASK_32(11, 0)
+#define CSR_POWERDOWNRCVR_LSB 0
+#define CSR_POWERDOWNRCVR_MASK GENMASK_32(8, 0)
+#define CSR_POWERDOWNRCVRDQS_LSB 9
+#define CSR_POWERDOWNRCVRDQS_MASK BIT(9)
+#define CSR_RXPADSTANDBYEN_LSB 10
+#define CSR_RXPADSTANDBYEN_MASK BIT(10)
+#define CSR_ENLPREQPDR_LSB 11
+#define CSR_ENLPREQPDR_MASK BIT(11)
+/* CSR_TXIMPEDANCECTRL2 */
+#define CSR_TXIMPEDANCECTRL2_LSB 0
+#define CSR_TXIMPEDANCECTRL2_MASK GENMASK_32(11, 0)
+#define CSR_DRVSTRENEQHIDQP_LSB 0
+#define CSR_DRVSTRENEQHIDQP_MASK GENMASK_32(5, 0)
+#define CSR_DRVSTRENEQLODQN_LSB 6
+#define CSR_DRVSTRENEQLODQN_MASK GENMASK_32(11, 6)
+/* CSR_DQDQSRCVCNTRL2 */
+#define CSR_DQDQSRCVCNTRL2_LSB 0
+#define CSR_DQDQSRCVCNTRL2_MASK BIT(0)
+#define CSR_ENRXAGRESSIVEPDR_LSB 0
+#define CSR_ENRXAGRESSIVEPDR_MASK BIT(0)
+/* CSR_TXODTDRVSTREN */
+#define CSR_TXODTDRVSTREN_LSB 0
+#define CSR_TXODTDRVSTREN_MASK GENMASK_32(11, 0)
+#define CSR_ODTSTRENP_LSB 0
+#define CSR_ODTSTRENP_MASK GENMASK_32(5, 0)
+#define CSR_ODTSTRENN_LSB 6
+#define CSR_ODTSTRENN_MASK GENMASK_32(11, 6)
+/* CSR_RXFIFOCHECKSTATUS */
+#define CSR_RXFIFOCHECKSTATUS_LSB 0
+#define CSR_RXFIFOCHECKSTATUS_MASK GENMASK_32(1, 0)
+#define CSR_RXFIFOLOCERR_LSB 0
+#define CSR_RXFIFOLOCERR_MASK BIT(0)
+#define CSR_RXFIFOLOCUERR_LSB 1
+#define CSR_RXFIFOLOCUERR_MASK BIT(1)
+/* CSR_RXFIFOCHECKERRVALUES */
+#define CSR_RXFIFOCHECKERRVALUES_LSB 0
+#define CSR_RXFIFOCHECKERRVALUES_MASK GENMASK_32(15, 0)
+#define CSR_RXFIFORDLOCERRVALUE_LSB 0
+#define CSR_RXFIFORDLOCERRVALUE_MASK GENMASK_32(3, 0)
+#define CSR_RXFIFOWRLOCERRVALUE_LSB 4
+#define CSR_RXFIFOWRLOCERRVALUE_MASK GENMASK_32(7, 4)
+#define CSR_RXFIFORDLOCUERRVALUE_LSB 8
+#define CSR_RXFIFORDLOCUERRVALUE_MASK GENMASK_32(11, 8)
+#define CSR_RXFIFOWRLOCUERRVALUE_LSB 12
+#define CSR_RXFIFOWRLOCUERRVALUE_MASK GENMASK_32(15, 12)
+/* CSR_RXFIFOINFO */
+#define CSR_RXFIFOINFO_LSB 0
+#define CSR_RXFIFOINFO_MASK GENMASK_32(15, 0)
+#define CSR_RXFIFORDLOC_LSB 0
+#define CSR_RXFIFORDLOC_MASK GENMASK_32(3, 0)
+#define CSR_RXFIFOWRLOC_LSB 4
+#define CSR_RXFIFOWRLOC_MASK GENMASK_32(7, 4)
+#define CSR_RXFIFORDLOCU_LSB 8
+#define CSR_RXFIFORDLOCU_MASK GENMASK_32(11, 8)
+#define CSR_RXFIFOWRLOCU_LSB 12
+#define CSR_RXFIFOWRLOCU_MASK GENMASK_32(15, 12)
+/* CSR_RXFIFOVISIBILITY */
+#define CSR_RXFIFOVISIBILITY_LSB 0
+#define CSR_RXFIFOVISIBILITY_MASK GENMASK_32(4, 0)
+#define CSR_RXFIFORDPTR_LSB 0
+#define CSR_RXFIFORDPTR_MASK GENMASK_32(2, 0)
+#define CSR_RXFIFORDPTROVR_LSB 3
+#define CSR_RXFIFORDPTROVR_MASK BIT(3)
+#define CSR_RXFIFORDEN_LSB 4
+#define CSR_RXFIFORDEN_MASK BIT(4)
+/* CSR_RXFIFOCONTENTSDQ3210 */
+#define CSR_RXFIFOCONTENTSDQ3210_LSB 0
+#define CSR_RXFIFOCONTENTSDQ3210_MASK GENMASK_32(15, 0)
+/* CSR_RXFIFOCONTENTSDQ7654 */
+#define CSR_RXFIFOCONTENTSDQ7654_LSB 0
+#define CSR_RXFIFOCONTENTSDQ7654_MASK GENMASK_32(15, 0)
+/* CSR_RXFIFOCONTENTSDBI */
+#define CSR_RXFIFOCONTENTSDBI_LSB 0
+#define CSR_RXFIFOCONTENTSDBI_MASK GENMASK_32(3, 0)
+/* CSR_TXSLEWRATE */
+#define CSR_TXSLEWRATE_LSB 0
+#define CSR_TXSLEWRATE_MASK GENMASK_32(10, 0)
+#define CSR_TXPREP_LSB 0
+#define CSR_TXPREP_MASK GENMASK_32(3, 0)
+#define CSR_TXPREN_LSB 4
+#define CSR_TXPREN_MASK GENMASK_32(7, 4)
+#define CSR_TXPREDRVMODE_LSB 8
+#define CSR_TXPREDRVMODE_MASK GENMASK_32(10, 8)
+/* CSR_TRAININGINCDECDTSMEN */
+#define CSR_TRAININGINCDECDTSMEN_LSB 0
+#define CSR_TRAININGINCDECDTSMEN_MASK GENMASK_32(8, 0)
+/* CSR_RXPBDLYTG0 */
+#define CSR_RXPBDLYTG0_LSB 0
+#define CSR_RXPBDLYTG0_MASK GENMASK_32(6, 0)
+/* CSR_RXPBDLYTG1 */
+#define CSR_RXPBDLYTG1_LSB 0
+#define CSR_RXPBDLYTG1_MASK GENMASK_32(6, 0)
+/* CSR_RXPBDLYTG2 */
+#define CSR_RXPBDLYTG2_LSB 0
+#define CSR_RXPBDLYTG2_MASK GENMASK_32(6, 0)
+/* CSR_RXPBDLYTG3 */
+#define CSR_RXPBDLYTG3_LSB 0
+#define CSR_RXPBDLYTG3_MASK GENMASK_32(6, 0)
+/* CSR_RXENDLYTG0 */
+#define CSR_RXENDLYTG0_LSB 0
+#define CSR_RXENDLYTG0_MASK GENMASK_32(10, 0)
+/* CSR_RXENDLYTG1 */
+#define CSR_RXENDLYTG1_LSB 0
+#define CSR_RXENDLYTG1_MASK GENMASK_32(10, 0)
+/* CSR_RXENDLYTG2 */
+#define CSR_RXENDLYTG2_LSB 0
+#define CSR_RXENDLYTG2_MASK GENMASK_32(10, 0)
+/* CSR_RXENDLYTG3 */
+#define CSR_RXENDLYTG3_LSB 0
+#define CSR_RXENDLYTG3_MASK GENMASK_32(10, 0)
+/* CSR_RXCLKDLYTG0 */
+#define CSR_RXCLKDLYTG0_LSB 0
+#define CSR_RXCLKDLYTG0_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKDLYTG1 */
+#define CSR_RXCLKDLYTG1_LSB 0
+#define CSR_RXCLKDLYTG1_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKDLYTG2 */
+#define CSR_RXCLKDLYTG2_LSB 0
+#define CSR_RXCLKDLYTG2_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKDLYTG3 */
+#define CSR_RXCLKDLYTG3_LSB 0
+#define CSR_RXCLKDLYTG3_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKCDLYTG0 */
+#define CSR_RXCLKCDLYTG0_LSB 0
+#define CSR_RXCLKCDLYTG0_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKCDLYTG1 */
+#define CSR_RXCLKCDLYTG1_LSB 0
+#define CSR_RXCLKCDLYTG1_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKCDLYTG2 */
+#define CSR_RXCLKCDLYTG2_LSB 0
+#define CSR_RXCLKCDLYTG2_MASK GENMASK_32(5, 0)
+/* CSR_RXCLKCDLYTG3 */
+#define CSR_RXCLKCDLYTG3_LSB 0
+#define CSR_RXCLKCDLYTG3_MASK GENMASK_32(5, 0)
+/* CSR_DQ0LNSEL */
+#define CSR_DQ0LNSEL_LSB 0
+#define CSR_DQ0LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ1LNSEL */
+#define CSR_DQ1LNSEL_LSB 0
+#define CSR_DQ1LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ2LNSEL */
+#define CSR_DQ2LNSEL_LSB 0
+#define CSR_DQ2LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ3LNSEL */
+#define CSR_DQ3LNSEL_LSB 0
+#define CSR_DQ3LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ4LNSEL */
+#define CSR_DQ4LNSEL_LSB 0
+#define CSR_DQ4LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ5LNSEL */
+#define CSR_DQ5LNSEL_LSB 0
+#define CSR_DQ5LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ6LNSEL */
+#define CSR_DQ6LNSEL_LSB 0
+#define CSR_DQ6LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_DQ7LNSEL */
+#define CSR_DQ7LNSEL_LSB 0
+#define CSR_DQ7LNSEL_MASK GENMASK_32(2, 0)
+/* CSR_PPTCTLSTATIC */
+#define CSR_PPTCTLSTATIC_LSB 0
+#define CSR_PPTCTLSTATIC_MASK GENMASK_32(11, 0)
+#define CSR_PPTENDQS2DQTG0_LSB 0
+#define CSR_PPTENDQS2DQTG0_MASK BIT(0)
+#define CSR_PPTENDQS2DQTG1_LSB 1
+#define CSR_PPTENDQS2DQTG1_MASK BIT(1)
+#define CSR_DOCBYTESELTG0_LSB 2
+#define CSR_DOCBYTESELTG0_MASK BIT(2)
+#define CSR_DOCBYTESELTG1_LSB 3
+#define CSR_DOCBYTESELTG1_MASK BIT(3)
+#define CSR_PPTINFOSEL_LSB 4
+#define CSR_PPTINFOSEL_MASK GENMASK_32(7, 4)
+#define CSR_PPTENRXENDLYTG0_LSB 8
+#define CSR_PPTENRXENDLYTG0_MASK BIT(8)
+#define CSR_PPTENRXENDLYTG1_LSB 9
+#define CSR_PPTENRXENDLYTG1_MASK BIT(9)
+#define CSR_PPTENRXENBACKOFF_LSB 10
+#define CSR_PPTENRXENBACKOFF_MASK GENMASK_32(11, 10)
+/* CSR_PPTCTLDYN */
+#define CSR_PPTCTLDYN_LSB 0
+#define CSR_PPTCTLDYN_MASK GENMASK_32(1, 0)
+#define CSR_PPTDQS2DQACTIVE_LSB 0
+#define CSR_PPTDQS2DQACTIVE_MASK BIT(0)
+#define CSR_PPTENRXENUSEDQSSAMPVAL_LSB 1
+#define CSR_PPTENRXENUSEDQSSAMPVAL_MASK BIT(1)
+/* CSR_PPTINFO */
+#define CSR_PPTINFO_LSB 0
+#define CSR_PPTINFO_MASK GENMASK_32(15, 0)
+/* CSR_PPTRXENEVNT */
+#define CSR_PPTRXENEVNT_LSB 0
+#define CSR_PPTRXENEVNT_MASK GENMASK_32(1, 0)
+#define CSR_PPTRXENINIT_LSB 0
+#define CSR_PPTRXENINIT_MASK BIT(0)
+#define CSR_PPTRXENMHUI_LSB 1
+#define CSR_PPTRXENMHUI_MASK BIT(1)
+/* CSR_PPTDQSCNTINVTRNTG0 */
+#define CSR_PPTDQSCNTINVTRNTG0_LSB 0
+#define CSR_PPTDQSCNTINVTRNTG0_MASK GENMASK_32(15, 0)
+/* CSR_PPTDQSCNTINVTRNTG1 */
+#define CSR_PPTDQSCNTINVTRNTG1_LSB 0
+#define CSR_PPTDQSCNTINVTRNTG1_MASK GENMASK_32(15, 0)
+/* CSR_DTSMBLANKINGCTRL */
+#define CSR_DTSMBLANKINGCTRL_LSB 0
+#define CSR_DTSMBLANKINGCTRL_MASK GENMASK_32(9, 0)
+#define CSR_DTSMBLANK_LSB 0
+#define CSR_DTSMBLANK_MASK GENMASK_32(9, 0)
+/* CSR_TSM0 */
+#define CSR_TSM0_LSB 0
+#define CSR_TSM0_MASK GENMASK_32(13, 0)
+#define CSR_DTSMENB_LSB 0
+#define CSR_DTSMENB_MASK BIT(0)
+#define CSR_DTSMDIR_LSB 1
+#define CSR_DTSMDIR_MASK BIT(1)
+#define CSR_DTSMIGNFRST_LSB 2
+#define CSR_DTSMIGNFRST_MASK BIT(2)
+#define CSR_DTSMODDPHASE_LSB 3
+#define CSR_DTSMODDPHASE_MASK BIT(3)
+#define CSR_DTSMFLTPRE_LSB 4
+#define CSR_DTSMFLTPRE_MASK BIT(4)
+#define CSR_DTSMFLTCUR_LSB 5
+#define CSR_DTSMFLTCUR_MASK BIT(5)
+#define CSR_DTSMFLTNXT_LSB 6
+#define CSR_DTSMFLTNXT_MASK BIT(6)
+#define CSR_DTSMFLTVAL_LSB 7
+#define CSR_DTSMFLTVAL_MASK GENMASK_32(9, 7)
+#define CSR_DTSMMSKBIT_LSB 10
+#define CSR_DTSMMSKBIT_MASK GENMASK_32(13, 10)
+/* CSR_TSM1 */
+#define CSR_TSM1_LSB 0
+#define CSR_TSM1_MASK GENMASK_32(15, 0)
+#define CSR_DTSMERRCNT_LSB 0
+#define CSR_DTSMERRCNT_MASK GENMASK_32(15, 0)
+/* CSR_TSM2 */
+#define CSR_TSM2_LSB 0
+#define CSR_TSM2_MASK BIT(0)
+#define CSR_DTSMDISERRCHK_LSB 0
+#define CSR_DTSMDISERRCHK_MASK BIT(0)
+/* CSR_TSM3 */
+#define CSR_TSM3_LSB 0
+#define CSR_TSM3_MASK GENMASK_32(9, 0)
+#define CSR_DTSMCLRERRCNTMSK_LSB 0
+#define CSR_DTSMCLRERRCNTMSK_MASK GENMASK_32(8, 0)
+#define CSR_DTSMCLRERRCNT_LSB 9
+#define CSR_DTSMCLRERRCNT_MASK BIT(9)
+/* CSR_TXCHKDATASELECTS */
+#define CSR_TXCHKDATASELECTS_LSB 0
+#define CSR_TXCHKDATASELECTS_MASK GENMASK_32(1, 0)
+#define CSR_SELCHKTOTX_LSB 0
+#define CSR_SELCHKTOTX_MASK BIT(0)
+#define CSR_SELTXTOCHK_LSB 1
+#define CSR_SELTXTOCHK_MASK BIT(1)
+/* CSR_DTSMUPTHLDXINGIND */
+#define CSR_DTSMUPTHLDXINGIND_LSB 0
+#define CSR_DTSMUPTHLDXINGIND_MASK GENMASK_32(8, 0)
+/* CSR_DTSMLOTHLDXINGIND */
+#define CSR_DTSMLOTHLDXINGIND_LSB 0
+#define CSR_DTSMLOTHLDXINGIND_MASK GENMASK_32(8, 0)
+/* CSR_DBYTEALLDTSMCTRL0 */
+#define CSR_DBYTEALLDTSMCTRL0_LSB 0
+#define CSR_DBYTEALLDTSMCTRL0_MASK GENMASK_32(8, 0)
+#define CSR_DTSMINHIBDTSM_LSB 0
+#define CSR_DTSMINHIBDTSM_MASK GENMASK_32(8, 0)
+/* CSR_DBYTEALLDTSMCTRL1 */
+#define CSR_DBYTEALLDTSMCTRL1_LSB 0
+#define CSR_DBYTEALLDTSMCTRL1_MASK GENMASK_32(8, 0)
+#define CSR_DTSMGATEINC_LSB 0
+#define CSR_DTSMGATEINC_MASK GENMASK_32(8, 0)
+/* CSR_DBYTEALLDTSMCTRL2 */
+#define CSR_DBYTEALLDTSMCTRL2_LSB 0
+#define CSR_DBYTEALLDTSMCTRL2_MASK GENMASK_32(8, 0)
+#define CSR_DTSMGATEDEC_LSB 0
+#define CSR_DTSMGATEDEC_MASK GENMASK_32(8, 0)
+/* CSR_TXDQDLYTG0 */
+#define CSR_TXDQDLYTG0_LSB 0
+#define CSR_TXDQDLYTG0_MASK GENMASK_32(8, 0)
+/* CSR_TXDQDLYTG1 */
+#define CSR_TXDQDLYTG1_LSB 0
+#define CSR_TXDQDLYTG1_MASK GENMASK_32(8, 0)
+/* CSR_TXDQDLYTG2 */
+#define CSR_TXDQDLYTG2_LSB 0
+#define CSR_TXDQDLYTG2_MASK GENMASK_32(8, 0)
+/* CSR_TXDQDLYTG3 */
+#define CSR_TXDQDLYTG3_LSB 0
+#define CSR_TXDQDLYTG3_MASK GENMASK_32(8, 0)
+/* CSR_TXDQSDLYTG0 */
+#define CSR_TXDQSDLYTG0_LSB 0
+#define CSR_TXDQSDLYTG0_MASK GENMASK_32(9, 0)
+/* CSR_TXDQSDLYTG1 */
+#define CSR_TXDQSDLYTG1_LSB 0
+#define CSR_TXDQSDLYTG1_MASK GENMASK_32(9, 0)
+/* CSR_TXDQSDLYTG2 */
+#define CSR_TXDQSDLYTG2_LSB 0
+#define CSR_TXDQSDLYTG2_MASK GENMASK_32(9, 0)
+/* CSR_TXDQSDLYTG3 */
+#define CSR_TXDQSDLYTG3_LSB 0
+#define CSR_TXDQSDLYTG3_MASK GENMASK_32(9, 0)
+/* CSR_DXLCDLSTATUS_ADDR */
+#define CSR_DXLCDLSTATUS_LSB 0
+#define CSR_DXLCDLSTATUS_MASK GENMASK_32(13, 0)
+#define CSR_DXLCDLFINESNAPVAL_LSB 0
+#define CSR_DXLCDLFINESNAPVAL_MASK GENMASK_32(9, 0)
+#define CSR_DXLCDLPHDSNAPVAL_LSB 10
+#define CSR_DXLCDLPHDSNAPVAL_MASK BIT(10)
+#define CSR_DXLCDLSTICKYLOCK_LSB 11
+#define CSR_DXLCDLSTICKYLOCK_MASK BIT(11)
+#define CSR_DXLCDLSTICKYUNLOCK_LSB 12
+#define CSR_DXLCDLSTICKYUNLOCK_MASK BIT(12)
+#define CSR_DXLCDLLIVELOCK_LSB 13
+#define CSR_DXLCDLLIVELOCK_MASK BIT(13)
+
+/* MASTER0 register offsets */
+/* CSR_RXFIFOINIT */
+#define CSR_RXFIFOINIT_LSB 0
+#define CSR_RXFIFOINIT_MASK GENMASK_32(1, 0)
+#define CSR_RXFIFOINITPTR_LSB 0
+#define CSR_RXFIFOINITPTR_MASK BIT(0)
+#define CSR_INHIBITRXFIFORD_LSB 1
+#define CSR_INHIBITRXFIFORD_MASK BIT(1)
+/* CSR_FORCECLKDISABLE */
+#define CSR_FORCECLKDISABLE_LSB 0
+#define CSR_FORCECLKDISABLE_MASK GENMASK_32(3, 0)
+/* CSR_CLOCKINGCTRL */
+#define CSR_CLOCKINGCTRL_LSB 0
+#define CSR_CLOCKINGCTRL_MASK GENMASK_32(1, 0)
+#define CSR_PCLKENASYNCCTRL_LSB 0
+#define CSR_PCLKENASYNCCTRL_MASK BIT(0)
+#define CSR_DLLTRACKENCTRL_LSB 1
+#define CSR_DLLTRACKENCTRL_MASK BIT(1)
+/* CSR_FORCEINTERNALUPDATE */
+#define CSR_FORCEINTERNALUPDATE_LSB 0
+#define CSR_FORCEINTERNALUPDATE_MASK BIT(0)
+/* CSR_PHYCONFIG */
+#define CSR_PHYCONFIG_LSB 0
+#define CSR_PHYCONFIG_MASK GENMASK_32(9, 0)
+#define CSR_PHYCONFIGANIBS_LSB 0
+#define CSR_PHYCONFIGANIBS_MASK GENMASK_32(3, 0)
+#define CSR_PHYCONFIGDBYTES_LSB 4
+#define CSR_PHYCONFIGDBYTES_MASK GENMASK_32(7, 4)
+#define CSR_PHYCONFIGDFI_LSB 8
+#define CSR_PHYCONFIGDFI_MASK GENMASK_32(9, 8)
+/* CSR_PGCR */
+#define CSR_PGCR_LSB 0
+#define CSR_PGCR_MASK BIT(0)
+#define CSR_RXCLKRISEFALLMODE_LSB 0
+#define CSR_RXCLKRISEFALLMODE_MASK BIT(0)
+/* CSR_TESTBUMPCNTRL1 */
+#define CSR_TESTBUMPCNTRL1_LSB 0
+#define CSR_TESTBUMPCNTRL1_MASK GENMASK_32(15, 0)
+#define CSR_TESTMAJORMODE_LSB 0
+#define CSR_TESTMAJORMODE_MASK GENMASK_32(2, 0)
+#define CSR_TESTBIASBYPASSEN_LSB 3
+#define CSR_TESTBIASBYPASSEN_MASK BIT(3)
+#define CSR_TESTANALOGOUTCTRL_LSB 4
+#define CSR_TESTANALOGOUTCTRL_MASK GENMASK_32(7, 4)
+#define CSR_TESTGAINCURRADJ_LSB 8
+#define CSR_TESTGAINCURRADJ_MASK GENMASK_32(12, 8)
+#define CSR_TESTSELEXTERNALVREF_LSB 13
+#define CSR_TESTSELEXTERNALVREF_MASK BIT(13)
+#define CSR_TESTEXTVREFRANGE_LSB 14
+#define CSR_TESTEXTVREFRANGE_MASK BIT(14)
+#define CSR_TESTPOWERGATEEN_LSB 15
+#define CSR_TESTPOWERGATEEN_MASK BIT(15)
+/* CSR_CALUCLKINFO */
+#define CSR_CALUCLKINFO_LSB 0
+#define CSR_CALUCLKINFO_MASK GENMASK_32(10, 0)
+#define CSR_CALUCLKTICKSPER1US_LSB 0
+#define CSR_CALUCLKTICKSPER1US_MASK GENMASK_32(10, 0)
+/* CSR_TESTBUMPCNTRL */
+#define CSR_TESTBUMPCNTRL_LSB 0
+#define CSR_TESTBUMPCNTRL_MASK GENMASK_32(9, 0)
+#define CSR_TESTBUMPEN_LSB 0
+#define CSR_TESTBUMPEN_MASK GENMASK_32(1, 0)
+#define CSR_TESTBUMPTOGGLE_LSB 2
+#define CSR_TESTBUMPTOGGLE_MASK BIT(2)
+#define CSR_TESTBUMPDATASEL_LSB 3
+#define CSR_TESTBUMPDATASEL_MASK GENMASK_32(8, 3)
+#define CSR_FORCEMTESTONALERT_LSB 9
+#define CSR_FORCEMTESTONALERT_MASK BIT(9)
+/* CSR_SEQ0BDLY0 */
+#define CSR_SEQ0BDLY0_LSB 0
+#define CSR_SEQ0BDLY0_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDLY1 */
+#define CSR_SEQ0BDLY1_LSB 0
+#define CSR_SEQ0BDLY1_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDLY2 */
+#define CSR_SEQ0BDLY2_LSB 0
+#define CSR_SEQ0BDLY2_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDLY3 */
+#define CSR_SEQ0BDLY3_LSB 0
+#define CSR_SEQ0BDLY3_MASK GENMASK_32(15, 0)
+/* CSR_PHYALERTSTATUS */
+#define CSR_PHYALERTSTATUS_LSB 0
+#define CSR_PHYALERTSTATUS_MASK BIT(0)
+#define CSR_PHYALERT_LSB 0
+#define CSR_PHYALERT_MASK BIT(0)
+/* CSR_PPTTRAINSETUP */
+#define CSR_PPTTRAINSETUP_LSB 0
+#define CSR_PPTTRAINSETUP_MASK GENMASK_32(6, 0)
+#define CSR_PHYMSTRTRAININTERVAL_LSB 0
+#define CSR_PHYMSTRTRAININTERVAL_MASK GENMASK_32(3, 0)
+#define CSR_PHYMSTRMAXREQTOACK_LSB 4
+#define CSR_PHYMSTRMAXREQTOACK_MASK GENMASK_32(6, 4)
+/* CSR_PPTTRAINSETUP2 */
+#define CSR_PPTTRAINSETUP2_LSB 0
+#define CSR_PPTTRAINSETUP2_MASK GENMASK_32(2, 0)
+#define CSR_PHYMSTRFREQOVERRIDE_LSB 0
+#define CSR_PHYMSTRFREQOVERRIDE_MASK GENMASK_32(2, 0)
+/* CSR_ATESTMODE */
+#define CSR_ATESTMODE_LSB 0
+#define CSR_ATESTMODE_MASK GENMASK_32(4, 0)
+#define CSR_ATESTPRBSEN_LSB 0
+#define CSR_ATESTPRBSEN_MASK BIT(0)
+#define CSR_ATESTCLKEN_LSB 1
+#define CSR_ATESTCLKEN_MASK BIT(1)
+#define CSR_ATESTMODESEL_LSB 2
+#define CSR_ATESTMODESEL_MASK GENMASK_32(4, 2)
+/* CSR_TXCALBINP */
+#define CSR_TXCALBINP_LSB 0
+#define CSR_TXCALBINP_MASK GENMASK_32(4, 0)
+/* CSR_TXCALBINN */
+#define CSR_TXCALBINN_LSB 0
+#define CSR_TXCALBINN_MASK GENMASK_32(4, 0)
+/* CSR_TXCALPOVR */
+#define CSR_TXCALPOVR_LSB 0
+#define CSR_TXCALPOVR_MASK GENMASK_32(5, 0)
+#define CSR_TXCALBINPOVRVAL_LSB 0
+#define CSR_TXCALBINPOVRVAL_MASK GENMASK_32(4, 0)
+#define CSR_TXCALBINPOVREN_LSB 5
+#define CSR_TXCALBINPOVREN_MASK BIT(5)
+/* CSR_TXCALNOVR */
+#define CSR_TXCALNOVR_LSB 0
+#define CSR_TXCALNOVR_MASK GENMASK_32(5, 0)
+#define CSR_TXCALBINNOVRVAL_LSB 0
+#define CSR_TXCALBINNOVRVAL_MASK GENMASK_32(4, 0)
+#define CSR_TXCALBINNOVREN_LSB 5
+#define CSR_TXCALBINNOVREN_MASK BIT(5)
+/* CSR_DFIMODE */
+#define CSR_DFIMODE_LSB 0
+#define CSR_DFIMODE_MASK GENMASK_32(2, 0)
+#define CSR_DFI0ENABLE_LSB 0
+#define CSR_DFI0ENABLE_MASK BIT(0)
+#define CSR_DFI1ENABLE_LSB 1
+#define CSR_DFI1ENABLE_MASK BIT(1)
+#define CSR_DFI1OVERRIDE_LSB 2
+#define CSR_DFI1OVERRIDE_MASK BIT(2)
+/* CSR_TRISTATEMODECA */
+#define CSR_TRISTATEMODECA_LSB 0
+#define CSR_TRISTATEMODECA_MASK GENMASK_32(3, 0)
+#define CSR_DISDYNADRTRI_LSB 0
+#define CSR_DISDYNADRTRI_MASK BIT(0)
+#define CSR_DDR2TMODE_LSB 1
+#define CSR_DDR2TMODE_MASK BIT(1)
+#define CSR_CKDISVAL_LSB 2
+#define CSR_CKDISVAL_MASK GENMASK_32(3, 2)
+/* MTESTMUXSEL already defined in ANIBx section */
+/* CSR_MTESTPGMINFO */
+#define CSR_MTESTPGMINFO_LSB 0
+#define CSR_MTESTPGMINFO_MASK BIT(0)
+/* CSR_DYNPWRDNUP */
+#define CSR_DYNPWRDNUP_LSB 0
+#define CSR_DYNPWRDNUP_MASK BIT(0)
+#define CSR_DYNPOWERDOWN_LSB 0
+#define CSR_DYNPOWERDOWN_MASK BIT(0)
+/* CSR_PMIENABLE */
+#define CSR_PMIENABLE_LSB 0
+#define CSR_PMIENABLE_MASK BIT(0)
+/* CSR_PHYTID */
+#define CSR_PHYTID_LSB 0
+#define CSR_PHYTID_MASK GENMASK_32(15, 0)
+/* CSR_HWTMRL */
+#define CSR_HWTMRL_LSB 0
+#define CSR_HWTMRL_MASK GENMASK_32(4, 0)
+/* CSR_DFIPHYUPD */
+#define CSR_DFIPHYUPD_LSB 0
+#define CSR_DFIPHYUPD_MASK GENMASK_32(15, 0)
+#define CSR_DFIPHYUPDCNT_LSB 0
+#define CSR_DFIPHYUPDCNT_MASK GENMASK_32(3, 0)
+#define CSR_DFIPHYUPDRESP_LSB 4
+#define CSR_DFIPHYUPDRESP_MASK GENMASK_32(6, 4)
+#define CSR_DFIPHYUPDMODE_LSB 7
+#define CSR_DFIPHYUPDMODE_MASK BIT(7)
+#define CSR_DFIPHYUPDTHRESHOLD_LSB 8
+#define CSR_DFIPHYUPDTHRESHOLD_MASK GENMASK_32(11, 8)
+#define CSR_DFIPHYUPDINTTHRESHOLD_LSB 12
+#define CSR_DFIPHYUPDINTTHRESHOLD_MASK GENMASK_32(15, 12)
+/* CSR_PDAMRSWRITEMODE */
+#define CSR_PDAMRSWRITEMODE_LSB 0
+#define CSR_PDAMRSWRITEMODE_MASK BIT(0)
+/* CSR_DFIGEARDOWNCTL */
+#define CSR_DFIGEARDOWNCTL_LSB 0
+#define CSR_DFIGEARDOWNCTL_MASK GENMASK_32(1, 0)
+/* CSR_DQSPREAMBLECONTROL */
+#define CSR_DQSPREAMBLECONTROL_LSB 0
+#define CSR_DQSPREAMBLECONTROL_MASK GENMASK_32(8, 0)
+#define CSR_TWOTCKRXDQSPRE_LSB 0
+#define CSR_TWOTCKRXDQSPRE_MASK BIT(0)
+#define CSR_TWOTCKTXDQSPRE_LSB 1
+#define CSR_TWOTCKTXDQSPRE_MASK BIT(1)
+#define CSR_POSITIONDFEINIT_LSB 2
+#define CSR_POSITIONDFEINIT_MASK GENMASK_32(4, 2)
+#define CSR_LP4TGLTWOTCKTXDQSPRE_LSB 5
+#define CSR_LP4TGLTWOTCKTXDQSPRE_MASK BIT(5)
+#define CSR_LP4POSTAMBLEEXT_LSB 6
+#define CSR_LP4POSTAMBLEEXT_MASK BIT(6)
+#define CSR_LP4STTCPREBRIDGERXEN_LSB 7
+#define CSR_LP4STTCPREBRIDGERXEN_MASK BIT(7)
+#define CSR_WDQSEXTENSION_LSB 8
+#define CSR_WDQSEXTENSION_MASK BIT(8)
+/* CSR_MASTERX4CONFIG */
+#define CSR_MASTERX4CONFIG_LSB 0
+#define CSR_MASTERX4CONFIG_MASK GENMASK_32(3, 0)
+#define CSR_X4TG_LSB 0
+#define CSR_X4TG_MASK GENMASK_32(3, 0)
+/* CSR_WRLEVBITS */
+#define CSR_WRLEVBITS_LSB 0
+#define CSR_WRLEVBITS_MASK GENMASK_32(7, 0)
+#define CSR_WRLEVFORDQSL_LSB 0
+#define CSR_WRLEVFORDQSL_MASK GENMASK_32(3, 0)
+#define CSR_WRLEVFORDQSU_LSB 4
+#define CSR_WRLEVFORDQSU_MASK GENMASK_32(7, 4)
+/* CSR_ENABLECSMULTICAST */
+#define CSR_ENABLECSMULTICAST_LSB 0
+#define CSR_ENABLECSMULTICAST_MASK BIT(0)
+/* CSR_HWTLPCSMULTICAST */
+#define CSR_HWTLPCSMULTICAST_LSB 0
+#define CSR_HWTLPCSMULTICAST_MASK BIT(0)
+/* CSR_ACX4ANIBDIS */
+#define CSR_ACX4ANIBDIS_LSB 0
+#define CSR_ACX4ANIBDIS_MASK GENMASK_32(11, 0)
+/* CSR_DMIPINPRESENT */
+#define CSR_DMIPINPRESENT_LSB 0
+#define CSR_DMIPINPRESENT_MASK BIT(0)
+#define CSR_RDDBIENABLED_LSB 0
+#define CSR_RDDBIENABLED_MASK BIT(0)
+/* CSR_ARDPTRINITVAL */
+#define CSR_ARDPTRINITVAL_LSB 0
+#define CSR_ARDPTRINITVAL_MASK GENMASK_32(3, 0)
+/* CSR_DB0LCDLCALPHDETOUT */
+#define CSR_DB0LCDLCALPHDETOUT_LSB 0
+#define CSR_DB0LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB1LCDLCALPHDETOUT */
+#define CSR_DB1LCDLCALPHDETOUT_LSB 0
+#define CSR_DB1LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB2LCDLCALPHDETOUT */
+#define CSR_DB2LCDLCALPHDETOUT_LSB 0
+#define CSR_DB2LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB3LCDLCALPHDETOUT */
+#define CSR_DB3LCDLCALPHDETOUT_LSB 0
+#define CSR_DB3LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB4LCDLCALPHDETOUT */
+#define CSR_DB4LCDLCALPHDETOUT_LSB 0
+#define CSR_DB4LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB5LCDLCALPHDETOUT */
+#define CSR_DB5LCDLCALPHDETOUT_LSB 0
+#define CSR_DB5LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB6LCDLCALPHDETOUT */
+#define CSR_DB6LCDLCALPHDETOUT_LSB 0
+#define CSR_DB6LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB7LCDLCALPHDETOUT */
+#define CSR_DB7LCDLCALPHDETOUT_LSB 0
+#define CSR_DB7LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB8LCDLCALPHDETOUT */
+#define CSR_DB8LCDLCALPHDETOUT_LSB 0
+#define CSR_DB8LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DB9LCDLCALPHDETOUT */
+#define CSR_DB9LCDLCALPHDETOUT_LSB 0
+#define CSR_DB9LCDLCALPHDETOUT_MASK GENMASK_32(15, 0)
+/* CSR_DBYTEDLLMODECNTRL */
+#define CSR_DBYTEDLLMODECNTRL_LSB 1
+#define CSR_DBYTEDLLMODECNTRL_MASK BIT(1)
+#define CSR_DLLRXPREAMBLEMODE_LSB 1
+#define CSR_DLLRXPREAMBLEMODE_MASK BIT(1)
+/* CSR_DBYTERXENTRAIN */
+#define CSR_DBYTERXENTRAIN_LSB 0
+#define CSR_DBYTERXENTRAIN_MASK BIT(0)
+#define CSR_RXENTRAIN_LSB 0
+#define CSR_RXENTRAIN_MASK BIT(0)
+/* CSR_ANLCDLCALPHDETOUT */
+#define CSR_ANLCDLCALPHDETOUT_LSB 0
+#define CSR_ANLCDLCALPHDETOUT_MASK GENMASK_32(11, 0)
+/* CSR_CALOFFSETS */
+#define CSR_CALOFFSETS_LSB 0
+#define CSR_CALOFFSETS_MASK GENMASK_32(13, 0)
+#define CSR_CALCMPR5OFFSET_LSB 0
+#define CSR_CALCMPR5OFFSET_MASK GENMASK_32(5, 0)
+#define CSR_CALDRVPDTHOFFSET_LSB 6
+#define CSR_CALDRVPDTHOFFSET_MASK GENMASK_32(9, 6)
+#define CSR_CALDRVPUTHOFFSET_LSB 10
+#define CSR_CALDRVPUTHOFFSET_MASK GENMASK_32(13, 10)
+/* CSR_SARINITVALS */
+#define CSR_SARINITVALS_LSB 0
+#define CSR_SARINITVALS_MASK GENMASK_32(8, 0)
+#define CSR_SARINITOFFSET05_LSB 0
+#define CSR_SARINITOFFSET05_MASK GENMASK_32(2, 0)
+#define CSR_SARINITNINT_LSB 3
+#define CSR_SARINITNINT_MASK GENMASK_32(5, 3)
+#define CSR_SARINITPEXT_LSB 6
+#define CSR_SARINITPEXT_MASK GENMASK_32(8, 6)
+/* CSR_CALPEXTOVR */
+#define CSR_CALPEXTOVR_LSB 0
+#define CSR_CALPEXTOVR_MASK GENMASK_32(4, 0)
+/* CSR_CALCMPR5OVR */
+#define CSR_CALCMPR5OVR_LSB 0
+#define CSR_CALCMPR5OVR_MASK GENMASK_32(7, 0)
+/* CSR_CALNINTOVR */
+#define CSR_CALNINTOVR_LSB 0
+#define CSR_CALNINTOVR_MASK GENMASK_32(4, 0)
+/* CSR_CALDRVSTR0 */
+#define CSR_CALDRVSTR0_LSB 0
+#define CSR_CALDRVSTR0_MASK GENMASK_32(7, 0)
+#define CSR_CALDRVSTRPD50_LSB 0
+#define CSR_CALDRVSTRPD50_MASK GENMASK_32(3, 0)
+#define CSR_CALDRVSTRPU50_LSB 4
+#define CSR_CALDRVSTRPU50_MASK GENMASK_32(7, 4)
+/* CSR_PROCODTCTL */
+#define CSR_PROCODTCTL_LSB 0
+#define CSR_PROCODTCTL_MASK GENMASK_32(1, 0)
+#define CSR_PROCODTALWAYSOFF_LSB 0
+#define CSR_PROCODTALWAYSOFF_MASK BIT(0)
+#define CSR_PROCODTALWAYSON_LSB 1
+#define CSR_PROCODTALWAYSON_MASK BIT(1)
+/* CSR_PROCODTTIMECTL */
+#define CSR_PROCODTTIMECTL_LSB 0
+#define CSR_PROCODTTIMECTL_MASK GENMASK_32(5, 0)
+#define CSR_PODTTAILWIDTH_LSB 0
+#define CSR_PODTTAILWIDTH_MASK GENMASK_32(1, 0)
+#define CSR_PODTSTARTDELAY_LSB 2
+#define CSR_PODTSTARTDELAY_MASK GENMASK_32(3, 2)
+#define CSR_PODTTAILWIDTHEXT_LSB 4
+#define CSR_PODTTAILWIDTHEXT_MASK GENMASK_32(5, 4)
+/* CSR_MEMALERTCONTROL */
+#define CSR_MEMALERTCONTROL_LSB 0
+#define CSR_MEMALERTCONTROL_MASK GENMASK_32(15, 0)
+#define CSR_MALERTVREFLEVEL_LSB 0
+#define CSR_MALERTVREFLEVEL_MASK GENMASK_32(6, 0)
+#define CSR_MALERTVREFEXTEN_LSB 7
+#define CSR_MALERTVREFEXTEN_MASK BIT(7)
+#define CSR_MALERTPUSTREN_LSB 8
+#define CSR_MALERTPUSTREN_MASK GENMASK_32(11, 8)
+#define CSR_MALERTPUEN_LSB 12
+#define CSR_MALERTPUEN_MASK BIT(12)
+#define CSR_MALERTRXEN_LSB 13
+#define CSR_MALERTRXEN_MASK BIT(13)
+#define CSR_MALERTDISABLEVAL_LSB 14
+#define CSR_MALERTDISABLEVAL_MASK BIT(14)
+#define CSR_MALERTFORCEERROR_LSB 15
+#define CSR_MALERTFORCEERROR_MASK BIT(15)
+/* CSR_MEMALERTCONTROL2 */
+#define CSR_MEMALERTCONTROL2_LSB 0
+#define CSR_MEMALERTCONTROL2_MASK BIT(0)
+#define CSR_MALERTSYNCBYPASS_LSB 0
+#define CSR_MALERTSYNCBYPASS_MASK BIT(0)
+/* CSR_MEMRESETL */
+#define CSR_MEMRESETL_LSB 0
+#define CSR_MEMRESETL_MASK GENMASK_32(1, 0)
+#define CSR_MEMRESETLVALUE_LSB 0
+#define CSR_MEMRESETLVALUE_MASK BIT(0)
+#define CSR_PROTECTMEMRESET_LSB 1
+#define CSR_PROTECTMEMRESET_MASK BIT(1)
+/* CSR_PUBMODE */
+#define CSR_PUBMODE_LSB 0
+#define CSR_PUBMODE_MASK BIT(0)
+#define CSR_HWTMEMSRC_LSB 0
+#define CSR_HWTMEMSRC_MASK BIT(0)
+/* CSR_MISCPHYSTATUS */
+#define CSR_MISCPHYSTATUS_LSB 0
+#define CSR_MISCPHYSTATUS_MASK GENMASK_32(1, 0)
+#define CSR_DCTSANE_LSB 0
+#define CSR_DCTSANE_MASK BIT(0)
+#define CSR_PORMEMRESET_LSB 1
+#define CSR_PORMEMRESET_MASK BIT(1)
+/* CSR_CORELOOPBACKSEL */
+#define CSR_CORELOOPBACKSEL_LSB 0
+#define CSR_CORELOOPBACKSEL_MASK BIT(0)
+/* CSR_DLLTRAINPARAM */
+#define CSR_DLLTRAINPARAM_LSB 0
+#define CSR_DLLTRAINPARAM_MASK GENMASK_32(1, 0)
+#define CSR_EXTENDPHDTIME_LSB 0
+#define CSR_EXTENDPHDTIME_MASK GENMASK_32(1, 0)
+/* CSR_HWTLPCSENA */
+#define CSR_HWTLPCSENA_LSB 0
+#define CSR_HWTLPCSENA_MASK GENMASK_32(1, 0)
+/* CSR_HWTLPCSENB */
+#define CSR_HWTLPCSENB_LSB 0
+#define CSR_HWTLPCSENB_MASK GENMASK_32(1, 0)
+/* CSR_HWTLPCSENBYPASS */
+#define CSR_HWTLPCSENBYPASS_LSB 0
+#define CSR_HWTLPCSENBYPASS_MASK BIT(0)
+/* CSR_DFICAMODE */
+#define CSR_DFICAMODE_LSB 0
+#define CSR_DFICAMODE_MASK GENMASK_32(3, 0)
+#define CSR_DFILP3CAMODE_LSB 0
+#define CSR_DFILP3CAMODE_MASK BIT(0)
+#define CSR_DFID4CAMODE_LSB 1
+#define CSR_DFID4CAMODE_MASK BIT(1)
+#define CSR_DFILP4CAMODE_LSB 2
+#define CSR_DFILP4CAMODE_MASK BIT(2)
+#define CSR_DFID4ALTCAMODE_LSB 3
+#define CSR_DFID4ALTCAMODE_MASK BIT(3)
+/* CSR_HWTCACTL */
+#define CSR_HWTCACTL_LSB 0
+#define CSR_HWTCACTL_MASK BIT(0)
+#define CSR_HWTDISDYNADRTRI_LSB 0
+#define CSR_HWTDISDYNADRTRI_MASK BIT(0)
+/* CSR_HWTCAMODE */
+#define CSR_HWTCAMODE_LSB 0
+#define CSR_HWTCAMODE_MASK GENMASK_32(5, 0)
+#define CSR_HWTLP3CAMODE_LSB 0
+#define CSR_HWTLP3CAMODE_MASK BIT(0)
+#define CSR_HWTD4CAMODE_LSB 1
+#define CSR_HWTD4CAMODE_MASK BIT(1)
+#define CSR_HWTLP4CAMODE_LSB 2
+#define CSR_HWTLP4CAMODE_MASK BIT(2)
+#define CSR_HWTD4ALTCAMODE_LSB 3
+#define CSR_HWTD4ALTCAMODE_MASK BIT(3)
+#define CSR_HWTCSINVERT_LSB 4
+#define CSR_HWTCSINVERT_MASK BIT(4)
+#define CSR_HWTDBIINVERT_LSB 5
+#define CSR_HWTDBIINVERT_MASK BIT(5)
+/* CSR_DLLCONTROL */
+#define CSR_DLLCONTROL_LSB 0
+#define CSR_DLLCONTROL_MASK GENMASK_32(2, 0)
+#define CSR_DLLRESETRELOCK_LSB 0
+#define CSR_DLLRESETRELOCK_MASK BIT(0)
+#define CSR_DLLRESETSLAVE_LSB 1
+#define CSR_DLLRESETSLAVE_MASK BIT(1)
+#define CSR_DLLRESETRSVD_LSB 2
+#define CSR_DLLRESETRSVD_MASK BIT(2)
+/* CSR_PULSEDLLUPDATEPHASE */
+#define CSR_PULSEDLLUPDATEPHASE_LSB 0
+#define CSR_PULSEDLLUPDATEPHASE_MASK GENMASK_32(7, 0)
+#define CSR_PULSEDBYTEDLLUPDATEPHASE_LSB 0
+#define CSR_PULSEDBYTEDLLUPDATEPHASE_MASK BIT(0)
+#define CSR_PULSEACKDLLUPDATEPHASE_LSB 1
+#define CSR_PULSEACKDLLUPDATEPHASE_MASK BIT(1)
+#define CSR_PULSEACADLLUPDATEPHASE_LSB 2
+#define CSR_PULSEACADLLUPDATEPHASE_MASK BIT(2)
+#define CSR_UPDATEPHASEDESTRESERVED_LSB 3
+#define CSR_UPDATEPHASEDESTRESERVED_MASK GENMASK_32(5, 3)
+#define CSR_TRAINUPDATEPHASEONLONGBUBBLE_LSB 6
+#define CSR_TRAINUPDATEPHASEONLONGBUBBLE_MASK BIT(6)
+#define CSR_ALWAYSUPDATELCDLPHASE_LSB 7
+#define CSR_ALWAYSUPDATELCDLPHASE_MASK BIT(7)
+/* CSR_HWTCONTROLOVR0 */
+#define CSR_HWTCONTROLOVR0_LSB 0
+#define CSR_HWTCONTROLOVR0_MASK GENMASK_32(12, 0)
+#define CSR_HWTCS0OVR0_LSB 0
+#define CSR_HWTCS0OVR0_MASK BIT(0)
+#define CSR_HWTCS1OVR0_LSB 1
+#define CSR_HWTCS1OVR0_MASK BIT(1)
+#define CSR_HWTCS2OVR0_LSB 2
+#define CSR_HWTCS2OVR0_MASK BIT(2)
+#define CSR_HWTCS3OVR0_LSB 3
+#define CSR_HWTCS3OVR0_MASK BIT(3)
+#define CSR_HWTCKE0OVR0_LSB 4
+#define CSR_HWTCKE0OVR0_MASK BIT(4)
+#define CSR_HWTCKE1OVR0_LSB 5
+#define CSR_HWTCKE1OVR0_MASK BIT(5)
+#define CSR_HWTCKE2OVR0_LSB 6
+#define CSR_HWTCKE2OVR0_MASK BIT(6)
+#define CSR_HWTCKE3OVR0_LSB 7
+#define CSR_HWTCKE3OVR0_MASK BIT(7)
+#define CSR_HWTODT0OVR0_LSB 8
+#define CSR_HWTODT0OVR0_MASK BIT(8)
+#define CSR_HWTODT1OVR0_LSB 9
+#define CSR_HWTODT1OVR0_MASK BIT(9)
+#define CSR_HWTODT2OVR0_LSB 10
+#define CSR_HWTODT2OVR0_MASK BIT(10)
+#define CSR_HWTODT3OVR0_LSB 11
+#define CSR_HWTODT3OVR0_MASK BIT(11)
+#define CSR_HWTPARITYOVR0_LSB 12
+#define CSR_HWTPARITYOVR0_MASK BIT(12)
+/* CSR_HWTCONTROLOVR1 */
+#define CSR_HWTCONTROLOVR1_LSB 0
+#define CSR_HWTCONTROLOVR1_MASK GENMASK_32(12, 0)
+#define CSR_HWTCS0OVR1_LSB 0
+#define CSR_HWTCS0OVR1_MASK BIT(0)
+#define CSR_HWTCS1OVR1_LSB 1
+#define CSR_HWTCS1OVR1_MASK BIT(1)
+#define CSR_HWTCS2OVR1_LSB 2
+#define CSR_HWTCS2OVR1_MASK BIT(2)
+#define CSR_HWTCS3OVR1_LSB 3
+#define CSR_HWTCS3OVR1_MASK BIT(3)
+#define CSR_HWTCKE0OVR1_LSB 4
+#define CSR_HWTCKE0OVR1_MASK BIT(4)
+#define CSR_HWTCKE1OVR1_LSB 5
+#define CSR_HWTCKE1OVR1_MASK BIT(5)
+#define CSR_HWTCKE2OVR1_LSB 6
+#define CSR_HWTCKE2OVR1_MASK BIT(6)
+#define CSR_HWTCKE3OVR1_LSB 7
+#define CSR_HWTCKE3OVR1_MASK BIT(7)
+#define CSR_HWTODT0OVR1_LSB 8
+#define CSR_HWTODT0OVR1_MASK BIT(8)
+#define CSR_HWTODT1OVR1_LSB 9
+#define CSR_HWTODT1OVR1_MASK BIT(9)
+#define CSR_HWTODT2OVR1_LSB 10
+#define CSR_HWTODT2OVR1_MASK BIT(10)
+#define CSR_HWTODT3OVR1_LSB 11
+#define CSR_HWTODT3OVR1_MASK BIT(11)
+#define CSR_HWTPARITYOVR1_LSB 12
+#define CSR_HWTPARITYOVR1_MASK BIT(12)
+/* CSR_DLLGAINCTL */
+#define CSR_DLLGAINCTL_LSB 0
+#define CSR_DLLGAINCTL_MASK GENMASK_32(11, 0)
+#define CSR_DLLGAINIV_LSB 0
+#define CSR_DLLGAINIV_MASK GENMASK_32(3, 0)
+#define CSR_DLLGAINTV_LSB 4
+#define CSR_DLLGAINTV_MASK GENMASK_32(7, 4)
+#define CSR_DLLSEEDSEL_LSB 8
+#define CSR_DLLSEEDSEL_MASK GENMASK_32(11, 8)
+/* CSR_DLLLOCKPARAM */
+#define CSR_DLLLOCKPARAM_LSB 0
+#define CSR_DLLLOCKPARAM_MASK GENMASK_32(12, 0)
+#define CSR_DISDLLSEEDSEL_LSB 0
+#define CSR_DISDLLSEEDSEL_MASK BIT(0)
+#define CSR_DISDLLGAINIVSEED_LSB 1
+#define CSR_DISDLLGAINIVSEED_MASK BIT(1)
+#define CSR_DLLLOCKPARAMSPARE_LSB 2
+#define CSR_DLLLOCKPARAMSPARE_MASK GENMASK_32(3, 2)
+#define CSR_LCDLSEED0_LSB 4
+#define CSR_LCDLSEED0_MASK GENMASK_32(12, 4)
+/* CSR_HWTCONTROLVAL0 */
+#define CSR_HWTCONTROLVAL0_LSB 0
+#define CSR_HWTCONTROLVAL0_MASK GENMASK_32(12, 0)
+#define CSR_HWTCS0VAL0_LSB 0
+#define CSR_HWTCS0VAL0_MASK BIT(0)
+#define CSR_HWTCS1VAL0_LSB 1
+#define CSR_HWTCS1VAL0_MASK BIT(1)
+#define CSR_HWTCS2VAL0_LSB 2
+#define CSR_HWTCS2VAL0_MASK BIT(2)
+#define CSR_HWTCS3VAL0_LSB 3
+#define CSR_HWTCS3VAL0_MASK BIT(3)
+#define CSR_HWTCKE0VAL0_LSB 4
+#define CSR_HWTCKE0VAL0_MASK BIT(4)
+#define CSR_HWTCKE1VAL0_LSB 5
+#define CSR_HWTCKE1VAL0_MASK BIT(5)
+#define CSR_HWTCKE2VAL0_LSB 6
+#define CSR_HWTCKE2VAL0_MASK BIT(6)
+#define CSR_HWTCKE3VAL0_LSB 7
+#define CSR_HWTCKE3VAL0_MASK BIT(7)
+#define CSR_HWTODT0VAL0_LSB 8
+#define CSR_HWTODT0VAL0_MASK BIT(8)
+#define CSR_HWTODT1VAL0_LSB 9
+#define CSR_HWTODT1VAL0_MASK BIT(9)
+#define CSR_HWTODT2VAL0_LSB 10
+#define CSR_HWTODT2VAL0_MASK BIT(10)
+#define CSR_HWTODT3VAL0_LSB 11
+#define CSR_HWTODT3VAL0_MASK BIT(11)
+#define CSR_HWTPARITYVAL0_LSB 12
+#define CSR_HWTPARITYVAL0_MASK BIT(12)
+/* CSR_HWTCONTROLVAL1 */
+#define CSR_HWTCONTROLVAL1_LSB 0
+#define CSR_HWTCONTROLVAL1_MASK GENMASK_32(12, 0)
+#define CSR_HWTCS0VAL1_LSB 0
+#define CSR_HWTCS0VAL1_MASK BIT(0)
+#define CSR_HWTCS1VAL1_LSB 1
+#define CSR_HWTCS1VAL1_MASK BIT(1)
+#define CSR_HWTCS2VAL1_LSB 2
+#define CSR_HWTCS2VAL1_MASK BIT(2)
+#define CSR_HWTCS3VAL1_LSB 3
+#define CSR_HWTCS3VAL1_MASK BIT(3)
+#define CSR_HWTCKE0VAL1_LSB 4
+#define CSR_HWTCKE0VAL1_MASK BIT(4)
+#define CSR_HWTCKE1VAL1_LSB 5
+#define CSR_HWTCKE1VAL1_MASK BIT(5)
+#define CSR_HWTCKE2VAL1_LSB 6
+#define CSR_HWTCKE2VAL1_MASK BIT(6)
+#define CSR_HWTCKE3VAL1_LSB 7
+#define CSR_HWTCKE3VAL1_MASK BIT(7)
+#define CSR_HWTODT0VAL1_LSB 8
+#define CSR_HWTODT0VAL1_MASK BIT(8)
+#define CSR_HWTODT1VAL1_LSB 9
+#define CSR_HWTODT1VAL1_MASK BIT(9)
+#define CSR_HWTODT2VAL1_LSB 10
+#define CSR_HWTODT2VAL1_MASK BIT(10)
+#define CSR_HWTODT3VAL1_LSB 11
+#define CSR_HWTODT3VAL1_MASK BIT(11)
+#define CSR_HWTPARITYVAL1_LSB 12
+#define CSR_HWTPARITYVAL1_MASK BIT(12)
+/* CSR_ACSMGLBLSTART */
+#define CSR_ACSMGLBLSTART_LSB 0
+#define CSR_ACSMGLBLSTART_MASK BIT(0)
+/* CSR_ACSMGLBLSGLSTPCTRL */
+#define CSR_ACSMGLBLSGLSTPCTRL_LSB 0
+#define CSR_ACSMGLBLSGLSTPCTRL_MASK GENMASK_32(1, 0)
+#define CSR_ACSMSGLSTPMODE_LSB 0
+#define CSR_ACSMSGLSTPMODE_MASK BIT(0)
+#define CSR_ACSMSGLSTP_LSB 1
+#define CSR_ACSMSGLSTP_MASK BIT(1)
+/* CSR_LCDLCALPHASE */
+#define CSR_LCDLCALPHASE_LSB 0
+#define CSR_LCDLCALPHASE_MASK GENMASK_32(8, 0)
+/* CSR_LCDLCALCTRL */
+#define CSR_LCDLCALCTRL_LSB 0
+#define CSR_LCDLCALCTRL_MASK GENMASK_32(6, 0)
+#define CSR_LCDLCALMODE_LSB 0
+#define CSR_LCDLCALMODE_MASK BIT(0)
+#define CSR_LCDLCALSLOWCLKSEL_LSB 1
+#define CSR_LCDLCALSLOWCLKSEL_MASK BIT(1)
+#define CSR_LCDLCALEN_LSB 2
+#define CSR_LCDLCALEN_MASK BIT(2)
+#define CSR_LCDLCALPHASEUPDATE_LSB 3
+#define CSR_LCDLCALPHASEUPDATE_MASK BIT(3)
+#define CSR_LCDLCALCLKEN_LSB 4
+#define CSR_LCDLCALCLKEN_MASK BIT(4)
+#define CSR_LCDLCALSAMPEN_LSB 5
+#define CSR_LCDLCALSAMPEN_MASK BIT(5)
+#define CSR_LCDLCALSLOWCLKEN_LSB 6
+#define CSR_LCDLCALSLOWCLKEN_MASK BIT(6)
+/* CSR_CALRATE */
+#define CSR_CALRATE_LSB 0
+#define CSR_CALRATE_MASK GENMASK_32(6, 0)
+#define CSR_CALINTERVAL_LSB 0
+#define CSR_CALINTERVAL_MASK GENMASK_32(3, 0)
+#define CSR_CALRUN_LSB 4
+#define CSR_CALRUN_MASK BIT(4)
+#define CSR_CALONCE_LSB 5
+#define CSR_CALONCE_MASK BIT(5)
+#define CSR_DISABLEBACKGROUNDZQUPDATES_LSB 6
+#define CSR_DISABLEBACKGROUNDZQUPDATES_MASK BIT(6)
+/* CSR_CALZAP */
+#define CSR_CALZAP_LSB 0
+#define CSR_CALZAP_MASK BIT(0)
+/* CSR_PSTATE */
+#define CSR_PSTATE_LSB 0
+#define CSR_PSTATE_MASK GENMASK_32(3, 0)
+/* CSR_CALPREDRIVEROVERRIDE */
+#define CSR_CALPREDRIVEROVERRIDE_LSB 0
+#define CSR_CALPREDRIVEROVERRIDE_MASK GENMASK_32(7, 0)
+#define CSR_TXPREOVN_LSB 0
+#define CSR_TXPREOVN_MASK GENMASK_32(3, 0)
+#define CSR_TXPREOVP_LSB 4
+#define CSR_TXPREOVP_MASK GENMASK_32(7, 4)
+/* CSR_PLLOUTGATECONTROL */
+#define CSR_PLLOUTGATECONTROL_LSB 0
+#define CSR_PLLOUTGATECONTROL_MASK GENMASK_32(1, 0)
+#define CSR_PCLKGATEEN_LSB 0
+#define CSR_PCLKGATEEN_MASK BIT(0)
+#define CSR_RESERVED2X1_LSB 1
+#define CSR_RESERVED2X1_MASK BIT(1)
+/* CSR_UCMEMRESETCONTROL */
+#define CSR_UCMEMRESETCONTROL_LSB 0
+#define CSR_UCMEMRESETCONTROL_MASK BIT(0)
+#define CSR_UCDCTSANE_LSB 0
+#define CSR_UCDCTSANE_MASK BIT(0)
+/* CSR_PORCONTROL */
+#define CSR_PORCONTROL_LSB 0
+#define CSR_PORCONTROL_MASK BIT(0)
+#define CSR_PLLDLLLOCKDONE_LSB 0
+#define CSR_PLLDLLLOCKDONE_MASK BIT(0)
+/* CSR_CALBUSY */
+#define CSR_CALBUSY_LSB 0
+#define CSR_CALBUSY_MASK BIT(0)
+/* CSR_CALMISC2 */
+#define CSR_CALMISC2_LSB 0
+#define CSR_CALMISC2_MASK GENMASK_32(15, 0)
+#define CSR_CALNUMVOTES_LSB 0
+#define CSR_CALNUMVOTES_MASK GENMASK_32(2, 0)
+#define CSR_RESERVED10X3_LSB 3
+#define CSR_RESERVED10X3_MASK GENMASK_32(10, 3)
+#define CSR_RESERVED11_LSB 11
+#define CSR_RESERVED11_MASK BIT(11)
+#define CSR_CALCMPTRRESTRIM_LSB 12
+#define CSR_CALCMPTRRESTRIM_MASK BIT(12)
+#define CSR_CALCANCELROUNDERRDIS_LSB 13
+#define CSR_CALCANCELROUNDERRDIS_MASK BIT(13)
+#define CSR_CALSLOWCMPANA_LSB 14
+#define CSR_CALSLOWCMPANA_MASK BIT(14)
+#define CSR_RESERVED15_LSB 15
+#define CSR_RESERVED15_MASK BIT(15)
+/* CSR_CALMISC */
+#define CSR_CALMISC_LSB 0
+#define CSR_CALMISC_MASK GENMASK_32(2, 0)
+#define CSR_CALCMPR5DIS_LSB 0
+#define CSR_CALCMPR5DIS_MASK BIT(0)
+#define CSR_CALNINTDIS_LSB 1
+#define CSR_CALNINTDIS_MASK BIT(1)
+#define CSR_CALPEXTDIS_LSB 2
+#define CSR_CALPEXTDIS_MASK BIT(2)
+/* CSR_CALVREFS */
+#define CSR_CALVREFS_LSB 0
+#define CSR_CALVREFS_MASK GENMASK_32(1, 0)
+/* CSR_CALCMPR5 */
+#define CSR_CALCMPR5_LSB 0
+#define CSR_CALCMPR5_MASK GENMASK_32(7, 0)
+/* CSR_CALNINT */
+#define CSR_CALNINT_LSB 0
+#define CSR_CALNINT_MASK GENMASK_32(4, 0)
+#define CSR_CALNINTTHB_LSB 0
+#define CSR_CALNINTTHB_MASK GENMASK_32(4, 0)
+/* CSR_CALPEXT */
+#define CSR_CALPEXT_LSB 0
+#define CSR_CALPEXT_MASK GENMASK_32(4, 0)
+#define CSR_CALPEXTTHB_LSB 0
+#define CSR_CALPEXTTHB_MASK GENMASK_32(4, 0)
+/* CSR_CALCMPINVERT */
+#define CSR_CALCMPINVERT_LSB 0
+#define CSR_CALCMPINVERT_MASK GENMASK_32(4, 0)
+#define CSR_CMPINVERTCALDAC50_LSB 0
+#define CSR_CMPINVERTCALDAC50_MASK BIT(0)
+#define CSR_CMPINVERTCALDRVPD50_LSB 1
+#define CSR_CMPINVERTCALDRVPD50_MASK BIT(1)
+#define CSR_CMPINVERTCALDRVPU50_LSB 2
+#define CSR_CMPINVERTCALDRVPU50_MASK BIT(2)
+#define CSR_CMPINVERTCALODTPD_LSB 3
+#define CSR_CMPINVERTCALODTPD_MASK BIT(3)
+#define CSR_CMPINVERTCALODTPU_LSB 4
+#define CSR_CMPINVERTCALODTPU_MASK BIT(4)
+/* CSR_CALCMPANACNTRL */
+#define CSR_CALCMPANACNTRL_LSB 0
+#define CSR_CALCMPANACNTRL_MASK GENMASK_32(9, 0)
+#define CSR_CMPRGAINCURRADJ_LSB 0
+#define CSR_CMPRGAINCURRADJ_MASK GENMASK_32(7, 0)
+#define CSR_CMPRGAINRESADJ_LSB 8
+#define CSR_CMPRGAINRESADJ_MASK BIT(8)
+#define CSR_CMPRBIASBYPASSEN_LSB 9
+#define CSR_CMPRBIASBYPASSEN_MASK BIT(9)
+/* CSR_DFIRDDATACSDESTMAP */
+#define CSR_DFIRDDATACSDESTMAP_LSB 0
+#define CSR_DFIRDDATACSDESTMAP_MASK GENMASK_32(7, 0)
+#define CSR_DFIRDDESTM0_LSB 0
+#define CSR_DFIRDDESTM0_MASK GENMASK_32(1, 0)
+#define CSR_DFIRDDESTM1_LSB 2
+#define CSR_DFIRDDESTM1_MASK GENMASK_32(3, 2)
+#define CSR_DFIRDDESTM2_LSB 4
+#define CSR_DFIRDDESTM2_MASK GENMASK_32(5, 4)
+#define CSR_DFIRDDESTM3_LSB 6
+#define CSR_DFIRDDESTM3_MASK GENMASK_32(7, 6)
+/* CSR_VREFINGLOBAL */
+#define CSR_VREFINGLOBAL_LSB 0
+#define CSR_VREFINGLOBAL_MASK GENMASK_32(14, 0)
+#define CSR_GLOBALVREFINSEL_LSB 0
+#define CSR_GLOBALVREFINSEL_MASK GENMASK_32(2, 0)
+#define CSR_GLOBALVREFINDAC_LSB 3
+#define CSR_GLOBALVREFINDAC_MASK GENMASK_32(9, 3)
+#define CSR_GLOBALVREFINTRIM_LSB 10
+#define CSR_GLOBALVREFINTRIM_MASK GENMASK_32(13, 10)
+#define CSR_GLOBALVREFINMODE_LSB 14
+#define CSR_GLOBALVREFINMODE_MASK BIT(14)
+/* CSR_DFIWRDATACSDESTMAP */
+#define CSR_DFIWRDATACSDESTMAP_LSB 0
+#define CSR_DFIWRDATACSDESTMAP_MASK GENMASK_32(7, 0)
+#define CSR_DFIWRDESTM0_LSB 0
+#define CSR_DFIWRDESTM0_MASK GENMASK_32(1, 0)
+#define CSR_DFIWRDESTM1_LSB 2
+#define CSR_DFIWRDESTM1_MASK GENMASK_32(3, 2)
+#define CSR_DFIWRDESTM2_LSB 4
+#define CSR_DFIWRDESTM2_MASK GENMASK_32(5, 4)
+#define CSR_DFIWRDESTM3_LSB 6
+#define CSR_DFIWRDESTM3_MASK GENMASK_32(7, 6)
+/* CSR_MASUPDGOODCTR */
+#define CSR_MASUPDGOODCTR_LSB 0
+#define CSR_MASUPDGOODCTR_MASK GENMASK_32(15, 0)
+/* CSR_PHYUPD0GOODCTR */
+#define CSR_PHYUPD0GOODCTR_LSB 0
+#define CSR_PHYUPD0GOODCTR_MASK GENMASK_32(15, 0)
+/* CSR_PHYUPD1GOODCTR */
+#define CSR_PHYUPD1GOODCTR_LSB 0
+#define CSR_PHYUPD1GOODCTR_MASK GENMASK_32(15, 0)
+/* CSR_CTLUPD0GOODCTR */
+#define CSR_CTLUPD0GOODCTR_LSB 0
+#define CSR_CTLUPD0GOODCTR_MASK GENMASK_32(15, 0)
+/* CSR_CTLUPD1GOODCTR */
+#define CSR_CTLUPD1GOODCTR_LSB 0
+#define CSR_CTLUPD1GOODCTR_MASK GENMASK_32(15, 0)
+/* CSR_MASUPDFAILCTR */
+#define CSR_MASUPDFAILCTR_LSB 0
+#define CSR_MASUPDFAILCTR_MASK GENMASK_32(15, 0)
+/* CSR_PHYUPD0FAILCTR */
+#define CSR_PHYUPD0FAILCTR_LSB 0
+#define CSR_PHYUPD0FAILCTR_MASK GENMASK_32(15, 0)
+/* CSR_PHYUPD1FAILCTR */
+#define CSR_PHYUPD1FAILCTR_LSB 0
+#define CSR_PHYUPD1FAILCTR_MASK GENMASK_32(15, 0)
+/* CSR_PHYPERFCTRENABLE */
+#define CSR_PHYPERFCTRENABLE_LSB 0
+#define CSR_PHYPERFCTRENABLE_MASK GENMASK_32(7, 0)
+#define CSR_MASUPDGOODCTL_LSB 0
+#define CSR_MASUPDGOODCTL_MASK BIT(0)
+#define CSR_PHYUPD0GOODCTL_LSB 1
+#define CSR_PHYUPD0GOODCTL_MASK BIT(1)
+#define CSR_PHYUPD1GOODCTL_LSB 2
+#define CSR_PHYUPD1GOODCTL_MASK BIT(2)
+#define CSR_CTLUPD0GOODCTL_LSB 3
+#define CSR_CTLUPD0GOODCTL_MASK BIT(3)
+#define CSR_CTLUPD1GOODCTL_LSB 4
+#define CSR_CTLUPD1GOODCTL_MASK BIT(4)
+#define CSR_MASUPDFAILCTL_LSB 5
+#define CSR_MASUPDFAILCTL_MASK BIT(5)
+#define CSR_PHYUPD0FAILCTL_LSB 6
+#define CSR_PHYUPD0FAILCTL_MASK BIT(6)
+#define CSR_PHYUPD1FAILCTL_LSB 7
+#define CSR_PHYUPD1FAILCTL_MASK BIT(7)
+/* CSR_DFIWRRDDATACSCONFIG */
+#define CSR_DFIWRRDDATACSCONFIG_LSB 0
+#define CSR_DFIWRRDDATACSCONFIG_MASK GENMASK_32(1, 0)
+#define CSR_DFIWRDATACSPOLARITY_LSB 0
+#define CSR_DFIWRDATACSPOLARITY_MASK BIT(0)
+#define CSR_DFIRDDATACSPOLARITY_LSB 1
+#define CSR_DFIRDDATACSPOLARITY_MASK BIT(1)
+/* CSR_PLLPWRDN */
+#define CSR_PLLPWRDN_LSB 0
+#define CSR_PLLPWRDN_MASK BIT(0)
+/* CSR_PLLRESET */
+#define CSR_PLLRESET_LSB 0
+#define CSR_PLLRESET_MASK BIT(0)
+/* CSR_PLLCTRL2 */
+#define CSR_PLLCTRL2_LSB 0
+#define CSR_PLLCTRL2_MASK GENMASK_32(4, 0)
+#define CSR_PLLFREQSEL_LSB 0
+#define CSR_PLLFREQSEL_MASK GENMASK_32(4, 0)
+/* CSR_PLLCTRL0 */
+#define CSR_PLLCTRL0_LSB 0
+#define CSR_PLLCTRL0_MASK GENMASK_32(15, 0)
+#define CSR_PLLSTANDBY_LSB 0
+#define CSR_PLLSTANDBY_MASK BIT(0)
+#define CSR_PLLBYPSEL_LSB 1
+#define CSR_PLLBYPSEL_MASK BIT(1)
+#define CSR_PLLX2MODE_LSB 2
+#define CSR_PLLX2MODE_MASK BIT(2)
+#define CSR_PLLOUTBYPEN_LSB 3
+#define CSR_PLLOUTBYPEN_MASK BIT(3)
+#define CSR_PLLPRESET_LSB 4
+#define CSR_PLLPRESET_MASK BIT(4)
+#define CSR_PLLBYPASSMODE_LSB 5
+#define CSR_PLLBYPASSMODE_MASK BIT(5)
+#define CSR_PLLSELDFIFREQRATIO_LSB 6
+#define CSR_PLLSELDFIFREQRATIO_MASK BIT(6)
+#define CSR_PLLSYNCBUSFLUSH_LSB 7
+#define CSR_PLLSYNCBUSFLUSH_MASK BIT(7)
+#define CSR_PLLSYNCBUSBYP_LSB 8
+#define CSR_PLLSYNCBUSBYP_MASK BIT(8)
+#define CSR_PLLRESERVED10X9_LSB 9
+#define CSR_PLLRESERVED10X9_MASK GENMASK_32(10, 9)
+#define CSR_PLLGEARSHIFT_LSB 11
+#define CSR_PLLGEARSHIFT_MASK BIT(11)
+#define CSR_PLLLOCKCNTSEL_LSB 12
+#define CSR_PLLLOCKCNTSEL_MASK BIT(12)
+#define CSR_PLLLOCKPHSEL_LSB 13
+#define CSR_PLLLOCKPHSEL_MASK GENMASK_32(14, 13)
+#define CSR_PLLSPARECTRL0_LSB 15
+#define CSR_PLLSPARECTRL0_MASK BIT(15)
+/* CSR_PLLCTRL1 */
+#define CSR_PLLCTRL1_LSB 0
+#define CSR_PLLCTRL1_MASK GENMASK_32(8, 0)
+#define CSR_PLLCPINTCTRL_LSB 0
+#define CSR_PLLCPINTCTRL_MASK GENMASK_32(4, 0)
+#define CSR_PLLCPPROPCTRL_LSB 5
+#define CSR_PLLCPPROPCTRL_MASK GENMASK_32(8, 5)
+/* CSR_PLLTST */
+#define CSR_PLLTST_LSB 0
+#define CSR_PLLTST_MASK GENMASK_32(8, 0)
+#define CSR_PLLANATSTEN_LSB 0
+#define CSR_PLLANATSTEN_MASK BIT(0)
+#define CSR_PLLANATSTSEL_LSB 1
+#define CSR_PLLANATSTSEL_MASK GENMASK_32(4, 1)
+#define CSR_PLLDIGTSTSEL_LSB 5
+#define CSR_PLLDIGTSTSEL_MASK GENMASK_32(8, 5)
+/* CSR_PLLLOCKSTATUS */
+#define CSR_PLLLOCKSTATUS_LSB 0
+#define CSR_PLLLOCKSTATUS_MASK BIT(0)
+/* CSR_PLLTESTMODE */
+#define CSR_PLLTESTMODE_LSB 0
+#define CSR_PLLTESTMODE_MASK GENMASK_32(15, 0)
+/* CSR_PLLCTRL3 */
+#define CSR_PLLCTRL3_LSB 0
+#define CSR_PLLCTRL3_MASK GENMASK_32(15, 0)
+#define CSR_PLLSPARE_LSB 0
+#define CSR_PLLSPARE_MASK GENMASK_32(3, 0)
+#define CSR_PLLMAXRANGE_LSB 4
+#define CSR_PLLMAXRANGE_MASK GENMASK_32(8, 4)
+#define CSR_PLLDACVALIN_LSB 9
+#define CSR_PLLDACVALIN_MASK GENMASK_32(13, 9)
+#define CSR_PLLFORCECAL_LSB 14
+#define CSR_PLLFORCECAL_MASK BIT(14)
+#define CSR_PLLENCAL_LSB 15
+#define CSR_PLLENCAL_MASK BIT(15)
+/* CSR_PLLCTRL4 */
+#define CSR_PLLCTRL4_LSB 0
+#define CSR_PLLCTRL4_MASK GENMASK_32(8, 0)
+#define CSR_PLLCPINTGSCTRL_LSB 0
+#define CSR_PLLCPINTGSCTRL_MASK GENMASK_32(4, 0)
+#define CSR_PLLCPPROPGSCTRL_LSB 5
+#define CSR_PLLCPPROPGSCTRL_MASK GENMASK_32(8, 5)
+/* CSR_PLLENDOFCAL */
+#define CSR_PLLENDOFCAL_LSB 0
+#define CSR_PLLENDOFCAL_MASK BIT(0)
+/* CSR_PLLSTANDBYEFF */
+#define CSR_PLLSTANDBYEFF_LSB 0
+#define CSR_PLLSTANDBYEFF_MASK BIT(0)
+/* CSR_PLLDACVALOUT */
+#define CSR_PLLDACVALOUT_LSB 0
+#define CSR_PLLDACVALOUT_MASK GENMASK_32(4, 0)
+/* CSR_DLYTESTSEQ */
+#define CSR_DLYTESTSEQ_LSB 0
+#define CSR_DLYTESTSEQ_MASK GENMASK_32(5, 0)
+#define CSR_DLYTESTEN_LSB 0
+#define CSR_DLYTESTEN_MASK BIT(0)
+#define CSR_DLYTESTCNTINIT_LSB 1
+#define CSR_DLYTESTCNTINIT_MASK BIT(1)
+#define CSR_DLYTESTENOVERRIDE1_LSB 2
+#define CSR_DLYTESTENOVERRIDE1_MASK BIT(2)
+#define CSR_DLYTESTENOVERRIDE2_LSB 3
+#define CSR_DLYTESTENOVERRIDE2_MASK BIT(3)
+#define CSR_SYNCDLYMULTIPLIER_LSB 4
+#define CSR_SYNCDLYMULTIPLIER_MASK GENMASK_32(5, 4)
+/* CSR_DLYTESTRINGSELDB */
+#define CSR_DLYTESTRINGSELDB_LSB 0
+#define CSR_DLYTESTRINGSELDB_MASK GENMASK_32(4, 0)
+#define CSR_DLYTESTCUTDB_LSB 0
+#define CSR_DLYTESTCUTDB_MASK GENMASK_32(4, 0)
+/* CSR_DLYTESTRINGSELAC */
+#define CSR_DLYTESTRINGSELAC_LSB 0
+#define CSR_DLYTESTRINGSELAC_MASK GENMASK_32(4, 0)
+#define CSR_DLYTESTCUTAC_LSB 0
+#define CSR_DLYTESTCUTAC_MASK GENMASK_32(4, 0)
+/* CSR_DLYTESTCNTDFICLKIV */
+#define CSR_DLYTESTCNTDFICLKIV_LSB 0
+#define CSR_DLYTESTCNTDFICLKIV_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTDFICLK */
+#define CSR_DLYTESTCNTDFICLK_LSB 0
+#define CSR_DLYTESTCNTDFICLK_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB0 */
+#define CSR_DLYTESTCNTRINGOSCDB0_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB0_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB1 */
+#define CSR_DLYTESTCNTRINGOSCDB1_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB1_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB2 */
+#define CSR_DLYTESTCNTRINGOSCDB2_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB2_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB3 */
+#define CSR_DLYTESTCNTRINGOSCDB3_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB3_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB4 */
+#define CSR_DLYTESTCNTRINGOSCDB4_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB4_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB5 */
+#define CSR_DLYTESTCNTRINGOSCDB5_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB5_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB6 */
+#define CSR_DLYTESTCNTRINGOSCDB6_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB6_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB7 */
+#define CSR_DLYTESTCNTRINGOSCDB7_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB7_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB8 */
+#define CSR_DLYTESTCNTRINGOSCDB8_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB8_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCDB9 */
+#define CSR_DLYTESTCNTRINGOSCDB9_LSB 0
+#define CSR_DLYTESTCNTRINGOSCDB9_MASK GENMASK_32(15, 0)
+/* CSR_DLYTESTCNTRINGOSCAC */
+#define CSR_DLYTESTCNTRINGOSCAC_LSB 0
+#define CSR_DLYTESTCNTRINGOSCAC_MASK GENMASK_32(15, 0)
+/* CSR_MSTLCDLDBGCNTL */
+#define CSR_MSTLCDLDBGCNTL_LSB 0
+#define CSR_MSTLCDLDBGCNTL_MASK GENMASK_32(11, 0)
+#define CSR_MSTLCDLFINEOVRVAL_LSB 0
+#define CSR_MSTLCDLFINEOVRVAL_MASK GENMASK_32(8, 0)
+#define CSR_MSTLCDLFINEOVR_LSB 9
+#define CSR_MSTLCDLFINEOVR_MASK BIT(9)
+#define CSR_MSTLCDLFINESNAP_LSB 10
+#define CSR_MSTLCDLFINESNAP_MASK BIT(10)
+#define CSR_MSTLCDLTSTENABLE_LSB 11
+#define CSR_MSTLCDLTSTENABLE_MASK BIT(11)
+/* CSR_MSTLCDL0DBGRES */
+#define CSR_MSTLCDL0DBGRES_LSB 0
+#define CSR_MSTLCDL0DBGRES_MASK GENMASK_32(12, 0)
+#define CSR_MSTLCDL0FINESNAPVAL_LSB 0
+#define CSR_MSTLCDL0FINESNAPVAL_MASK GENMASK_32(8, 0)
+#define CSR_MSTLCDL0PHDSNAPVAL_LSB 9
+#define CSR_MSTLCDL0PHDSNAPVAL_MASK BIT(9)
+#define CSR_MSTLCDL0STICKYLOCK_LSB 10
+#define CSR_MSTLCDL0STICKYLOCK_MASK BIT(10)
+#define CSR_MSTLCDL0STICKYUNLOCK_LSB 11
+#define CSR_MSTLCDL0STICKYUNLOCK_MASK BIT(11)
+#define CSR_MSTLCDL0LIVELOCK_LSB 12
+#define CSR_MSTLCDL0LIVELOCK_MASK BIT(12)
+/* CSR_MSTLCDL1DBGRES */
+#define CSR_MSTLCDL1DBGRES_LSB 0
+#define CSR_MSTLCDL1DBGRES_MASK GENMASK_32(12, 0)
+#define CSR_MSTLCDL1FINESNAPVAL_LSB 0
+#define CSR_MSTLCDL1FINESNAPVAL_MASK GENMASK_32(8, 0)
+#define CSR_MSTLCDL1PHDSNAPVAL_LSB 9
+#define CSR_MSTLCDL1PHDSNAPVAL_MASK BIT(9)
+#define CSR_MSTLCDL1STICKYLOCK_LSB 10
+#define CSR_MSTLCDL1STICKYLOCK_MASK BIT(10)
+#define CSR_MSTLCDL1STICKYUNLOCK_LSB 11
+#define CSR_MSTLCDL1STICKYUNLOCK_MASK BIT(11)
+#define CSR_MSTLCDL1LIVELOCK_LSB 12
+#define CSR_MSTLCDL1LIVELOCK_MASK BIT(12)
+/* CSR_LCDLDBGCNTL */
+#define CSR_LCDLDBGCNTL_LSB 0
+#define CSR_LCDLDBGCNTL_MASK GENMASK_32(15, 0)
+#define CSR_LCDLFINEOVRVAL_LSB 0
+#define CSR_LCDLFINEOVRVAL_MASK GENMASK_32(8, 0)
+#define CSR_LCDLFINEOVR_LSB 9
+#define CSR_LCDLFINEOVR_MASK BIT(9)
+#define CSR_LCDLFINESNAP_LSB 10
+#define CSR_LCDLFINESNAP_MASK BIT(10)
+#define CSR_LCDLTSTENABLE_LSB 11
+#define CSR_LCDLTSTENABLE_MASK BIT(11)
+#define CSR_LCDLSTATUSSEL_LSB 12
+#define CSR_LCDLSTATUSSEL_MASK GENMASK_32(15, 12)
+/* CSR_ACLCDLSTATUS */
+#define CSR_ACLCDLSTATUS_LSB 0
+#define CSR_ACLCDLSTATUS_MASK GENMASK_32(13, 0)
+#define CSR_ACLCDLFINESNAPVAL_LSB 0
+#define CSR_ACLCDLFINESNAPVAL_MASK GENMASK_32(9, 0)
+#define CSR_ACLCDLPHDSNAPVAL_LSB 10
+#define CSR_ACLCDLPHDSNAPVAL_MASK BIT(10)
+#define CSR_ACLCDLSTICKYLOCK_LSB 11
+#define CSR_ACLCDLSTICKYLOCK_MASK BIT(11)
+#define CSR_ACLCDLSTICKYUNLOCK_LSB 12
+#define CSR_ACLCDLSTICKYUNLOCK_MASK BIT(12)
+#define CSR_ACLCDLLIVELOCK_LSB 13
+#define CSR_ACLCDLLIVELOCK_MASK BIT(13)
+/* CSR_CUSTPHYREV */
+#define CSR_CUSTPHYREV_LSB 0
+#define CSR_CUSTPHYREV_MASK GENMASK_32(5, 0)
+/* CSR_PHYREV */
+#define CSR_PHYREV_LSB 0
+#define CSR_PHYREV_MASK GENMASK_32(15, 0)
+#define CSR_PHYMNR_LSB 0
+#define CSR_PHYMNR_MASK GENMASK_32(3, 0)
+#define CSR_PHYMDR_LSB 4
+#define CSR_PHYMDR_MASK GENMASK_32(7, 4)
+#define CSR_PHYMJR_LSB 8
+#define CSR_PHYMJR_MASK GENMASK_32(15, 8)
+/* CSR_LP3EXITSEQ0BSTARTVECTOR */
+#define CSR_LP3EXITSEQ0BSTARTVECTOR_LSB 0
+#define CSR_LP3EXITSEQ0BSTARTVECTOR_MASK GENMASK_32(7, 0)
+#define CSR_LP3EXITSEQ0BSTARTVECPLLENABLED_LSB 0
+#define CSR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK GENMASK_32(3, 0)
+#define CSR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_LSB 4
+#define CSR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK GENMASK_32(7, 4)
+/* CSR_DFIFREQXLAT0 */
+#define CSR_DFIFREQXLAT0_LSB 0
+#define CSR_DFIFREQXLAT0_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL0_LSB 0
+#define CSR_DFIFREQXLATVAL0_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL1_LSB 4
+#define CSR_DFIFREQXLATVAL1_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL2_LSB 8
+#define CSR_DFIFREQXLATVAL2_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL3_LSB 12
+#define CSR_DFIFREQXLATVAL3_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT1 */
+#define CSR_DFIFREQXLAT1_LSB 0
+#define CSR_DFIFREQXLAT1_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL4_LSB 0
+#define CSR_DFIFREQXLATVAL4_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL5_LSB 4
+#define CSR_DFIFREQXLATVAL5_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL6_LSB 8
+#define CSR_DFIFREQXLATVAL6_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL7_LSB 12
+#define CSR_DFIFREQXLATVAL7_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT2 */
+#define CSR_DFIFREQXLAT2_LSB 0
+#define CSR_DFIFREQXLAT2_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL8_LSB 0
+#define CSR_DFIFREQXLATVAL8_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL9_LSB 4
+#define CSR_DFIFREQXLATVAL9_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL10_LSB 8
+#define CSR_DFIFREQXLATVAL10_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL11_LSB 12
+#define CSR_DFIFREQXLATVAL11_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT3 */
+#define CSR_DFIFREQXLAT3_LSB 0
+#define CSR_DFIFREQXLAT3_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL12_LSB 0
+#define CSR_DFIFREQXLATVAL12_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL13_LSB 4
+#define CSR_DFIFREQXLATVAL13_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL14_LSB 8
+#define CSR_DFIFREQXLATVAL14_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL15_LSB 12
+#define CSR_DFIFREQXLATVAL15_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT4 */
+#define CSR_DFIFREQXLAT4_LSB 0
+#define CSR_DFIFREQXLAT4_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL16_LSB 0
+#define CSR_DFIFREQXLATVAL16_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL17_LSB 4
+#define CSR_DFIFREQXLATVAL17_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL18_LSB 8
+#define CSR_DFIFREQXLATVAL18_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL19_LSB 12
+#define CSR_DFIFREQXLATVAL19_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT5 */
+#define CSR_DFIFREQXLAT5_LSB 0
+#define CSR_DFIFREQXLAT5_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL20_LSB 0
+#define CSR_DFIFREQXLATVAL20_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL21_LSB 4
+#define CSR_DFIFREQXLATVAL21_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL22_LSB 8
+#define CSR_DFIFREQXLATVAL22_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL23_LSB 12
+#define CSR_DFIFREQXLATVAL23_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT6 */
+#define CSR_DFIFREQXLAT6_LSB 0
+#define CSR_DFIFREQXLAT6_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL24_LSB 0
+#define CSR_DFIFREQXLATVAL24_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL25_LSB 4
+#define CSR_DFIFREQXLATVAL25_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL26_LSB 8
+#define CSR_DFIFREQXLATVAL26_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL27_LSB 12
+#define CSR_DFIFREQXLATVAL27_MASK GENMASK_32(15, 12)
+/* CSR_DFIFREQXLAT7 */
+#define CSR_DFIFREQXLAT7_LSB 0
+#define CSR_DFIFREQXLAT7_MASK GENMASK_32(15, 0)
+#define CSR_DFIFREQXLATVAL28_LSB 0
+#define CSR_DFIFREQXLATVAL28_MASK GENMASK_32(3, 0)
+#define CSR_DFIFREQXLATVAL29_LSB 4
+#define CSR_DFIFREQXLATVAL29_MASK GENMASK_32(7, 4)
+#define CSR_DFIFREQXLATVAL30_LSB 8
+#define CSR_DFIFREQXLATVAL30_MASK GENMASK_32(11, 8)
+#define CSR_DFIFREQXLATVAL31_LSB 12
+#define CSR_DFIFREQXLATVAL31_MASK GENMASK_32(15, 12)
+/* CSR_TXRDPTRINIT */
+#define CSR_TXRDPTRINIT_LSB 0
+#define CSR_TXRDPTRINIT_MASK BIT(0)
+/* CSR_DFIINITCOMPLETE */
+#define CSR_DFIINITCOMPLETE_LSB 0
+#define CSR_DFIINITCOMPLETE_MASK BIT(0)
+/* CSR_DFIFREQRATIO */
+#define CSR_DFIFREQRATIO_LSB 0
+#define CSR_DFIFREQRATIO_MASK GENMASK_32(1, 0)
+/* CSR_RXFIFOCHECKS */
+#define CSR_RXFIFOCHECKS_LSB 0
+#define CSR_RXFIFOCHECKS_MASK BIT(0)
+#define CSR_DOFREQUENTRXFIFOCHECKS_LSB 0
+#define CSR_DOFREQUENTRXFIFOCHECKS_MASK BIT(0)
+/* CSR_MTESTDTOCTRL */
+#define CSR_MTESTDTOCTRL_LSB 0
+#define CSR_MTESTDTOCTRL_MASK BIT(0)
+#define CSR_MTESTDTOEN_LSB 0
+#define CSR_MTESTDTOEN_MASK BIT(0)
+/* CSR_MAPCAA0TODFI */
+#define CSR_MAPCAA0TODFI_LSB 0
+#define CSR_MAPCAA0TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA1TODFI */
+#define CSR_MAPCAA1TODFI_LSB 0
+#define CSR_MAPCAA1TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA2TODFI */
+#define CSR_MAPCAA2TODFI_LSB 0
+#define CSR_MAPCAA2TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA3TODFI */
+#define CSR_MAPCAA3TODFI_LSB 0
+#define CSR_MAPCAA3TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA4TODFI */
+#define CSR_MAPCAA4TODFI_LSB 0
+#define CSR_MAPCAA4TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA5TODFI */
+#define CSR_MAPCAA5TODFI_LSB 0
+#define CSR_MAPCAA5TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA6TODFI */
+#define CSR_MAPCAA6TODFI_LSB 0
+#define CSR_MAPCAA6TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA7TODFI */
+#define CSR_MAPCAA7TODFI_LSB 0
+#define CSR_MAPCAA7TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA8TODFI */
+#define CSR_MAPCAA8TODFI_LSB 0
+#define CSR_MAPCAA8TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAA9TODFI */
+#define CSR_MAPCAA9TODFI_LSB 0
+#define CSR_MAPCAA9TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB0TODFI */
+#define CSR_MAPCAB0TODFI_LSB 0
+#define CSR_MAPCAB0TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB1TODFI */
+#define CSR_MAPCAB1TODFI_LSB 0
+#define CSR_MAPCAB1TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB2TODFI */
+#define CSR_MAPCAB2TODFI_LSB 0
+#define CSR_MAPCAB2TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB3TODFI */
+#define CSR_MAPCAB3TODFI_LSB 0
+#define CSR_MAPCAB3TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB4TODFI */
+#define CSR_MAPCAB4TODFI_LSB 0
+#define CSR_MAPCAB4TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB5TODFI */
+#define CSR_MAPCAB5TODFI_LSB 0
+#define CSR_MAPCAB5TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB6TODFI */
+#define CSR_MAPCAB6TODFI_LSB 0
+#define CSR_MAPCAB6TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB7TODFI */
+#define CSR_MAPCAB7TODFI_LSB 0
+#define CSR_MAPCAB7TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB8TODFI */
+#define CSR_MAPCAB8TODFI_LSB 0
+#define CSR_MAPCAB8TODFI_MASK GENMASK_32(3, 0)
+/* CSR_MAPCAB9TODFI */
+#define CSR_MAPCAB9TODFI_LSB 0
+#define CSR_MAPCAB9TODFI_MASK GENMASK_32(3, 0)
+/* CSR_PHYINTERRUPTENABLE */
+#define CSR_PHYINTERRUPTENABLE_LSB 0
+#define CSR_PHYINTERRUPTENABLE_MASK GENMASK_32(15, 0)
+#define CSR_PHYTRNGCMPLTEN_LSB 0
+#define CSR_PHYTRNGCMPLTEN_MASK BIT(0)
+#define CSR_PHYINITCMPLTEN_LSB 1
+#define CSR_PHYINITCMPLTEN_MASK BIT(1)
+#define CSR_PHYTRNGFAILEN_LSB 2
+#define CSR_PHYTRNGFAILEN_MASK BIT(2)
+#define CSR_PHYFWRESERVEDEN_LSB 3
+#define CSR_PHYFWRESERVEDEN_MASK GENMASK_32(7, 3)
+#define CSR_PHYVTDRIFTALARMEN_LSB 8
+#define CSR_PHYVTDRIFTALARMEN_MASK GENMASK_32(9, 8)
+#define CSR_PHYRXFIFOCHECKEN_LSB 10
+#define CSR_PHYRXFIFOCHECKEN_MASK BIT(10)
+#define CSR_PHYHWRESERVEDEN_LSB 11
+#define CSR_PHYHWRESERVEDEN_MASK GENMASK_32(15, 11)
+/* CSR_PHYINTERRUPTFWCONTROL */
+#define CSR_PHYINTERRUPTFWCONTROL_LSB 0
+#define CSR_PHYINTERRUPTFWCONTROL_MASK GENMASK_32(7, 0)
+#define CSR_PHYTRNGCMPLTFW_LSB 0
+#define CSR_PHYTRNGCMPLTFW_MASK BIT(0)
+#define CSR_PHYINITCMPLTFW_LSB 1
+#define CSR_PHYINITCMPLTFW_MASK BIT(1)
+#define CSR_PHYTRNGFAILFW_LSB 2
+#define CSR_PHYTRNGFAILFW_MASK BIT(2)
+#define CSR_PHYFWRESERVEDFW_LSB 3
+#define CSR_PHYFWRESERVEDFW_MASK GENMASK_32(7, 3)
+/* CSR_PHYINTERRUPTMASK */
+#define CSR_PHYINTERRUPTMASK_LSB 0
+#define CSR_PHYINTERRUPTMASK_MASK GENMASK_32(15, 0)
+#define CSR_PHYTRNGCMPLTMSK_LSB 0
+#define CSR_PHYTRNGCMPLTMSK_MASK BIT(0)
+#define CSR_PHYINITCMPLTMSK_LSB 1
+#define CSR_PHYINITCMPLTMSK_MASK BIT(1)
+#define CSR_PHYTRNGFAILMSK_LSB 2
+#define CSR_PHYTRNGFAILMSK_MASK BIT(2)
+#define CSR_PHYFWRESERVEDMSK_LSB 3
+#define CSR_PHYFWRESERVEDMSK_MASK GENMASK_32(7, 3)
+#define CSR_PHYVTDRIFTALARMMSK_LSB 8
+#define CSR_PHYVTDRIFTALARMMSK_MASK GENMASK_32(9, 8)
+#define CSR_PHYRXFIFOCHECKMSK_LSB 10
+#define CSR_PHYRXFIFOCHECKMSK_MASK BIT(10)
+#define CSR_PHYHWRESERVEDMSK_LSB 11
+#define CSR_PHYHWRESERVEDMSK_MASK GENMASK_32(15, 11)
+/* CSR_PHYINTERRUPTCLEAR */
+#define CSR_PHYINTERRUPTCLEAR_LSB 0
+#define CSR_PHYINTERRUPTCLEAR_MASK GENMASK_32(15, 0)
+#define CSR_PHYTRNGCMPLTCLR_LSB 0
+#define CSR_PHYTRNGCMPLTCLR_MASK BIT(0)
+#define CSR_PHYINITCMPLTCLR_LSB 1
+#define CSR_PHYINITCMPLTCLR_MASK BIT(1)
+#define CSR_PHYTRNGFAILCLR_LSB 2
+#define CSR_PHYTRNGFAILCLR_MASK BIT(2)
+#define CSR_PHYFWRESERVEDCLR_LSB 3
+#define CSR_PHYFWRESERVEDCLR_MASK GENMASK_32(7, 3)
+#define CSR_PHYVTDRIFTALARMCLR_LSB 8
+#define CSR_PHYVTDRIFTALARMCLR_MASK GENMASK_32(9, 8)
+#define CSR_PHYRXFIFOCHECKCLR_LSB 10
+#define CSR_PHYRXFIFOCHECKCLR_MASK BIT(10)
+#define CSR_PHYHWRESERVEDCLR_LSB 11
+#define CSR_PHYHWRESERVEDCLR_MASK GENMASK_32(15, 11)
+/* CSR_PHYINTERRUPTSTATUS */
+#define CSR_PHYINTERRUPTSTATUS_LSB 0
+#define CSR_PHYINTERRUPTSTATUS_MASK GENMASK_32(15, 0)
+#define CSR_PHYTRNGCMPLT_LSB 0
+#define CSR_PHYTRNGCMPLT_MASK BIT(0)
+#define CSR_PHYINITCMPLT_LSB 1
+#define CSR_PHYINITCMPLT_MASK BIT(1)
+#define CSR_PHYTRNGFAIL_LSB 2
+#define CSR_PHYTRNGFAIL_MASK BIT(2)
+#define CSR_PHYFWRESERVED_LSB 3
+#define CSR_PHYFWRESERVED_MASK GENMASK_32(7, 3)
+#define CSR_VTDRIFTALARM_LSB 8
+#define CSR_VTDRIFTALARM_MASK GENMASK_32(9, 8)
+#define CSR_PHYRXFIFOCHECK_LSB 10
+#define CSR_PHYRXFIFOCHECK_MASK BIT(10)
+#define CSR_PHYHWRESERVED_LSB 11
+#define CSR_PHYHWRESERVED_MASK GENMASK_32(15, 11)
+/* CSR_HWTSWIZZLEHWTADDRESS0 */
+#define CSR_HWTSWIZZLEHWTADDRESS0_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS0_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS1 */
+#define CSR_HWTSWIZZLEHWTADDRESS1_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS1_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS2 */
+#define CSR_HWTSWIZZLEHWTADDRESS2_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS2_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS3 */
+#define CSR_HWTSWIZZLEHWTADDRESS3_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS3_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS4 */
+#define CSR_HWTSWIZZLEHWTADDRESS4_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS4_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS5 */
+#define CSR_HWTSWIZZLEHWTADDRESS5_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS5_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS6 */
+#define CSR_HWTSWIZZLEHWTADDRESS6_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS6_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS7 */
+#define CSR_HWTSWIZZLEHWTADDRESS7_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS7_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS8 */
+#define CSR_HWTSWIZZLEHWTADDRESS8_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS8_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS9 */
+#define CSR_HWTSWIZZLEHWTADDRESS9_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS9_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS10 */
+#define CSR_HWTSWIZZLEHWTADDRESS10_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS10_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS11 */
+#define CSR_HWTSWIZZLEHWTADDRESS11_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS11_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS12 */
+#define CSR_HWTSWIZZLEHWTADDRESS12_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS12_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS13 */
+#define CSR_HWTSWIZZLEHWTADDRESS13_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS13_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS14 */
+#define CSR_HWTSWIZZLEHWTADDRESS14_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS14_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS15 */
+#define CSR_HWTSWIZZLEHWTADDRESS15_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS15_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTADDRESS17 */
+#define CSR_HWTSWIZZLEHWTADDRESS17_LSB 0
+#define CSR_HWTSWIZZLEHWTADDRESS17_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTACTN */
+#define CSR_HWTSWIZZLEHWTACTN_LSB 0
+#define CSR_HWTSWIZZLEHWTACTN_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTBANK0 */
+#define CSR_HWTSWIZZLEHWTBANK0_LSB 0
+#define CSR_HWTSWIZZLEHWTBANK0_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTBANK1 */
+#define CSR_HWTSWIZZLEHWTBANK1_LSB 0
+#define CSR_HWTSWIZZLEHWTBANK1_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTBANK2 */
+#define CSR_HWTSWIZZLEHWTBANK2_LSB 0
+#define CSR_HWTSWIZZLEHWTBANK2_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTBG0 */
+#define CSR_HWTSWIZZLEHWTBG0_LSB 0
+#define CSR_HWTSWIZZLEHWTBG0_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTBG1 */
+#define CSR_HWTSWIZZLEHWTBG1_LSB 0
+#define CSR_HWTSWIZZLEHWTBG1_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTCASN */
+#define CSR_HWTSWIZZLEHWTCASN_LSB 0
+#define CSR_HWTSWIZZLEHWTCASN_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTRASN */
+#define CSR_HWTSWIZZLEHWTRASN_LSB 0
+#define CSR_HWTSWIZZLEHWTRASN_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTWEN */
+#define CSR_HWTSWIZZLEHWTWEN_LSB 0
+#define CSR_HWTSWIZZLEHWTWEN_MASK GENMASK_32(4, 0)
+/* CSR_HWTSWIZZLEHWTPARITYIN */
+#define CSR_HWTSWIZZLEHWTPARITYIN_LSB 0
+#define CSR_HWTSWIZZLEHWTPARITYIN_MASK GENMASK_32(4, 0)
+/* CSR_DFIHANDSHAKEDELAYS0 */
+#define CSR_DFIHANDSHAKEDELAYS0_LSB 0
+#define CSR_DFIHANDSHAKEDELAYS0_MASK GENMASK_32(15, 0)
+#define CSR_PHYUPDACKDELAY0_LSB 0
+#define CSR_PHYUPDACKDELAY0_MASK GENMASK_32(3, 0)
+#define CSR_PHYUPDREQDELAY0_LSB 4
+#define CSR_PHYUPDREQDELAY0_MASK GENMASK_32(7, 4)
+#define CSR_CTRLUPDACKDELAY0_LSB 8
+#define CSR_CTRLUPDACKDELAY0_MASK GENMASK_32(11, 8)
+#define CSR_CTRLUPDREQDELAY0_LSB 12
+#define CSR_CTRLUPDREQDELAY0_MASK GENMASK_32(15, 12)
+/* CSR_DFIHANDSHAKEDELAYS1 */
+#define CSR_DFIHANDSHAKEDELAYS1_LSB 0
+#define CSR_DFIHANDSHAKEDELAYS1_MASK GENMASK_32(15, 0)
+#define CSR_PHYUPDACKDELAY1_LSB 0
+#define CSR_PHYUPDACKDELAY1_MASK GENMASK_32(3, 0)
+#define CSR_PHYUPDREQDELAY1_LSB 4
+#define CSR_PHYUPDREQDELAY1_MASK GENMASK_32(7, 4)
+#define CSR_CTRLUPDACKDELAY1_LSB 8
+#define CSR_CTRLUPDACKDELAY1_MASK GENMASK_32(11, 8)
+#define CSR_CTRLUPDREQDELAY1_LSB 12
+#define CSR_CTRLUPDREQDELAY1_MASK GENMASK_32(15, 12)
+/* CSR_REMOTEIMPCAL */
+#define CSR_REMOTEIMPCAL_LSB 0
+#define CSR_REMOTEIMPCAL_MASK GENMASK_32(1, 0)
+#define CSR_CALIBSLAVE_LSB 0
+#define CSR_CALIBSLAVE_MASK BIT(0)
+#define CSR_SLAVECODEUPDATED_LSB 1
+#define CSR_SLAVECODEUPDATED_MASK BIT(1)
+/* CSR_ACLOOPBACKCTL */
+#define CSR_ACLOOPBACKCTL_LSB 0
+#define CSR_ACLOOPBACKCTL_MASK GENMASK_32(1, 0)
+#define CSR_TERMINATION_LSB 0
+#define CSR_TERMINATION_MASK BIT(0)
+#define CSR_NOISECANCEL_LSB 1
+#define CSR_NOISECANCEL_MASK BIT(1)
+
+/* ACSM0 register offsets */
+/* CSR_ACSMSEQ0X0 */
+#define CSR_ACSMSEQ0X0_LSB 0
+#define CSR_ACSMSEQ0X0_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY0_LSB 0
+#define CSR_ACSMMCLKDLY0_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE0_LSB 8
+#define CSR_ACSMDDRWE0_MASK BIT(8)
+#define CSR_ACSMDDRCAS0_LSB 9
+#define CSR_ACSMDDRCAS0_MASK BIT(9)
+#define CSR_ACSMDDRRAS0_LSB 10
+#define CSR_ACSMDDRRAS0_MASK BIT(10)
+#define CSR_ACSMDDRCKESET0_LSB 11
+#define CSR_ACSMDDRCKESET0_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR0_LSB 12
+#define CSR_ACSMDDRCKECLR0_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD0_LSB 13
+#define CSR_ACSMSEQGATECMD0_MASK BIT(13)
+#define CSR_ACSMSEQTERM0_LSB 14
+#define CSR_ACSMSEQTERM0_MASK BIT(14)
+#define CSR_ACSMLP3CA30_LSB 15
+#define CSR_ACSMLP3CA30_MASK BIT(15)
+/* CSR_ACSMSEQ0X1 */
+#define CSR_ACSMSEQ0X1_LSB 0
+#define CSR_ACSMSEQ0X1_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY1_LSB 0
+#define CSR_ACSMMCLKDLY1_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE1_LSB 8
+#define CSR_ACSMDDRWE1_MASK BIT(8)
+#define CSR_ACSMDDRCAS1_LSB 9
+#define CSR_ACSMDDRCAS1_MASK BIT(9)
+#define CSR_ACSMDDRRAS1_LSB 10
+#define CSR_ACSMDDRRAS1_MASK BIT(10)
+#define CSR_ACSMDDRCKESET1_LSB 11
+#define CSR_ACSMDDRCKESET1_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR1_LSB 12
+#define CSR_ACSMDDRCKECLR1_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD1_LSB 13
+#define CSR_ACSMSEQGATECMD1_MASK BIT(13)
+#define CSR_ACSMSEQTERM1_LSB 14
+#define CSR_ACSMSEQTERM1_MASK BIT(14)
+#define CSR_ACSMLP3CA31_LSB 15
+#define CSR_ACSMLP3CA31_MASK BIT(15)
+/* CSR_ACSMSEQ0X2 */
+#define CSR_ACSMSEQ0X2_LSB 0
+#define CSR_ACSMSEQ0X2_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY2_LSB 0
+#define CSR_ACSMMCLKDLY2_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE2_LSB 8
+#define CSR_ACSMDDRWE2_MASK BIT(8)
+#define CSR_ACSMDDRCAS2_LSB 9
+#define CSR_ACSMDDRCAS2_MASK BIT(9)
+#define CSR_ACSMDDRRAS2_LSB 10
+#define CSR_ACSMDDRRAS2_MASK BIT(10)
+#define CSR_ACSMDDRCKESET2_LSB 11
+#define CSR_ACSMDDRCKESET2_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR2_LSB 12
+#define CSR_ACSMDDRCKECLR2_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD2_LSB 13
+#define CSR_ACSMSEQGATECMD2_MASK BIT(13)
+#define CSR_ACSMSEQTERM2_LSB 14
+#define CSR_ACSMSEQTERM2_MASK BIT(14)
+#define CSR_ACSMLP3CA32_LSB 15
+#define CSR_ACSMLP3CA32_MASK BIT(15)
+/* CSR_ACSMSEQ0X3 */
+#define CSR_ACSMSEQ0X3_LSB 0
+#define CSR_ACSMSEQ0X3_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY3_LSB 0
+#define CSR_ACSMMCLKDLY3_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE3_LSB 8
+#define CSR_ACSMDDRWE3_MASK BIT(8)
+#define CSR_ACSMDDRCAS3_LSB 9
+#define CSR_ACSMDDRCAS3_MASK BIT(9)
+#define CSR_ACSMDDRRAS3_LSB 10
+#define CSR_ACSMDDRRAS3_MASK BIT(10)
+#define CSR_ACSMDDRCKESET3_LSB 11
+#define CSR_ACSMDDRCKESET3_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR3_LSB 12
+#define CSR_ACSMDDRCKECLR3_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD3_LSB 13
+#define CSR_ACSMSEQGATECMD3_MASK BIT(13)
+#define CSR_ACSMSEQTERM3_LSB 14
+#define CSR_ACSMSEQTERM3_MASK BIT(14)
+#define CSR_ACSMLP3CA33_LSB 15
+#define CSR_ACSMLP3CA33_MASK BIT(15)
+/* CSR_ACSMSEQ0X4 */
+#define CSR_ACSMSEQ0X4_LSB 0
+#define CSR_ACSMSEQ0X4_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY4_LSB 0
+#define CSR_ACSMMCLKDLY4_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE4_LSB 8
+#define CSR_ACSMDDRWE4_MASK BIT(8)
+#define CSR_ACSMDDRCAS4_LSB 9
+#define CSR_ACSMDDRCAS4_MASK BIT(9)
+#define CSR_ACSMDDRRAS4_LSB 10
+#define CSR_ACSMDDRRAS4_MASK BIT(10)
+#define CSR_ACSMDDRCKESET4_LSB 11
+#define CSR_ACSMDDRCKESET4_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR4_LSB 12
+#define CSR_ACSMDDRCKECLR4_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD4_LSB 13
+#define CSR_ACSMSEQGATECMD4_MASK BIT(13)
+#define CSR_ACSMSEQTERM4_LSB 14
+#define CSR_ACSMSEQTERM4_MASK BIT(14)
+#define CSR_ACSMLP3CA34_LSB 15
+#define CSR_ACSMLP3CA34_MASK BIT(15)
+/* CSR_ACSMSEQ0X5 */
+#define CSR_ACSMSEQ0X5_LSB 0
+#define CSR_ACSMSEQ0X5_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY5_LSB 0
+#define CSR_ACSMMCLKDLY5_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE5_LSB 8
+#define CSR_ACSMDDRWE5_MASK BIT(8)
+#define CSR_ACSMDDRCAS5_LSB 9
+#define CSR_ACSMDDRCAS5_MASK BIT(9)
+#define CSR_ACSMDDRRAS5_LSB 10
+#define CSR_ACSMDDRRAS5_MASK BIT(10)
+#define CSR_ACSMDDRCKESET5_LSB 11
+#define CSR_ACSMDDRCKESET5_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR5_LSB 12
+#define CSR_ACSMDDRCKECLR5_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD5_LSB 13
+#define CSR_ACSMSEQGATECMD5_MASK BIT(13)
+#define CSR_ACSMSEQTERM5_LSB 14
+#define CSR_ACSMSEQTERM5_MASK BIT(14)
+#define CSR_ACSMLP3CA35_LSB 15
+#define CSR_ACSMLP3CA35_MASK BIT(15)
+/* CSR_ACSMSEQ0X6 */
+#define CSR_ACSMSEQ0X6_LSB 0
+#define CSR_ACSMSEQ0X6_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY6_LSB 0
+#define CSR_ACSMMCLKDLY6_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE6_LSB 8
+#define CSR_ACSMDDRWE6_MASK BIT(8)
+#define CSR_ACSMDDRCAS6_LSB 9
+#define CSR_ACSMDDRCAS6_MASK BIT(9)
+#define CSR_ACSMDDRRAS6_LSB 10
+#define CSR_ACSMDDRRAS6_MASK BIT(10)
+#define CSR_ACSMDDRCKESET6_LSB 11
+#define CSR_ACSMDDRCKESET6_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR6_LSB 12
+#define CSR_ACSMDDRCKECLR6_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD6_LSB 13
+#define CSR_ACSMSEQGATECMD6_MASK BIT(13)
+#define CSR_ACSMSEQTERM6_LSB 14
+#define CSR_ACSMSEQTERM6_MASK BIT(14)
+#define CSR_ACSMLP3CA36_LSB 15
+#define CSR_ACSMLP3CA36_MASK BIT(15)
+/* CSR_ACSMSEQ0X7 */
+#define CSR_ACSMSEQ0X7_LSB 0
+#define CSR_ACSMSEQ0X7_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY7_LSB 0
+#define CSR_ACSMMCLKDLY7_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE7_LSB 8
+#define CSR_ACSMDDRWE7_MASK BIT(8)
+#define CSR_ACSMDDRCAS7_LSB 9
+#define CSR_ACSMDDRCAS7_MASK BIT(9)
+#define CSR_ACSMDDRRAS7_LSB 10
+#define CSR_ACSMDDRRAS7_MASK BIT(10)
+#define CSR_ACSMDDRCKESET7_LSB 11
+#define CSR_ACSMDDRCKESET7_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR7_LSB 12
+#define CSR_ACSMDDRCKECLR7_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD7_LSB 13
+#define CSR_ACSMSEQGATECMD7_MASK BIT(13)
+#define CSR_ACSMSEQTERM7_LSB 14
+#define CSR_ACSMSEQTERM7_MASK BIT(14)
+#define CSR_ACSMLP3CA37_LSB 15
+#define CSR_ACSMLP3CA37_MASK BIT(15)
+/* CSR_ACSMSEQ0X8 */
+#define CSR_ACSMSEQ0X8_LSB 0
+#define CSR_ACSMSEQ0X8_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY8_LSB 0
+#define CSR_ACSMMCLKDLY8_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE8_LSB 8
+#define CSR_ACSMDDRWE8_MASK BIT(8)
+#define CSR_ACSMDDRCAS8_LSB 9
+#define CSR_ACSMDDRCAS8_MASK BIT(9)
+#define CSR_ACSMDDRRAS8_LSB 10
+#define CSR_ACSMDDRRAS8_MASK BIT(10)
+#define CSR_ACSMDDRCKESET8_LSB 11
+#define CSR_ACSMDDRCKESET8_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR8_LSB 12
+#define CSR_ACSMDDRCKECLR8_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD8_LSB 13
+#define CSR_ACSMSEQGATECMD8_MASK BIT(13)
+#define CSR_ACSMSEQTERM8_LSB 14
+#define CSR_ACSMSEQTERM8_MASK BIT(14)
+#define CSR_ACSMLP3CA38_LSB 15
+#define CSR_ACSMLP3CA38_MASK BIT(15)
+/* CSR_ACSMSEQ0X9 */
+#define CSR_ACSMSEQ0X9_LSB 0
+#define CSR_ACSMSEQ0X9_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY9_LSB 0
+#define CSR_ACSMMCLKDLY9_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE9_LSB 8
+#define CSR_ACSMDDRWE9_MASK BIT(8)
+#define CSR_ACSMDDRCAS9_LSB 9
+#define CSR_ACSMDDRCAS9_MASK BIT(9)
+#define CSR_ACSMDDRRAS9_LSB 10
+#define CSR_ACSMDDRRAS9_MASK BIT(10)
+#define CSR_ACSMDDRCKESET9_LSB 11
+#define CSR_ACSMDDRCKESET9_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR9_LSB 12
+#define CSR_ACSMDDRCKECLR9_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD9_LSB 13
+#define CSR_ACSMSEQGATECMD9_MASK BIT(13)
+#define CSR_ACSMSEQTERM9_LSB 14
+#define CSR_ACSMSEQTERM9_MASK BIT(14)
+#define CSR_ACSMLP3CA39_LSB 15
+#define CSR_ACSMLP3CA39_MASK BIT(15)
+/* CSR_ACSMSEQ0X10 */
+#define CSR_ACSMSEQ0X10_LSB 0
+#define CSR_ACSMSEQ0X10_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY10_LSB 0
+#define CSR_ACSMMCLKDLY10_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE10_LSB 8
+#define CSR_ACSMDDRWE10_MASK BIT(8)
+#define CSR_ACSMDDRCAS10_LSB 9
+#define CSR_ACSMDDRCAS10_MASK BIT(9)
+#define CSR_ACSMDDRRAS10_LSB 10
+#define CSR_ACSMDDRRAS10_MASK BIT(10)
+#define CSR_ACSMDDRCKESET10_LSB 11
+#define CSR_ACSMDDRCKESET10_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR10_LSB 12
+#define CSR_ACSMDDRCKECLR10_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD10_LSB 13
+#define CSR_ACSMSEQGATECMD10_MASK BIT(13)
+#define CSR_ACSMSEQTERM10_LSB 14
+#define CSR_ACSMSEQTERM10_MASK BIT(14)
+#define CSR_ACSMLP3CA310_LSB 15
+#define CSR_ACSMLP3CA310_MASK BIT(15)
+/* CSR_ACSMSEQ0X11 */
+#define CSR_ACSMSEQ0X11_LSB 0
+#define CSR_ACSMSEQ0X11_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY11_LSB 0
+#define CSR_ACSMMCLKDLY11_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE11_LSB 8
+#define CSR_ACSMDDRWE11_MASK BIT(8)
+#define CSR_ACSMDDRCAS11_LSB 9
+#define CSR_ACSMDDRCAS11_MASK BIT(9)
+#define CSR_ACSMDDRRAS11_LSB 10
+#define CSR_ACSMDDRRAS11_MASK BIT(10)
+#define CSR_ACSMDDRCKESET11_LSB 11
+#define CSR_ACSMDDRCKESET11_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR11_LSB 12
+#define CSR_ACSMDDRCKECLR11_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD11_LSB 13
+#define CSR_ACSMSEQGATECMD11_MASK BIT(13)
+#define CSR_ACSMSEQTERM11_LSB 14
+#define CSR_ACSMSEQTERM11_MASK BIT(14)
+#define CSR_ACSMLP3CA311_LSB 15
+#define CSR_ACSMLP3CA311_MASK BIT(15)
+/* CSR_ACSMSEQ0X12 */
+#define CSR_ACSMSEQ0X12_LSB 0
+#define CSR_ACSMSEQ0X12_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY12_LSB 0
+#define CSR_ACSMMCLKDLY12_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE12_LSB 8
+#define CSR_ACSMDDRWE12_MASK BIT(8)
+#define CSR_ACSMDDRCAS12_LSB 9
+#define CSR_ACSMDDRCAS12_MASK BIT(9)
+#define CSR_ACSMDDRRAS12_LSB 10
+#define CSR_ACSMDDRRAS12_MASK BIT(10)
+#define CSR_ACSMDDRCKESET12_LSB 11
+#define CSR_ACSMDDRCKESET12_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR12_LSB 12
+#define CSR_ACSMDDRCKECLR12_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD12_LSB 13
+#define CSR_ACSMSEQGATECMD12_MASK BIT(13)
+#define CSR_ACSMSEQTERM12_LSB 14
+#define CSR_ACSMSEQTERM12_MASK BIT(14)
+#define CSR_ACSMLP3CA312_LSB 15
+#define CSR_ACSMLP3CA312_MASK BIT(15)
+/* CSR_ACSMSEQ0X13 */
+#define CSR_ACSMSEQ0X13_LSB 0
+#define CSR_ACSMSEQ0X13_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY13_LSB 0
+#define CSR_ACSMMCLKDLY13_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE13_LSB 8
+#define CSR_ACSMDDRWE13_MASK BIT(8)
+#define CSR_ACSMDDRCAS13_LSB 9
+#define CSR_ACSMDDRCAS13_MASK BIT(9)
+#define CSR_ACSMDDRRAS13_LSB 10
+#define CSR_ACSMDDRRAS13_MASK BIT(10)
+#define CSR_ACSMDDRCKESET13_LSB 11
+#define CSR_ACSMDDRCKESET13_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR13_LSB 12
+#define CSR_ACSMDDRCKECLR13_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD13_LSB 13
+#define CSR_ACSMSEQGATECMD13_MASK BIT(13)
+#define CSR_ACSMSEQTERM13_LSB 14
+#define CSR_ACSMSEQTERM13_MASK BIT(14)
+#define CSR_ACSMLP3CA313_LSB 15
+#define CSR_ACSMLP3CA313_MASK BIT(15)
+/* CSR_ACSMSEQ0X14 */
+#define CSR_ACSMSEQ0X14_LSB 0
+#define CSR_ACSMSEQ0X14_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY14_LSB 0
+#define CSR_ACSMMCLKDLY14_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE14_LSB 8
+#define CSR_ACSMDDRWE14_MASK BIT(8)
+#define CSR_ACSMDDRCAS14_LSB 9
+#define CSR_ACSMDDRCAS14_MASK BIT(9)
+#define CSR_ACSMDDRRAS14_LSB 10
+#define CSR_ACSMDDRRAS14_MASK BIT(10)
+#define CSR_ACSMDDRCKESET14_LSB 11
+#define CSR_ACSMDDRCKESET14_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR14_LSB 12
+#define CSR_ACSMDDRCKECLR14_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD14_LSB 13
+#define CSR_ACSMSEQGATECMD14_MASK BIT(13)
+#define CSR_ACSMSEQTERM14_LSB 14
+#define CSR_ACSMSEQTERM14_MASK BIT(14)
+#define CSR_ACSMLP3CA314_LSB 15
+#define CSR_ACSMLP3CA314_MASK BIT(15)
+/* CSR_ACSMSEQ0X15 */
+#define CSR_ACSMSEQ0X15_LSB 0
+#define CSR_ACSMSEQ0X15_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY15_LSB 0
+#define CSR_ACSMMCLKDLY15_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE15_LSB 8
+#define CSR_ACSMDDRWE15_MASK BIT(8)
+#define CSR_ACSMDDRCAS15_LSB 9
+#define CSR_ACSMDDRCAS15_MASK BIT(9)
+#define CSR_ACSMDDRRAS15_LSB 10
+#define CSR_ACSMDDRRAS15_MASK BIT(10)
+#define CSR_ACSMDDRCKESET15_LSB 11
+#define CSR_ACSMDDRCKESET15_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR15_LSB 12
+#define CSR_ACSMDDRCKECLR15_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD15_LSB 13
+#define CSR_ACSMSEQGATECMD15_MASK BIT(13)
+#define CSR_ACSMSEQTERM15_LSB 14
+#define CSR_ACSMSEQTERM15_MASK BIT(14)
+#define CSR_ACSMLP3CA315_LSB 15
+#define CSR_ACSMLP3CA315_MASK BIT(15)
+/* CSR_ACSMSEQ0X16 */
+#define CSR_ACSMSEQ0X16_LSB 0
+#define CSR_ACSMSEQ0X16_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY16_LSB 0
+#define CSR_ACSMMCLKDLY16_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE16_LSB 8
+#define CSR_ACSMDDRWE16_MASK BIT(8)
+#define CSR_ACSMDDRCAS16_LSB 9
+#define CSR_ACSMDDRCAS16_MASK BIT(9)
+#define CSR_ACSMDDRRAS16_LSB 10
+#define CSR_ACSMDDRRAS16_MASK BIT(10)
+#define CSR_ACSMDDRCKESET16_LSB 11
+#define CSR_ACSMDDRCKESET16_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR16_LSB 12
+#define CSR_ACSMDDRCKECLR16_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD16_LSB 13
+#define CSR_ACSMSEQGATECMD16_MASK BIT(13)
+#define CSR_ACSMSEQTERM16_LSB 14
+#define CSR_ACSMSEQTERM16_MASK BIT(14)
+#define CSR_ACSMLP3CA316_LSB 15
+#define CSR_ACSMLP3CA316_MASK BIT(15)
+/* CSR_ACSMSEQ0X17 */
+#define CSR_ACSMSEQ0X17_LSB 0
+#define CSR_ACSMSEQ0X17_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY17_LSB 0
+#define CSR_ACSMMCLKDLY17_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE17_LSB 8
+#define CSR_ACSMDDRWE17_MASK BIT(8)
+#define CSR_ACSMDDRCAS17_LSB 9
+#define CSR_ACSMDDRCAS17_MASK BIT(9)
+#define CSR_ACSMDDRRAS17_LSB 10
+#define CSR_ACSMDDRRAS17_MASK BIT(10)
+#define CSR_ACSMDDRCKESET17_LSB 11
+#define CSR_ACSMDDRCKESET17_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR17_LSB 12
+#define CSR_ACSMDDRCKECLR17_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD17_LSB 13
+#define CSR_ACSMSEQGATECMD17_MASK BIT(13)
+#define CSR_ACSMSEQTERM17_LSB 14
+#define CSR_ACSMSEQTERM17_MASK BIT(14)
+#define CSR_ACSMLP3CA317_LSB 15
+#define CSR_ACSMLP3CA317_MASK BIT(15)
+/* CSR_ACSMSEQ0X18 */
+#define CSR_ACSMSEQ0X18_LSB 0
+#define CSR_ACSMSEQ0X18_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY18_LSB 0
+#define CSR_ACSMMCLKDLY18_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE18_LSB 8
+#define CSR_ACSMDDRWE18_MASK BIT(8)
+#define CSR_ACSMDDRCAS18_LSB 9
+#define CSR_ACSMDDRCAS18_MASK BIT(9)
+#define CSR_ACSMDDRRAS18_LSB 10
+#define CSR_ACSMDDRRAS18_MASK BIT(10)
+#define CSR_ACSMDDRCKESET18_LSB 11
+#define CSR_ACSMDDRCKESET18_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR18_LSB 12
+#define CSR_ACSMDDRCKECLR18_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD18_LSB 13
+#define CSR_ACSMSEQGATECMD18_MASK BIT(13)
+#define CSR_ACSMSEQTERM18_LSB 14
+#define CSR_ACSMSEQTERM18_MASK BIT(14)
+#define CSR_ACSMLP3CA318_LSB 15
+#define CSR_ACSMLP3CA318_MASK BIT(15)
+/* CSR_ACSMSEQ0X19 */
+#define CSR_ACSMSEQ0X19_LSB 0
+#define CSR_ACSMSEQ0X19_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY19_LSB 0
+#define CSR_ACSMMCLKDLY19_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE19_LSB 8
+#define CSR_ACSMDDRWE19_MASK BIT(8)
+#define CSR_ACSMDDRCAS19_LSB 9
+#define CSR_ACSMDDRCAS19_MASK BIT(9)
+#define CSR_ACSMDDRRAS19_LSB 10
+#define CSR_ACSMDDRRAS19_MASK BIT(10)
+#define CSR_ACSMDDRCKESET19_LSB 11
+#define CSR_ACSMDDRCKESET19_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR19_LSB 12
+#define CSR_ACSMDDRCKECLR19_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD19_LSB 13
+#define CSR_ACSMSEQGATECMD19_MASK BIT(13)
+#define CSR_ACSMSEQTERM19_LSB 14
+#define CSR_ACSMSEQTERM19_MASK BIT(14)
+#define CSR_ACSMLP3CA319_LSB 15
+#define CSR_ACSMLP3CA319_MASK BIT(15)
+/* CSR_ACSMSEQ0X20 */
+#define CSR_ACSMSEQ0X20_LSB 0
+#define CSR_ACSMSEQ0X20_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY20_LSB 0
+#define CSR_ACSMMCLKDLY20_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE20_LSB 8
+#define CSR_ACSMDDRWE20_MASK BIT(8)
+#define CSR_ACSMDDRCAS20_LSB 9
+#define CSR_ACSMDDRCAS20_MASK BIT(9)
+#define CSR_ACSMDDRRAS20_LSB 10
+#define CSR_ACSMDDRRAS20_MASK BIT(10)
+#define CSR_ACSMDDRCKESET20_LSB 11
+#define CSR_ACSMDDRCKESET20_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR20_LSB 12
+#define CSR_ACSMDDRCKECLR20_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD20_LSB 13
+#define CSR_ACSMSEQGATECMD20_MASK BIT(13)
+#define CSR_ACSMSEQTERM20_LSB 14
+#define CSR_ACSMSEQTERM20_MASK BIT(14)
+#define CSR_ACSMLP3CA320_LSB 15
+#define CSR_ACSMLP3CA320_MASK BIT(15)
+/* CSR_ACSMSEQ0X21 */
+#define CSR_ACSMSEQ0X21_LSB 0
+#define CSR_ACSMSEQ0X21_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY21_LSB 0
+#define CSR_ACSMMCLKDLY21_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE21_LSB 8
+#define CSR_ACSMDDRWE21_MASK BIT(8)
+#define CSR_ACSMDDRCAS21_LSB 9
+#define CSR_ACSMDDRCAS21_MASK BIT(9)
+#define CSR_ACSMDDRRAS21_LSB 10
+#define CSR_ACSMDDRRAS21_MASK BIT(10)
+#define CSR_ACSMDDRCKESET21_LSB 11
+#define CSR_ACSMDDRCKESET21_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR21_LSB 12
+#define CSR_ACSMDDRCKECLR21_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD21_LSB 13
+#define CSR_ACSMSEQGATECMD21_MASK BIT(13)
+#define CSR_ACSMSEQTERM21_LSB 14
+#define CSR_ACSMSEQTERM21_MASK BIT(14)
+#define CSR_ACSMLP3CA321_LSB 15
+#define CSR_ACSMLP3CA321_MASK BIT(15)
+/* CSR_ACSMSEQ0X22 */
+#define CSR_ACSMSEQ0X22_LSB 0
+#define CSR_ACSMSEQ0X22_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY22_LSB 0
+#define CSR_ACSMMCLKDLY22_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE22_LSB 8
+#define CSR_ACSMDDRWE22_MASK BIT(8)
+#define CSR_ACSMDDRCAS22_LSB 9
+#define CSR_ACSMDDRCAS22_MASK BIT(9)
+#define CSR_ACSMDDRRAS22_LSB 10
+#define CSR_ACSMDDRRAS22_MASK BIT(10)
+#define CSR_ACSMDDRCKESET22_LSB 11
+#define CSR_ACSMDDRCKESET22_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR22_LSB 12
+#define CSR_ACSMDDRCKECLR22_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD22_LSB 13
+#define CSR_ACSMSEQGATECMD22_MASK BIT(13)
+#define CSR_ACSMSEQTERM22_LSB 14
+#define CSR_ACSMSEQTERM22_MASK BIT(14)
+#define CSR_ACSMLP3CA322_LSB 15
+#define CSR_ACSMLP3CA322_MASK BIT(15)
+/* CSR_ACSMSEQ0X23 */
+#define CSR_ACSMSEQ0X23_LSB 0
+#define CSR_ACSMSEQ0X23_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY23_LSB 0
+#define CSR_ACSMMCLKDLY23_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE23_LSB 8
+#define CSR_ACSMDDRWE23_MASK BIT(8)
+#define CSR_ACSMDDRCAS23_LSB 9
+#define CSR_ACSMDDRCAS23_MASK BIT(9)
+#define CSR_ACSMDDRRAS23_LSB 10
+#define CSR_ACSMDDRRAS23_MASK BIT(10)
+#define CSR_ACSMDDRCKESET23_LSB 11
+#define CSR_ACSMDDRCKESET23_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR23_LSB 12
+#define CSR_ACSMDDRCKECLR23_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD23_LSB 13
+#define CSR_ACSMSEQGATECMD23_MASK BIT(13)
+#define CSR_ACSMSEQTERM23_LSB 14
+#define CSR_ACSMSEQTERM23_MASK BIT(14)
+#define CSR_ACSMLP3CA323_LSB 15
+#define CSR_ACSMLP3CA323_MASK BIT(15)
+/* CSR_ACSMSEQ0X24 */
+#define CSR_ACSMSEQ0X24_LSB 0
+#define CSR_ACSMSEQ0X24_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY24_LSB 0
+#define CSR_ACSMMCLKDLY24_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE24_LSB 8
+#define CSR_ACSMDDRWE24_MASK BIT(8)
+#define CSR_ACSMDDRCAS24_LSB 9
+#define CSR_ACSMDDRCAS24_MASK BIT(9)
+#define CSR_ACSMDDRRAS24_LSB 10
+#define CSR_ACSMDDRRAS24_MASK BIT(10)
+#define CSR_ACSMDDRCKESET24_LSB 11
+#define CSR_ACSMDDRCKESET24_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR24_LSB 12
+#define CSR_ACSMDDRCKECLR24_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD24_LSB 13
+#define CSR_ACSMSEQGATECMD24_MASK BIT(13)
+#define CSR_ACSMSEQTERM24_LSB 14
+#define CSR_ACSMSEQTERM24_MASK BIT(14)
+#define CSR_ACSMLP3CA324_LSB 15
+#define CSR_ACSMLP3CA324_MASK BIT(15)
+/* CSR_ACSMSEQ0X25 */
+#define CSR_ACSMSEQ0X25_LSB 0
+#define CSR_ACSMSEQ0X25_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY25_LSB 0
+#define CSR_ACSMMCLKDLY25_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE25_LSB 8
+#define CSR_ACSMDDRWE25_MASK BIT(8)
+#define CSR_ACSMDDRCAS25_LSB 9
+#define CSR_ACSMDDRCAS25_MASK BIT(9)
+#define CSR_ACSMDDRRAS25_LSB 10
+#define CSR_ACSMDDRRAS25_MASK BIT(10)
+#define CSR_ACSMDDRCKESET25_LSB 11
+#define CSR_ACSMDDRCKESET25_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR25_LSB 12
+#define CSR_ACSMDDRCKECLR25_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD25_LSB 13
+#define CSR_ACSMSEQGATECMD25_MASK BIT(13)
+#define CSR_ACSMSEQTERM25_LSB 14
+#define CSR_ACSMSEQTERM25_MASK BIT(14)
+#define CSR_ACSMLP3CA325_LSB 15
+#define CSR_ACSMLP3CA325_MASK BIT(15)
+/* CSR_ACSMSEQ0X26 */
+#define CSR_ACSMSEQ0X26_LSB 0
+#define CSR_ACSMSEQ0X26_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY26_LSB 0
+#define CSR_ACSMMCLKDLY26_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE26_LSB 8
+#define CSR_ACSMDDRWE26_MASK BIT(8)
+#define CSR_ACSMDDRCAS26_LSB 9
+#define CSR_ACSMDDRCAS26_MASK BIT(9)
+#define CSR_ACSMDDRRAS26_LSB 10
+#define CSR_ACSMDDRRAS26_MASK BIT(10)
+#define CSR_ACSMDDRCKESET26_LSB 11
+#define CSR_ACSMDDRCKESET26_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR26_LSB 12
+#define CSR_ACSMDDRCKECLR26_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD26_LSB 13
+#define CSR_ACSMSEQGATECMD26_MASK BIT(13)
+#define CSR_ACSMSEQTERM26_LSB 14
+#define CSR_ACSMSEQTERM26_MASK BIT(14)
+#define CSR_ACSMLP3CA326_LSB 15
+#define CSR_ACSMLP3CA326_MASK BIT(15)
+/* CSR_ACSMSEQ0X27 */
+#define CSR_ACSMSEQ0X27_LSB 0
+#define CSR_ACSMSEQ0X27_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY27_LSB 0
+#define CSR_ACSMMCLKDLY27_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE27_LSB 8
+#define CSR_ACSMDDRWE27_MASK BIT(8)
+#define CSR_ACSMDDRCAS27_LSB 9
+#define CSR_ACSMDDRCAS27_MASK BIT(9)
+#define CSR_ACSMDDRRAS27_LSB 10
+#define CSR_ACSMDDRRAS27_MASK BIT(10)
+#define CSR_ACSMDDRCKESET27_LSB 11
+#define CSR_ACSMDDRCKESET27_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR27_LSB 12
+#define CSR_ACSMDDRCKECLR27_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD27_LSB 13
+#define CSR_ACSMSEQGATECMD27_MASK BIT(13)
+#define CSR_ACSMSEQTERM27_LSB 14
+#define CSR_ACSMSEQTERM27_MASK BIT(14)
+#define CSR_ACSMLP3CA327_LSB 15
+#define CSR_ACSMLP3CA327_MASK BIT(15)
+/* CSR_ACSMSEQ0X28 */
+#define CSR_ACSMSEQ0X28_LSB 0
+#define CSR_ACSMSEQ0X28_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY28_LSB 0
+#define CSR_ACSMMCLKDLY28_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE28_LSB 8
+#define CSR_ACSMDDRWE28_MASK BIT(8)
+#define CSR_ACSMDDRCAS28_LSB 9
+#define CSR_ACSMDDRCAS28_MASK BIT(9)
+#define CSR_ACSMDDRRAS28_LSB 10
+#define CSR_ACSMDDRRAS28_MASK BIT(10)
+#define CSR_ACSMDDRCKESET28_LSB 11
+#define CSR_ACSMDDRCKESET28_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR28_LSB 12
+#define CSR_ACSMDDRCKECLR28_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD28_LSB 13
+#define CSR_ACSMSEQGATECMD28_MASK BIT(13)
+#define CSR_ACSMSEQTERM28_LSB 14
+#define CSR_ACSMSEQTERM28_MASK BIT(14)
+#define CSR_ACSMLP3CA328_LSB 15
+#define CSR_ACSMLP3CA328_MASK BIT(15)
+/* CSR_ACSMSEQ0X29 */
+#define CSR_ACSMSEQ0X29_LSB 0
+#define CSR_ACSMSEQ0X29_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY29_LSB 0
+#define CSR_ACSMMCLKDLY29_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE29_LSB 8
+#define CSR_ACSMDDRWE29_MASK BIT(8)
+#define CSR_ACSMDDRCAS29_LSB 9
+#define CSR_ACSMDDRCAS29_MASK BIT(9)
+#define CSR_ACSMDDRRAS29_LSB 10
+#define CSR_ACSMDDRRAS29_MASK BIT(10)
+#define CSR_ACSMDDRCKESET29_LSB 11
+#define CSR_ACSMDDRCKESET29_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR29_LSB 12
+#define CSR_ACSMDDRCKECLR29_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD29_LSB 13
+#define CSR_ACSMSEQGATECMD29_MASK BIT(13)
+#define CSR_ACSMSEQTERM29_LSB 14
+#define CSR_ACSMSEQTERM29_MASK BIT(14)
+#define CSR_ACSMLP3CA329_LSB 15
+#define CSR_ACSMLP3CA329_MASK BIT(15)
+/* CSR_ACSMSEQ0X30 */
+#define CSR_ACSMSEQ0X30_LSB 0
+#define CSR_ACSMSEQ0X30_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY30_LSB 0
+#define CSR_ACSMMCLKDLY30_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE30_LSB 8
+#define CSR_ACSMDDRWE30_MASK BIT(8)
+#define CSR_ACSMDDRCAS30_LSB 9
+#define CSR_ACSMDDRCAS30_MASK BIT(9)
+#define CSR_ACSMDDRRAS30_LSB 10
+#define CSR_ACSMDDRRAS30_MASK BIT(10)
+#define CSR_ACSMDDRCKESET30_LSB 11
+#define CSR_ACSMDDRCKESET30_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR30_LSB 12
+#define CSR_ACSMDDRCKECLR30_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD30_LSB 13
+#define CSR_ACSMSEQGATECMD30_MASK BIT(13)
+#define CSR_ACSMSEQTERM30_LSB 14
+#define CSR_ACSMSEQTERM30_MASK BIT(14)
+#define CSR_ACSMLP3CA330_LSB 15
+#define CSR_ACSMLP3CA330_MASK BIT(15)
+/* CSR_ACSMSEQ0X31 */
+#define CSR_ACSMSEQ0X31_LSB 0
+#define CSR_ACSMSEQ0X31_MASK GENMASK_32(15, 0)
+#define CSR_ACSMMCLKDLY31_LSB 0
+#define CSR_ACSMMCLKDLY31_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDDRWE31_LSB 8
+#define CSR_ACSMDDRWE31_MASK BIT(8)
+#define CSR_ACSMDDRCAS31_LSB 9
+#define CSR_ACSMDDRCAS31_MASK BIT(9)
+#define CSR_ACSMDDRRAS31_LSB 10
+#define CSR_ACSMDDRRAS31_MASK BIT(10)
+#define CSR_ACSMDDRCKESET31_LSB 11
+#define CSR_ACSMDDRCKESET31_MASK BIT(11)
+#define CSR_ACSMDDRCKECLR31_LSB 12
+#define CSR_ACSMDDRCKECLR31_MASK BIT(12)
+#define CSR_ACSMSEQGATECMD31_LSB 13
+#define CSR_ACSMSEQGATECMD31_MASK BIT(13)
+#define CSR_ACSMSEQTERM31_LSB 14
+#define CSR_ACSMSEQTERM31_MASK BIT(14)
+#define CSR_ACSMLP3CA331_LSB 15
+#define CSR_ACSMLP3CA331_MASK BIT(15)
+/* CSR_ACSMSEQ1X0 */
+#define CSR_ACSMSEQ1X0_LSB 0
+#define CSR_ACSMSEQ1X0_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS0_LSB 0
+#define CSR_ACSMDDRCS0_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN0_LSB 8
+#define CSR_ACSMSAVEGEN0_MASK BIT(8)
+#define CSR_ACSMLOADCHK0_LSB 9
+#define CSR_ACSMLOADCHK0_MASK BIT(9)
+#define CSR_ACSMNORXENB0_LSB 10
+#define CSR_ACSMNORXENB0_MASK BIT(10)
+#define CSR_ACSMNORXVAL0_LSB 11
+#define CSR_ACSMNORXVAL0_MASK BIT(11)
+#define CSR_ACSMDDRBNK0_LSB 12
+#define CSR_ACSMDDRBNK0_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X1 */
+#define CSR_ACSMSEQ1X1_LSB 0
+#define CSR_ACSMSEQ1X1_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS1_LSB 0
+#define CSR_ACSMDDRCS1_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN1_LSB 8
+#define CSR_ACSMSAVEGEN1_MASK BIT(8)
+#define CSR_ACSMLOADCHK1_LSB 9
+#define CSR_ACSMLOADCHK1_MASK BIT(9)
+#define CSR_ACSMNORXENB1_LSB 10
+#define CSR_ACSMNORXENB1_MASK BIT(10)
+#define CSR_ACSMNORXVAL1_LSB 11
+#define CSR_ACSMNORXVAL1_MASK BIT(11)
+#define CSR_ACSMDDRBNK1_LSB 12
+#define CSR_ACSMDDRBNK1_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X2 */
+#define CSR_ACSMSEQ1X2_LSB 0
+#define CSR_ACSMSEQ1X2_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS2_LSB 0
+#define CSR_ACSMDDRCS2_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN2_LSB 8
+#define CSR_ACSMSAVEGEN2_MASK BIT(8)
+#define CSR_ACSMLOADCHK2_LSB 9
+#define CSR_ACSMLOADCHK2_MASK BIT(9)
+#define CSR_ACSMNORXENB2_LSB 10
+#define CSR_ACSMNORXENB2_MASK BIT(10)
+#define CSR_ACSMNORXVAL2_LSB 11
+#define CSR_ACSMNORXVAL2_MASK BIT(11)
+#define CSR_ACSMDDRBNK2_LSB 12
+#define CSR_ACSMDDRBNK2_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X3 */
+#define CSR_ACSMSEQ1X3_LSB 0
+#define CSR_ACSMSEQ1X3_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS3_LSB 0
+#define CSR_ACSMDDRCS3_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN3_LSB 8
+#define CSR_ACSMSAVEGEN3_MASK BIT(8)
+#define CSR_ACSMLOADCHK3_LSB 9
+#define CSR_ACSMLOADCHK3_MASK BIT(9)
+#define CSR_ACSMNORXENB3_LSB 10
+#define CSR_ACSMNORXENB3_MASK BIT(10)
+#define CSR_ACSMNORXVAL3_LSB 11
+#define CSR_ACSMNORXVAL3_MASK BIT(11)
+#define CSR_ACSMDDRBNK3_LSB 12
+#define CSR_ACSMDDRBNK3_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X4 */
+#define CSR_ACSMSEQ1X4_LSB 0
+#define CSR_ACSMSEQ1X4_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS4_LSB 0
+#define CSR_ACSMDDRCS4_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN4_LSB 8
+#define CSR_ACSMSAVEGEN4_MASK BIT(8)
+#define CSR_ACSMLOADCHK4_LSB 9
+#define CSR_ACSMLOADCHK4_MASK BIT(9)
+#define CSR_ACSMNORXENB4_LSB 10
+#define CSR_ACSMNORXENB4_MASK BIT(10)
+#define CSR_ACSMNORXVAL4_LSB 11
+#define CSR_ACSMNORXVAL4_MASK BIT(11)
+#define CSR_ACSMDDRBNK4_LSB 12
+#define CSR_ACSMDDRBNK4_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X5 */
+#define CSR_ACSMSEQ1X5_LSB 0
+#define CSR_ACSMSEQ1X5_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS5_LSB 0
+#define CSR_ACSMDDRCS5_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN5_LSB 8
+#define CSR_ACSMSAVEGEN5_MASK BIT(8)
+#define CSR_ACSMLOADCHK5_LSB 9
+#define CSR_ACSMLOADCHK5_MASK BIT(9)
+#define CSR_ACSMNORXENB5_LSB 10
+#define CSR_ACSMNORXENB5_MASK BIT(10)
+#define CSR_ACSMNORXVAL5_LSB 11
+#define CSR_ACSMNORXVAL5_MASK BIT(11)
+#define CSR_ACSMDDRBNK5_LSB 12
+#define CSR_ACSMDDRBNK5_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X6 */
+#define CSR_ACSMSEQ1X6_LSB 0
+#define CSR_ACSMSEQ1X6_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS6_LSB 0
+#define CSR_ACSMDDRCS6_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN6_LSB 8
+#define CSR_ACSMSAVEGEN6_MASK BIT(8)
+#define CSR_ACSMLOADCHK6_LSB 9
+#define CSR_ACSMLOADCHK6_MASK BIT(9)
+#define CSR_ACSMNORXENB6_LSB 10
+#define CSR_ACSMNORXENB6_MASK BIT(10)
+#define CSR_ACSMNORXVAL6_LSB 11
+#define CSR_ACSMNORXVAL6_MASK BIT(11)
+#define CSR_ACSMDDRBNK6_LSB 12
+#define CSR_ACSMDDRBNK6_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X7 */
+#define CSR_ACSMSEQ1X7_LSB 0
+#define CSR_ACSMSEQ1X7_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS7_LSB 0
+#define CSR_ACSMDDRCS7_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN7_LSB 8
+#define CSR_ACSMSAVEGEN7_MASK BIT(8)
+#define CSR_ACSMLOADCHK7_LSB 9
+#define CSR_ACSMLOADCHK7_MASK BIT(9)
+#define CSR_ACSMNORXENB7_LSB 10
+#define CSR_ACSMNORXENB7_MASK BIT(10)
+#define CSR_ACSMNORXVAL7_LSB 11
+#define CSR_ACSMNORXVAL7_MASK BIT(11)
+#define CSR_ACSMDDRBNK7_LSB 12
+#define CSR_ACSMDDRBNK7_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X8 */
+#define CSR_ACSMSEQ1X8_LSB 0
+#define CSR_ACSMSEQ1X8_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS8_LSB 0
+#define CSR_ACSMDDRCS8_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN8_LSB 8
+#define CSR_ACSMSAVEGEN8_MASK BIT(8)
+#define CSR_ACSMLOADCHK8_LSB 9
+#define CSR_ACSMLOADCHK8_MASK BIT(9)
+#define CSR_ACSMNORXENB8_LSB 10
+#define CSR_ACSMNORXENB8_MASK BIT(10)
+#define CSR_ACSMNORXVAL8_LSB 11
+#define CSR_ACSMNORXVAL8_MASK BIT(11)
+#define CSR_ACSMDDRBNK8_LSB 12
+#define CSR_ACSMDDRBNK8_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X9 */
+#define CSR_ACSMSEQ1X9_LSB 0
+#define CSR_ACSMSEQ1X9_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS9_LSB 0
+#define CSR_ACSMDDRCS9_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN9_LSB 8
+#define CSR_ACSMSAVEGEN9_MASK BIT(8)
+#define CSR_ACSMLOADCHK9_LSB 9
+#define CSR_ACSMLOADCHK9_MASK BIT(9)
+#define CSR_ACSMNORXENB9_LSB 10
+#define CSR_ACSMNORXENB9_MASK BIT(10)
+#define CSR_ACSMNORXVAL9_LSB 11
+#define CSR_ACSMNORXVAL9_MASK BIT(11)
+#define CSR_ACSMDDRBNK9_LSB 12
+#define CSR_ACSMDDRBNK9_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X10 */
+#define CSR_ACSMSEQ1X10_LSB 0
+#define CSR_ACSMSEQ1X10_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS10_LSB 0
+#define CSR_ACSMDDRCS10_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN10_LSB 8
+#define CSR_ACSMSAVEGEN10_MASK BIT(8)
+#define CSR_ACSMLOADCHK10_LSB 9
+#define CSR_ACSMLOADCHK10_MASK BIT(9)
+#define CSR_ACSMNORXENB10_LSB 10
+#define CSR_ACSMNORXENB10_MASK BIT(10)
+#define CSR_ACSMNORXVAL10_LSB 11
+#define CSR_ACSMNORXVAL10_MASK BIT(11)
+#define CSR_ACSMDDRBNK10_LSB 12
+#define CSR_ACSMDDRBNK10_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X11 */
+#define CSR_ACSMSEQ1X11_LSB 0
+#define CSR_ACSMSEQ1X11_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS11_LSB 0
+#define CSR_ACSMDDRCS11_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN11_LSB 8
+#define CSR_ACSMSAVEGEN11_MASK BIT(8)
+#define CSR_ACSMLOADCHK11_LSB 9
+#define CSR_ACSMLOADCHK11_MASK BIT(9)
+#define CSR_ACSMNORXENB11_LSB 10
+#define CSR_ACSMNORXENB11_MASK BIT(10)
+#define CSR_ACSMNORXVAL11_LSB 11
+#define CSR_ACSMNORXVAL11_MASK BIT(11)
+#define CSR_ACSMDDRBNK11_LSB 12
+#define CSR_ACSMDDRBNK11_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X12 */
+#define CSR_ACSMSEQ1X12_LSB 0
+#define CSR_ACSMSEQ1X12_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS12_LSB 0
+#define CSR_ACSMDDRCS12_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN12_LSB 8
+#define CSR_ACSMSAVEGEN12_MASK BIT(8)
+#define CSR_ACSMLOADCHK12_LSB 9
+#define CSR_ACSMLOADCHK12_MASK BIT(9)
+#define CSR_ACSMNORXENB12_LSB 10
+#define CSR_ACSMNORXENB12_MASK BIT(10)
+#define CSR_ACSMNORXVAL12_LSB 11
+#define CSR_ACSMNORXVAL12_MASK BIT(11)
+#define CSR_ACSMDDRBNK12_LSB 12
+#define CSR_ACSMDDRBNK12_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X13 */
+#define CSR_ACSMSEQ1X13_LSB 0
+#define CSR_ACSMSEQ1X13_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS13_LSB 0
+#define CSR_ACSMDDRCS13_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN13_LSB 8
+#define CSR_ACSMSAVEGEN13_MASK BIT(8)
+#define CSR_ACSMLOADCHK13_LSB 9
+#define CSR_ACSMLOADCHK13_MASK BIT(9)
+#define CSR_ACSMNORXENB13_LSB 10
+#define CSR_ACSMNORXENB13_MASK BIT(10)
+#define CSR_ACSMNORXVAL13_LSB 11
+#define CSR_ACSMNORXVAL13_MASK BIT(11)
+#define CSR_ACSMDDRBNK13_LSB 12
+#define CSR_ACSMDDRBNK13_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X14 */
+#define CSR_ACSMSEQ1X14_LSB 0
+#define CSR_ACSMSEQ1X14_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS14_LSB 0
+#define CSR_ACSMDDRCS14_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN14_LSB 8
+#define CSR_ACSMSAVEGEN14_MASK BIT(8)
+#define CSR_ACSMLOADCHK14_LSB 9
+#define CSR_ACSMLOADCHK14_MASK BIT(9)
+#define CSR_ACSMNORXENB14_LSB 10
+#define CSR_ACSMNORXENB14_MASK BIT(10)
+#define CSR_ACSMNORXVAL14_LSB 11
+#define CSR_ACSMNORXVAL14_MASK BIT(11)
+#define CSR_ACSMDDRBNK14_LSB 12
+#define CSR_ACSMDDRBNK14_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X15 */
+#define CSR_ACSMSEQ1X15_LSB 0
+#define CSR_ACSMSEQ1X15_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS15_LSB 0
+#define CSR_ACSMDDRCS15_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN15_LSB 8
+#define CSR_ACSMSAVEGEN15_MASK BIT(8)
+#define CSR_ACSMLOADCHK15_LSB 9
+#define CSR_ACSMLOADCHK15_MASK BIT(9)
+#define CSR_ACSMNORXENB15_LSB 10
+#define CSR_ACSMNORXENB15_MASK BIT(10)
+#define CSR_ACSMNORXVAL15_LSB 11
+#define CSR_ACSMNORXVAL15_MASK BIT(11)
+#define CSR_ACSMDDRBNK15_LSB 12
+#define CSR_ACSMDDRBNK15_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X16 */
+#define CSR_ACSMSEQ1X16_LSB 0
+#define CSR_ACSMSEQ1X16_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS16_LSB 0
+#define CSR_ACSMDDRCS16_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN16_LSB 8
+#define CSR_ACSMSAVEGEN16_MASK BIT(8)
+#define CSR_ACSMLOADCHK16_LSB 9
+#define CSR_ACSMLOADCHK16_MASK BIT(9)
+#define CSR_ACSMNORXENB16_LSB 10
+#define CSR_ACSMNORXENB16_MASK BIT(10)
+#define CSR_ACSMNORXVAL16_LSB 11
+#define CSR_ACSMNORXVAL16_MASK BIT(11)
+#define CSR_ACSMDDRBNK16_LSB 12
+#define CSR_ACSMDDRBNK16_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X17 */
+#define CSR_ACSMSEQ1X17_LSB 0
+#define CSR_ACSMSEQ1X17_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS17_LSB 0
+#define CSR_ACSMDDRCS17_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN17_LSB 8
+#define CSR_ACSMSAVEGEN17_MASK BIT(8)
+#define CSR_ACSMLOADCHK17_LSB 9
+#define CSR_ACSMLOADCHK17_MASK BIT(9)
+#define CSR_ACSMNORXENB17_LSB 10
+#define CSR_ACSMNORXENB17_MASK BIT(10)
+#define CSR_ACSMNORXVAL17_LSB 11
+#define CSR_ACSMNORXVAL17_MASK BIT(11)
+#define CSR_ACSMDDRBNK17_LSB 12
+#define CSR_ACSMDDRBNK17_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X18 */
+#define CSR_ACSMSEQ1X18_LSB 0
+#define CSR_ACSMSEQ1X18_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS18_LSB 0
+#define CSR_ACSMDDRCS18_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN18_LSB 8
+#define CSR_ACSMSAVEGEN18_MASK BIT(8)
+#define CSR_ACSMLOADCHK18_LSB 9
+#define CSR_ACSMLOADCHK18_MASK BIT(9)
+#define CSR_ACSMNORXENB18_LSB 10
+#define CSR_ACSMNORXENB18_MASK BIT(10)
+#define CSR_ACSMNORXVAL18_LSB 11
+#define CSR_ACSMNORXVAL18_MASK BIT(11)
+#define CSR_ACSMDDRBNK18_LSB 12
+#define CSR_ACSMDDRBNK18_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X19 */
+#define CSR_ACSMSEQ1X19_LSB 0
+#define CSR_ACSMSEQ1X19_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS19_LSB 0
+#define CSR_ACSMDDRCS19_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN19_LSB 8
+#define CSR_ACSMSAVEGEN19_MASK BIT(8)
+#define CSR_ACSMLOADCHK19_LSB 9
+#define CSR_ACSMLOADCHK19_MASK BIT(9)
+#define CSR_ACSMNORXENB19_LSB 10
+#define CSR_ACSMNORXENB19_MASK BIT(10)
+#define CSR_ACSMNORXVAL19_LSB 11
+#define CSR_ACSMNORXVAL19_MASK BIT(11)
+#define CSR_ACSMDDRBNK19_LSB 12
+#define CSR_ACSMDDRBNK19_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X20 */
+#define CSR_ACSMSEQ1X20_LSB 0
+#define CSR_ACSMSEQ1X20_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS20_LSB 0
+#define CSR_ACSMDDRCS20_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN20_LSB 8
+#define CSR_ACSMSAVEGEN20_MASK BIT(8)
+#define CSR_ACSMLOADCHK20_LSB 9
+#define CSR_ACSMLOADCHK20_MASK BIT(9)
+#define CSR_ACSMNORXENB20_LSB 10
+#define CSR_ACSMNORXENB20_MASK BIT(10)
+#define CSR_ACSMNORXVAL20_LSB 11
+#define CSR_ACSMNORXVAL20_MASK BIT(11)
+#define CSR_ACSMDDRBNK20_LSB 12
+#define CSR_ACSMDDRBNK20_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X21 */
+#define CSR_ACSMSEQ1X21_LSB 0
+#define CSR_ACSMSEQ1X21_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS21_LSB 0
+#define CSR_ACSMDDRCS21_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN21_LSB 8
+#define CSR_ACSMSAVEGEN21_MASK BIT(8)
+#define CSR_ACSMLOADCHK21_LSB 9
+#define CSR_ACSMLOADCHK21_MASK BIT(9)
+#define CSR_ACSMNORXENB21_LSB 10
+#define CSR_ACSMNORXENB21_MASK BIT(10)
+#define CSR_ACSMNORXVAL21_LSB 11
+#define CSR_ACSMNORXVAL21_MASK BIT(11)
+#define CSR_ACSMDDRBNK21_LSB 12
+#define CSR_ACSMDDRBNK21_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X22 */
+#define CSR_ACSMSEQ1X22_LSB 0
+#define CSR_ACSMSEQ1X22_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS22_LSB 0
+#define CSR_ACSMDDRCS22_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN22_LSB 8
+#define CSR_ACSMSAVEGEN22_MASK BIT(8)
+#define CSR_ACSMLOADCHK22_LSB 9
+#define CSR_ACSMLOADCHK22_MASK BIT(9)
+#define CSR_ACSMNORXENB22_LSB 10
+#define CSR_ACSMNORXENB22_MASK BIT(10)
+#define CSR_ACSMNORXVAL22_LSB 11
+#define CSR_ACSMNORXVAL22_MASK BIT(11)
+#define CSR_ACSMDDRBNK22_LSB 12
+#define CSR_ACSMDDRBNK22_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X23 */
+#define CSR_ACSMSEQ1X23_LSB 0
+#define CSR_ACSMSEQ1X23_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS23_LSB 0
+#define CSR_ACSMDDRCS23_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN23_LSB 8
+#define CSR_ACSMSAVEGEN23_MASK BIT(8)
+#define CSR_ACSMLOADCHK23_LSB 9
+#define CSR_ACSMLOADCHK23_MASK BIT(9)
+#define CSR_ACSMNORXENB23_LSB 10
+#define CSR_ACSMNORXENB23_MASK BIT(10)
+#define CSR_ACSMNORXVAL23_LSB 11
+#define CSR_ACSMNORXVAL23_MASK BIT(11)
+#define CSR_ACSMDDRBNK23_LSB 12
+#define CSR_ACSMDDRBNK23_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X24 */
+#define CSR_ACSMSEQ1X24_LSB 0
+#define CSR_ACSMSEQ1X24_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS24_LSB 0
+#define CSR_ACSMDDRCS24_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN24_LSB 8
+#define CSR_ACSMSAVEGEN24_MASK BIT(8)
+#define CSR_ACSMLOADCHK24_LSB 9
+#define CSR_ACSMLOADCHK24_MASK BIT(9)
+#define CSR_ACSMNORXENB24_LSB 10
+#define CSR_ACSMNORXENB24_MASK BIT(10)
+#define CSR_ACSMNORXVAL24_LSB 11
+#define CSR_ACSMNORXVAL24_MASK BIT(11)
+#define CSR_ACSMDDRBNK24_LSB 12
+#define CSR_ACSMDDRBNK24_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X25 */
+#define CSR_ACSMSEQ1X25_LSB 0
+#define CSR_ACSMSEQ1X25_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS25_LSB 0
+#define CSR_ACSMDDRCS25_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN25_LSB 8
+#define CSR_ACSMSAVEGEN25_MASK BIT(8)
+#define CSR_ACSMLOADCHK25_LSB 9
+#define CSR_ACSMLOADCHK25_MASK BIT(9)
+#define CSR_ACSMNORXENB25_LSB 10
+#define CSR_ACSMNORXENB25_MASK BIT(10)
+#define CSR_ACSMNORXVAL25_LSB 11
+#define CSR_ACSMNORXVAL25_MASK BIT(11)
+#define CSR_ACSMDDRBNK25_LSB 12
+#define CSR_ACSMDDRBNK25_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X26 */
+#define CSR_ACSMSEQ1X26_LSB 0
+#define CSR_ACSMSEQ1X26_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS26_LSB 0
+#define CSR_ACSMDDRCS26_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN26_LSB 8
+#define CSR_ACSMSAVEGEN26_MASK BIT(8)
+#define CSR_ACSMLOADCHK26_LSB 9
+#define CSR_ACSMLOADCHK26_MASK BIT(9)
+#define CSR_ACSMNORXENB26_LSB 10
+#define CSR_ACSMNORXENB26_MASK BIT(10)
+#define CSR_ACSMNORXVAL26_LSB 11
+#define CSR_ACSMNORXVAL26_MASK BIT(11)
+#define CSR_ACSMDDRBNK26_LSB 12
+#define CSR_ACSMDDRBNK26_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X27 */
+#define CSR_ACSMSEQ1X27_LSB 0
+#define CSR_ACSMSEQ1X27_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS27_LSB 0
+#define CSR_ACSMDDRCS27_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN27_LSB 8
+#define CSR_ACSMSAVEGEN27_MASK BIT(8)
+#define CSR_ACSMLOADCHK27_LSB 9
+#define CSR_ACSMLOADCHK27_MASK BIT(9)
+#define CSR_ACSMNORXENB27_LSB 10
+#define CSR_ACSMNORXENB27_MASK BIT(10)
+#define CSR_ACSMNORXVAL27_LSB 11
+#define CSR_ACSMNORXVAL27_MASK BIT(11)
+#define CSR_ACSMDDRBNK27_LSB 12
+#define CSR_ACSMDDRBNK27_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X28 */
+#define CSR_ACSMSEQ1X28_LSB 0
+#define CSR_ACSMSEQ1X28_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS28_LSB 0
+#define CSR_ACSMDDRCS28_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN28_LSB 8
+#define CSR_ACSMSAVEGEN28_MASK BIT(8)
+#define CSR_ACSMLOADCHK28_LSB 9
+#define CSR_ACSMLOADCHK28_MASK BIT(9)
+#define CSR_ACSMNORXENB28_LSB 10
+#define CSR_ACSMNORXENB28_MASK BIT(10)
+#define CSR_ACSMNORXVAL28_LSB 11
+#define CSR_ACSMNORXVAL28_MASK BIT(11)
+#define CSR_ACSMDDRBNK28_LSB 12
+#define CSR_ACSMDDRBNK28_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X29 */
+#define CSR_ACSMSEQ1X29_LSB 0
+#define CSR_ACSMSEQ1X29_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS29_LSB 0
+#define CSR_ACSMDDRCS29_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN29_LSB 8
+#define CSR_ACSMSAVEGEN29_MASK BIT(8)
+#define CSR_ACSMLOADCHK29_LSB 9
+#define CSR_ACSMLOADCHK29_MASK BIT(9)
+#define CSR_ACSMNORXENB29_LSB 10
+#define CSR_ACSMNORXENB29_MASK BIT(10)
+#define CSR_ACSMNORXVAL29_LSB 11
+#define CSR_ACSMNORXVAL29_MASK BIT(11)
+#define CSR_ACSMDDRBNK29_LSB 12
+#define CSR_ACSMDDRBNK29_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X30 */
+#define CSR_ACSMSEQ1X30_LSB 0
+#define CSR_ACSMSEQ1X30_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS30_LSB 0
+#define CSR_ACSMDDRCS30_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN30_LSB 8
+#define CSR_ACSMSAVEGEN30_MASK BIT(8)
+#define CSR_ACSMLOADCHK30_LSB 9
+#define CSR_ACSMLOADCHK30_MASK BIT(9)
+#define CSR_ACSMNORXENB30_LSB 10
+#define CSR_ACSMNORXENB30_MASK BIT(10)
+#define CSR_ACSMNORXVAL30_LSB 11
+#define CSR_ACSMNORXVAL30_MASK BIT(11)
+#define CSR_ACSMDDRBNK30_LSB 12
+#define CSR_ACSMDDRBNK30_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ1X31 */
+#define CSR_ACSMSEQ1X31_LSB 0
+#define CSR_ACSMSEQ1X31_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRCS31_LSB 0
+#define CSR_ACSMDDRCS31_MASK GENMASK_32(7, 0)
+#define CSR_ACSMSAVEGEN31_LSB 8
+#define CSR_ACSMSAVEGEN31_MASK BIT(8)
+#define CSR_ACSMLOADCHK31_LSB 9
+#define CSR_ACSMLOADCHK31_MASK BIT(9)
+#define CSR_ACSMNORXENB31_LSB 10
+#define CSR_ACSMNORXENB31_MASK BIT(10)
+#define CSR_ACSMNORXVAL31_LSB 11
+#define CSR_ACSMNORXVAL31_MASK BIT(11)
+#define CSR_ACSMDDRBNK31_LSB 12
+#define CSR_ACSMDDRBNK31_MASK GENMASK_32(15, 12)
+/* CSR_ACSMSEQ2X0 */
+#define CSR_ACSMSEQ2X0_LSB 0
+#define CSR_ACSMSEQ2X0_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X0_LSB 0
+#define CSR_ACSMDDRADRX15X0X0_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X1 */
+#define CSR_ACSMSEQ2X1_LSB 0
+#define CSR_ACSMSEQ2X1_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X1_LSB 0
+#define CSR_ACSMDDRADRX15X0X1_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X2 */
+#define CSR_ACSMSEQ2X2_LSB 0
+#define CSR_ACSMSEQ2X2_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X2_LSB 0
+#define CSR_ACSMDDRADRX15X0X2_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X3 */
+#define CSR_ACSMSEQ2X3_LSB 0
+#define CSR_ACSMSEQ2X3_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X3_LSB 0
+#define CSR_ACSMDDRADRX15X0X3_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X4 */
+#define CSR_ACSMSEQ2X4_LSB 0
+#define CSR_ACSMSEQ2X4_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X4_LSB 0
+#define CSR_ACSMDDRADRX15X0X4_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X5 */
+#define CSR_ACSMSEQ2X5_LSB 0
+#define CSR_ACSMSEQ2X5_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X5_LSB 0
+#define CSR_ACSMDDRADRX15X0X5_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X6 */
+#define CSR_ACSMSEQ2X6_LSB 0
+#define CSR_ACSMSEQ2X6_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X6_LSB 0
+#define CSR_ACSMDDRADRX15X0X6_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X7 */
+#define CSR_ACSMSEQ2X7_LSB 0
+#define CSR_ACSMSEQ2X7_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X7_LSB 0
+#define CSR_ACSMDDRADRX15X0X7_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X8 */
+#define CSR_ACSMSEQ2X8_LSB 0
+#define CSR_ACSMSEQ2X8_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X8_LSB 0
+#define CSR_ACSMDDRADRX15X0X8_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X9 */
+#define CSR_ACSMSEQ2X9_LSB 0
+#define CSR_ACSMSEQ2X9_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X9_LSB 0
+#define CSR_ACSMDDRADRX15X0X9_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X10 */
+#define CSR_ACSMSEQ2X10_LSB 0
+#define CSR_ACSMSEQ2X10_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X10_LSB 0
+#define CSR_ACSMDDRADRX15X0X10_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X11 */
+#define CSR_ACSMSEQ2X11_LSB 0
+#define CSR_ACSMSEQ2X11_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X11_LSB 0
+#define CSR_ACSMDDRADRX15X0X11_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X12 */
+#define CSR_ACSMSEQ2X12_LSB 0
+#define CSR_ACSMSEQ2X12_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X12_LSB 0
+#define CSR_ACSMDDRADRX15X0X12_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X13 */
+#define CSR_ACSMSEQ2X13_LSB 0
+#define CSR_ACSMSEQ2X13_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X13_LSB 0
+#define CSR_ACSMDDRADRX15X0X13_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X14 */
+#define CSR_ACSMSEQ2X14_LSB 0
+#define CSR_ACSMSEQ2X14_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X14_LSB 0
+#define CSR_ACSMDDRADRX15X0X14_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X15 */
+#define CSR_ACSMSEQ2X15_LSB 0
+#define CSR_ACSMSEQ2X15_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X15_LSB 0
+#define CSR_ACSMDDRADRX15X0X15_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X16 */
+#define CSR_ACSMSEQ2X16_LSB 0
+#define CSR_ACSMSEQ2X16_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X16_LSB 0
+#define CSR_ACSMDDRADRX15X0X16_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X17 */
+#define CSR_ACSMSEQ2X17_LSB 0
+#define CSR_ACSMSEQ2X17_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X17_LSB 0
+#define CSR_ACSMDDRADRX15X0X17_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X18 */
+#define CSR_ACSMSEQ2X18_LSB 0
+#define CSR_ACSMSEQ2X18_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X18_LSB 0
+#define CSR_ACSMDDRADRX15X0X18_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X19 */
+#define CSR_ACSMSEQ2X19_LSB 0
+#define CSR_ACSMSEQ2X19_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X19_LSB 0
+#define CSR_ACSMDDRADRX15X0X19_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X20 */
+#define CSR_ACSMSEQ2X20_LSB 0
+#define CSR_ACSMSEQ2X20_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X20_LSB 0
+#define CSR_ACSMDDRADRX15X0X20_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X21 */
+#define CSR_ACSMSEQ2X21_LSB 0
+#define CSR_ACSMSEQ2X21_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X21_LSB 0
+#define CSR_ACSMDDRADRX15X0X21_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X22 */
+#define CSR_ACSMSEQ2X22_LSB 0
+#define CSR_ACSMSEQ2X22_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X22_LSB 0
+#define CSR_ACSMDDRADRX15X0X22_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X23 */
+#define CSR_ACSMSEQ2X23_LSB 0
+#define CSR_ACSMSEQ2X23_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X23_LSB 0
+#define CSR_ACSMDDRADRX15X0X23_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X24 */
+#define CSR_ACSMSEQ2X24_LSB 0
+#define CSR_ACSMSEQ2X24_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X24_LSB 0
+#define CSR_ACSMDDRADRX15X0X24_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X25 */
+#define CSR_ACSMSEQ2X25_LSB 0
+#define CSR_ACSMSEQ2X25_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X25_LSB 0
+#define CSR_ACSMDDRADRX15X0X25_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X26 */
+#define CSR_ACSMSEQ2X26_LSB 0
+#define CSR_ACSMSEQ2X26_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X26_LSB 0
+#define CSR_ACSMDDRADRX15X0X26_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X27 */
+#define CSR_ACSMSEQ2X27_LSB 0
+#define CSR_ACSMSEQ2X27_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X27_LSB 0
+#define CSR_ACSMDDRADRX15X0X27_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X28 */
+#define CSR_ACSMSEQ2X28_LSB 0
+#define CSR_ACSMSEQ2X28_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X28_LSB 0
+#define CSR_ACSMDDRADRX15X0X28_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X29 */
+#define CSR_ACSMSEQ2X29_LSB 0
+#define CSR_ACSMSEQ2X29_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X29_LSB 0
+#define CSR_ACSMDDRADRX15X0X29_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X30 */
+#define CSR_ACSMSEQ2X30_LSB 0
+#define CSR_ACSMSEQ2X30_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X30_LSB 0
+#define CSR_ACSMDDRADRX15X0X30_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ2X31 */
+#define CSR_ACSMSEQ2X31_LSB 0
+#define CSR_ACSMSEQ2X31_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRX15X0X31_LSB 0
+#define CSR_ACSMDDRADRX15X0X31_MASK GENMASK_32(15, 0)
+/* CSR_ACSMSEQ3X0 */
+#define CSR_ACSMSEQ3X0_LSB 0
+#define CSR_ACSMSEQ3X0_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT0_LSB 0
+#define CSR_ACSMCMDREPCNT0_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV0_LSB 8
+#define CSR_ACSMADRADV0_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV0_LSB 10
+#define CSR_ACSMBNKADV0_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD0_LSB 12
+#define CSR_ACSMADRSELLOAD0_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD0_LSB 14
+#define CSR_ACSMBNKSELLOAD0_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE0_LSB 15
+#define CSR_ACSMLONGBUBBLE0_MASK BIT(15)
+/* CSR_ACSMSEQ3X1 */
+#define CSR_ACSMSEQ3X1_LSB 0
+#define CSR_ACSMSEQ3X1_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT1_LSB 0
+#define CSR_ACSMCMDREPCNT1_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV1_LSB 8
+#define CSR_ACSMADRADV1_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV1_LSB 10
+#define CSR_ACSMBNKADV1_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD1_LSB 12
+#define CSR_ACSMADRSELLOAD1_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD1_LSB 14
+#define CSR_ACSMBNKSELLOAD1_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE1_LSB 15
+#define CSR_ACSMLONGBUBBLE1_MASK BIT(15)
+/* CSR_ACSMSEQ3X2 */
+#define CSR_ACSMSEQ3X2_LSB 0
+#define CSR_ACSMSEQ3X2_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT2_LSB 0
+#define CSR_ACSMCMDREPCNT2_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV2_LSB 8
+#define CSR_ACSMADRADV2_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV2_LSB 10
+#define CSR_ACSMBNKADV2_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD2_LSB 12
+#define CSR_ACSMADRSELLOAD2_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD2_LSB 14
+#define CSR_ACSMBNKSELLOAD2_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE2_LSB 15
+#define CSR_ACSMLONGBUBBLE2_MASK BIT(15)
+/* CSR_ACSMSEQ3X3 */
+#define CSR_ACSMSEQ3X3_LSB 0
+#define CSR_ACSMSEQ3X3_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT3_LSB 0
+#define CSR_ACSMCMDREPCNT3_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV3_LSB 8
+#define CSR_ACSMADRADV3_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV3_LSB 10
+#define CSR_ACSMBNKADV3_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD3_LSB 12
+#define CSR_ACSMADRSELLOAD3_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD3_LSB 14
+#define CSR_ACSMBNKSELLOAD3_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE3_LSB 15
+#define CSR_ACSMLONGBUBBLE3_MASK BIT(15)
+/* CSR_ACSMSEQ3X4 */
+#define CSR_ACSMSEQ3X4_LSB 0
+#define CSR_ACSMSEQ3X4_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT4_LSB 0
+#define CSR_ACSMCMDREPCNT4_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV4_LSB 8
+#define CSR_ACSMADRADV4_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV4_LSB 10
+#define CSR_ACSMBNKADV4_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD4_LSB 12
+#define CSR_ACSMADRSELLOAD4_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD4_LSB 14
+#define CSR_ACSMBNKSELLOAD4_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE4_LSB 15
+#define CSR_ACSMLONGBUBBLE4_MASK BIT(15)
+/* CSR_ACSMSEQ3X5 */
+#define CSR_ACSMSEQ3X5_LSB 0
+#define CSR_ACSMSEQ3X5_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT5_LSB 0
+#define CSR_ACSMCMDREPCNT5_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV5_LSB 8
+#define CSR_ACSMADRADV5_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV5_LSB 10
+#define CSR_ACSMBNKADV5_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD5_LSB 12
+#define CSR_ACSMADRSELLOAD5_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD5_LSB 14
+#define CSR_ACSMBNKSELLOAD5_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE5_LSB 15
+#define CSR_ACSMLONGBUBBLE5_MASK BIT(15)
+/* CSR_ACSMSEQ3X6 */
+#define CSR_ACSMSEQ3X6_LSB 0
+#define CSR_ACSMSEQ3X6_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT6_LSB 0
+#define CSR_ACSMCMDREPCNT6_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV6_LSB 8
+#define CSR_ACSMADRADV6_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV6_LSB 10
+#define CSR_ACSMBNKADV6_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD6_LSB 12
+#define CSR_ACSMADRSELLOAD6_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD6_LSB 14
+#define CSR_ACSMBNKSELLOAD6_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE6_LSB 15
+#define CSR_ACSMLONGBUBBLE6_MASK BIT(15)
+/* CSR_ACSMSEQ3X7 */
+#define CSR_ACSMSEQ3X7_LSB 0
+#define CSR_ACSMSEQ3X7_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT7_LSB 0
+#define CSR_ACSMCMDREPCNT7_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV7_LSB 8
+#define CSR_ACSMADRADV7_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV7_LSB 10
+#define CSR_ACSMBNKADV7_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD7_LSB 12
+#define CSR_ACSMADRSELLOAD7_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD7_LSB 14
+#define CSR_ACSMBNKSELLOAD7_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE7_LSB 15
+#define CSR_ACSMLONGBUBBLE7_MASK BIT(15)
+/* CSR_ACSMSEQ3X8 */
+#define CSR_ACSMSEQ3X8_LSB 0
+#define CSR_ACSMSEQ3X8_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT8_LSB 0
+#define CSR_ACSMCMDREPCNT8_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV8_LSB 8
+#define CSR_ACSMADRADV8_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV8_LSB 10
+#define CSR_ACSMBNKADV8_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD8_LSB 12
+#define CSR_ACSMADRSELLOAD8_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD8_LSB 14
+#define CSR_ACSMBNKSELLOAD8_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE8_LSB 15
+#define CSR_ACSMLONGBUBBLE8_MASK BIT(15)
+/* CSR_ACSMSEQ3X9 */
+#define CSR_ACSMSEQ3X9_LSB 0
+#define CSR_ACSMSEQ3X9_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT9_LSB 0
+#define CSR_ACSMCMDREPCNT9_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV9_LSB 8
+#define CSR_ACSMADRADV9_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV9_LSB 10
+#define CSR_ACSMBNKADV9_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD9_LSB 12
+#define CSR_ACSMADRSELLOAD9_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD9_LSB 14
+#define CSR_ACSMBNKSELLOAD9_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE9_LSB 15
+#define CSR_ACSMLONGBUBBLE9_MASK BIT(15)
+/* CSR_ACSMSEQ3X10 */
+#define CSR_ACSMSEQ3X10_LSB 0
+#define CSR_ACSMSEQ3X10_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT10_LSB 0
+#define CSR_ACSMCMDREPCNT10_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV10_LSB 8
+#define CSR_ACSMADRADV10_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV10_LSB 10
+#define CSR_ACSMBNKADV10_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD10_LSB 12
+#define CSR_ACSMADRSELLOAD10_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD10_LSB 14
+#define CSR_ACSMBNKSELLOAD10_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE10_LSB 15
+#define CSR_ACSMLONGBUBBLE10_MASK BIT(15)
+/* CSR_ACSMSEQ3X11 */
+#define CSR_ACSMSEQ3X11_LSB 0
+#define CSR_ACSMSEQ3X11_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT11_LSB 0
+#define CSR_ACSMCMDREPCNT11_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV11_LSB 8
+#define CSR_ACSMADRADV11_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV11_LSB 10
+#define CSR_ACSMBNKADV11_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD11_LSB 12
+#define CSR_ACSMADRSELLOAD11_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD11_LSB 14
+#define CSR_ACSMBNKSELLOAD11_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE11_LSB 15
+#define CSR_ACSMLONGBUBBLE11_MASK BIT(15)
+/* CSR_ACSMSEQ3X12 */
+#define CSR_ACSMSEQ3X12_LSB 0
+#define CSR_ACSMSEQ3X12_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT12_LSB 0
+#define CSR_ACSMCMDREPCNT12_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV12_LSB 8
+#define CSR_ACSMADRADV12_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV12_LSB 10
+#define CSR_ACSMBNKADV12_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD12_LSB 12
+#define CSR_ACSMADRSELLOAD12_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD12_LSB 14
+#define CSR_ACSMBNKSELLOAD12_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE12_LSB 15
+#define CSR_ACSMLONGBUBBLE12_MASK BIT(15)
+/* CSR_ACSMSEQ3X13 */
+#define CSR_ACSMSEQ3X13_LSB 0
+#define CSR_ACSMSEQ3X13_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT13_LSB 0
+#define CSR_ACSMCMDREPCNT13_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV13_LSB 8
+#define CSR_ACSMADRADV13_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV13_LSB 10
+#define CSR_ACSMBNKADV13_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD13_LSB 12
+#define CSR_ACSMADRSELLOAD13_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD13_LSB 14
+#define CSR_ACSMBNKSELLOAD13_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE13_LSB 15
+#define CSR_ACSMLONGBUBBLE13_MASK BIT(15)
+/* CSR_ACSMSEQ3X14 */
+#define CSR_ACSMSEQ3X14_LSB 0
+#define CSR_ACSMSEQ3X14_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT14_LSB 0
+#define CSR_ACSMCMDREPCNT14_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV14_LSB 8
+#define CSR_ACSMADRADV14_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV14_LSB 10
+#define CSR_ACSMBNKADV14_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD14_LSB 12
+#define CSR_ACSMADRSELLOAD14_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD14_LSB 14
+#define CSR_ACSMBNKSELLOAD14_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE14_LSB 15
+#define CSR_ACSMLONGBUBBLE14_MASK BIT(15)
+/* CSR_ACSMSEQ3X15 */
+#define CSR_ACSMSEQ3X15_LSB 0
+#define CSR_ACSMSEQ3X15_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT15_LSB 0
+#define CSR_ACSMCMDREPCNT15_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV15_LSB 8
+#define CSR_ACSMADRADV15_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV15_LSB 10
+#define CSR_ACSMBNKADV15_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD15_LSB 12
+#define CSR_ACSMADRSELLOAD15_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD15_LSB 14
+#define CSR_ACSMBNKSELLOAD15_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE15_LSB 15
+#define CSR_ACSMLONGBUBBLE15_MASK BIT(15)
+/* CSR_ACSMSEQ3X16 */
+#define CSR_ACSMSEQ3X16_LSB 0
+#define CSR_ACSMSEQ3X16_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT16_LSB 0
+#define CSR_ACSMCMDREPCNT16_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV16_LSB 8
+#define CSR_ACSMADRADV16_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV16_LSB 10
+#define CSR_ACSMBNKADV16_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD16_LSB 12
+#define CSR_ACSMADRSELLOAD16_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD16_LSB 14
+#define CSR_ACSMBNKSELLOAD16_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE16_LSB 15
+#define CSR_ACSMLONGBUBBLE16_MASK BIT(15)
+/* CSR_ACSMSEQ3X17 */
+#define CSR_ACSMSEQ3X17_LSB 0
+#define CSR_ACSMSEQ3X17_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT17_LSB 0
+#define CSR_ACSMCMDREPCNT17_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV17_LSB 8
+#define CSR_ACSMADRADV17_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV17_LSB 10
+#define CSR_ACSMBNKADV17_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD17_LSB 12
+#define CSR_ACSMADRSELLOAD17_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD17_LSB 14
+#define CSR_ACSMBNKSELLOAD17_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE17_LSB 15
+#define CSR_ACSMLONGBUBBLE17_MASK BIT(15)
+/* CSR_ACSMSEQ3X18 */
+#define CSR_ACSMSEQ3X18_LSB 0
+#define CSR_ACSMSEQ3X18_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT18_LSB 0
+#define CSR_ACSMCMDREPCNT18_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV18_LSB 8
+#define CSR_ACSMADRADV18_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV18_LSB 10
+#define CSR_ACSMBNKADV18_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD18_LSB 12
+#define CSR_ACSMADRSELLOAD18_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD18_LSB 14
+#define CSR_ACSMBNKSELLOAD18_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE18_LSB 15
+#define CSR_ACSMLONGBUBBLE18_MASK BIT(15)
+/* CSR_ACSMSEQ3X19 */
+#define CSR_ACSMSEQ3X19_LSB 0
+#define CSR_ACSMSEQ3X19_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT19_LSB 0
+#define CSR_ACSMCMDREPCNT19_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV19_LSB 8
+#define CSR_ACSMADRADV19_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV19_LSB 10
+#define CSR_ACSMBNKADV19_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD19_LSB 12
+#define CSR_ACSMADRSELLOAD19_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD19_LSB 14
+#define CSR_ACSMBNKSELLOAD19_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE19_LSB 15
+#define CSR_ACSMLONGBUBBLE19_MASK BIT(15)
+/* CSR_ACSMSEQ3X20 */
+#define CSR_ACSMSEQ3X20_LSB 0
+#define CSR_ACSMSEQ3X20_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT20_LSB 0
+#define CSR_ACSMCMDREPCNT20_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV20_LSB 8
+#define CSR_ACSMADRADV20_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV20_LSB 10
+#define CSR_ACSMBNKADV20_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD20_LSB 12
+#define CSR_ACSMADRSELLOAD20_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD20_LSB 14
+#define CSR_ACSMBNKSELLOAD20_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE20_LSB 15
+#define CSR_ACSMLONGBUBBLE20_MASK BIT(15)
+/* CSR_ACSMSEQ3X21 */
+#define CSR_ACSMSEQ3X21_LSB 0
+#define CSR_ACSMSEQ3X21_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT21_LSB 0
+#define CSR_ACSMCMDREPCNT21_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV21_LSB 8
+#define CSR_ACSMADRADV21_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV21_LSB 10
+#define CSR_ACSMBNKADV21_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD21_LSB 12
+#define CSR_ACSMADRSELLOAD21_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD21_LSB 14
+#define CSR_ACSMBNKSELLOAD21_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE21_LSB 15
+#define CSR_ACSMLONGBUBBLE21_MASK BIT(15)
+/* CSR_ACSMSEQ3X22 */
+#define CSR_ACSMSEQ3X22_LSB 0
+#define CSR_ACSMSEQ3X22_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT22_LSB 0
+#define CSR_ACSMCMDREPCNT22_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV22_LSB 8
+#define CSR_ACSMADRADV22_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV22_LSB 10
+#define CSR_ACSMBNKADV22_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD22_LSB 12
+#define CSR_ACSMADRSELLOAD22_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD22_LSB 14
+#define CSR_ACSMBNKSELLOAD22_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE22_LSB 15
+#define CSR_ACSMLONGBUBBLE22_MASK BIT(15)
+/* CSR_ACSMSEQ3X23 */
+#define CSR_ACSMSEQ3X23_LSB 0
+#define CSR_ACSMSEQ3X23_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT23_LSB 0
+#define CSR_ACSMCMDREPCNT23_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV23_LSB 8
+#define CSR_ACSMADRADV23_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV23_LSB 10
+#define CSR_ACSMBNKADV23_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD23_LSB 12
+#define CSR_ACSMADRSELLOAD23_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD23_LSB 14
+#define CSR_ACSMBNKSELLOAD23_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE23_LSB 15
+#define CSR_ACSMLONGBUBBLE23_MASK BIT(15)
+/* CSR_ACSMSEQ3X24 */
+#define CSR_ACSMSEQ3X24_LSB 0
+#define CSR_ACSMSEQ3X24_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT24_LSB 0
+#define CSR_ACSMCMDREPCNT24_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV24_LSB 8
+#define CSR_ACSMADRADV24_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV24_LSB 10
+#define CSR_ACSMBNKADV24_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD24_LSB 12
+#define CSR_ACSMADRSELLOAD24_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD24_LSB 14
+#define CSR_ACSMBNKSELLOAD24_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE24_LSB 15
+#define CSR_ACSMLONGBUBBLE24_MASK BIT(15)
+/* CSR_ACSMSEQ3X25 */
+#define CSR_ACSMSEQ3X25_LSB 0
+#define CSR_ACSMSEQ3X25_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT25_LSB 0
+#define CSR_ACSMCMDREPCNT25_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV25_LSB 8
+#define CSR_ACSMADRADV25_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV25_LSB 10
+#define CSR_ACSMBNKADV25_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD25_LSB 12
+#define CSR_ACSMADRSELLOAD25_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD25_LSB 14
+#define CSR_ACSMBNKSELLOAD25_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE25_LSB 15
+#define CSR_ACSMLONGBUBBLE25_MASK BIT(15)
+/* CSR_ACSMSEQ3X26 */
+#define CSR_ACSMSEQ3X26_LSB 0
+#define CSR_ACSMSEQ3X26_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT26_LSB 0
+#define CSR_ACSMCMDREPCNT26_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV26_LSB 8
+#define CSR_ACSMADRADV26_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV26_LSB 10
+#define CSR_ACSMBNKADV26_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD26_LSB 12
+#define CSR_ACSMADRSELLOAD26_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD26_LSB 14
+#define CSR_ACSMBNKSELLOAD26_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE26_LSB 15
+#define CSR_ACSMLONGBUBBLE26_MASK BIT(15)
+/* CSR_ACSMSEQ3X27 */
+#define CSR_ACSMSEQ3X27_LSB 0
+#define CSR_ACSMSEQ3X27_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT27_LSB 0
+#define CSR_ACSMCMDREPCNT27_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV27_LSB 8
+#define CSR_ACSMADRADV27_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV27_LSB 10
+#define CSR_ACSMBNKADV27_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD27_LSB 12
+#define CSR_ACSMADRSELLOAD27_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD27_LSB 14
+#define CSR_ACSMBNKSELLOAD27_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE27_LSB 15
+#define CSR_ACSMLONGBUBBLE27_MASK BIT(15)
+/* CSR_ACSMSEQ3X28 */
+#define CSR_ACSMSEQ3X28_LSB 0
+#define CSR_ACSMSEQ3X28_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT28_LSB 0
+#define CSR_ACSMCMDREPCNT28_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV28_LSB 8
+#define CSR_ACSMADRADV28_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV28_LSB 10
+#define CSR_ACSMBNKADV28_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD28_LSB 12
+#define CSR_ACSMADRSELLOAD28_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD28_LSB 14
+#define CSR_ACSMBNKSELLOAD28_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE28_LSB 15
+#define CSR_ACSMLONGBUBBLE28_MASK BIT(15)
+/* CSR_ACSMSEQ3X29 */
+#define CSR_ACSMSEQ3X29_LSB 0
+#define CSR_ACSMSEQ3X29_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT29_LSB 0
+#define CSR_ACSMCMDREPCNT29_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV29_LSB 8
+#define CSR_ACSMADRADV29_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV29_LSB 10
+#define CSR_ACSMBNKADV29_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD29_LSB 12
+#define CSR_ACSMADRSELLOAD29_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD29_LSB 14
+#define CSR_ACSMBNKSELLOAD29_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE29_LSB 15
+#define CSR_ACSMLONGBUBBLE29_MASK BIT(15)
+/* CSR_ACSMSEQ3X30 */
+#define CSR_ACSMSEQ3X30_LSB 0
+#define CSR_ACSMSEQ3X30_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT30_LSB 0
+#define CSR_ACSMCMDREPCNT30_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV30_LSB 8
+#define CSR_ACSMADRADV30_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV30_LSB 10
+#define CSR_ACSMBNKADV30_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD30_LSB 12
+#define CSR_ACSMADRSELLOAD30_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD30_LSB 14
+#define CSR_ACSMBNKSELLOAD30_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE30_LSB 15
+#define CSR_ACSMLONGBUBBLE30_MASK BIT(15)
+/* CSR_ACSMSEQ3X31 */
+#define CSR_ACSMSEQ3X31_LSB 0
+#define CSR_ACSMSEQ3X31_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCMDREPCNT31_LSB 0
+#define CSR_ACSMCMDREPCNT31_MASK GENMASK_32(7, 0)
+#define CSR_ACSMADRADV31_LSB 8
+#define CSR_ACSMADRADV31_MASK GENMASK_32(9, 8)
+#define CSR_ACSMBNKADV31_LSB 10
+#define CSR_ACSMBNKADV31_MASK GENMASK_32(11, 10)
+#define CSR_ACSMADRSELLOAD31_LSB 12
+#define CSR_ACSMADRSELLOAD31_MASK GENMASK_32(13, 12)
+#define CSR_ACSMBNKSELLOAD31_LSB 14
+#define CSR_ACSMBNKSELLOAD31_MASK BIT(14)
+#define CSR_ACSMLONGBUBBLE31_LSB 15
+#define CSR_ACSMLONGBUBBLE31_MASK BIT(15)
+/* CSR_ACSMPLAYBACK0X0 */
+#define CSR_ACSMPLAYBACK0X0_LSB 0
+#define CSR_ACSMPLAYBACK0X0_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X0 */
+#define CSR_ACSMPLAYBACK1X0_LSB 0
+#define CSR_ACSMPLAYBACK1X0_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X1 */
+#define CSR_ACSMPLAYBACK0X1_LSB 0
+#define CSR_ACSMPLAYBACK0X1_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X1 */
+#define CSR_ACSMPLAYBACK1X1_LSB 0
+#define CSR_ACSMPLAYBACK1X1_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X2 */
+#define CSR_ACSMPLAYBACK0X2_LSB 0
+#define CSR_ACSMPLAYBACK0X2_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X2 */
+#define CSR_ACSMPLAYBACK1X2_LSB 0
+#define CSR_ACSMPLAYBACK1X2_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X3 */
+#define CSR_ACSMPLAYBACK0X3_LSB 0
+#define CSR_ACSMPLAYBACK0X3_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X3 */
+#define CSR_ACSMPLAYBACK1X3_LSB 0
+#define CSR_ACSMPLAYBACK1X3_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X4 */
+#define CSR_ACSMPLAYBACK0X4_LSB 0
+#define CSR_ACSMPLAYBACK0X4_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X4 */
+#define CSR_ACSMPLAYBACK1X4_LSB 0
+#define CSR_ACSMPLAYBACK1X4_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X5 */
+#define CSR_ACSMPLAYBACK0X5_LSB 0
+#define CSR_ACSMPLAYBACK0X5_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X5 */
+#define CSR_ACSMPLAYBACK1X5_LSB 0
+#define CSR_ACSMPLAYBACK1X5_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X6 */
+#define CSR_ACSMPLAYBACK0X6_LSB 0
+#define CSR_ACSMPLAYBACK0X6_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X6 */
+#define CSR_ACSMPLAYBACK1X6_LSB 0
+#define CSR_ACSMPLAYBACK1X6_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK0X7 */
+#define CSR_ACSMPLAYBACK0X7_LSB 0
+#define CSR_ACSMPLAYBACK0X7_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPLAYBACK1X7 */
+#define CSR_ACSMPLAYBACK1X7_LSB 0
+#define CSR_ACSMPLAYBACK1X7_MASK GENMASK_32(11, 0)
+/* CSR_ACSMPSTATEOVREN */
+#define CSR_ACSMPSTATEOVREN_LSB 0
+#define CSR_ACSMPSTATEOVREN_MASK BIT(0)
+/* CSR_ACSMPSTATEOVRVAL */
+#define CSR_ACSMPSTATEOVRVAL_LSB 0
+#define CSR_ACSMPSTATEOVRVAL_MASK GENMASK_32(3, 0)
+/* CSR_ACSMCTRL23 */
+#define CSR_ACSMCTRL23_LSB 0
+#define CSR_ACSMCTRL23_MASK GENMASK_32(12, 0)
+#define CSR_ACSMCSMASK_LSB 0
+#define CSR_ACSMCSMASK_MASK GENMASK_32(7, 0)
+#define CSR_ACSMCSMODE_LSB 8
+#define CSR_ACSMCSMODE_MASK BIT(8)
+#define CSR_ACSMPARMASK_LSB 9
+#define CSR_ACSMPARMASK_MASK GENMASK_32(12, 9)
+/* CSR_ACSMCKEVAL */
+#define CSR_ACSMCKEVAL_LSB 0
+#define CSR_ACSMCKEVAL_MASK GENMASK_32(3, 0)
+/* CSR_LOWSPEEDCLOCKDIVIDER */
+#define CSR_LOWSPEEDCLOCKDIVIDER_LSB 0
+#define CSR_LOWSPEEDCLOCKDIVIDER_MASK GENMASK_32(5, 0)
+/* CSR_ACSMCSMAPCTRL0 */
+#define CSR_ACSMCSMAPCTRL0_LSB 0
+#define CSR_ACSMCSMAPCTRL0_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP0_LSB 0
+#define CSR_ACSMCSMAP0_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP0_LSB 8
+#define CSR_ACSMDESTMAP0_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP0_LSB 12
+#define CSR_ACSMODTMAP0_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL1 */
+#define CSR_ACSMCSMAPCTRL1_LSB 0
+#define CSR_ACSMCSMAPCTRL1_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP1_LSB 0
+#define CSR_ACSMCSMAP1_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP1_LSB 8
+#define CSR_ACSMDESTMAP1_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP1_LSB 12
+#define CSR_ACSMODTMAP1_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL2 */
+#define CSR_ACSMCSMAPCTRL2_LSB 0
+#define CSR_ACSMCSMAPCTRL2_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP2_LSB 0
+#define CSR_ACSMCSMAP2_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP2_LSB 8
+#define CSR_ACSMDESTMAP2_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP2_LSB 12
+#define CSR_ACSMODTMAP2_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL3 */
+#define CSR_ACSMCSMAPCTRL3_LSB 0
+#define CSR_ACSMCSMAPCTRL3_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP3_LSB 0
+#define CSR_ACSMCSMAP3_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP3_LSB 8
+#define CSR_ACSMDESTMAP3_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP3_LSB 12
+#define CSR_ACSMODTMAP3_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL4 */
+#define CSR_ACSMCSMAPCTRL4_LSB 0
+#define CSR_ACSMCSMAPCTRL4_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP4_LSB 0
+#define CSR_ACSMCSMAP4_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP4_LSB 8
+#define CSR_ACSMDESTMAP4_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP4_LSB 12
+#define CSR_ACSMODTMAP4_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL5 */
+#define CSR_ACSMCSMAPCTRL5_LSB 0
+#define CSR_ACSMCSMAPCTRL5_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP5_LSB 0
+#define CSR_ACSMCSMAP5_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP5_LSB 8
+#define CSR_ACSMDESTMAP5_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP5_LSB 12
+#define CSR_ACSMODTMAP5_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL6 */
+#define CSR_ACSMCSMAPCTRL6_LSB 0
+#define CSR_ACSMCSMAPCTRL6_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP6_LSB 0
+#define CSR_ACSMCSMAP6_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP6_LSB 8
+#define CSR_ACSMDESTMAP6_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP6_LSB 12
+#define CSR_ACSMODTMAP6_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL7 */
+#define CSR_ACSMCSMAPCTRL7_LSB 0
+#define CSR_ACSMCSMAPCTRL7_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP7_LSB 0
+#define CSR_ACSMCSMAP7_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP7_LSB 8
+#define CSR_ACSMDESTMAP7_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP7_LSB 12
+#define CSR_ACSMODTMAP7_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL8 */
+#define CSR_ACSMCSMAPCTRL8_LSB 0
+#define CSR_ACSMCSMAPCTRL8_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP8_LSB 0
+#define CSR_ACSMCSMAP8_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP8_LSB 8
+#define CSR_ACSMDESTMAP8_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP8_LSB 12
+#define CSR_ACSMODTMAP8_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL9 */
+#define CSR_ACSMCSMAPCTRL9_LSB 0
+#define CSR_ACSMCSMAPCTRL9_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP9_LSB 0
+#define CSR_ACSMCSMAP9_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP9_LSB 8
+#define CSR_ACSMDESTMAP9_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP9_LSB 12
+#define CSR_ACSMODTMAP9_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL10 */
+#define CSR_ACSMCSMAPCTRL10_LSB 0
+#define CSR_ACSMCSMAPCTRL10_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP10_LSB 0
+#define CSR_ACSMCSMAP10_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP10_LSB 8
+#define CSR_ACSMDESTMAP10_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP10_LSB 12
+#define CSR_ACSMODTMAP10_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL11 */
+#define CSR_ACSMCSMAPCTRL11_LSB 0
+#define CSR_ACSMCSMAPCTRL11_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP11_LSB 0
+#define CSR_ACSMCSMAP11_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP11_LSB 8
+#define CSR_ACSMDESTMAP11_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP11_LSB 12
+#define CSR_ACSMODTMAP11_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL12 */
+#define CSR_ACSMCSMAPCTRL12_LSB 0
+#define CSR_ACSMCSMAPCTRL12_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP12_LSB 0
+#define CSR_ACSMCSMAP12_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP12_LSB 8
+#define CSR_ACSMDESTMAP12_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP12_LSB 12
+#define CSR_ACSMODTMAP12_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL13 */
+#define CSR_ACSMCSMAPCTRL13_LSB 0
+#define CSR_ACSMCSMAPCTRL13_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP13_LSB 0
+#define CSR_ACSMCSMAP13_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP13_LSB 8
+#define CSR_ACSMDESTMAP13_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP13_LSB 12
+#define CSR_ACSMODTMAP13_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL14 */
+#define CSR_ACSMCSMAPCTRL14_LSB 0
+#define CSR_ACSMCSMAPCTRL14_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP14_LSB 0
+#define CSR_ACSMCSMAP14_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP14_LSB 8
+#define CSR_ACSMDESTMAP14_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP14_LSB 12
+#define CSR_ACSMODTMAP14_MASK GENMASK_32(14, 12)
+/* CSR_ACSMCSMAPCTRL15 */
+#define CSR_ACSMCSMAPCTRL15_LSB 0
+#define CSR_ACSMCSMAPCTRL15_MASK GENMASK_32(14, 0)
+#define CSR_ACSMCSMAP15_LSB 0
+#define CSR_ACSMCSMAP15_MASK GENMASK_32(7, 0)
+#define CSR_ACSMDESTMAP15_LSB 8
+#define CSR_ACSMDESTMAP15_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTMAP15_LSB 12
+#define CSR_ACSMODTMAP15_MASK GENMASK_32(14, 12)
+/* CSR_ACSMODTCTRL0 */
+#define CSR_ACSMODTCTRL0_LSB 0
+#define CSR_ACSMODTCTRL0_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS0_LSB 0
+#define CSR_ACSMODTWRPATCS0_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS0_LSB 4
+#define CSR_ACSMODTRDPATCS0_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL1 */
+#define CSR_ACSMODTCTRL1_LSB 0
+#define CSR_ACSMODTCTRL1_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS1_LSB 0
+#define CSR_ACSMODTWRPATCS1_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS1_LSB 4
+#define CSR_ACSMODTRDPATCS1_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL2 */
+#define CSR_ACSMODTCTRL2_LSB 0
+#define CSR_ACSMODTCTRL2_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS2_LSB 0
+#define CSR_ACSMODTWRPATCS2_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS2_LSB 4
+#define CSR_ACSMODTRDPATCS2_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL3 */
+#define CSR_ACSMODTCTRL3_LSB 0
+#define CSR_ACSMODTCTRL3_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS3_LSB 0
+#define CSR_ACSMODTWRPATCS3_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS3_LSB 4
+#define CSR_ACSMODTRDPATCS3_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL4 */
+#define CSR_ACSMODTCTRL4_LSB 0
+#define CSR_ACSMODTCTRL4_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS4_LSB 0
+#define CSR_ACSMODTWRPATCS4_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS4_LSB 4
+#define CSR_ACSMODTRDPATCS4_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL5 */
+#define CSR_ACSMODTCTRL5_LSB 0
+#define CSR_ACSMODTCTRL5_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS5_LSB 0
+#define CSR_ACSMODTWRPATCS5_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS5_LSB 4
+#define CSR_ACSMODTRDPATCS5_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL6 */
+#define CSR_ACSMODTCTRL6_LSB 0
+#define CSR_ACSMODTCTRL6_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS6_LSB 0
+#define CSR_ACSMODTWRPATCS6_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS6_LSB 4
+#define CSR_ACSMODTRDPATCS6_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL7 */
+#define CSR_ACSMODTCTRL7_LSB 0
+#define CSR_ACSMODTCTRL7_MASK GENMASK_32(7, 0)
+#define CSR_ACSMODTWRPATCS7_LSB 0
+#define CSR_ACSMODTWRPATCS7_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDPATCS7_LSB 4
+#define CSR_ACSMODTRDPATCS7_MASK GENMASK_32(7, 4)
+/* CSR_ACSMODTCTRL8 */
+#define CSR_ACSMODTCTRL8_LSB 0
+#define CSR_ACSMODTCTRL8_MASK GENMASK_32(15, 0)
+#define CSR_ACSMODTWRDURCTRL_LSB 0
+#define CSR_ACSMODTWRDURCTRL_MASK GENMASK_32(3, 0)
+#define CSR_ACSMODTRDDURCTRL_LSB 4
+#define CSR_ACSMODTRDDURCTRL_MASK GENMASK_32(7, 4)
+#define CSR_ACSMODTWRSTRTCTRL_LSB 8
+#define CSR_ACSMODTWRSTRTCTRL_MASK GENMASK_32(11, 8)
+#define CSR_ACSMODTRDSTRTCTRL_LSB 12
+#define CSR_ACSMODTRDSTRTCTRL_MASK GENMASK_32(15, 12)
+/* CSR_ACSMCTRL16 */
+#define CSR_ACSMCTRL16_LSB 0
+#define CSR_ACSMCTRL16_MASK GENMASK_32(15, 0)
+#define CSR_ACSMDDRADRUP_LSB 0
+#define CSR_ACSMDDRADRUP_MASK GENMASK_32(3, 0)
+#define CSR_ACSMHIGHADDR_LSB 4
+#define CSR_ACSMHIGHADDR_MASK BIT(4)
+#define CSR_ACSMADR13PLUGHOLE_LSB 5
+#define CSR_ACSMADR13PLUGHOLE_MASK BIT(5)
+#define CSR_ACSMCTRL16RSVD_LSB 6
+#define CSR_ACSMCTRL16RSVD_MASK BIT(6)
+#define CSR_ACSMWRTLVLODTCTRL_LSB 7
+#define CSR_ACSMWRTLVLODTCTRL_MASK BIT(7)
+#define CSR_ACSMWRTLVLODT_LSB 8
+#define CSR_ACSMWRTLVLODT_MASK GENMASK_32(11, 8)
+#define CSR_ACSM2TGRPINHIBIT_LSB 12
+#define CSR_ACSM2TGRPINHIBIT_MASK GENMASK_32(15, 12)
+/* CSR_LOWSPEEDCLOCKSTOPVAL */
+#define CSR_LOWSPEEDCLOCKSTOPVAL_LSB 0
+#define CSR_LOWSPEEDCLOCKSTOPVAL_MASK BIT(0)
+/* CSR_ACSMCTRL18 */
+#define CSR_ACSMCTRL18_LSB 0
+#define CSR_ACSMCTRL18_MASK GENMASK_32(1, 0)
+#define CSR_ACSMLOCALDONE_LSB 0
+#define CSR_ACSMLOCALDONE_MASK BIT(0)
+#define CSR_ACSMSTOPONERRASRTD_LSB 1
+#define CSR_ACSMSTOPONERRASRTD_MASK BIT(1)
+/* CSR_ACSMCTRL19 */
+#define CSR_ACSMCTRL19_LSB 0
+#define CSR_ACSMCTRL19_MASK GENMASK_32(2, 0)
+#define CSR_ACSMVISSEL_LSB 0
+#define CSR_ACSMVISSEL_MASK GENMASK_32(2, 0)
+/* CSR_ACSMCTRL20 */
+#define CSR_ACSMCTRL20_LSB 0
+#define CSR_ACSMCTRL20_MASK GENMASK_32(15, 0)
+#define CSR_ACSMVISVAL_LSB 0
+#define CSR_ACSMVISVAL_MASK GENMASK_32(15, 0)
+/* CSR_ACSMCTRL21 */
+#define CSR_ACSMCTRL21_LSB 0
+#define CSR_ACSMCTRL21_MASK GENMASK_32(11, 0)
+#define CSR_ACSMMAPDIMMCS0_LSB 0
+#define CSR_ACSMMAPDIMMCS0_MASK GENMASK_32(2, 0)
+#define CSR_ACSMMAPDIMMCS1_LSB 3
+#define CSR_ACSMMAPDIMMCS1_MASK GENMASK_32(5, 3)
+#define CSR_ACSMMAPDIMMCS2_LSB 6
+#define CSR_ACSMMAPDIMMCS2_MASK GENMASK_32(8, 6)
+#define CSR_ACSMMAPDIMMCS3_LSB 9
+#define CSR_ACSMMAPDIMMCS3_MASK GENMASK_32(11, 9)
+/* CSR_ACSMCTRL22 */
+#define CSR_ACSMCTRL22_LSB 0
+#define CSR_ACSMCTRL22_MASK GENMASK_32(11, 0)
+#define CSR_ACSMMAPDIMMCS4_LSB 0
+#define CSR_ACSMMAPDIMMCS4_MASK GENMASK_32(2, 0)
+#define CSR_ACSMMAPDIMMCS5_LSB 3
+#define CSR_ACSMMAPDIMMCS5_MASK GENMASK_32(5, 3)
+#define CSR_ACSMMAPDIMMCS6_LSB 6
+#define CSR_ACSMMAPDIMMCS6_MASK GENMASK_32(8, 6)
+#define CSR_ACSMMAPDIMMCS7_LSB 9
+#define CSR_ACSMMAPDIMMCS7_MASK GENMASK_32(11, 9)
+/* CSR_ACSMCTRL0 */
+#define CSR_ACSMCTRL0_LSB 0
+#define CSR_ACSMCTRL0_MASK GENMASK_32(15, 0)
+#define CSR_ACSMRSVDCTRL00_LSB 0
+#define CSR_ACSMRSVDCTRL00_MASK BIT(0)
+#define CSR_ACSMDYNBLMODE_LSB 1
+#define CSR_ACSMDYNBLMODE_MASK BIT(1)
+#define CSR_ACSMBURSTLEN_LSB 2
+#define CSR_ACSMBURSTLEN_MASK BIT(2)
+#define CSR_ACSMINFLOOP_LSB 3
+#define CSR_ACSMINFLOOP_MASK BIT(3)
+#define CSR_ACSMRXVALMODE_LSB 4
+#define CSR_ACSMRXVALMODE_MASK BIT(4)
+#define CSR_ACSMSTPONERRMODE_LSB 5
+#define CSR_ACSMSTPONERRMODE_MASK BIT(5)
+#define CSR_ACSM2TMODE_LSB 6
+#define CSR_ACSM2TMODE_MASK BIT(6)
+#define CSR_ACSMTRAINSOEMODE_LSB 7
+#define CSR_ACSMTRAINSOEMODE_MASK BIT(7)
+#define CSR_ACSMGATEDDRCMD_LSB 8
+#define CSR_ACSMGATEDDRCMD_MASK BIT(8)
+#define CSR_ACSMGEARDOWNMODE_LSB 9
+#define CSR_ACSMGEARDOWNMODE_MASK BIT(9)
+#define CSR_ACSMGEARDOWNPHASE_LSB 10
+#define CSR_ACSMGEARDOWNPHASE_MASK BIT(10)
+#define CSR_ACSMGEARDOWNSYNC_LSB 11
+#define CSR_ACSMGEARDOWNSYNC_MASK BIT(11)
+#define CSR_ACSMCAPRBSMODE_LSB 12
+#define CSR_ACSMCAPRBSMODE_MASK BIT(12)
+#define CSR_ACSMGATERXFIFOWRITE_LSB 13
+#define CSR_ACSMGATERXFIFOWRITE_MASK BIT(13)
+#define CSR_ACSMPARMODE_LSB 14
+#define CSR_ACSMPARMODE_MASK BIT(14)
+#define CSR_ACSMTDSMODE_LSB 15
+#define CSR_ACSMTDSMODE_MASK BIT(15)
+/* CSR_ACSMCTRL1 */
+#define CSR_ACSMCTRL1_LSB 0
+#define CSR_ACSMCTRL1_MASK GENMASK_32(15, 0)
+#define CSR_ACSMREPCNT_LSB 0
+#define CSR_ACSMREPCNT_MASK GENMASK_32(15, 0)
+/* CSR_ACSMCTRL2 */
+#define CSR_ACSMCTRL2_LSB 0
+#define CSR_ACSMCTRL2_MASK GENMASK_32(4, 0)
+#define CSR_ACSMSTARTPTR_LSB 0
+#define CSR_ACSMSTARTPTR_MASK GENMASK_32(4, 0)
+/* CSR_ACSMCTRL3 */
+#define CSR_ACSMCTRL3_LSB 0
+#define CSR_ACSMCTRL3_MASK GENMASK_32(4, 0)
+#define CSR_ACSMLOOPPTR_LSB 0
+#define CSR_ACSMLOOPPTR_MASK GENMASK_32(4, 0)
+/* CSR_ACSMCTRL4 */
+#define CSR_ACSMCTRL4_LSB 0
+#define CSR_ACSMCTRL4_MASK GENMASK_32(4, 0)
+#define CSR_ACSMENDPTR_LSB 0
+#define CSR_ACSMENDPTR_MASK GENMASK_32(4, 0)
+/* CSR_ACSMCTRL5 */
+#define CSR_ACSMCTRL5_LSB 0
+#define CSR_ACSMCTRL5_MASK GENMASK_32(13, 0)
+#define CSR_ACSMMXRDLAT_LSB 0
+#define CSR_ACSMMXRDLAT_MASK GENMASK_32(7, 0)
+#define CSR_ACSMRCASLAT_LSB 8
+#define CSR_ACSMRCASLAT_MASK GENMASK_32(13, 8)
+/* CSR_ACSMCTRL6 */
+#define CSR_ACSMCTRL6_LSB 0
+#define CSR_ACSMCTRL6_MASK GENMASK_32(10, 0)
+#define CSR_ACSMWCASLAT_LSB 0
+#define CSR_ACSMWCASLAT_MASK GENMASK_32(5, 0)
+#define CSR_ACSMWRRSVD_LSB 6
+#define CSR_ACSMWRRSVD_MASK GENMASK_32(7, 6)
+#define CSR_ACSMWRDATLAT_LSB 8
+#define CSR_ACSMWRDATLAT_MASK GENMASK_32(10, 8)
+/* CSR_ACSMCTRL7 */
+#define CSR_ACSMCTRL7_LSB 0
+#define CSR_ACSMCTRL7_MASK GENMASK_32(15, 0)
+#define CSR_ACSMRASPCFG_LSB 0
+#define CSR_ACSMRASPCFG_MASK GENMASK_32(15, 0)
+/* CSR_ACSMCTRL8 */
+#define CSR_ACSMCTRL8_LSB 0
+#define CSR_ACSMCTRL8_MASK GENMASK_32(15, 0)
+#define CSR_ACSMRASPSEED_LSB 0
+#define CSR_ACSMRASPSEED_MASK GENMASK_32(15, 0)
+/* CSR_ACSMCTRL9 */
+#define CSR_ACSMCTRL9_LSB 0
+#define CSR_ACSMCTRL9_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCASPCFG_LSB 0
+#define CSR_ACSMCASPCFG_MASK GENMASK_32(15, 0)
+/* CSR_ACSMCTRL10 */
+#define CSR_ACSMCTRL10_LSB 0
+#define CSR_ACSMCTRL10_MASK GENMASK_32(15, 0)
+#define CSR_ACSMCASPSEED_LSB 0
+#define CSR_ACSMCASPSEED_MASK GENMASK_32(15, 0)
+/* CSR_ACSMCTRL11 */
+#define CSR_ACSMCTRL11_LSB 0
+#define CSR_ACSMCTRL11_MASK GENMASK_32(15, 0)
+#define CSR_ACSMRASADRINC_LSB 0
+#define CSR_ACSMRASADRINC_MASK GENMASK_32(7, 0)
+#define CSR_ACSMCASADRINC_LSB 8
+#define CSR_ACSMCASADRINC_MASK GENMASK_32(15, 8)
+/* CSR_ACSMCTRL12 */
+#define CSR_ACSMCTRL12_LSB 0
+#define CSR_ACSMCTRL12_MASK GENMASK_32(11, 0)
+#define CSR_ACSMBNKPCFG_LSB 0
+#define CSR_ACSMBNKPCFG_MASK GENMASK_32(3, 0)
+#define CSR_ACSMBNKPSEED_LSB 4
+#define CSR_ACSMBNKPSEED_MASK GENMASK_32(7, 4)
+#define CSR_ACSMBNKADRINC_LSB 8
+#define CSR_ACSMBNKADRINC_MASK GENMASK_32(11, 8)
+/* CSR_ACSMCTRL13 */
+#define CSR_ACSMCTRL13_LSB 0
+#define CSR_ACSMCTRL13_MASK GENMASK_32(3, 0)
+#define CSR_ACSMCKEENB_LSB 0
+#define CSR_ACSMCKEENB_MASK GENMASK_32(3, 0)
+/* CSR_ACSMCTRL14 */
+#define CSR_ACSMCTRL14_LSB 0
+#define CSR_ACSMCTRL14_MASK GENMASK_32(3, 0)
+#define CSR_ACSMRASPCFGUP_LSB 0
+#define CSR_ACSMRASPCFGUP_MASK GENMASK_32(3, 0)
+/* CSR_ACSMCTRL15 */
+#define CSR_ACSMCTRL15_LSB 0
+#define CSR_ACSMCTRL15_MASK GENMASK_32(3, 0)
+#define CSR_ACSMRASPSEEDUP_LSB 0
+#define CSR_ACSMRASPSEEDUP_MASK GENMASK_32(3, 0)
+
+/* PPGC0 register offsets */
+/* CSR_PPGCCTRL1 */
+#define CSR_PPGCCTRL1_LSB 1
+#define CSR_PPGCCTRL1_MASK GENMASK_32(4, 1)
+#define CSR_HWTTXDBIEN_LSB 1
+#define CSR_HWTTXDBIEN_MASK BIT(1)
+#define CSR_HWTRXDBIEN_LSB 2
+#define CSR_HWTRXDBIEN_MASK BIT(2)
+#define CSR_HWTTXDMDBIVAL_LSB 3
+#define CSR_HWTTXDMDBIVAL_MASK BIT(3)
+#define CSR_HWTTXDMDBISEL_LSB 4
+#define CSR_HWTTXDMDBISEL_MASK BIT(4)
+/* CSR_PPGCLANE2CRCINMAP0 */
+#define CSR_PPGCLANE2CRCINMAP0_LSB 0
+#define CSR_PPGCLANE2CRCINMAP0_MASK GENMASK_32(11, 0)
+#define CSR_PPGCCRCLANEMAP0_LSB 0
+#define CSR_PPGCCRCLANEMAP0_MASK GENMASK_32(2, 0)
+#define CSR_PPGCCRCLANEMAP1_LSB 3
+#define CSR_PPGCCRCLANEMAP1_MASK GENMASK_32(5, 3)
+#define CSR_PPGCCRCLANEMAP2_LSB 6
+#define CSR_PPGCCRCLANEMAP2_MASK GENMASK_32(8, 6)
+#define CSR_PPGCCRCLANEMAP3_LSB 9
+#define CSR_PPGCCRCLANEMAP3_MASK GENMASK_32(11, 9)
+/* CSR_PPGCLANE2CRCINMAP1 */
+#define CSR_PPGCLANE2CRCINMAP1_LSB 0
+#define CSR_PPGCLANE2CRCINMAP1_MASK GENMASK_32(11, 0)
+#define CSR_PPGCCRCLANEMAP4_LSB 0
+#define CSR_PPGCCRCLANEMAP4_MASK GENMASK_32(2, 0)
+#define CSR_PPGCCRCLANEMAP5_LSB 3
+#define CSR_PPGCCRCLANEMAP5_MASK GENMASK_32(5, 3)
+#define CSR_PPGCCRCLANEMAP6_LSB 6
+#define CSR_PPGCCRCLANEMAP6_MASK GENMASK_32(8, 6)
+#define CSR_PPGCCRCLANEMAP7_LSB 9
+#define CSR_PPGCCRCLANEMAP7_MASK GENMASK_32(11, 9)
+/* CSR_PRBSTAPDLY0 */
+#define CSR_PRBSTAPDLY0_LSB 0
+#define CSR_PRBSTAPDLY0_MASK GENMASK_32(15, 0)
+/* CSR_PRBSTAPDLY1 */
+#define CSR_PRBSTAPDLY1_LSB 0
+#define CSR_PRBSTAPDLY1_MASK GENMASK_32(15, 0)
+/* CSR_PRBSTAPDLY2 */
+#define CSR_PRBSTAPDLY2_LSB 0
+#define CSR_PRBSTAPDLY2_MASK GENMASK_32(15, 0)
+/* CSR_PRBSTAPDLY3 */
+#define CSR_PRBSTAPDLY3_LSB 0
+#define CSR_PRBSTAPDLY3_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE0 */
+#define CSR_GENPRBSBYTE0_LSB 0
+#define CSR_GENPRBSBYTE0_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE1² */
+#define CSR_GENPRBSBYTE1_LSB 0
+#define CSR_GENPRBSBYTE1_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE2 */
+#define CSR_GENPRBSBYTE2_LSB 0
+#define CSR_GENPRBSBYTE2_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE3 */
+#define CSR_GENPRBSBYTE3_LSB 0
+#define CSR_GENPRBSBYTE3_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE4 */
+#define CSR_GENPRBSBYTE4_LSB 0
+#define CSR_GENPRBSBYTE4_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE5 */
+#define CSR_GENPRBSBYTE5_LSB 0
+#define CSR_GENPRBSBYTE5_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE6 */
+#define CSR_GENPRBSBYTE6_LSB 0
+#define CSR_GENPRBSBYTE6_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE7 */
+#define CSR_GENPRBSBYTE7_LSB 0
+#define CSR_GENPRBSBYTE7_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE8 */
+#define CSR_GENPRBSBYTE8_LSB 0
+#define CSR_GENPRBSBYTE8_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE9 */
+#define CSR_GENPRBSBYTE9_LSB 0
+#define CSR_GENPRBSBYTE9_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE10 */
+#define CSR_GENPRBSBYTE10_LSB 0
+#define CSR_GENPRBSBYTE10_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE11 */
+#define CSR_GENPRBSBYTE11_LSB 0
+#define CSR_GENPRBSBYTE11_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE12 */
+#define CSR_GENPRBSBYTE12_LSB 0
+#define CSR_GENPRBSBYTE12_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE13 */
+#define CSR_GENPRBSBYTE13_LSB 0
+#define CSR_GENPRBSBYTE13_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE14 */
+#define CSR_GENPRBSBYTE14_LSB 0
+#define CSR_GENPRBSBYTE14_MASK GENMASK_32(15, 0)
+/* CSR_GENPRBSBYTE15 */
+#define CSR_GENPRBSBYTE15_LSB 0
+#define CSR_GENPRBSBYTE15_MASK GENMASK_32(15, 0)
+/* CSR_PRBSGENCTL */
+#define CSR_PRBSGENCTL_LSB 0
+#define CSR_PRBSGENCTL_MASK GENMASK_32(6, 0)
+#define CSR_PPGCMODE_LSB 0
+#define CSR_PPGCMODE_MASK BIT(0)
+#define CSR_PPGCDMMODE_LSB 1
+#define CSR_PPGCDMMODE_MASK BIT(1)
+#define CSR_PPGCLDFFMODE_LSB 2
+#define CSR_PPGCLDFFMODE_MASK BIT(2)
+#define CSR_PPGCSEL23BPRBS_LSB 3
+#define CSR_PPGCSEL23BPRBS_MASK BIT(3)
+#define CSR_PPGCPATADV_LSB 4
+#define CSR_PPGCPATADV_MASK GENMASK_32(5, 4)
+#define CSR_PPGCENBPATSTRESSMODE_LSB 6
+#define CSR_PPGCENBPATSTRESSMODE_MASK BIT(6)
+/* CSR_PRBSGENSTATELO */
+#define CSR_PRBSGENSTATELO_LSB 0
+#define CSR_PRBSGENSTATELO_MASK GENMASK_32(15, 0)
+/* CSR_PRBSGENSTATEHI */
+#define CSR_PRBSGENSTATEHI_LSB 0
+#define CSR_PRBSGENSTATEHI_MASK GENMASK_32(6, 0)
+/* CSR_PRBSCHKSTATELO */
+#define CSR_PRBSCHKSTATELO_LSB 0
+#define CSR_PRBSCHKSTATELO_MASK GENMASK_32(15, 0)
+/* CSR_PRBSCHKSTATEHI */
+#define CSR_PRBSCHKSTATEHI_LSB 0
+#define CSR_PRBSCHKSTATEHI_MASK GENMASK_32(6, 0)
+/* CSR_PRBSGENCTL1 */
+#define CSR_PRBSGENCTL1_LSB 0
+#define CSR_PRBSGENCTL1_MASK GENMASK_32(8, 0)
+#define CSR_PPGCMODELANE_LSB 0
+#define CSR_PPGCMODELANE_MASK GENMASK_32(8, 0)
+/* CSR_PRBSGENCTL2 */
+#define CSR_PRBSGENCTL2_LSB 0
+#define CSR_PRBSGENCTL2_MASK GENMASK_32(15, 0)
+#define CSR_PPGCMSKPERIODLIM_LSB 0
+#define CSR_PPGCMSKPERIODLIM_MASK GENMASK_32(15, 0)
+
+/* INITENG0 register offsets */
+/* CSR_PRESEQUENCEREG0B0S0 */
+#define CSR_PRESEQUENCEREG0B0S0_LSB 0
+#define CSR_PRESEQUENCEREG0B0S0_MASK GENMASK_32(15, 0)
+/* CSR_PRESEQUENCEREG0B0S1 */
+#define CSR_PRESEQUENCEREG0B0S1_LSB 0
+#define CSR_PRESEQUENCEREG0B0S1_MASK GENMASK_32(15, 0)
+/* CSR_PRESEQUENCEREG0B0S2 */
+#define CSR_PRESEQUENCEREG0B0S2_LSB 0
+#define CSR_PRESEQUENCEREG0B0S2_MASK GENMASK_32(8, 0)
+/* CSR_PRESEQUENCEREG0B1S0 */
+#define CSR_PRESEQUENCEREG0B1S0_LSB 0
+#define CSR_PRESEQUENCEREG0B1S0_MASK GENMASK_32(15, 0)
+/* CSR_PRESEQUENCEREG0B1S1 */
+#define CSR_PRESEQUENCEREG0B1S1_LSB 0
+#define CSR_PRESEQUENCEREG0B1S1_MASK GENMASK_32(15, 0)
+/* CSR_PRESEQUENCEREG0B1S2 */
+#define CSR_PRESEQUENCEREG0B1S2_LSB 0
+#define CSR_PRESEQUENCEREG0B1S2_MASK GENMASK_32(8, 0)
+/* CSR_POSTSEQUENCEREG0B0S0 */
+#define CSR_POSTSEQUENCEREG0B0S0_LSB 0
+#define CSR_POSTSEQUENCEREG0B0S0_MASK GENMASK_32(15, 0)
+/* CSR_POSTSEQUENCEREG0B0S1 */
+#define CSR_POSTSEQUENCEREG0B0S1_LSB 0
+#define CSR_POSTSEQUENCEREG0B0S1_MASK GENMASK_32(15, 0)
+/* CSR_POSTSEQUENCEREG0B0S2 */
+#define CSR_POSTSEQUENCEREG0B0S2_LSB 0
+#define CSR_POSTSEQUENCEREG0B0S2_MASK GENMASK_32(8, 0)
+/* CSR_POSTSEQUENCEREG0B1S0 */
+#define CSR_POSTSEQUENCEREG0B1S0_LSB 0
+#define CSR_POSTSEQUENCEREG0B1S0_MASK GENMASK_32(15, 0)
+/* CSR_POSTSEQUENCEREG0B1S1 */
+#define CSR_POSTSEQUENCEREG0B1S1_LSB 0
+#define CSR_POSTSEQUENCEREG0B1S1_MASK GENMASK_32(15, 0)
+/* CSR_POSTSEQUENCEREG0B1S2 */
+#define CSR_POSTSEQUENCEREG0B1S2_LSB 0
+#define CSR_POSTSEQUENCEREG0B1S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQ0BDISABLEFLAG0 */
+#define CSR_SEQ0BDISABLEFLAG0_LSB 0
+#define CSR_SEQ0BDISABLEFLAG0_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG1 */
+#define CSR_SEQ0BDISABLEFLAG1_LSB 0
+#define CSR_SEQ0BDISABLEFLAG1_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG2 */
+#define CSR_SEQ0BDISABLEFLAG2_LSB 0
+#define CSR_SEQ0BDISABLEFLAG2_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG3 */
+#define CSR_SEQ0BDISABLEFLAG3_LSB 0
+#define CSR_SEQ0BDISABLEFLAG3_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG4 */
+#define CSR_SEQ0BDISABLEFLAG4_LSB 0
+#define CSR_SEQ0BDISABLEFLAG4_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG5 */
+#define CSR_SEQ0BDISABLEFLAG5_LSB 0
+#define CSR_SEQ0BDISABLEFLAG5_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG6 */
+#define CSR_SEQ0BDISABLEFLAG6_LSB 0
+#define CSR_SEQ0BDISABLEFLAG6_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BDISABLEFLAG7 */
+#define CSR_SEQ0BDISABLEFLAG7_LSB 0
+#define CSR_SEQ0BDISABLEFLAG7_MASK GENMASK_32(15, 0)
+/* CSR_STARTVECTOR0B0 */
+#define CSR_STARTVECTOR0B0_LSB 0
+#define CSR_STARTVECTOR0B0_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC0_LSB 0
+#define CSR_SEQ0BSTARTVEC0_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B1 */
+#define CSR_STARTVECTOR0B1_LSB 0
+#define CSR_STARTVECTOR0B1_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC1_LSB 0
+#define CSR_SEQ0BSTARTVEC1_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B2 */
+#define CSR_STARTVECTOR0B2_LSB 0
+#define CSR_STARTVECTOR0B2_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC2_LSB 0
+#define CSR_SEQ0BSTARTVEC2_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B3 */
+#define CSR_STARTVECTOR0B3_LSB 0
+#define CSR_STARTVECTOR0B3_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC3_LSB 0
+#define CSR_SEQ0BSTARTVEC3_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B4 */
+#define CSR_STARTVECTOR0B4_LSB 0
+#define CSR_STARTVECTOR0B4_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC4_LSB 0
+#define CSR_SEQ0BSTARTVEC4_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B5 */
+#define CSR_STARTVECTOR0B5_LSB 0
+#define CSR_STARTVECTOR0B5_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC5_LSB 0
+#define CSR_SEQ0BSTARTVEC5_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B6 */
+#define CSR_STARTVECTOR0B6_LSB 0
+#define CSR_STARTVECTOR0B6_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC6_LSB 0
+#define CSR_SEQ0BSTARTVEC6_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B7 */
+#define CSR_STARTVECTOR0B7_LSB 0
+#define CSR_STARTVECTOR0B7_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC7_LSB 0
+#define CSR_SEQ0BSTARTVEC7_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B8 */
+#define CSR_STARTVECTOR0B8_LSB 0
+#define CSR_STARTVECTOR0B8_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC8_LSB 0
+#define CSR_SEQ0BSTARTVEC8_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B9 */
+#define CSR_STARTVECTOR0B9_LSB 0
+#define CSR_STARTVECTOR0B9_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC9_LSB 0
+#define CSR_SEQ0BSTARTVEC9_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B10 */
+#define CSR_STARTVECTOR0B10_LSB 0
+#define CSR_STARTVECTOR0B10_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC10_LSB 0
+#define CSR_SEQ0BSTARTVEC10_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B11 */
+#define CSR_STARTVECTOR0B11_LSB 0
+#define CSR_STARTVECTOR0B11_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC11_LSB 0
+#define CSR_SEQ0BSTARTVEC11_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B12 */
+#define CSR_STARTVECTOR0B12_LSB 0
+#define CSR_STARTVECTOR0B12_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC12_LSB 0
+#define CSR_SEQ0BSTARTVEC12_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B13 */
+#define CSR_STARTVECTOR0B13_LSB 0
+#define CSR_STARTVECTOR0B13_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC13_LSB 0
+#define CSR_SEQ0BSTARTVEC13_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B14 */
+#define CSR_STARTVECTOR0B14_LSB 0
+#define CSR_STARTVECTOR0B14_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC14_LSB 0
+#define CSR_SEQ0BSTARTVEC14_MASK GENMASK_32(6, 0)
+/* CSR_STARTVECTOR0B15 */
+#define CSR_STARTVECTOR0B15_LSB 0
+#define CSR_STARTVECTOR0B15_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BSTARTVEC15_LSB 0
+#define CSR_SEQ0BSTARTVEC15_MASK GENMASK_32(6, 0)
+/* CSR_SEQ0BWAITCONDSEL */
+#define CSR_SEQ0BWAITCONDSEL_LSB 0
+#define CSR_SEQ0BWAITCONDSEL_MASK GENMASK_32(2, 0)
+/* CSR_PHYINLP3 */
+#define CSR_PHYINLP3_LSB 0
+#define CSR_PHYINLP3_MASK BIT(0)
+/* CSR_SEQUENCEREG0B0S0 */
+#define CSR_SEQUENCEREG0B0S0_LSB 0
+#define CSR_SEQUENCEREG0B0S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B0S1 */
+#define CSR_SEQUENCEREG0B0S1_LSB 0
+#define CSR_SEQUENCEREG0B0S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B0S2 */
+#define CSR_SEQUENCEREG0B0S2_LSB 0
+#define CSR_SEQUENCEREG0B0S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B1S0 */
+#define CSR_SEQUENCEREG0B1S0_LSB 0
+#define CSR_SEQUENCEREG0B1S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B1S1 */
+#define CSR_SEQUENCEREG0B1S1_LSB 0
+#define CSR_SEQUENCEREG0B1S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B1S2 */
+#define CSR_SEQUENCEREG0B1S2_LSB 0
+#define CSR_SEQUENCEREG0B1S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B2S0 */
+#define CSR_SEQUENCEREG0B2S0_LSB 0
+#define CSR_SEQUENCEREG0B2S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B2S1 */
+#define CSR_SEQUENCEREG0B2S1_LSB 0
+#define CSR_SEQUENCEREG0B2S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B2S2 */
+#define CSR_SEQUENCEREG0B2S2_LSB 0
+#define CSR_SEQUENCEREG0B2S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B3S0 */
+#define CSR_SEQUENCEREG0B3S0_LSB 0
+#define CSR_SEQUENCEREG0B3S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B3S1 */
+#define CSR_SEQUENCEREG0B3S1_LSB 0
+#define CSR_SEQUENCEREG0B3S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B3S2 */
+#define CSR_SEQUENCEREG0B3S2_LSB 0
+#define CSR_SEQUENCEREG0B3S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B4S0 */
+#define CSR_SEQUENCEREG0B4S0_LSB 0
+#define CSR_SEQUENCEREG0B4S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B4S1 */
+#define CSR_SEQUENCEREG0B4S1_LSB 0
+#define CSR_SEQUENCEREG0B4S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B4S2 */
+#define CSR_SEQUENCEREG0B4S2_LSB 0
+#define CSR_SEQUENCEREG0B4S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B5S0 */
+#define CSR_SEQUENCEREG0B5S0_LSB 0
+#define CSR_SEQUENCEREG0B5S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B5S1 */
+#define CSR_SEQUENCEREG0B5S1_LSB 0
+#define CSR_SEQUENCEREG0B5S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B5S2 */
+#define CSR_SEQUENCEREG0B5S2_LSB 0
+#define CSR_SEQUENCEREG0B5S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B6S0 */
+#define CSR_SEQUENCEREG0B6S0_LSB 0
+#define CSR_SEQUENCEREG0B6S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B6S1 */
+#define CSR_SEQUENCEREG0B6S1_LSB 0
+#define CSR_SEQUENCEREG0B6S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B6S2 */
+#define CSR_SEQUENCEREG0B6S2_LSB 0
+#define CSR_SEQUENCEREG0B6S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B7S0 */
+#define CSR_SEQUENCEREG0B7S0_LSB 0
+#define CSR_SEQUENCEREG0B7S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B7S1 */
+#define CSR_SEQUENCEREG0B7S1_LSB 0
+#define CSR_SEQUENCEREG0B7S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B7S2 */
+#define CSR_SEQUENCEREG0B7S2_LSB 0
+#define CSR_SEQUENCEREG0B7S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B8S0 */
+#define CSR_SEQUENCEREG0B8S0_LSB 0
+#define CSR_SEQUENCEREG0B8S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B8S1 */
+#define CSR_SEQUENCEREG0B8S1_LSB 0
+#define CSR_SEQUENCEREG0B8S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B8S2 */
+#define CSR_SEQUENCEREG0B8S2_LSB 0
+#define CSR_SEQUENCEREG0B8S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B9S0 */
+#define CSR_SEQUENCEREG0B9S0_LSB 0
+#define CSR_SEQUENCEREG0B9S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B9S1 */
+#define CSR_SEQUENCEREG0B9S1_LSB 0
+#define CSR_SEQUENCEREG0B9S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B9S2 */
+#define CSR_SEQUENCEREG0B9S2_LSB 0
+#define CSR_SEQUENCEREG0B9S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B10S0 */
+#define CSR_SEQUENCEREG0B10S0_LSB 0
+#define CSR_SEQUENCEREG0B10S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B10S1 */
+#define CSR_SEQUENCEREG0B10S1_LSB 0
+#define CSR_SEQUENCEREG0B10S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B10S2 */
+#define CSR_SEQUENCEREG0B10S2_LSB 0
+#define CSR_SEQUENCEREG0B10S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B11S0 */
+#define CSR_SEQUENCEREG0B11S0_LSB 0
+#define CSR_SEQUENCEREG0B11S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B11S1 */
+#define CSR_SEQUENCEREG0B11S1_LSB 0
+#define CSR_SEQUENCEREG0B11S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B11S2 */
+#define CSR_SEQUENCEREG0B11S2_LSB 0
+#define CSR_SEQUENCEREG0B11S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B12S0 */
+#define CSR_SEQUENCEREG0B12S0_LSB 0
+#define CSR_SEQUENCEREG0B12S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B12S1 */
+#define CSR_SEQUENCEREG0B12S1_LSB 0
+#define CSR_SEQUENCEREG0B12S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B12S2 */
+#define CSR_SEQUENCEREG0B12S2_LSB 0
+#define CSR_SEQUENCEREG0B12S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B13S0 */
+#define CSR_SEQUENCEREG0B13S0_LSB 0
+#define CSR_SEQUENCEREG0B13S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B13S1 */
+#define CSR_SEQUENCEREG0B13S1_LSB 0
+#define CSR_SEQUENCEREG0B13S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B13S2 */
+#define CSR_SEQUENCEREG0B13S2_LSB 0
+#define CSR_SEQUENCEREG0B13S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B14S0 */
+#define CSR_SEQUENCEREG0B14S0_LSB 0
+#define CSR_SEQUENCEREG0B14S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B14S1 */
+#define CSR_SEQUENCEREG0B14S1_LSB 0
+#define CSR_SEQUENCEREG0B14S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B14S2 */
+#define CSR_SEQUENCEREG0B14S2_LSB 0
+#define CSR_SEQUENCEREG0B14S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B15S0 */
+#define CSR_SEQUENCEREG0B15S0_LSB 0
+#define CSR_SEQUENCEREG0B15S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B15S1 */
+#define CSR_SEQUENCEREG0B15S1_LSB 0
+#define CSR_SEQUENCEREG0B15S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B15S2 */
+#define CSR_SEQUENCEREG0B15S2_LSB 0
+#define CSR_SEQUENCEREG0B15S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B16S0 */
+#define CSR_SEQUENCEREG0B16S0_LSB 0
+#define CSR_SEQUENCEREG0B16S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B16S1 */
+#define CSR_SEQUENCEREG0B16S1_LSB 0
+#define CSR_SEQUENCEREG0B16S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B16S2 */
+#define CSR_SEQUENCEREG0B16S2_LSB 0
+#define CSR_SEQUENCEREG0B16S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B17S0 */
+#define CSR_SEQUENCEREG0B17S0_LSB 0
+#define CSR_SEQUENCEREG0B17S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B17S1 */
+#define CSR_SEQUENCEREG0B17S1_LSB 0
+#define CSR_SEQUENCEREG0B17S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B17S2 */
+#define CSR_SEQUENCEREG0B17S2_LSB 0
+#define CSR_SEQUENCEREG0B17S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B18S0 */
+#define CSR_SEQUENCEREG0B18S0_LSB 0
+#define CSR_SEQUENCEREG0B18S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B18S1 */
+#define CSR_SEQUENCEREG0B18S1_LSB 0
+#define CSR_SEQUENCEREG0B18S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B18S2 */
+#define CSR_SEQUENCEREG0B18S2_LSB 0
+#define CSR_SEQUENCEREG0B18S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B19S0 */
+#define CSR_SEQUENCEREG0B19S0_LSB 0
+#define CSR_SEQUENCEREG0B19S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B19S1 */
+#define CSR_SEQUENCEREG0B19S1_LSB 0
+#define CSR_SEQUENCEREG0B19S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B19S2 */
+#define CSR_SEQUENCEREG0B19S2_LSB 0
+#define CSR_SEQUENCEREG0B19S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B20S0 */
+#define CSR_SEQUENCEREG0B20S0_LSB 0
+#define CSR_SEQUENCEREG0B20S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B20S1 */
+#define CSR_SEQUENCEREG0B20S1_LSB 0
+#define CSR_SEQUENCEREG0B20S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B20S2 */
+#define CSR_SEQUENCEREG0B20S2_LSB 0
+#define CSR_SEQUENCEREG0B20S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B21S0 */
+#define CSR_SEQUENCEREG0B21S0_LSB 0
+#define CSR_SEQUENCEREG0B21S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B21S1 */
+#define CSR_SEQUENCEREG0B21S1_LSB 0
+#define CSR_SEQUENCEREG0B21S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B21S2 */
+#define CSR_SEQUENCEREG0B21S2_LSB 0
+#define CSR_SEQUENCEREG0B21S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B22S0 */
+#define CSR_SEQUENCEREG0B22S0_LSB 0
+#define CSR_SEQUENCEREG0B22S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B22S1 */
+#define CSR_SEQUENCEREG0B22S1_LSB 0
+#define CSR_SEQUENCEREG0B22S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B22S2 */
+#define CSR_SEQUENCEREG0B22S2_LSB 0
+#define CSR_SEQUENCEREG0B22S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B23S0 */
+#define CSR_SEQUENCEREG0B23S0_LSB 0
+#define CSR_SEQUENCEREG0B23S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B23S1 */
+#define CSR_SEQUENCEREG0B23S1_LSB 0
+#define CSR_SEQUENCEREG0B23S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B23S2 */
+#define CSR_SEQUENCEREG0B23S2_LSB 0
+#define CSR_SEQUENCEREG0B23S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B24S0 */
+#define CSR_SEQUENCEREG0B24S0_LSB 0
+#define CSR_SEQUENCEREG0B24S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B24S1 */
+#define CSR_SEQUENCEREG0B24S1_LSB 0
+#define CSR_SEQUENCEREG0B24S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B24S2 */
+#define CSR_SEQUENCEREG0B24S2_LSB 0
+#define CSR_SEQUENCEREG0B24S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B25S0 */
+#define CSR_SEQUENCEREG0B25S0_LSB 0
+#define CSR_SEQUENCEREG0B25S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B25S1 */
+#define CSR_SEQUENCEREG0B25S1_LSB 0
+#define CSR_SEQUENCEREG0B25S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B25S2 */
+#define CSR_SEQUENCEREG0B25S2_LSB 0
+#define CSR_SEQUENCEREG0B25S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B26S0 */
+#define CSR_SEQUENCEREG0B26S0_LSB 0
+#define CSR_SEQUENCEREG0B26S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B26S1 */
+#define CSR_SEQUENCEREG0B26S1_LSB 0
+#define CSR_SEQUENCEREG0B26S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B26S2 */
+#define CSR_SEQUENCEREG0B26S2_LSB 0
+#define CSR_SEQUENCEREG0B26S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B27S0 */
+#define CSR_SEQUENCEREG0B27S0_LSB 0
+#define CSR_SEQUENCEREG0B27S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B27S1 */
+#define CSR_SEQUENCEREG0B27S1_LSB 0
+#define CSR_SEQUENCEREG0B27S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B27S2 */
+#define CSR_SEQUENCEREG0B27S2_LSB 0
+#define CSR_SEQUENCEREG0B27S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B28S0 */
+#define CSR_SEQUENCEREG0B28S0_LSB 0
+#define CSR_SEQUENCEREG0B28S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B28S1 */
+#define CSR_SEQUENCEREG0B28S1_LSB 0
+#define CSR_SEQUENCEREG0B28S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B28S2 */
+#define CSR_SEQUENCEREG0B28S2_LSB 0
+#define CSR_SEQUENCEREG0B28S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B29S0 */
+#define CSR_SEQUENCEREG0B29S0_LSB 0
+#define CSR_SEQUENCEREG0B29S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B29S1 */
+#define CSR_SEQUENCEREG0B29S1_LSB 0
+#define CSR_SEQUENCEREG0B29S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B29S2 */
+#define CSR_SEQUENCEREG0B29S2_LSB 0
+#define CSR_SEQUENCEREG0B29S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B30S0 */
+#define CSR_SEQUENCEREG0B30S0_LSB 0
+#define CSR_SEQUENCEREG0B30S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B30S1 */
+#define CSR_SEQUENCEREG0B30S1_LSB 0
+#define CSR_SEQUENCEREG0B30S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B30S2 */
+#define CSR_SEQUENCEREG0B30S2_LSB 0
+#define CSR_SEQUENCEREG0B30S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B31S0 */
+#define CSR_SEQUENCEREG0B31S0_LSB 0
+#define CSR_SEQUENCEREG0B31S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B31S1 */
+#define CSR_SEQUENCEREG0B31S1_LSB 0
+#define CSR_SEQUENCEREG0B31S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B31S2 */
+#define CSR_SEQUENCEREG0B31S2_LSB 0
+#define CSR_SEQUENCEREG0B31S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B32S0 */
+#define CSR_SEQUENCEREG0B32S0_LSB 0
+#define CSR_SEQUENCEREG0B32S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B32S1 */
+#define CSR_SEQUENCEREG0B32S1_LSB 0
+#define CSR_SEQUENCEREG0B32S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B32S2 */
+#define CSR_SEQUENCEREG0B32S2_LSB 0
+#define CSR_SEQUENCEREG0B32S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B33S0 */
+#define CSR_SEQUENCEREG0B33S0_LSB 0
+#define CSR_SEQUENCEREG0B33S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B33S1 */
+#define CSR_SEQUENCEREG0B33S1_LSB 0
+#define CSR_SEQUENCEREG0B33S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B33S2 */
+#define CSR_SEQUENCEREG0B33S2_LSB 0
+#define CSR_SEQUENCEREG0B33S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B34S0 */
+#define CSR_SEQUENCEREG0B34S0_LSB 0
+#define CSR_SEQUENCEREG0B34S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B34S1 */
+#define CSR_SEQUENCEREG0B34S1_LSB 0
+#define CSR_SEQUENCEREG0B34S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B34S2 */
+#define CSR_SEQUENCEREG0B34S2_LSB 0
+#define CSR_SEQUENCEREG0B34S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B35S0 */
+#define CSR_SEQUENCEREG0B35S0_LSB 0
+#define CSR_SEQUENCEREG0B35S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B35S1 */
+#define CSR_SEQUENCEREG0B35S1_LSB 0
+#define CSR_SEQUENCEREG0B35S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B35S2 */
+#define CSR_SEQUENCEREG0B35S2_LSB 0
+#define CSR_SEQUENCEREG0B35S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B36S0 */
+#define CSR_SEQUENCEREG0B36S0_LSB 0
+#define CSR_SEQUENCEREG0B36S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B36S1 */
+#define CSR_SEQUENCEREG0B36S1_LSB 0
+#define CSR_SEQUENCEREG0B36S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B36S2 */
+#define CSR_SEQUENCEREG0B36S2_LSB 0
+#define CSR_SEQUENCEREG0B36S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B37S0 */
+#define CSR_SEQUENCEREG0B37S0_LSB 0
+#define CSR_SEQUENCEREG0B37S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B37S1 */
+#define CSR_SEQUENCEREG0B37S1_LSB 0
+#define CSR_SEQUENCEREG0B37S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B37S2 */
+#define CSR_SEQUENCEREG0B37S2_LSB 0
+#define CSR_SEQUENCEREG0B37S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B38S0 */
+#define CSR_SEQUENCEREG0B38S0_LSB 0
+#define CSR_SEQUENCEREG0B38S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B38S1 */
+#define CSR_SEQUENCEREG0B38S1_LSB 0
+#define CSR_SEQUENCEREG0B38S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B38S2 */
+#define CSR_SEQUENCEREG0B38S2_LSB 0
+#define CSR_SEQUENCEREG0B38S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B39S0 */
+#define CSR_SEQUENCEREG0B39S0_LSB 0
+#define CSR_SEQUENCEREG0B39S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B39S1 */
+#define CSR_SEQUENCEREG0B39S1_LSB 0
+#define CSR_SEQUENCEREG0B39S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B39S2 */
+#define CSR_SEQUENCEREG0B39S2_LSB 0
+#define CSR_SEQUENCEREG0B39S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B40S0 */
+#define CSR_SEQUENCEREG0B40S0_LSB 0
+#define CSR_SEQUENCEREG0B40S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B40S1 */
+#define CSR_SEQUENCEREG0B40S1_LSB 0
+#define CSR_SEQUENCEREG0B40S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B40S2 */
+#define CSR_SEQUENCEREG0B40S2_LSB 0
+#define CSR_SEQUENCEREG0B40S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B41S0 */
+#define CSR_SEQUENCEREG0B41S0_LSB 0
+#define CSR_SEQUENCEREG0B41S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B41S1 */
+#define CSR_SEQUENCEREG0B41S1_LSB 0
+#define CSR_SEQUENCEREG0B41S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B41S2 */
+#define CSR_SEQUENCEREG0B41S2_LSB 0
+#define CSR_SEQUENCEREG0B41S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B42S0 */
+#define CSR_SEQUENCEREG0B42S0_LSB 0
+#define CSR_SEQUENCEREG0B42S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B42S1 */
+#define CSR_SEQUENCEREG0B42S1_LSB 0
+#define CSR_SEQUENCEREG0B42S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B42S2 */
+#define CSR_SEQUENCEREG0B42S2_LSB 0
+#define CSR_SEQUENCEREG0B42S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B43S0 */
+#define CSR_SEQUENCEREG0B43S0_LSB 0
+#define CSR_SEQUENCEREG0B43S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B43S1 */
+#define CSR_SEQUENCEREG0B43S1_LSB 0
+#define CSR_SEQUENCEREG0B43S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B43S2 */
+#define CSR_SEQUENCEREG0B43S2_LSB 0
+#define CSR_SEQUENCEREG0B43S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B44S0 */
+#define CSR_SEQUENCEREG0B44S0_LSB 0
+#define CSR_SEQUENCEREG0B44S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B44S1 */
+#define CSR_SEQUENCEREG0B44S1_LSB 0
+#define CSR_SEQUENCEREG0B44S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B44S2 */
+#define CSR_SEQUENCEREG0B44S2_LSB 0
+#define CSR_SEQUENCEREG0B44S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B45S0 */
+#define CSR_SEQUENCEREG0B45S0_LSB 0
+#define CSR_SEQUENCEREG0B45S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B45S1 */
+#define CSR_SEQUENCEREG0B45S1_LSB 0
+#define CSR_SEQUENCEREG0B45S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B45S2 */
+#define CSR_SEQUENCEREG0B45S2_LSB 0
+#define CSR_SEQUENCEREG0B45S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B46S0 */
+#define CSR_SEQUENCEREG0B46S0_LSB 0
+#define CSR_SEQUENCEREG0B46S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B46S1 */
+#define CSR_SEQUENCEREG0B46S1_LSB 0
+#define CSR_SEQUENCEREG0B46S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B46S2 */
+#define CSR_SEQUENCEREG0B46S2_LSB 0
+#define CSR_SEQUENCEREG0B46S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B47S0 */
+#define CSR_SEQUENCEREG0B47S0_LSB 0
+#define CSR_SEQUENCEREG0B47S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B47S1 */
+#define CSR_SEQUENCEREG0B47S1_LSB 0
+#define CSR_SEQUENCEREG0B47S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B47S2 */
+#define CSR_SEQUENCEREG0B47S2_LSB 0
+#define CSR_SEQUENCEREG0B47S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B48S0 */
+#define CSR_SEQUENCEREG0B48S0_LSB 0
+#define CSR_SEQUENCEREG0B48S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B48S1 */
+#define CSR_SEQUENCEREG0B48S1_LSB 0
+#define CSR_SEQUENCEREG0B48S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B48S2 */
+#define CSR_SEQUENCEREG0B48S2_LSB 0
+#define CSR_SEQUENCEREG0B48S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B49S0 */
+#define CSR_SEQUENCEREG0B49S0_LSB 0
+#define CSR_SEQUENCEREG0B49S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B49S1 */
+#define CSR_SEQUENCEREG0B49S1_LSB 0
+#define CSR_SEQUENCEREG0B49S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B49S2 */
+#define CSR_SEQUENCEREG0B49S2_LSB 0
+#define CSR_SEQUENCEREG0B49S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B50S0 */
+#define CSR_SEQUENCEREG0B50S0_LSB 0
+#define CSR_SEQUENCEREG0B50S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B50S1 */
+#define CSR_SEQUENCEREG0B50S1_LSB 0
+#define CSR_SEQUENCEREG0B50S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B50S2 */
+#define CSR_SEQUENCEREG0B50S2_LSB 0
+#define CSR_SEQUENCEREG0B50S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B51S0 */
+#define CSR_SEQUENCEREG0B51S0_LSB 0
+#define CSR_SEQUENCEREG0B51S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B51S1 */
+#define CSR_SEQUENCEREG0B51S1_LSB 0
+#define CSR_SEQUENCEREG0B51S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B51S2 */
+#define CSR_SEQUENCEREG0B51S2_LSB 0
+#define CSR_SEQUENCEREG0B51S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B52S0 */
+#define CSR_SEQUENCEREG0B52S0_LSB 0
+#define CSR_SEQUENCEREG0B52S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B52S1 */
+#define CSR_SEQUENCEREG0B52S1_LSB 0
+#define CSR_SEQUENCEREG0B52S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B52S2 */
+#define CSR_SEQUENCEREG0B52S2_LSB 0
+#define CSR_SEQUENCEREG0B52S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B53S0 */
+#define CSR_SEQUENCEREG0B53S0_LSB 0
+#define CSR_SEQUENCEREG0B53S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B53S1 */
+#define CSR_SEQUENCEREG0B53S1_LSB 0
+#define CSR_SEQUENCEREG0B53S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B53S2 */
+#define CSR_SEQUENCEREG0B53S2_LSB 0
+#define CSR_SEQUENCEREG0B53S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B54S0 */
+#define CSR_SEQUENCEREG0B54S0_LSB 0
+#define CSR_SEQUENCEREG0B54S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B54S1 */
+#define CSR_SEQUENCEREG0B54S1_LSB 0
+#define CSR_SEQUENCEREG0B54S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B54S2 */
+#define CSR_SEQUENCEREG0B54S2_LSB 0
+#define CSR_SEQUENCEREG0B54S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B55S0 */
+#define CSR_SEQUENCEREG0B55S0_LSB 0
+#define CSR_SEQUENCEREG0B55S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B55S1 */
+#define CSR_SEQUENCEREG0B55S1_LSB 0
+#define CSR_SEQUENCEREG0B55S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B55S2 */
+#define CSR_SEQUENCEREG0B55S2_LSB 0
+#define CSR_SEQUENCEREG0B55S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B56S0 */
+#define CSR_SEQUENCEREG0B56S0_LSB 0
+#define CSR_SEQUENCEREG0B56S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B56S1 */
+#define CSR_SEQUENCEREG0B56S1_LSB 0
+#define CSR_SEQUENCEREG0B56S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B56S2 */
+#define CSR_SEQUENCEREG0B56S2_LSB 0
+#define CSR_SEQUENCEREG0B56S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B57S0 */
+#define CSR_SEQUENCEREG0B57S0_LSB 0
+#define CSR_SEQUENCEREG0B57S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B57S1 */
+#define CSR_SEQUENCEREG0B57S1_LSB 0
+#define CSR_SEQUENCEREG0B57S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B57S2 */
+#define CSR_SEQUENCEREG0B57S2_LSB 0
+#define CSR_SEQUENCEREG0B57S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B58S0 */
+#define CSR_SEQUENCEREG0B58S0_LSB 0
+#define CSR_SEQUENCEREG0B58S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B58S1 */
+#define CSR_SEQUENCEREG0B58S1_LSB 0
+#define CSR_SEQUENCEREG0B58S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B58S2 */
+#define CSR_SEQUENCEREG0B58S2_LSB 0
+#define CSR_SEQUENCEREG0B58S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B59S0 */
+#define CSR_SEQUENCEREG0B59S0_LSB 0
+#define CSR_SEQUENCEREG0B59S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B59S1 */
+#define CSR_SEQUENCEREG0B59S1_LSB 0
+#define CSR_SEQUENCEREG0B59S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B59S2 */
+#define CSR_SEQUENCEREG0B59S2_LSB 0
+#define CSR_SEQUENCEREG0B59S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B60S0 */
+#define CSR_SEQUENCEREG0B60S0_LSB 0
+#define CSR_SEQUENCEREG0B60S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B60S1 */
+#define CSR_SEQUENCEREG0B60S1_LSB 0
+#define CSR_SEQUENCEREG0B60S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B60S2 */
+#define CSR_SEQUENCEREG0B60S2_LSB 0
+#define CSR_SEQUENCEREG0B60S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B61S0 */
+#define CSR_SEQUENCEREG0B61S0_LSB 0
+#define CSR_SEQUENCEREG0B61S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B61S1 */
+#define CSR_SEQUENCEREG0B61S1_LSB 0
+#define CSR_SEQUENCEREG0B61S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B61S2 */
+#define CSR_SEQUENCEREG0B61S2_LSB 0
+#define CSR_SEQUENCEREG0B61S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B62S0 */
+#define CSR_SEQUENCEREG0B62S0_LSB 0
+#define CSR_SEQUENCEREG0B62S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B62S1 */
+#define CSR_SEQUENCEREG0B62S1_LSB 0
+#define CSR_SEQUENCEREG0B62S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B62S2 */
+#define CSR_SEQUENCEREG0B62S2_LSB 0
+#define CSR_SEQUENCEREG0B62S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B63S0 */
+#define CSR_SEQUENCEREG0B63S0_LSB 0
+#define CSR_SEQUENCEREG0B63S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B63S1 */
+#define CSR_SEQUENCEREG0B63S1_LSB 0
+#define CSR_SEQUENCEREG0B63S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B63S2 */
+#define CSR_SEQUENCEREG0B63S2_LSB 0
+#define CSR_SEQUENCEREG0B63S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B64S0 */
+#define CSR_SEQUENCEREG0B64S0_LSB 0
+#define CSR_SEQUENCEREG0B64S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B64S1 */
+#define CSR_SEQUENCEREG0B64S1_LSB 0
+#define CSR_SEQUENCEREG0B64S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B64S2 */
+#define CSR_SEQUENCEREG0B64S2_LSB 0
+#define CSR_SEQUENCEREG0B64S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B65S0 */
+#define CSR_SEQUENCEREG0B65S0_LSB 0
+#define CSR_SEQUENCEREG0B65S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B65S1 */
+#define CSR_SEQUENCEREG0B65S1_LSB 0
+#define CSR_SEQUENCEREG0B65S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B65S2 */
+#define CSR_SEQUENCEREG0B65S2_LSB 0
+#define CSR_SEQUENCEREG0B65S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B66S0 */
+#define CSR_SEQUENCEREG0B66S0_LSB 0
+#define CSR_SEQUENCEREG0B66S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B66S1 */
+#define CSR_SEQUENCEREG0B66S1_LSB 0
+#define CSR_SEQUENCEREG0B66S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B66S2 */
+#define CSR_SEQUENCEREG0B66S2_LSB 0
+#define CSR_SEQUENCEREG0B66S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B67S0 */
+#define CSR_SEQUENCEREG0B67S0_LSB 0
+#define CSR_SEQUENCEREG0B67S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B67S1 */
+#define CSR_SEQUENCEREG0B67S1_LSB 0
+#define CSR_SEQUENCEREG0B67S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B67S2 */
+#define CSR_SEQUENCEREG0B67S2_LSB 0
+#define CSR_SEQUENCEREG0B67S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B68S0 */
+#define CSR_SEQUENCEREG0B68S0_LSB 0
+#define CSR_SEQUENCEREG0B68S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B68S1 */
+#define CSR_SEQUENCEREG0B68S1_LSB 0
+#define CSR_SEQUENCEREG0B68S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B68S2 */
+#define CSR_SEQUENCEREG0B68S2_LSB 0
+#define CSR_SEQUENCEREG0B68S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B69S0 */
+#define CSR_SEQUENCEREG0B69S0_LSB 0
+#define CSR_SEQUENCEREG0B69S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B69S1 */
+#define CSR_SEQUENCEREG0B69S1_LSB 0
+#define CSR_SEQUENCEREG0B69S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B69S2 */
+#define CSR_SEQUENCEREG0B69S2_LSB 0
+#define CSR_SEQUENCEREG0B69S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B70S0 */
+#define CSR_SEQUENCEREG0B70S0_LSB 0
+#define CSR_SEQUENCEREG0B70S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B70S1 */
+#define CSR_SEQUENCEREG0B70S1_LSB 0
+#define CSR_SEQUENCEREG0B70S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B70S2 */
+#define CSR_SEQUENCEREG0B70S2_LSB 0
+#define CSR_SEQUENCEREG0B70S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B71S0 */
+#define CSR_SEQUENCEREG0B71S0_LSB 0
+#define CSR_SEQUENCEREG0B71S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B71S1 */
+#define CSR_SEQUENCEREG0B71S1_LSB 0
+#define CSR_SEQUENCEREG0B71S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B71S2 */
+#define CSR_SEQUENCEREG0B71S2_LSB 0
+#define CSR_SEQUENCEREG0B71S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B72S0 */
+#define CSR_SEQUENCEREG0B72S0_LSB 0
+#define CSR_SEQUENCEREG0B72S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B72S1 */
+#define CSR_SEQUENCEREG0B72S1_LSB 0
+#define CSR_SEQUENCEREG0B72S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B72S2 */
+#define CSR_SEQUENCEREG0B72S2_LSB 0
+#define CSR_SEQUENCEREG0B72S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B73S0 */
+#define CSR_SEQUENCEREG0B73S0_LSB 0
+#define CSR_SEQUENCEREG0B73S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B73S1 */
+#define CSR_SEQUENCEREG0B73S1_LSB 0
+#define CSR_SEQUENCEREG0B73S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B73S2 */
+#define CSR_SEQUENCEREG0B73S2_LSB 0
+#define CSR_SEQUENCEREG0B73S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B74S0 */
+#define CSR_SEQUENCEREG0B74S0_LSB 0
+#define CSR_SEQUENCEREG0B74S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B74S1 */
+#define CSR_SEQUENCEREG0B74S1_LSB 0
+#define CSR_SEQUENCEREG0B74S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B74S2 */
+#define CSR_SEQUENCEREG0B74S2_LSB 0
+#define CSR_SEQUENCEREG0B74S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B75S0 */
+#define CSR_SEQUENCEREG0B75S0_LSB 0
+#define CSR_SEQUENCEREG0B75S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B75S1 */
+#define CSR_SEQUENCEREG0B75S1_LSB 0
+#define CSR_SEQUENCEREG0B75S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B75S2 */
+#define CSR_SEQUENCEREG0B75S2_LSB 0
+#define CSR_SEQUENCEREG0B75S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B76S0 */
+#define CSR_SEQUENCEREG0B76S0_LSB 0
+#define CSR_SEQUENCEREG0B76S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B76S1 */
+#define CSR_SEQUENCEREG0B76S1_LSB 0
+#define CSR_SEQUENCEREG0B76S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B76S2 */
+#define CSR_SEQUENCEREG0B76S2_LSB 0
+#define CSR_SEQUENCEREG0B76S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B77S0 */
+#define CSR_SEQUENCEREG0B77S0_LSB 0
+#define CSR_SEQUENCEREG0B77S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B77S1 */
+#define CSR_SEQUENCEREG0B77S1_LSB 0
+#define CSR_SEQUENCEREG0B77S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B77S2 */
+#define CSR_SEQUENCEREG0B77S2_LSB 0
+#define CSR_SEQUENCEREG0B77S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B78S0 */
+#define CSR_SEQUENCEREG0B78S0_LSB 0
+#define CSR_SEQUENCEREG0B78S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B78S1 */
+#define CSR_SEQUENCEREG0B78S1_LSB 0
+#define CSR_SEQUENCEREG0B78S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B78S2 */
+#define CSR_SEQUENCEREG0B78S2_LSB 0
+#define CSR_SEQUENCEREG0B78S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B79S0 */
+#define CSR_SEQUENCEREG0B79S0_LSB 0
+#define CSR_SEQUENCEREG0B79S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B79S1 */
+#define CSR_SEQUENCEREG0B79S1_LSB 0
+#define CSR_SEQUENCEREG0B79S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B79S2 */
+#define CSR_SEQUENCEREG0B79S2_LSB 0
+#define CSR_SEQUENCEREG0B79S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B80S0 */
+#define CSR_SEQUENCEREG0B80S0_LSB 0
+#define CSR_SEQUENCEREG0B80S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B80S1 */
+#define CSR_SEQUENCEREG0B80S1_LSB 0
+#define CSR_SEQUENCEREG0B80S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B80S2 */
+#define CSR_SEQUENCEREG0B80S2_LSB 0
+#define CSR_SEQUENCEREG0B80S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B81S0 */
+#define CSR_SEQUENCEREG0B81S0_LSB 0
+#define CSR_SEQUENCEREG0B81S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B81S1 */
+#define CSR_SEQUENCEREG0B81S1_LSB 0
+#define CSR_SEQUENCEREG0B81S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B81S2 */
+#define CSR_SEQUENCEREG0B81S2_LSB 0
+#define CSR_SEQUENCEREG0B81S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B82S0 */
+#define CSR_SEQUENCEREG0B82S0_LSB 0
+#define CSR_SEQUENCEREG0B82S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B82S1 */
+#define CSR_SEQUENCEREG0B82S1_LSB 0
+#define CSR_SEQUENCEREG0B82S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B82S2 */
+#define CSR_SEQUENCEREG0B82S2_LSB 0
+#define CSR_SEQUENCEREG0B82S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B83S0 */
+#define CSR_SEQUENCEREG0B83S0_LSB 0
+#define CSR_SEQUENCEREG0B83S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B83S1 */
+#define CSR_SEQUENCEREG0B83S1_LSB 0
+#define CSR_SEQUENCEREG0B83S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B83S2 */
+#define CSR_SEQUENCEREG0B83S2_LSB 0
+#define CSR_SEQUENCEREG0B83S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B84S0 */
+#define CSR_SEQUENCEREG0B84S0_LSB 0
+#define CSR_SEQUENCEREG0B84S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B84S1 */
+#define CSR_SEQUENCEREG0B84S1_LSB 0
+#define CSR_SEQUENCEREG0B84S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B84S2 */
+#define CSR_SEQUENCEREG0B84S2_LSB 0
+#define CSR_SEQUENCEREG0B84S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B85S0 */
+#define CSR_SEQUENCEREG0B85S0_LSB 0
+#define CSR_SEQUENCEREG0B85S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B85S1 */
+#define CSR_SEQUENCEREG0B85S1_LSB 0
+#define CSR_SEQUENCEREG0B85S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B85S2 */
+#define CSR_SEQUENCEREG0B85S2_LSB 0
+#define CSR_SEQUENCEREG0B85S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B86S0 */
+#define CSR_SEQUENCEREG0B86S0_LSB 0
+#define CSR_SEQUENCEREG0B86S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B86S1 */
+#define CSR_SEQUENCEREG0B86S1_LSB 0
+#define CSR_SEQUENCEREG0B86S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B86S2 */
+#define CSR_SEQUENCEREG0B86S2_LSB 0
+#define CSR_SEQUENCEREG0B86S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B87S0 */
+#define CSR_SEQUENCEREG0B87S0_LSB 0
+#define CSR_SEQUENCEREG0B87S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B87S1 */
+#define CSR_SEQUENCEREG0B87S1_LSB 0
+#define CSR_SEQUENCEREG0B87S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B87S2 */
+#define CSR_SEQUENCEREG0B87S2_LSB 0
+#define CSR_SEQUENCEREG0B87S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B88S0 */
+#define CSR_SEQUENCEREG0B88S0_LSB 0
+#define CSR_SEQUENCEREG0B88S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B88S1 */
+#define CSR_SEQUENCEREG0B88S1_LSB 0
+#define CSR_SEQUENCEREG0B88S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B88S2 */
+#define CSR_SEQUENCEREG0B88S2_LSB 0
+#define CSR_SEQUENCEREG0B88S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B89S0 */
+#define CSR_SEQUENCEREG0B89S0_LSB 0
+#define CSR_SEQUENCEREG0B89S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B89S1 */
+#define CSR_SEQUENCEREG0B89S1_LSB 0
+#define CSR_SEQUENCEREG0B89S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B89S2 */
+#define CSR_SEQUENCEREG0B89S2_LSB 0
+#define CSR_SEQUENCEREG0B89S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B90S0 */
+#define CSR_SEQUENCEREG0B90S0_LSB 0
+#define CSR_SEQUENCEREG0B90S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B90S1 */
+#define CSR_SEQUENCEREG0B90S1_LSB 0
+#define CSR_SEQUENCEREG0B90S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B90S2 */
+#define CSR_SEQUENCEREG0B90S2_LSB 0
+#define CSR_SEQUENCEREG0B90S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B91S0 */
+#define CSR_SEQUENCEREG0B91S0_LSB 0
+#define CSR_SEQUENCEREG0B91S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B91S1 */
+#define CSR_SEQUENCEREG0B91S1_LSB 0
+#define CSR_SEQUENCEREG0B91S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B91S2 */
+#define CSR_SEQUENCEREG0B91S2_LSB 0
+#define CSR_SEQUENCEREG0B91S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B92S0 */
+#define CSR_SEQUENCEREG0B92S0_LSB 0
+#define CSR_SEQUENCEREG0B92S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B92S1 */
+#define CSR_SEQUENCEREG0B92S1_LSB 0
+#define CSR_SEQUENCEREG0B92S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B92S2 */
+#define CSR_SEQUENCEREG0B92S2_LSB 0
+#define CSR_SEQUENCEREG0B92S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B93S0 */
+#define CSR_SEQUENCEREG0B93S0_LSB 0
+#define CSR_SEQUENCEREG0B93S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B93S1 */
+#define CSR_SEQUENCEREG0B93S1_LSB 0
+#define CSR_SEQUENCEREG0B93S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B93S2 */
+#define CSR_SEQUENCEREG0B93S2_LSB 0
+#define CSR_SEQUENCEREG0B93S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B94S0 */
+#define CSR_SEQUENCEREG0B94S0_LSB 0
+#define CSR_SEQUENCEREG0B94S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B94S1 */
+#define CSR_SEQUENCEREG0B94S1_LSB 0
+#define CSR_SEQUENCEREG0B94S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B94S2 */
+#define CSR_SEQUENCEREG0B94S2_LSB 0
+#define CSR_SEQUENCEREG0B94S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B95S0 */
+#define CSR_SEQUENCEREG0B95S0_LSB 0
+#define CSR_SEQUENCEREG0B95S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B95S1 */
+#define CSR_SEQUENCEREG0B95S1_LSB 0
+#define CSR_SEQUENCEREG0B95S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B95S2 */
+#define CSR_SEQUENCEREG0B95S2_LSB 0
+#define CSR_SEQUENCEREG0B95S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B96S0 */
+#define CSR_SEQUENCEREG0B96S0_LSB 0
+#define CSR_SEQUENCEREG0B96S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B96S1 */
+#define CSR_SEQUENCEREG0B96S1_LSB 0
+#define CSR_SEQUENCEREG0B96S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B96S2 */
+#define CSR_SEQUENCEREG0B96S2_LSB 0
+#define CSR_SEQUENCEREG0B96S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B97S0 */
+#define CSR_SEQUENCEREG0B97S0_LSB 0
+#define CSR_SEQUENCEREG0B97S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B97S1 */
+#define CSR_SEQUENCEREG0B97S1_LSB 0
+#define CSR_SEQUENCEREG0B97S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B97S2 */
+#define CSR_SEQUENCEREG0B97S2_LSB 0
+#define CSR_SEQUENCEREG0B97S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B98S0 */
+#define CSR_SEQUENCEREG0B98S0_LSB 0
+#define CSR_SEQUENCEREG0B98S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B98S1 */
+#define CSR_SEQUENCEREG0B98S1_LSB 0
+#define CSR_SEQUENCEREG0B98S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B98S2 */
+#define CSR_SEQUENCEREG0B98S2_LSB 0
+#define CSR_SEQUENCEREG0B98S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B99S0 */
+#define CSR_SEQUENCEREG0B99S0_LSB 0
+#define CSR_SEQUENCEREG0B99S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B99S1 */
+#define CSR_SEQUENCEREG0B99S1_LSB 0
+#define CSR_SEQUENCEREG0B99S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B99S2 */
+#define CSR_SEQUENCEREG0B99S2_LSB 0
+#define CSR_SEQUENCEREG0B99S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B100S0 */
+#define CSR_SEQUENCEREG0B100S0_LSB 0
+#define CSR_SEQUENCEREG0B100S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B100S1 */
+#define CSR_SEQUENCEREG0B100S1_LSB 0
+#define CSR_SEQUENCEREG0B100S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B100S2 */
+#define CSR_SEQUENCEREG0B100S2_LSB 0
+#define CSR_SEQUENCEREG0B100S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B101S0 */
+#define CSR_SEQUENCEREG0B101S0_LSB 0
+#define CSR_SEQUENCEREG0B101S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B101S1 */
+#define CSR_SEQUENCEREG0B101S1_LSB 0
+#define CSR_SEQUENCEREG0B101S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B101S2 */
+#define CSR_SEQUENCEREG0B101S2_LSB 0
+#define CSR_SEQUENCEREG0B101S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B102S0 */
+#define CSR_SEQUENCEREG0B102S0_LSB 0
+#define CSR_SEQUENCEREG0B102S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B102S1 */
+#define CSR_SEQUENCEREG0B102S1_LSB 0
+#define CSR_SEQUENCEREG0B102S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B102S2 */
+#define CSR_SEQUENCEREG0B102S2_LSB 0
+#define CSR_SEQUENCEREG0B102S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B103S0 */
+#define CSR_SEQUENCEREG0B103S0_LSB 0
+#define CSR_SEQUENCEREG0B103S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B103S1 */
+#define CSR_SEQUENCEREG0B103S1_LSB 0
+#define CSR_SEQUENCEREG0B103S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B103S2 */
+#define CSR_SEQUENCEREG0B103S2_LSB 0
+#define CSR_SEQUENCEREG0B103S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B104S0 */
+#define CSR_SEQUENCEREG0B104S0_LSB 0
+#define CSR_SEQUENCEREG0B104S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B104S1 */
+#define CSR_SEQUENCEREG0B104S1_LSB 0
+#define CSR_SEQUENCEREG0B104S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B104S2 */
+#define CSR_SEQUENCEREG0B104S2_LSB 0
+#define CSR_SEQUENCEREG0B104S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B105S0 */
+#define CSR_SEQUENCEREG0B105S0_LSB 0
+#define CSR_SEQUENCEREG0B105S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B105S1 */
+#define CSR_SEQUENCEREG0B105S1_LSB 0
+#define CSR_SEQUENCEREG0B105S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B105S2 */
+#define CSR_SEQUENCEREG0B105S2_LSB 0
+#define CSR_SEQUENCEREG0B105S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B106S0 */
+#define CSR_SEQUENCEREG0B106S0_LSB 0
+#define CSR_SEQUENCEREG0B106S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B106S1 */
+#define CSR_SEQUENCEREG0B106S1_LSB 0
+#define CSR_SEQUENCEREG0B106S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B106S2 */
+#define CSR_SEQUENCEREG0B106S2_LSB 0
+#define CSR_SEQUENCEREG0B106S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B107S0 */
+#define CSR_SEQUENCEREG0B107S0_LSB 0
+#define CSR_SEQUENCEREG0B107S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B107S1 */
+#define CSR_SEQUENCEREG0B107S1_LSB 0
+#define CSR_SEQUENCEREG0B107S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B107S2 */
+#define CSR_SEQUENCEREG0B107S2_LSB 0
+#define CSR_SEQUENCEREG0B107S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B108S0 */
+#define CSR_SEQUENCEREG0B108S0_LSB 0
+#define CSR_SEQUENCEREG0B108S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B108S1 */
+#define CSR_SEQUENCEREG0B108S1_LSB 0
+#define CSR_SEQUENCEREG0B108S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B108S2 */
+#define CSR_SEQUENCEREG0B108S2_LSB 0
+#define CSR_SEQUENCEREG0B108S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B109S0 */
+#define CSR_SEQUENCEREG0B109S0_LSB 0
+#define CSR_SEQUENCEREG0B109S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B109S1 */
+#define CSR_SEQUENCEREG0B109S1_LSB 0
+#define CSR_SEQUENCEREG0B109S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B109S2 */
+#define CSR_SEQUENCEREG0B109S2_LSB 0
+#define CSR_SEQUENCEREG0B109S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B110S0 */
+#define CSR_SEQUENCEREG0B110S0_LSB 0
+#define CSR_SEQUENCEREG0B110S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B110S1 */
+#define CSR_SEQUENCEREG0B110S1_LSB 0
+#define CSR_SEQUENCEREG0B110S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B110S2 */
+#define CSR_SEQUENCEREG0B110S2_LSB 0
+#define CSR_SEQUENCEREG0B110S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B111S0 */
+#define CSR_SEQUENCEREG0B111S0_LSB 0
+#define CSR_SEQUENCEREG0B111S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B111S1 */
+#define CSR_SEQUENCEREG0B111S1_LSB 0
+#define CSR_SEQUENCEREG0B111S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B111S2 */
+#define CSR_SEQUENCEREG0B111S2_LSB 0
+#define CSR_SEQUENCEREG0B111S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B112S0 */
+#define CSR_SEQUENCEREG0B112S0_LSB 0
+#define CSR_SEQUENCEREG0B112S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B112S1 */
+#define CSR_SEQUENCEREG0B112S1_LSB 0
+#define CSR_SEQUENCEREG0B112S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B112S2 */
+#define CSR_SEQUENCEREG0B112S2_LSB 0
+#define CSR_SEQUENCEREG0B112S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B113S0 */
+#define CSR_SEQUENCEREG0B113S0_LSB 0
+#define CSR_SEQUENCEREG0B113S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B113S1 */
+#define CSR_SEQUENCEREG0B113S1_LSB 0
+#define CSR_SEQUENCEREG0B113S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B113S2 */
+#define CSR_SEQUENCEREG0B113S2_LSB 0
+#define CSR_SEQUENCEREG0B113S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B114S0 */
+#define CSR_SEQUENCEREG0B114S0_LSB 0
+#define CSR_SEQUENCEREG0B114S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B114S1 */
+#define CSR_SEQUENCEREG0B114S1_LSB 0
+#define CSR_SEQUENCEREG0B114S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B114S2 */
+#define CSR_SEQUENCEREG0B114S2_LSB 0
+#define CSR_SEQUENCEREG0B114S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B115S0 */
+#define CSR_SEQUENCEREG0B115S0_LSB 0
+#define CSR_SEQUENCEREG0B115S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B115S1 */
+#define CSR_SEQUENCEREG0B115S1_LSB 0
+#define CSR_SEQUENCEREG0B115S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B115S2 */
+#define CSR_SEQUENCEREG0B115S2_LSB 0
+#define CSR_SEQUENCEREG0B115S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B116S0 */
+#define CSR_SEQUENCEREG0B116S0_LSB 0
+#define CSR_SEQUENCEREG0B116S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B116S1 */
+#define CSR_SEQUENCEREG0B116S1_LSB 0
+#define CSR_SEQUENCEREG0B116S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B116S2 */
+#define CSR_SEQUENCEREG0B116S2_LSB 0
+#define CSR_SEQUENCEREG0B116S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B117S0 */
+#define CSR_SEQUENCEREG0B117S0_LSB 0
+#define CSR_SEQUENCEREG0B117S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B117S1 */
+#define CSR_SEQUENCEREG0B117S1_LSB 0
+#define CSR_SEQUENCEREG0B117S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B117S2 */
+#define CSR_SEQUENCEREG0B117S2_LSB 0
+#define CSR_SEQUENCEREG0B117S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B118S0 */
+#define CSR_SEQUENCEREG0B118S0_LSB 0
+#define CSR_SEQUENCEREG0B118S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B118S1 */
+#define CSR_SEQUENCEREG0B118S1_LSB 0
+#define CSR_SEQUENCEREG0B118S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B118S2 */
+#define CSR_SEQUENCEREG0B118S2_LSB 0
+#define CSR_SEQUENCEREG0B118S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B119S0 */
+#define CSR_SEQUENCEREG0B119S0_LSB 0
+#define CSR_SEQUENCEREG0B119S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B119S1 */
+#define CSR_SEQUENCEREG0B119S1_LSB 0
+#define CSR_SEQUENCEREG0B119S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B119S2 */
+#define CSR_SEQUENCEREG0B119S2_LSB 0
+#define CSR_SEQUENCEREG0B119S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B120S0 */
+#define CSR_SEQUENCEREG0B120S0_LSB 0
+#define CSR_SEQUENCEREG0B120S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B120S1 */
+#define CSR_SEQUENCEREG0B120S1_LSB 0
+#define CSR_SEQUENCEREG0B120S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B120S2 */
+#define CSR_SEQUENCEREG0B120S2_LSB 0
+#define CSR_SEQUENCEREG0B120S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQUENCEREG0B121S0 */
+#define CSR_SEQUENCEREG0B121S0_LSB 0
+#define CSR_SEQUENCEREG0B121S0_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B121S1 */
+#define CSR_SEQUENCEREG0B121S1_LSB 0
+#define CSR_SEQUENCEREG0B121S1_MASK GENMASK_32(15, 0)
+/* CSR_SEQUENCEREG0B121S2 */
+#define CSR_SEQUENCEREG0B121S2_LSB 0
+#define CSR_SEQUENCEREG0B121S2_MASK GENMASK_32(8, 0)
+/* CSR_SEQ0BGPR1 */
+#define CSR_SEQ0BGPR1_LSB 0
+#define CSR_SEQ0BGPR1_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR2 */
+#define CSR_SEQ0BGPR2_LSB 0
+#define CSR_SEQ0BGPR2_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR3 */
+#define CSR_SEQ0BGPR3_LSB 0
+#define CSR_SEQ0BGPR3_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR4 */
+#define CSR_SEQ0BGPR4_LSB 0
+#define CSR_SEQ0BGPR4_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR5 */
+#define CSR_SEQ0BGPR5_LSB 0
+#define CSR_SEQ0BGPR5_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR6 */
+#define CSR_SEQ0BGPR6_LSB 0
+#define CSR_SEQ0BGPR6_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR7 */
+#define CSR_SEQ0BGPR7_LSB 0
+#define CSR_SEQ0BGPR7_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BGPR8 */
+#define CSR_SEQ0BGPR8_LSB 0
+#define CSR_SEQ0BGPR8_MASK GENMASK_32(15, 0)
+/* CSR_SEQ0BFIXEDADDRBITS */
+#define CSR_SEQ0BFIXEDADDRBITS_LSB 0
+#define CSR_SEQ0BFIXEDADDRBITS_MASK GENMASK_32(6, 0)
+#define CSR_SEQ0BCHIPLETBITS_LSB 0
+#define CSR_SEQ0BCHIPLETBITS_MASK GENMASK_32(3, 0)
+#define CSR_SEQ0BPSTATEBITS_LSB 4
+#define CSR_SEQ0BPSTATEBITS_MASK GENMASK_32(6, 4)
+
+/* DRTUB0 register offsets */
+/* CSR_DCTSHADOWREGS */
+#define CSR_DCTSHADOWREGS_LSB 0
+#define CSR_DCTSHADOWREGS_MASK BIT(0)
+#define CSR_DCTWRITEPROTSHADOW_LSB 0
+#define CSR_DCTWRITEPROTSHADOW_MASK BIT(0)
+/* CSR_DCTWRITEONLYSHADOW */
+#define CSR_DCTWRITEONLYSHADOW_LSB 0
+#define CSR_DCTWRITEONLYSHADOW_MASK GENMASK_32(15, 0)
+/* CSR_UCTWRITEONLY */
+#define CSR_UCTWRITEONLY_LSB 0
+#define CSR_UCTWRITEONLY_MASK GENMASK_32(15, 0)
+/* CSR_UCTWRITEPROT */
+#define CSR_UCTWRITEPROT_LSB 0
+#define CSR_UCTWRITEPROT_MASK BIT(0)
+/* CSR_UCTDATWRITEONLY */
+#define CSR_UCTDATWRITEONLY_LSB 0
+#define CSR_UCTDATWRITEONLY_MASK GENMASK_32(15, 0)
+/* CSR_UCTDATWRITEPROT */
+#define CSR_UCTDATWRITEPROT_LSB 0
+#define CSR_UCTDATWRITEPROT_MASK BIT(0)
+/* CSR_UCTLERR */
+#define CSR_UCTLERR_LSB 0
+#define CSR_UCTLERR_MASK BIT(0)
+/* CSR_UCCLKHCLKENABLES */
+#define CSR_UCCLKHCLKENABLES_LSB 0
+#define CSR_UCCLKHCLKENABLES_MASK GENMASK_32(1, 0)
+#define CSR_UCCLKEN_LSB 0
+#define CSR_UCCLKEN_MASK BIT(0)
+#define CSR_HCLKEN_LSB 1
+#define CSR_HCLKEN_MASK BIT(1)
+/* CSR_CURPSTATE0B */
+#define CSR_CURPSTATE0B_LSB 0
+#define CSR_CURPSTATE0B_MASK GENMASK_32(3, 0)
+/* CSR_CLRWAKEUPSTICKY */
+#define CSR_CLRWAKEUPSTICKY_LSB 0
+#define CSR_CLRWAKEUPSTICKY_MASK GENMASK_32(3, 0)
+/* CSR_WAKEUPMASK */
+#define CSR_WAKEUPMASK_LSB 0
+#define CSR_WAKEUPMASK_MASK GENMASK_32(3, 0)
+/* CSR_CUSTPUBREV */
+#define CSR_CUSTPUBREV_LSB 0
+#define CSR_CUSTPUBREV_MASK GENMASK_32(5, 0)
+/* CSR_PUBREV */
+#define CSR_PUBREV_LSB 0
+#define CSR_PUBREV_MASK GENMASK_32(15, 0)
+#define CSR_RESERVEDPUBREV_LSB 0
+#define CSR_RESERVEDPUBREV_MASK GENMASK_32(3, 0)
+#define CSR_PUBMNR_LSB 4
+#define CSR_PUBMNR_MASK GENMASK_32(7, 4)
+#define CSR_PUBMDR_LSB 8
+#define CSR_PUBMDR_MASK GENMASK_32(11, 8)
+#define CSR_PUBMJR_LSB 12
+#define CSR_PUBMJR_MASK GENMASK_32(15, 12)
+
+/* APBONLY0 register offsets */
+/* CSR_MICROCONTMUXSEL */
+#define CSR_MICROCONTMUXSEL_LSB 0
+#define CSR_MICROCONTMUXSEL_MASK BIT(0)
+/* CSR_UCTSHADOWREGS */
+#define CSR_UCTSHADOWREGS_LSB 0
+#define CSR_UCTSHADOWREGS_MASK GENMASK_32(1, 0)
+#define CSR_UCTWRITEPROTSHADOW_LSB 0
+#define CSR_UCTWRITEPROTSHADOW_MASK BIT(0)
+#define CSR_UCTDATWRITEPROTSHADOW_LSB 1
+#define CSR_UCTDATWRITEPROTSHADOW_MASK BIT(1)
+/* CSR_DCTWRITEONLY */
+#define CSR_DCTWRITEONLY_LSB 0
+#define CSR_DCTWRITEONLY_MASK GENMASK_32(15, 0)
+/* CSR_DCTWRITEPROT */
+#define CSR_DCTWRITEPROT_LSB 0
+#define CSR_DCTWRITEPROT_MASK BIT(0)
+/* CSR_UCTWRITEONLYSHADOW */
+#define CSR_UCTWRITEONLYSHADOW_LSB 0
+#define CSR_UCTWRITEONLYSHADOW_MASK GENMASK_32(15, 0)
+/* CSR_UCTDATWRITEONLYSHADOW */
+#define CSR_UCTDATWRITEONLYSHADOW_LSB 0
+#define CSR_UCTDATWRITEONLYSHADOW_MASK GENMASK_32(15, 0)
+/* CSR_NEVERGATECSRCLOCK */
+#define CSR_NEVERGATECSRCLOCK_LSB 0
+#define CSR_NEVERGATECSRCLOCK_MASK BIT(0)
+/* CSR_DFICFGRDDATAVALIDTICKS */
+#define CSR_DFICFGRDDATAVALIDTICKS_LSB 0
+#define CSR_DFICFGRDDATAVALIDTICKS_MASK GENMASK_32(5, 0)
+/* CSR_MICRORESET */
+#define CSR_MICRORESET_LSB 0
+#define CSR_MICRORESET_MASK GENMASK_32(3, 0)
+#define CSR_STALLTOMICRO_LSB 0
+#define CSR_STALLTOMICRO_MASK BIT(0)
+#define CSR_TESTWAKEUP_LSB 1
+#define CSR_TESTWAKEUP_MASK BIT(1)
+#define CSR_RSVDMICRO_LSB 2
+#define CSR_RSVDMICRO_MASK BIT(2)
+#define CSR_RESETTOMICRO_LSB 3
+#define CSR_RESETTOMICRO_MASK BIT(3)
+/* CSR_SEQUENCEROVERRIDE */
+#define CSR_SEQUENCEROVERRIDE_LSB 0
+#define CSR_SEQUENCEROVERRIDE_MASK GENMASK_32(10, 0)
+#define CSR_FORCESEQ0BDFIFREQ_LSB 0
+#define CSR_FORCESEQ0BDFIFREQ_MASK GENMASK_32(4, 0)
+#define CSR_FORCESEQ0BSTART_LSB 5
+#define CSR_FORCESEQ0BSTART_MASK BIT(5)
+#define CSR_FORCESEQ0BSTOP_LSB 6
+#define CSR_FORCESEQ0BSTOP_MASK BIT(6)
+#define CSR_BLOCKSEQ0BREQUESTS_LSB 7
+#define CSR_BLOCKSEQ0BREQUESTS_MASK BIT(7)
+#define CSR_BLOCKSEQ0BACK_LSB 8
+#define CSR_BLOCKSEQ0BACK_MASK BIT(8)
+#define CSR_DISABLETERMINATEFLAG_LSB 9
+#define CSR_DISABLETERMINATEFLAG_MASK BIT(9)
+#define CSR_SELECTDFIFREQTOGPRMUX_LSB 10
+#define CSR_SELECTDFIFREQTOGPRMUX_MASK BIT(10)
+/* CSR_DFIINITCOMPLETESHADOW */
+#define CSR_DFIINITCOMPLETESHADOW_LSB 0
+#define CSR_DFIINITCOMPLETESHADOW_MASK BIT(0)
+
+/* Fields brought to you by the letter B */
+#define B_MIN 0U
+#define B_MAX 1U
+#define B0 0x0U
+#define B1 0x100U
+#define BBRD 0xF00U
+#define BB_MIN 0U
+#define BB_MAX 15U
+#define BB0 0x0U
+#define BB1 0x1000U
+#define BB2 0x2000U
+#define BB3 0x3000U
+#define BB4 0x4000U
+#define BB5 0x5000U
+#define BB6 0x6000U
+#define BB7 0x7000U
+#define BB8 0x8000U
+#define BB9 0x9000U
+#define BB10 0xA000U
+#define BB11 0xB000U
+#define BB12 0xC000U
+#define BB13 0xD000U
+#define BB14 0xE000U
+#define BB15 0xF000U
+#define BBBRD 0xF000U
+/* Fields brought to you by the letter C */
+#define C_MIN 0U
+#define C_MAX 15U
+#define C0 0x0U
+#define C1 0x1000U
+#define C2 0x2000U
+#define C3 0x3000U
+#define C4 0x4000U
+#define C5 0x5000U
+#define C6 0x6000U
+#define C7 0x7000U
+#define C8 0x8000U
+#define C9 0x9000U
+#define C10 0xA000U
+#define C11 0xB000U
+#define C12 0xC000U
+#define C13 0xD000U
+#define C14 0xE000U
+#define C15 0xF000U
+#define CBRD 0xF000U
+/* Fields brought to you by the letter D */
+#define D_MIN 0U
+#define D_MAX 3U
+#define D0 0x0U
+#define D1 0x100U
+#define D2 0x200U
+#define D3 0x300U
+#define DBRD 0xF00U
+/* Fields brought to you by the letter I */
+#define I_MIN 0U
+#define I_MAX 8U
+#define I0 0x0U
+#define I1 0x100U
+#define I2 0x200U
+#define I3 0x300U
+#define I4 0x400U
+#define I5 0x500U
+#define I6 0x600U
+#define I7 0x700U
+#define I8 0x800U
+#define IBRD 0xF00U
+/* Fields brought to you by the letter J */
+#define J_MIN 0U
+#define J_MAX 0U
+#define J0 0x0U
+#define JBRD 0xF00U
+/* Fields brought to you by the letter L */
+#define L_MIN 0U
+#define L_MAX 13U
+#define L0 0x0U
+#define L1 0x100U
+#define L2 0x200U
+#define L3 0x300U
+#define L4 0x400U
+#define L5 0x500U
+#define L6 0x600U
+#define L7 0x700U
+#define L8 0x800U
+#define L9 0x900U
+#define L10 0xA00U
+#define L11 0xB00U
+#define L12 0xC00U
+#define L13 0xD00U
+#define LBRD 0xF00U
+/* Fields brought to you by the letter M */
+#define M_MIN 0U
+#define M_MAX 8U
+#define M0 0x0U
+#define M1 0x100U
+#define M2 0x200U
+#define M3 0x300U
+#define M4 0x400U
+#define M5 0x500U
+#define M6 0x600U
+#define M7 0x700U
+#define M8 0x800U
+#define MBRD 0xF00U
+/* Fields brought to you by the letter N */
+#define N_MIN 0U
+#define N_MAX 15U
+#define N0 0x0U
+#define N1 0x100U
+#define N2 0x200U
+#define N3 0x300U
+#define N4 0x400U
+#define N5 0x500U
+#define N6 0x600U
+#define N7 0x700U
+#define N8 0x800U
+#define N9 0x900U
+#define N10 0xA00U
+#define N11 0xB00U
+#define N12 0xC00U
+#define N13 0xD00U
+#define N14 0xE00U
+#define N15 0xF00U
+#define NBRD 0xF00U
+/* Fields brought to you by the letter P */
+#define P_MIN 0U
+#define P_MAX 3U
+#define P0 0x0U
+#define P1 0x100000U
+#define P2 0x200000U
+#define P3 0x300000U
+#define PBRD 0x700000U
+#define PP_MIN 0U
+#define PP_MAX 3U
+#define PP0 0x0U
+#define PP1 0x100000U
+#define PP2 0x200000U
+#define PP3 0x300000U
+#define PPBRD 0x700000U
+/* Fields brought to you by the letter Q */
+#define Q_MIN 0U
+#define Q_MAX 3U
+#define Q0 0x0U
+#define Q1 0x100000U
+#define Q2 0x200000U
+#define Q3 0x300000U
+#define QBRD 0x700000U
+/* Fields brought to you by the letter R */
+#define R_MIN 0U
+#define R_MAX 8U
+#define R0 0x0U
+#define R1 0x100U
+#define R2 0x200U
+#define R3 0x300U
+#define R4 0x400U
+#define R5 0x500U
+#define R6 0x600U
+#define R7 0x700U
+#define R8 0x800U
+#define RBRD 0xF00U
+/* Fields brought to you by the letter T */
+#define T_MIN 0U
+#define T_MAX 15U
+#define T0 0x0U
+#define T1 0x10000U
+#define T2 0x20000U
+#define T3 0x30000U
+#define T4 0x40000U
+#define T5 0x50000U
+#define T6 0x60000U
+#define T7 0x70000U
+#define T8 0x80000U
+#define T9 0x90000U
+#define T10 0xA0000U
+#define T11 0xB0000U
+#define T12 0xC0000U
+#define T13 0xD0000U
+#define T14 0xE0000U
+#define T15 0xF0000U
+#define TBRD 0xF0000U
+/* Fields brought to you by the letter U */
+#define U_MIN 0U
+#define U_MAX 1U
+#define U0 0x0U
+#define U1 0x100U
+#define UBRD 0xF00U
+/* Fields brought to you by the letter Y */
+#define Y_MIN 0U
+#define Y_MAX 0U
+#define Y0 0x0U
+#define YBRD 0xF000000U
+
+#define TACSM 0x40000U
+#define TACSMBRD 0x4F000U
+#define TALL 0xF0000U
+#define TALLBRD 0xFF000U
+#define TANIB 0x0U
+#define TANIBBRD 0xF000U
+#define TAPBONLY 0xD0000U
+#define TAPBONLYBRD 0xDF000U
+#define TDBYTE 0x10000U
+#define TDBYTEBRD 0x1F000U
+#define TDRTUB 0xC0000U
+#define TDRTUBBRD 0xCF000U
+#define TINITENG 0x90000U
+#define TINITENGBRD 0x9F000U
+#define TMASTER 0x20000U
+#define TMASTERBRD 0x2F000U
+#define TPPGC 0x70000U
+#define TPPGCBRD 0x7F000U
+#define TUCTL_MEM 0x50000U
+#define TUCTL_MEMBRD 0x5F000U
+
+#define DBYTE_NUM 9U
+#define ANIB_NUM 12U
+
+#endif /* DDRPHY_PHYINIT_CSR_ALL_DEFINES_H */
diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit.h
new file mode 100644
index 0000000..acd7072
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DDRPHY_PHYINIT_H
+#define DDRPHY_PHYINIT_H
+
+#include <stdbool.h>
+
+#include <ddrphy_phyinit_usercustom.h>
+
+enum message_block_field {
+ MB_FIELD_PSTATE,
+ MB_FIELD_PLLBYPASSEN,
+ MB_FIELD_DRAMFREQ,
+ MB_FIELD_DFIFREQRATIO,
+ MB_FIELD_BPZNRESVAL,
+ MB_FIELD_PHYODTIMPEDANCE,
+ MB_FIELD_PHYDRVIMPEDANCE,
+ MB_FIELD_DRAMTYPE,
+ MB_FIELD_DISABLEDDBYTE,
+ MB_FIELD_ENABLEDDQS,
+ MB_FIELD_PHYCFG,
+ MB_FIELD_X16PRESENT,
+ MB_FIELD_ENABLEDDQSCHA,
+ MB_FIELD_CSPRESENTCHA,
+ MB_FIELD_ENABLEDDQSCHB,
+ MB_FIELD_CSPRESENTCHB,
+};
+
+/* Function definitions */
+int ddrphy_phyinit_softsetmb(struct pmu_smb_ddr_1d *mb_ddr_1d, enum message_block_field field,
+ uint32_t value);
+void ddrphy_phyinit_initstruct(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
+#endif /* DDRPHY_PHYINIT_H */
diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_struct.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_struct.h
new file mode 100644
index 0000000..ae34c0c
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_struct.h
@@ -0,0 +1,786 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DDRPHY_PHYINIT_STRUCT_H
+#define DDRPHY_PHYINIT_STRUCT_H
+
+/* This file defines the internal data structures used in PhyInit to store user configuration */
+
+/* DIMM Type definitions */
+#define DDR_DIMMTYPE_NODIMM 4U /* No DIMM (Soldered-on) */
+
+/*
+ * Structure for basic user inputs
+ *
+ * The following basic data structure must be set and completed correctly so
+ * that the PhyInit software package can accurate program PHY registers.
+ */
+struct user_input_basic {
+ uint32_t dramtype; /*
+ * DRAM module type.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | DDR4
+ * 0x1 | DDR3
+ * 0x2 | LPDDR4
+ */
+
+ uint32_t dimmtype; /*
+ * DIMM type.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x4 | No DIMM (Soldered-on) (DDR_DIMMTYPE_NODIMM)
+ */
+
+ uint32_t lp4xmode; /*
+ * LPDDR4X mode support.
+ * Only used for LPDDR4, but not valid here.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | LPDDR4 mode, when dramtype is LPDDR4
+ */
+
+ uint32_t numdbyte; /* Number of dbytes physically instantiated */
+
+ uint32_t numactivedbytedfi0; /* Number of active dbytes to be controlled by dfi0 */
+
+ uint32_t numactivedbytedfi1; /*
+ * Number of active dbytes to be controlled by dfi1.
+ * Only used for LPDDR4.
+ */
+
+ uint32_t numanib; /* Number of ANIBs physically instantiated */
+
+ uint32_t numrank_dfi0; /* Number of ranks in DFI0 channel */
+
+ uint32_t numrank_dfi1; /* Number of ranks in DFI1 channel (if DFI1 exists) */
+
+ uint32_t dramdatawidth; /*
+ * Width of the DRAM device.
+ *
+ * Enter 4,8,16 or 32 depending on protocol and dram type
+ * according below table.
+ *
+ * Protocol | Valid Options | Default
+ * -------- | ------------- | ---
+ * DDR3 | 4,8,16 | 8
+ * DDR4 | 4,8,16 | 8
+ * LPDDR4 | 8,16 | 16
+ *
+ * For mixed x8 and x16 width devices, set variable to x8.
+ */
+
+ uint32_t numpstates; /* Number of p-states used. Must be set to 1 */
+
+ uint32_t frequency; /*
+ * Memclk frequency for each PState.
+ * Memclk frequency in MHz round up to next highest integer.
+ * Enter 334 for 333.333, etc.
+ */
+
+ uint32_t pllbypass; /*
+ * Indicates if PLL should be in Bypass mode.
+ * If DDR datarate < 333, PLL must be in Bypass Mode.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x1 | Enabled
+ * 0x0 | Disabled
+ */
+
+ uint32_t dfifreqratio; /*
+ * Selected Dfi Frequency ratio.
+ * Used to program the dfifreqratio register. This register
+ * controls how dfi_freq_ratio input pin should be driven
+ * inaccordance with DFI Spec.
+ *
+ * Binary Value | Description
+ * ----- | ------
+ * 2'b01 | 1:2 DFI Frequency Ratio (default)
+ */
+
+ uint32_t dfi1exists; /* Indicates if the PHY configuration has Dfi1 channel */
+
+ uint32_t train2d; /* Obsolete. Not used. */
+
+ uint32_t hardmacrover; /*
+ * Hard Macro Family version in use.
+ *
+ * Value | Description
+ * ----- | ------
+ * 3 | hardmacro family D
+ */
+
+ uint32_t readdbienable; /* Obsolete. Not Used. */
+
+ uint32_t dfimode; /* Obsolete. Not Used. */
+};
+
+/*
+ * Structure for advanced user inputs
+ */
+struct user_input_advanced {
+ uint32_t lp4rxpreamblemode; /*
+ * Selects between DRAM read static vs toggle preamble.
+ * Determine desired DRAM Read Preamble Mode based on SI
+ * Analysis and DRAM Part in use.
+ * The PHY training firmware will program DRAM mr1-OP[3]
+ * after training based on setting.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x1 | toggling preamble
+ * 0x0 | static preamble
+ */
+
+ uint32_t lp4postambleext; /*
+ * Extend write postamble in LPDDR4.
+ * Only used for LPDDR4.
+ * This variable is used to calculate LPDDR4 mr3-OP[1] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Set value according to your SI analysis and DRAM
+ * requirement.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | half Memclk postamble
+ * 0x1 | 1.5 Memclk postabmle (default)
+ */
+
+ uint32_t d4rxpreamblelength; /*
+ * Length of read preamble in DDR4 mode.
+ * Only used for DDR4.
+ * This variable is used to calculate DDR4 mr4-OP[11] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Set value according to your SI analysis and DRAM
+ * requirement.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | 1 Tck
+ * 0x1 | 2 Tck (default)
+ */
+
+ uint32_t d4txpreamblelength; /*
+ * Length of write preamble in DDR4 mode.
+ * Only used for DDR4.
+ * This variable is used to calculate DDR4 mr4-OP[12] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Set value according to your SI analysis and DRAM
+ * requirement.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | 1 Tck (default)
+ * 0x1 | 2 Tck
+ */
+
+ uint32_t extcalresval; /*
+ * External Impedance calibration pull-down resistor value
+ * select.
+ * Indicates value of impedance calibration pull-down
+ * resistor connected to BP_ZN pin of the PHY.
+ * Value | Description
+ * ----- | ------
+ * 0x0 | 240 ohm (default)
+ */
+
+ uint32_t is2ttiming; /*
+ * Set to 1 to use 2T timing for address/command, otherwise
+ * 1T timing will be used.
+ * Determine 1T or 2T Timing operation mode based on SI
+ * Analysis and DRAM Timing.
+ * - In 1T mode, CK, CS, CA all have the same nominal
+ * timing, ie. ATxDly[6:0] will have same value for all
+ * ANIBs.
+ * - In 2T mode, CK, CS,have the same nominal timing
+ * (e.g. AtxDly[6:0]=0x00), while CA is delayed by 1UI
+ * (e.g. ATxDly[6:0]=0x40)
+ * Used to program phycfg setting in messageBlock.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | 1T Timing (default)
+ * 0x1 | 2T Timing
+ */
+
+ uint32_t odtimpedance; /*
+ * ODT impedance in ohm.
+ * Used for programming TxOdtDrvStren registers.
+ * Enter 0 for open/high-impedance.
+ * Default value: 60
+ */
+
+ uint32_t tximpedance; /*
+ * Tx Drive Impedance for DQ/DQS in ohm.
+ * Used for programming TxImpedanceCtrl1 registers.
+ * Enter 0 for open/high-impedance.
+ * Default value: 60
+ */
+
+ uint32_t atximpedance; /*
+ * Tx Drive Impedance for AC in ohm.
+ * Used for programming ATxImpedance register.
+ * Enter 0 for open/high-impedance
+ * Default value: 20 (HMA,HMB,HMC,HMD), 40 (HME)
+ */
+
+ uint32_t memalerten; /*
+ * Enables BP_ALERT programming of PHY registers.
+ * Only used for DDR3 and DDR4.
+ * Used for programming MemAlertControl and MemAlertControl2
+ * registers.
+ * Program if you require using BP_ALERT pin (to receive or
+ * terminate signal) of the PHY otherwise leave at default
+ * value to save power.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | Disable BP_ALERT (default)
+ */
+
+ uint32_t memalertpuimp; /*
+ * Specify MemAlert Pull-up Termination Impedance.
+ * Programs the pull-up termination on BP_ALERT.
+ * Not valid here (fixed 0 value).
+ */
+
+ uint32_t memalertvreflevel; /*
+ * Specify the Vref level for BP_ALERT(MemAlert) Receiver.
+ * Not valid here (fixed 0 value).
+ */
+
+ uint32_t memalertsyncbypass; /*
+ * When set, this bit bypasses the DfiClk synchronizer on
+ * dfi_alert_n.
+ * Not valid here (fixed 0 value).
+ */
+
+ uint32_t disdynadrtri; /*
+ * Disable Dynamic Per-MEMCLK Address Tristate feature.
+ * Program this variable if you require to disable this
+ * feature.
+ * - In DDR3/2T and DDR4/2T/2N modes, the dynamic tristate
+ * feature should be disabled if the controller cannot
+ * follow the 2T PHY tristate protocol.
+ * - In LPDDR4 mode, the dynamic tristate feature should
+ * be disabled.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x1 | Disable Dynamic Tristate
+ */
+
+ uint32_t phymstrtraininterval; /*
+ * Specifies the how frequent dfi_phymstr_req is issued by
+ * PHY.
+ * Only required in LPDDR4.
+ * Based on SI analysis determine how frequent DRAM drift
+ * compensation and re-training is required.
+ * Determine if Memory controller supports DFI PHY Master
+ * Interface.
+ * Program based on desired setting for
+ * PPTTrainSetup.PhyMstrTrainInterval register.
+ * Default value: 0xa
+ *
+ * Example:
+ * Value | Description
+ * ----- | ------
+ * 0xa | PPT Train Interval = 268435456 MEMCLKs (default)
+ */
+
+ uint32_t phymstrmaxreqtoack; /*
+ * Max time from dfi_phymstr_req asserted to dfi_phymstr_ack
+ * asserted.
+ * Only required in LPDDR4.
+ * Based on your Memory controller's(MC) specification
+ * determine how long the PHY should wait for the assertion
+ * of dfi_phymstr_ack once dfi_phymstr_req has been issued
+ * by the PHY. If the MC does not ack the PHY's request, PHY
+ * may issue dfi_error.
+ * This value will be used to program
+ * PPTTrainSetup.PhyMstrMaxReqToAck register.
+ * Default value: 0x5
+ *
+ * Example:
+ * Value | Description
+ * ----- | ------
+ * 0x5 | PPT Max. Req to Ack. = 8192 MEMCLKs (default)
+ */
+
+ uint32_t wdqsext; /*
+ * Enable Write DQS Extension feature of PHY.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | Disable Write DQS Extension feature. (default)
+ * 0x1 | Enable Write DQS Extension feature.
+ */
+
+ uint32_t calinterval; /*
+ * Specifies the interval between successive calibrations,
+ * in mS.
+ * Program variable based on desired setting for
+ * CalRate.CalInterval register.
+ * - Fixed 0x9 value (20mS interval)
+ */
+
+ uint32_t calonce; /*
+ * This setting changes the behaviour of CalRun register.
+ * If you desire to manually trigger impedance calibration
+ * in mission mode set this variable to 1, and toggle CalRun
+ * in mission mode.
+ *
+ * Value | Description
+ * ----- | ------
+ * 0x0 | Calibration will proceed at the rate determined
+ * | by CalInterval. This field should only be changed
+ * | while the calibrator is idle. ie before csr
+ * | CalRun is set.
+ */
+
+ uint32_t lp4rl; /*
+ * LPDDR4 Dram Read Latency.
+ * Applicable only if dramtype == LPDDR4.
+ * This variable is used to calculate LPDDR4 mr2-OP[2:0]
+ * set in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
+ * definition of MR.
+ * Determine values based on your DRAM part's supported
+ * speed and latency bin.
+ * Default: calculated based on user_input_basic.frequency
+ * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write
+ * Latencies".
+ * Lowest latency selected when more than one latency can be
+ * used. For example given configuration for LPDDR4, x16,
+ * NoDbi and DDR533, RL=10 is selected rather than 14.
+ */
+
+ uint32_t lp4wl; /*
+ * LPDDR4 Dram Write Latency.
+ * Applicable only if dramtype == LPDDR4.
+ * This variable is used to calculate LPDDR4 mr2-OP[5:3]
+ * set in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
+ * definition of MR.
+ * Determine values based on your DRAM part's supported
+ * speed and latency bin.
+ * Default: calculated based on user_input_basic.frequency
+ * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write
+ * Latencies".
+ * Lowest latency selected when more than one latency can be
+ * used.
+ */
+
+ uint32_t lp4wls; /*
+ * LPDDR4 Dram WL Set.
+ * Applicable only if dramtype == LPDDR4.
+ * This variable is used to calculate LPDDR4 mr2-OP[6] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
+ * definition of MR.
+ * Determine value based on Memory controllers requirement
+ * of DRAM State after PHY training.
+ *
+ * Value | Description
+ * --- | ---
+ * 0x0 | WL Set "A" (default)
+ */
+
+ uint32_t lp4dbird; /*
+ * LPDDR4 Dram DBI-Read Enable.
+ * Applicable only if dramtype == LPDDR4.
+ * Determine if you require to using DBI for the given
+ * PState.
+ * If Read DBI is not used PHY receivers are turned off to
+ * save power.
+ * This variable is used to calculate LPDDR4 mr3-OP[6] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * PHY register DMIPinPresent is programmed based on this
+ * parameter.
+ * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
+ * definition of MR.
+ *
+ * Value | Description
+ * --- | ---
+ * 0x0 | Disabled (default)
+ * 0x1 | Enabled
+ */
+
+ uint32_t lp4dbiwr; /*
+ * LPDDR4 Dram DBI-Write Enable.
+ * Applicable only if dramtype == LPDDR4.
+ * This variable is used to calculate LPDDR4 mr3-OP[7] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
+ * definition of MR.
+ *
+ * Value | Description
+ * --- | ---
+ * 0x0 | Disabled (default)
+ * 0x1 | Enabled
+ */
+
+ uint32_t lp4nwr; /*
+ * LPDDR4 Write-Recovery for Auto- Pre-charge commands.
+ * Applicable only if dramtype == LPDDR4.
+ * This variable is used to calculate LPDDR4 mr1-OP[6:4] set
+ * in the messageBlock.
+ * The training firmware will set DRAM MR according to MR
+ * value in the messageBlock at the end of training.
+ * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
+ * definition of MR.
+ * Determine values based on your DRAM part's supported
+ * speed and latency bin.
+ * Default: calculated based on user_input_basic.frequency
+ * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write
+ * Latencies".
+ * Lowest latency selected when more than one latency can be
+ * used.
+ *
+ * Binary Value | Description
+ * --- | ---
+ * 000 | nWR = 6 (default)
+ * 001 | nWR = 10
+ * 010 | nWR = 16
+ * 011 | nWR = 20
+ * 100 | nWR = 24
+ * 101 | nWR = 30
+ * 110 | nWR = 34
+ * 111 | nWR = 40
+ */
+
+ uint32_t lp4lowpowerdrv; /*
+ * Configure output Driver in Low power mode.
+ * Feature only supported for Hard Macro Family E (HME).
+ * Use NMOS Pull-up for Low-Power IO.
+ * Not valid here
+ */
+
+ uint32_t drambyteswap; /*
+ * DRAM Oscillator count source mapping for skip_training.
+ * The PHY supports swapping of DRAM oscillator count values
+ * between paired DBytes for the purpose of tDQSDQ DRAM
+ * Drift Compensation(DDC).
+ * Each DByte has a register bit to control the source of
+ * the oscillator count value used to perform tDQSDQ Drift
+ * compensation.
+ * On silicon the training firmware will determine the DByte
+ * swap and program PptCtlStatic register to select
+ * oscillator count source. When skip_train is used,
+ * training firmware is skipped thus manual programming may
+ * be required depending on configuration.
+ * The default hardware configuration is for odd Dbyte
+ * instance n to use oscillator count values from its paired
+ * Dbyte instance n-1. So Dbyte1 will use the oscillator
+ * count values from Dbyte0, Dbyte3 will use Dbyte2 and so
+ * on. This is required for DRAM Data width =16.
+ * Each bit of this field corresponds to a DBYTE:
+ * - bit-0 = setting for DBYTE0
+ * - bit-1 = setting for DBYTE1
+ * - bit-2 = setting for DBYTE2
+ * - . . .
+ * - bit-n = setting for DBYTEn
+ * By setting the associated bit for each DByte to 1, PHY
+ * will use non-default source for count value.
+ * - for even Dbytes, non-default source is to use the odd
+ * pair count value.
+ * - for odd Dbytes, no-default source to use data
+ * received directly from the DRAM.
+ * Byte swapping must be the same across different ranks.
+ * Default value: 0x0
+ * If Byte mode devices are indicated via the x8mode
+ * messageBlock parameter, this variable is ignored as PHY
+ * only supports a limited configuration set based on Byte
+ * mode configuration.
+ *
+ * Example:
+ * DramByteSwap = 0x03 - Dbyte0: use count values from
+ * Dbyte1, Dbyte1 uses count values received directly
+ * received from DRAM.
+ * Rest of Dbytes have default source for DRAM oscilator
+ * count.
+ */
+
+ uint32_t rxenbackoff; /*
+ * Determines the Placement of PHY Read Gate signal.
+ * Only used in LPDDR4 when lp4rxpreamblemode==0 (static
+ * preamble) for skip_train==true.
+ * For other dramtypes or LPDDR4-toggling-preamble no
+ * options are available and PhyInit will set position as
+ * required. See source code in
+ * ddrphy_phyinit_c_initphyconfig() to see how the
+ * RxEnBackOff register is set.
+ * For skip_train==false, FW will set the position based on
+ * Preamble.
+ * We recommend keeping this setting at default value.
+ * SI analysis is required to determine if default value
+ * needs to be changed.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x1 | Position read gate 1UI from the first valid edge
+ * | of DQS_t (LPDDR4 Static preamble only) (default)
+ */
+
+ uint32_t trainsequencectrl; /*
+ * Firmware Training Sequence Control.
+ * This input is used to program sequencectrl in
+ * messageBlock.
+ * It controls the training stages executed by firmware.
+ * For production silicon we recommend to use default value
+ * programmed by PhyInit.
+ */
+
+ uint32_t snpsumctlopt; /*
+ * Enable Fast Frequency Change (FFC) Optimizations
+ * specific to UMCTL2 (DDRCTRL).
+ * Not valid for dimmtype=NODIMM.
+ * Consult DDRCTRL documentation in Reference Manual to
+ * ensure when optimizations can be enabled.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0 | Disable FFC MRW optimization (default)
+ */
+
+ uint32_t snpsumctlf0rc5x; /*
+ * F0RX5x RCD Control Word when using Fast Frequency
+ * Change(FFC) optimizations specific to UMCTL2
+ * Not valid for dimmtype=NODIMM.
+ * Only valid for when SnpsUmctlOpt=1.
+ * When UMCTL2 optimizations are enabled PHY will perform
+ * RCD MRW during fast frequency change request.
+ * The correct RCD control word value for each PState must
+ * be programmed in this field.
+ * Consult the RCD spec and UMCTL documentation to
+ * determine the correct value based on DRAM configuration
+ * and operating speed.
+ */
+
+ uint32_t txslewrisedq; /*
+ * Pull-up slew rate control for DBYTE Tx.
+ * Value specified here will be written to register
+ * TxSlewRate.TxPreP by PhyInit.
+ * See register description for more information.
+ */
+
+ uint32_t txslewfalldq; /*
+ * Pull-down slew rate control for DBYTE Tx.
+ * Value specified here will be written to
+ * TxSlewRate.TxPreN by PhyInit.
+ * See register description for more information.
+ */
+
+ uint32_t txslewriseac; /*
+ * Pull-up slew rate control for ANIB Tx.
+ * Value specified here will be written to
+ * ATxSlewRate.ATxPreP.
+ * See register description for more information.
+ */
+
+ uint32_t txslewfallac; /*
+ * Pull-down slew rate control for ANIB Tx.
+ * Value specified here will be written to
+ * ATxSlewRate.ATxPreN.
+ * See register description for more information.
+ */
+
+ uint32_t disableretraining; /*
+ * Disable PHY DRAM Drift compensation re-training.
+ * Only applied to LPDDR4. No retraining is required in
+ * DDR4/3.
+ * Disable PHY re-training during DFI frequency change
+ * requests in LPDDR4.
+ * The purpose of retraining is to compensate for drift in
+ * the DRAM.
+ * Determine based on SI analysis and DRAM datasheet if
+ * retraining can be disabled.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x1 | Disable retraining
+ * 0x0 | Enable retraining
+ */
+
+ uint32_t disablephyupdate; /*
+ * Disable DFI PHY Update feature.
+ * Only effects LPDDR4.
+ * Disable DFI PHY Update feature. When set PHY will not
+ * assert dfi0/1_phyupd_req.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x1 | Disable DFI PHY Update
+ * 0x0 | Enable DFI PHY Update
+ */
+
+ uint32_t enablehighclkskewfix; /*
+ * Enable alternative PIE program.
+ * If enabled the PIE reinitializes the FIFO pointers a
+ * second time due for designs with large skew between
+ * chiplet DfiClk branches. If enabled PIE latencies in all
+ * protocols are increased by 60 DfiClks.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x0 | Disable (default)
+ */
+
+ uint32_t disableunusedaddrlns; /*
+ * Turn off or tristate Address Lanes when possible.
+ *
+ * When enabled, PHY will tristate unused address lanes to
+ * save power when possible by using Acx4AnibDis and
+ * AForceTriCont registers.
+ * This feature is only implemented for the default PHY
+ * Address bump mapping and Ranks must be populated in
+ * order. ie Rank1 cannot be used if Rank0 is unpopulated.
+ * For alternative bump mapping follow the following
+ * guideline to achieve maximum power savings:
+ * - For each unused BP_A bump program AForceTriCont[4:0]
+ * bits based on register description.
+ * - if all lanes of an Anib are unused _AND_ ANIB is not
+ * the first or last instance set bit associated with
+ * the instance in Acs4AnibDis registers. see register
+ * description for details.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x1 | Enable
+ */
+
+ uint32_t phyinitsequencenum; /*
+ * Switches between supported phyinit training sequences.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x0 | Minimizes number of Imem/Dmem loads (default)
+ */
+
+ uint32_t enabledficspolarityfix;/*
+ * Enable alternative PIE program.
+ * Set to 1 if PUB_VERSION <2.43a, otherwise set to 0. If
+ * enabled the PIE programs Dfi{Rd,Wr}DataCsDestMap CSR's
+ * to default values 0x00E4 before running PPT.
+ * Before exiting PPT, PIE will restore
+ * Dfi{Rd,Wr}DataCsDestMap CSR's to 0x00E1.
+ *
+ * Value | Description
+ * ----- | ---
+ * 0x0 | Disable (default)
+ */
+
+ uint32_t phyvref; /*
+ * Must be programmed with the Vref level to be used by the
+ * PHY during reads.
+ * The units of this field are a percentage of VDDQ
+ * according to the following equation:
+ * Receiver Vref = VDDQ*phyvref[6:0]/128
+ * For example to set Vref at 0.75*VDDQ, set this field to
+ * 0x60.
+ * For digital simulation, any legal value can be used. For
+ * silicon, the users must calculate the analytical Vref by
+ * using the impedances, terminations, and series resistance
+ * present in the system.
+ */
+
+ uint32_t sequencectrl; /*
+ * Controls the training steps to be run. Each bit
+ * corresponds to a training step.
+ * If the bit is set to 1, the training step will run.
+ * If the bit is set to 0, the training step will be
+ * skipped.
+ * Training step to bit mapping:
+ * sequencectrl[0] = Run DevInit - Device/phy
+ * initialization. Should always be set.
+ * sequencectrl[1] = Run WrLvl - Write leveling
+ * sequencectrl[2] = Run RxEn - Read gate training
+ * sequencectrl[3] = Run RdDQS1D - 1d read dqs training
+ * sequencectrl[4] = Run WrDQ1D - 1d write dq training
+ * sequencectrl[5] = RFU, must be zero
+ * sequencectrl[6] = RFU, must be zero
+ * sequencectrl[7] = RFU, must be zero
+ * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew
+ * training
+ * sequencectrl[9] = Run MxRdLat - Max read latency training
+ * sequencectrl[10] = RFU, must be zero
+ * sequencectrl[11] = RFU, must be zero
+ * sequencectrl[12] = RFU, must be zero
+ * sequencectrl[13] = RFU, must be zero
+ * sequencectrl[15-14] = RFU, must be zero
+ */
+};
+
+/*
+ * Structure for mode register user inputs
+ *
+ * The following data structure must be set and completed correctly so that the PhyInit software
+ * package can accurate fill message block structure.
+ * Only some mrx are used per DDR type, on related width:
+ * - DDR3: mr0..2 are used (16-bits values)
+ * - DDR4: mr0..6 are used (16-bits values)
+ * - LPDDR4: mr1..4 and mr11..22 are used (8-bits values)
+ */
+struct user_input_mode_register {
+ uint32_t mr0;
+ uint32_t mr1;
+ uint32_t mr2;
+ uint32_t mr3;
+ uint32_t mr4;
+ uint32_t mr5;
+ uint32_t mr6;
+ uint32_t mr11;
+ uint32_t mr12;
+ uint32_t mr13;
+ uint32_t mr14;
+ uint32_t mr22;
+};
+
+/*
+ * Structure for swizzle user inputs
+ *
+ * The following data structure must be set and completed correctly sothat the PhyInit software
+ * package can accurate set swizzle (IO muxing) config.
+ * Only some swizzles are used per DDR type:
+ * - DDR3/DDR4: swizzle 0..32 are used
+ * - 26 for hwtswizzle
+ * - 7 for acswizzle
+ * - LPDDR4: swizzle 0..43 are used
+ * - 8 per byte for dqlnsel (total 32)
+ * - 6 for mapcaatodfi
+ * - 6 for mapcabtodfi
+ */
+#define NB_HWT_SWIZZLE 26U
+#define NB_AC_SWIZZLE 7U
+#define NB_DQLNSEL_SWIZZLE_PER_BYTE 8U
+#define NB_MAPCAATODFI_SWIZZLE 6U
+#define NB_MAPCABTODFI_SWIZZLE 6U
+#define NB_SWIZZLE 44
+struct user_input_swizzle {
+ uint32_t swizzle[NB_SWIZZLE];
+};
+
+#endif /* DDRPHY_PHYINIT_STRUCT_H */
diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_usercustom.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_usercustom.h
new file mode 100644
index 0000000..b248f59
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_usercustom.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DDRPHY_PHYINIT_USERCUSTOM_H
+#define DDRPHY_PHYINIT_USERCUSTOM_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <ddrphy_csr_all_cdefines.h>
+
+#include <drivers/st/stm32mp2_ddr.h>
+
+/* Message Block Structure Definitions */
+#if STM32MP_DDR3_TYPE
+#include <mnpmusrammsgblock_ddr3.h>
+#elif STM32MP_DDR4_TYPE
+#include <mnpmusrammsgblock_ddr4.h>
+#else /* STM32MP_LPDDR4_TYPE */
+#include <mnpmusrammsgblock_lpddr4.h>
+#endif /* STM32MP_DDR3_TYPE */
+
+/*
+ * -------------------------------------------------------------
+ * Defines for Firmware Images
+ * - indicate IMEM/DMEM address, size (bytes) and offsets.
+ * -------------------------------------------------------------
+ *
+ * IMEM_SIZE max size of instruction memory.
+ * DMEM_SIZE max size of data memory.
+ *
+ * IMEM_ST_ADDR start of IMEM address in memory.
+ * DMEM_ST_ADDR start of DMEM address in memory.
+ * DMEM_BIN_OFFSET start offset in DMEM memory (message block).
+ */
+#if STM32MP_DDR3_TYPE
+#define IMEM_SIZE 0x4C28U
+#define DMEM_SIZE 0x6C8U
+#elif STM32MP_DDR4_TYPE
+#define IMEM_SIZE 0x6D24U
+#define DMEM_SIZE 0x6CCU
+#else /* STM32MP_LPDDR4_TYPE */
+#define IMEM_SIZE 0x7E50U
+#define DMEM_SIZE 0x67CU
+#endif /* STM32MP_DDR3_TYPE */
+#define IMEM_ST_ADDR 0x50000U
+#define DMEM_ST_ADDR 0x54000U
+#define DMEM_BIN_OFFSET 0x200U
+
+/*
+ * ------------------
+ * Type definitions
+ * ------------------
+ */
+
+/* A structure used to SRAM memory address space */
+enum return_offset_lastaddr {
+ RETURN_OFFSET,
+ RETURN_LASTADDR
+};
+
+/* Enumeration of instructions for PhyInit Register Interface */
+enum reginstr {
+ STARTTRACK, /* Start register tracking */
+ STOPTRACK, /* Stop register tracking */
+ SAVEREGS, /* Save(read) tracked register values */
+ RESTOREREGS, /* Restore (write) saved register values */
+};
+
+/* Data structure to store register address/value pairs */
+struct reg_addr_val {
+ uint32_t address; /* Register address */
+ uint16_t value; /* Register value */
+};
+
+/* Target CSR for the impedance value for ddrphy_phyinit_mapdrvstren() */
+enum drvtype {
+ DRVSTRENFSDQP,
+ DRVSTRENFSDQN,
+ ODTSTRENP,
+ ODTSTRENN,
+ ADRVSTRENP,
+ ADRVSTRENN
+};
+
+/*
+ * -------------------------------------------------------------
+ * Fixed Function prototypes
+ * -------------------------------------------------------------
+ */
+int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten);
+int ddrphy_phyinit_restore_sequence(void);
+int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t *ardptrinitval);
+void ddrphy_phyinit_d_loadimem(void);
+void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t ardptrinitval);
+int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
+int ddrphy_phyinit_g_execfw(void);
+void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training);
+void ddrphy_phyinit_loadpieprodcode(void);
+int ddrphy_phyinit_mapdrvstren(uint32_t drvstren_ohm, enum drvtype targetcsr);
+int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
+void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size);
+void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size);
+int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t dbytenumber);
+int ddrphy_phyinit_trackreg(uint32_t adr);
+int ddrphy_phyinit_reginterface(enum reginstr myreginstr, uint32_t adr, uint16_t dat);
+
+void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config);
+int ddrphy_phyinit_usercustom_g_waitfwdone(void);
+int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config);
+
+#endif /* DDRPHY_PHYINIT_USERCUSTOM_H */
diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_wrapper.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_wrapper.h
new file mode 100644
index 0000000..ed4be1c
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_wrapper.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DDRPHY_WRAPPER_H
+#define DDRPHY_WRAPPER_H
+
+static inline long long fmodll(long long x, long long y)
+{
+ return x - ((x / y) * y);
+}
+
+static inline int fmodi(int x, int y)
+{
+ return (int)fmodll((long long)x, (long long)y);
+}
+
+#endif /* DDRPHY_WRAPPER_H */
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c
new file mode 100644
index 0000000..a0712b5
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c
@@ -0,0 +1,1140 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+#include <ddrphy_wrapper.h>
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <platform_def.h>
+
+/*
+ * Program txslewrate:
+ * - txslewrate::txpredrvmode is dependent on dramtype.
+ * - txslewrate::txprep and txslewrate::txpren are technology-specific.
+ */
+static void txslewrate_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t txpredrvmode;
+ uint32_t byte;
+ uint32_t txpren; /* Default to 0xf (max). Optimal setting is technology specific */
+ uint32_t txprep; /* Default to 0xf (max). Optimal setting is technology specific */
+ uint16_t txslewrate;
+
+#if STM32MP_DDR3_TYPE
+ txpredrvmode = 0x3U;
+#elif STM32MP_DDR4_TYPE
+ txpredrvmode = 0x2U;
+#else /* STM32MP_LPDDR4_TYPE */
+ txpredrvmode = 0x1U;
+#endif /* STM32MP_DDR3_TYPE */
+
+ txprep = config->uia.txslewrisedq;
+ txpren = config->uia.txslewfalldq;
+
+ txslewrate = (uint16_t)((txpredrvmode << CSR_TXPREDRVMODE_LSB) |
+ (txpren << CSR_TXPREN_LSB) |
+ (txprep << CSR_TXPREP_LSB));
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t lane;
+
+ c_addr = byte << 12;
+ for (lane = 0U; lane <= B_MAX; lane++) {
+ uint32_t b_addr;
+
+ b_addr = lane << 8;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr |
+ CSR_TXSLEWRATE_ADDR))),
+ txslewrate);
+ }
+ }
+}
+
+/*
+ * Program atxslewrate:
+ * - atxslewrate::atxpredrvmode is dependent on dramtype and whether
+ * the ACX4 instance is used for AC or CK.
+ * - atxslewrate::atxprep and atxslewrate::atxpren are technology-specific.
+ */
+static void atxslewrate_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t anib;
+ uint32_t atxpren; /* Default to 0xf (max). Optimal setting is technology specific */
+ uint32_t atxprep; /* Default to 0xf (max). Optimal setting is technology specific */
+ uint32_t ck_anib_inst[2] = {0};
+
+ atxprep = config->uia.txslewriseac;
+ atxpren = config->uia.txslewfallac;
+
+ /*
+ * # of ANIBs CK ANIB Instance
+ * ACX8 ANIB 1
+ */
+ if (config->uib.numanib == 8U) {
+ ck_anib_inst[0] = 1U;
+ ck_anib_inst[1] = 1U;
+ }
+
+ for (anib = 0U; anib < config->uib.numanib; anib++) {
+ uint32_t atxpredrvmode;
+ uint32_t c_addr;
+ uint16_t atxslewrate;
+
+ c_addr = anib << 12;
+
+ if ((anib == ck_anib_inst[0]) || (anib == ck_anib_inst[1])) {
+ /* CK ANIB instance */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ atxpredrvmode = 0x0U;
+#else /* STM32MP_LPDDR4_TYPE */
+ atxpredrvmode = 0x1U;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ } else {
+ /* non-CK ANIB instance */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ atxpredrvmode = 0x3U;
+#else /* STM32MP_LPDDR4_TYPE */
+ atxpredrvmode = 0x1U;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ }
+
+ atxslewrate = (uint16_t)((atxpredrvmode << CSR_ATXPREDRVMODE_LSB) |
+ (atxpren << CSR_ATXPREN_LSB) |
+ (atxprep << CSR_ATXPREP_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr |
+ CSR_ATXSLEWRATE_ADDR))),
+ atxslewrate);
+ }
+}
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+/*
+ * Program dfirddatacsdestmap and dfiwrdatacsdestmap:
+ * - Dependencies: mb_ddr_1d->msgmisc[6] Determine Partial Rank Support.
+ */
+static void dfidatacsdestmap_program(struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ if ((mb_ddr_1d->msgmisc & 0x40U) != 0U) {
+ uint16_t dfirddatacsdestmap = 0xA0U;
+ uint16_t dfiwrdatacsdestmap = 0xA0U;
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER |
+ CSR_DFIRDDATACSDESTMAP_ADDR))),
+ dfirddatacsdestmap);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER |
+ CSR_DFIWRDATACSDESTMAP_ADDR))),
+ dfiwrdatacsdestmap);
+ }
+}
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+/*
+ * Program pllctrl2:
+ * - Calculate PLL controls from frequency.
+ */
+static void pllctrl2_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t pllctrl2;
+ uint32_t halffreq = config->uib.frequency / 2U;
+
+ if (halffreq < 235U) {
+ pllctrl2 = 0x7U;
+ } else if (halffreq < 313U) {
+ pllctrl2 = 0x6U;
+ } else if (halffreq < 469U) {
+ pllctrl2 = 0xBU;
+ } else if (halffreq < 625U) {
+ pllctrl2 = 0xAU;
+ } else if (halffreq < 938U) {
+ pllctrl2 = 0x19U;
+ } else if (halffreq < 1067U) {
+ pllctrl2 = 0x18U;
+ } else {
+ pllctrl2 = 0x19U;
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PLLCTRL2_ADDR))), pllctrl2);
+}
+
+/*
+ * Program ardptrinitval:
+ * - The values programmed here assume ideal properties of DfiClk and Pclk including:
+ * - DfiClk skew
+ * - DfiClk jitter
+ * - DfiClk PVT variations
+ * - Pclk skew
+ * - Pclk jitter
+ *
+ * ardptrinitval Programmed differently based on PLL Bypass mode and frequency:
+ * - PLL Bypassed mode:
+ * - For MemClk frequency > 933MHz, the valid range of ardptrinitval[3:0] is: 2-5
+ * - For MemClk frequency < 933MHz, the valid range of ardptrinitval[3:0] is: 1-5
+ * - PLL Enabled mode:
+ * - For MemClk frequency > 933MHz, the valid range of ardptrinitval[3:0] is: 1-5
+ * - For MemClk frequency < 933MHz, the valid range of ardptrinitval[3:0] is: 0-5
+ */
+static void ardptrinitval_program(struct stm32mp_ddr_config *config, uint32_t *ardptrinitval)
+{
+ uint16_t regdata;
+
+ if (config->uib.frequency >= 933U) {
+ regdata = 0x2U;
+ } else {
+ regdata = 0x1U;
+ }
+
+ /* Add one UI for synchronizer on SyncBus when PLL is bypassed */
+ if (config->uib.pllbypass == 1U) {
+ regdata++;
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_ARDPTRINITVAL_ADDR))),
+ regdata);
+
+ *ardptrinitval = (uint32_t)regdata;
+}
+
+#if STM32MP_LPDDR4_TYPE
+/*
+ * Program ProcOdtCtl:
+ * - Sets procodtalwayson/procodtalwaysoff for LPDDR4 using the PIE register seq0bgpr4.
+ */
+static void procodtctl_program(void)
+{
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | C0 | CSR_SEQ0BGPR4_ADDR))), 0U);
+}
+#endif /* STM32MP_LPDDR4_TYPE */
+
+/*
+ * Program dbytedllmodecntrl:
+ * - dllrxpreamblemode
+ * Program dqspreamblecontrol:
+ * - Fields:
+ * - twotckrxdqspre
+ * - twotcktxdqspre
+ * - positiondfeinit
+ * - lp4tgltwotcktxdqspre
+ * - lp4postambleext
+ * - lp4sttcprebridgerxen
+ * - Dependencies:
+ * - user_input_advanced.lp4rxpreamblemode (LPDDR4)
+ * - user_input_advanced.lp4postambleext (LPDDR4)
+ * - user_input_advanced.wdqsext (LPDDR4)
+ * - user_input_advanced.d4rxpreamblelength (DDR4)
+ * - user_input_advanced.d4txpreamblelength (DDR4)
+ */
+static void dbytedllmodecntrl_program(struct stm32mp_ddr_config *config, uint32_t *twotckrxdqspre)
+{
+ uint32_t disdllgainivseed = 1U;
+ uint32_t disdllseedsel = 0U;
+ uint32_t dllgainiv = 0x1U;
+ uint32_t dllgaintv = 0x6U;
+ uint32_t dllrxpreamblemode = 0U;
+ uint32_t lcdlseed0 = 0x21U;
+ uint32_t lp4postambleext = 0U;
+ uint32_t lp4sttcprebridgerxen = 0U;
+ uint32_t lp4tgltwotcktxdqspre = 0U;
+ uint32_t positiondfeinit;
+ uint32_t twotcktxdqspre = 0U;
+ uint32_t wdqsextension = 0U;
+ uint16_t dbytedllmodecntrl;
+ uint16_t dllgainctl;
+ uint16_t dlllockparam;
+ uint16_t dqspreamblecontrol;
+
+#if STM32MP_DDR3_TYPE
+ /* Same as default */
+ *twotckrxdqspre = 0x0U;
+ lp4sttcprebridgerxen = 0x0U;
+ dllrxpreamblemode = 0x0U;
+ twotcktxdqspre = 0x0U;
+ lp4tgltwotcktxdqspre = 0x0U;
+ positiondfeinit = 0x0U;
+ lp4postambleext = 0x0U;
+#elif STM32MP_DDR4_TYPE
+ *twotckrxdqspre = config->uia.d4rxpreamblelength;
+ lp4sttcprebridgerxen = 0x0U;
+ dllrxpreamblemode = 0x1U;
+ twotcktxdqspre = config->uia.d4txpreamblelength;
+ lp4tgltwotcktxdqspre = 0x0U;
+ positiondfeinit = 0x2U;
+ lp4postambleext = 0x0U;
+#else /* STM32MP_LPDDR4_TYPE */
+ /* Set to 1 if static Rx preamble */
+ *twotckrxdqspre = (config->uia.lp4rxpreamblemode == 0U) ? 1U : 0U;
+ /* Set to 1 if static Rx preamble */
+ lp4sttcprebridgerxen = (config->uia.lp4rxpreamblemode == 0U) ? 1U : 0U;
+ dllrxpreamblemode = 0x1U;
+ /* Must be 2*Tck Tx preamble according to JEDEC (mr1.OP[2] = 1) */
+ twotcktxdqspre = 0x1U;
+ /* Must be toggling Tx preamble */
+ lp4tgltwotcktxdqspre = 0x1U;
+ positiondfeinit = 0x0U;
+ lp4postambleext = config->uia.lp4postambleext;
+ wdqsextension = config->uia.wdqsext;
+#endif /* STM32MP_DDR3_TYPE */
+
+ dqspreamblecontrol = (uint16_t)((wdqsextension << CSR_WDQSEXTENSION_LSB) |
+ (lp4sttcprebridgerxen << CSR_LP4STTCPREBRIDGERXEN_LSB) |
+ (lp4postambleext << CSR_LP4POSTAMBLEEXT_LSB) |
+ (lp4tgltwotcktxdqspre << CSR_LP4TGLTWOTCKTXDQSPRE_LSB) |
+ (positiondfeinit << CSR_POSITIONDFEINIT_LSB) |
+ (twotcktxdqspre << CSR_TWOTCKTXDQSPRE_LSB) |
+ (*twotckrxdqspre << CSR_TWOTCKRXDQSPRE_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DQSPREAMBLECONTROL_ADDR))),
+ dqspreamblecontrol);
+
+ dbytedllmodecntrl = (uint16_t)(dllrxpreamblemode << CSR_DLLRXPREAMBLEMODE_LSB);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DBYTEDLLMODECNTRL_ADDR))),
+ dbytedllmodecntrl);
+
+ dllgainctl = (uint16_t)(dllgainiv | (dllgaintv << CSR_DLLGAINTV_LSB));
+ dlllockparam = (uint16_t)(disdllseedsel | (disdllgainivseed << CSR_DISDLLGAINIVSEED_LSB) |
+ (lcdlseed0 << CSR_LCDLSEED0_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLLOCKPARAM_ADDR))),
+ dlllockparam);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLGAINCTL_ADDR))),
+ dllgainctl);
+}
+
+/*
+ * Program procodttimectl:
+ * - Fields:
+ * - POdtStartDelay[3:2]
+ * - POdtTailWidth[1:0]
+ * - Dependencies:
+ * - user_input_basic.frequency
+ * - user_input_advanced.wdqsext
+ */
+static void procodttimectl_program(struct stm32mp_ddr_config *config, uint32_t twotckrxdqspre)
+{
+ uint16_t procodttimectl;
+
+ if (config->uia.wdqsext != 0U) {
+ /* POdtStartDelay = 0x0 and POdtTailWidth = 0x3 */
+ procodttimectl = 0x3U;
+ } else if (config->uib.frequency <= 933U) {
+ /* Memclk Freq <= 933MHz: POdtStartDelay = 0x2 and POdtTailWidth = 0x2 */
+ procodttimectl = 0xAU;
+ } else if (config->uib.frequency <= 1200U) {
+ /* 933MHz < Memclk Freq <= 1200MHz */
+ if (twotckrxdqspre == 1U) {
+ /* POdtStartDelay = 0x0 and POdtTailWidth = 0x2 */
+ procodttimectl = 0x2U;
+ } else {
+ /* POdtStartDelay = 0x1 and POdtTailWidth = 0x2 */
+ procodttimectl = 0x6U;
+ }
+ } else {
+ /* Memclk Freq > 1200MHz */
+ if (twotckrxdqspre == 1U) {
+ /* POdtStartDelay = 0x0 and POdtTailWidth = 0x3 */
+ procodttimectl = 0x3U;
+ } else {
+ /* POdtStartDelay = 0x1 and POdtTailWidth = 0x3 */
+ procodttimectl = 0x7U;
+ }
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PROCODTTIMECTL_ADDR))),
+ procodttimectl);
+}
+
+/*
+ * Program txodtdrvstren:
+ * - Fields:
+ * - ODTStrenP_px[5:0]
+ * - ODTStrenN_px[11:6]
+ * - Dependencies:
+ * - user_input_basic.numdbyte
+ * - user_input_advanced.odtimpedance
+ * \return 0 on success.
+ */
+static int txodtdrvstren_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t byte;
+ int odtstrenn_state;
+ int odtstrenp_state;
+ uint16_t txodtdrvstren;
+
+ odtstrenp_state = ddrphy_phyinit_mapdrvstren(config->uia.odtimpedance, ODTSTRENP);
+ if (odtstrenp_state < 0) {
+ return odtstrenp_state;
+ }
+
+ odtstrenn_state = ddrphy_phyinit_mapdrvstren(config->uia.odtimpedance, ODTSTRENN);
+ if (odtstrenn_state < 0) {
+ return odtstrenn_state;
+ }
+
+ txodtdrvstren = (uint16_t)((odtstrenn_state << CSR_ODTSTRENN_LSB) | odtstrenp_state);
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t lane;
+
+ c_addr = byte << 12;
+ for (lane = 0U; lane <= B_MAX; lane++) {
+ uint32_t b_addr;
+
+ b_addr = lane << 8;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr |
+ CSR_TXODTDRVSTREN_ADDR))),
+ txodtdrvstren);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Program tximpedancectrl1:
+ * - Fields:
+ * - DrvStrenFSDqP[5:0]
+ * - DrvStrenFSDqN[11:6]
+ * - Dependencies:
+ * - user_input_basic.numdbyte
+ * - user_input_advanced.tximpedance
+ * \return 0 on success.
+ */
+static int tximpedancectrl1_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t byte;
+ int drvstrenfsdqn_state;
+ int drvstrenfsdqp_state;
+ uint16_t tximpedancectrl1;
+
+ drvstrenfsdqp_state = ddrphy_phyinit_mapdrvstren(config->uia.tximpedance,
+ DRVSTRENFSDQP);
+ if (drvstrenfsdqp_state < 0) {
+ return drvstrenfsdqp_state;
+ }
+
+ drvstrenfsdqn_state = ddrphy_phyinit_mapdrvstren(config->uia.tximpedance,
+ DRVSTRENFSDQN);
+ if (drvstrenfsdqn_state < 0) {
+ return drvstrenfsdqn_state;
+ }
+
+ tximpedancectrl1 = (uint16_t)((drvstrenfsdqn_state << CSR_DRVSTRENFSDQN_LSB) |
+ (drvstrenfsdqp_state << CSR_DRVSTRENFSDQP_LSB));
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t lane;
+
+ c_addr = byte << 12;
+ for (lane = 0U; lane <= B_MAX; lane++) {
+ uint32_t b_addr;
+
+ b_addr = lane << 8;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U *
+ (TDBYTE | c_addr | b_addr |
+ CSR_TXIMPEDANCECTRL1_ADDR))),
+ tximpedancectrl1);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Program atximpedance:
+ * - Fields:
+ * - ADrvStrenP[4:0]
+ * - ADrvStrenN[9:5]
+ * - Dependencies:
+ * - user_input_basic.numanib
+ * - user_input_advanced.atximpedance
+ * \return 0 on success.
+ */
+static int atximpedance_program(struct stm32mp_ddr_config *config)
+{
+ int adrvstrenn_state;
+ int adrvstrenp_state;
+ uint32_t anib;
+ uint16_t atximpedance;
+
+ adrvstrenp_state = ddrphy_phyinit_mapdrvstren(config->uia.atximpedance,
+ ADRVSTRENP);
+ if (adrvstrenp_state < 0) {
+ return adrvstrenp_state;
+ }
+
+ adrvstrenn_state = ddrphy_phyinit_mapdrvstren(config->uia.atximpedance,
+ ADRVSTRENN);
+ if (adrvstrenn_state < 0) {
+ return adrvstrenn_state;
+ }
+
+ atximpedance = (uint16_t)((adrvstrenn_state << CSR_ADRVSTRENN_LSB) |
+ (adrvstrenp_state << CSR_ADRVSTRENP_LSB));
+
+ for (anib = 0U; anib < config->uib.numanib; anib++) {
+ uint32_t c_addr;
+
+ c_addr = anib << 12;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr |
+ CSR_ATXIMPEDANCE_ADDR))),
+ atximpedance);
+ }
+
+ return 0;
+}
+
+/*
+ * Program dfimode:
+ * - Dependencies:
+ * - user_input_basic.dfi1exists
+ */
+static void dfimode_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t dfimode = 0x5U;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if (config->uib.dfi1exists == 0U) {
+ dfimode = 0x1U; /* DFI1 does not physically exists */
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFIMODE_ADDR))), dfimode);
+}
+
+/*
+ * Program dficamode:
+ * - Fields:
+ * - DfiLp3CAMode
+ * - DfiD4CAMode
+ * - DfiLp4CAMode
+ * - DfiD4AltCAMode
+ */
+static void dficamode_program(void)
+{
+ uint16_t dficamode;
+
+#if STM32MP_DDR3_TYPE
+ dficamode = 0U;
+#elif STM32MP_DDR4_TYPE
+ dficamode = 2U;
+#else /* STM32MP_LPDDR4_TYPE */
+ dficamode = 4U;
+#endif /* STM32MP_DDR3_TYPE */
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFICAMODE_ADDR))), dficamode);
+}
+
+/*
+ * Program caldrvstr0:
+ * - Fields:
+ * - caldrvstrpd50[3:0]
+ * - caldrvstrpu50[7:4]
+ * - Dependencies:
+ * - user_input_advanced.extcalresval
+ */
+static void caldrvstr0_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t caldrvstr0;
+ uint16_t caldrvstrp50 = (uint16_t)config->uia.extcalresval;
+
+ caldrvstr0 = (caldrvstrp50 << CSR_CALDRVSTRPU50_LSB) | caldrvstrp50;
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALDRVSTR0_ADDR))),
+ caldrvstr0);
+}
+
+/*
+ * Program CalUclkInfo:
+ * - Impedance calibration CLK Counter.
+ * - Fields:
+ * - caluclkticksper1us
+ * - Dependencies:
+ * - user_input_basic.frequency
+ */
+static void caluclkinfo_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t caluclkticksper1us_x10;
+ uint16_t caluclkticksper1us;
+
+ /* Number of DfiClk cycles per 1us */
+ caluclkticksper1us_x10 = (10U * config->uib.frequency) / 2U;
+ caluclkticksper1us = (uint16_t)(caluclkticksper1us_x10 / 10U);
+
+ if ((config->uib.frequency % 2U) != 0U) {
+ caluclkticksper1us++;
+ }
+
+ if (caluclkticksper1us < 24U) {
+ /* Minimum value of caluclkticksper1us = 24 */
+ caluclkticksper1us = 24U;
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALUCLKINFO_ADDR))),
+ caluclkticksper1us);
+}
+
+/*
+ * Program Calibration CSRs based on user input
+ * - Fields:
+ * - calinterval
+ * - calonce
+ * - Dependencies:
+ * - user_input_advanced.calinterval
+ * - user_input_advanced.calonce
+ */
+static void calibration_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t calinterval;
+ uint32_t calonce;
+ uint16_t calrate;
+
+ calinterval = config->uia.calinterval;
+ calonce = config->uia.calonce;
+
+ calrate = (uint16_t)((calonce << CSR_CALONCE_LSB) | (calinterval << CSR_CALINTERVAL_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALRATE_ADDR))), calrate);
+}
+
+/*
+ * Program vrefinglobal:
+ * - dqdqsrcvcntrl and csrvrefinglobal to select Global VREF
+ * from Master to be used in each DQ.
+ * - Fields:
+ * - globalvrefinsel: Select Range of GlobalVref DAC. Default: set to 1.
+ * - globalvrefindac: Vref level is set based on mb_ddr_1d->phyvref value.
+ * The following formula is used to convert the phyvref into the register setting.
+ * \f{eqnarray*}{
+ * PhyVrefPrcnt &=& \frac{mb_ddr_1d->phyvref}{128} \\
+ * if globalvrefinsel = 1 :
+ * globalvrefindac &=& 1+\frac{PhyVrefPrcnt}{0.005} \\
+ * if globalvrefinsel = 0 :
+ * globalvrefindac &=& \frac{(PhyVrefPrcnt-0.345)}{0.005} \\
+ * RxVref &=& (globalvrefindac == 0) ? Hi-Z : (PhyVrefPrcnt \times VDDQ)
+ * \f}
+ *
+ * Program dqdqsrcvcntrl:
+ * - dqdqsrcvcntrl and csrvrefinglobal to select Global VREF
+ * from Master to be used in each DQ
+ * - Fields:
+ * - selanalogvref
+ * - majormodedbyte
+ * - ExtVrefRange
+ * - DfeCtrl
+ * - GainCurrAdj
+ * - Dependencies:
+ * - user_input_basic.numdbyte
+ */
+static void vrefinglobal_program(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ uint32_t majormodedbyte;
+ int32_t vref_percentvddq = (int32_t)mb_ddr_1d->phyvref * 1000 * 100 / 128;
+ uint8_t globalvrefindac = 0x0U;
+ uint8_t globalvrefinsel = 0x4U;
+ uint32_t byte;
+ uint32_t dfectrl_defval = 0U;
+ uint32_t extvrefrange_defval = 0U;
+ uint32_t gaincurradj_defval = 0xBU;
+ uint32_t selanalogvref = 1U; /* Use Global VREF from Master */
+ uint16_t dqdqsrcvcntrl;
+ uint16_t vrefinglobal;
+
+#if STM32MP_DDR3_TYPE
+ majormodedbyte = 0U;
+#elif STM32MP_DDR4_TYPE
+ majormodedbyte = 3U;
+#else /* STM32MP_LPDDR4_TYPE */
+ majormodedbyte = 2U;
+#endif /* STM32MP_DDR3_TYPE */
+
+ /* Check range1 first. Only use range0 if customer input maxes out range1. */
+ globalvrefindac = (uint8_t)((vref_percentvddq / 500) + 1);
+ if (globalvrefindac > 127U) {
+ /* Min value is 1 */
+ globalvrefindac = (uint8_t)(MAX((vref_percentvddq - 34500), 500) / 500);
+ globalvrefinsel = 0x0U;
+ }
+ globalvrefindac = MIN(globalvrefindac, (uint8_t)127);
+
+ vrefinglobal = (uint16_t)((globalvrefindac << CSR_GLOBALVREFINDAC_LSB) | globalvrefinsel);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_VREFINGLOBAL_ADDR))),
+ vrefinglobal);
+
+ dqdqsrcvcntrl = (uint16_t)((gaincurradj_defval << CSR_GAINCURRADJ_LSB) |
+ (majormodedbyte << CSR_MAJORMODEDBYTE_LSB) |
+ (dfectrl_defval << CSR_DFECTRL_LSB) |
+ (extvrefrange_defval << CSR_EXTVREFRANGE_LSB) |
+ (selanalogvref << CSR_SELANALOGVREF_LSB));
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t lane;
+
+ c_addr = byte << 12;
+ for (lane = 0U; lane <= B_MAX; lane++) {
+ uint32_t b_addr;
+
+ b_addr = lane << 8;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr |
+ CSR_DQDQSRCVCNTRL_ADDR))),
+ dqdqsrcvcntrl);
+ }
+ }
+}
+
+/*
+ * Program dfifreqratio :
+ * - Dependencies:
+ * - user_input_basic.dfifreqratio
+ */
+static void dfifreqratio_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t dfifreqratio;
+
+ dfifreqratio = (uint16_t)config->uib.dfifreqratio;
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFIFREQRATIO_ADDR))),
+ dfifreqratio);
+}
+
+/*
+ * Program tristatemodeca based on dramtype and 2T Timing
+ * - Fields:
+ * - CkDisVal
+ * - disdynadrtri
+ * - ddr2tmode
+ * - Dependencies:
+ * - user_input_advanced.is2ttiming
+ * - user_input_advanced.disdynadrtri
+ */
+static void tristatemodeca_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t ckdisval_def;
+ uint32_t ddr2tmode;
+ uint32_t disdynadrtri;
+ uint16_t tristatemodeca;
+
+ /* CkDisVal depends on dramtype */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ ckdisval_def = 1U; /* {CLK_t,CLK_c} = 2'b00; */
+#else /* STM32MP_LPDDR4_TYPE */
+ ckdisval_def = 0U; /* {CLK_t,CLK_c} = 2'b01; */
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ disdynadrtri = config->uia.disdynadrtri;
+#else /* STM32MP_LPDDR4_TYPE */
+ disdynadrtri = 1U;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ ddr2tmode = config->uia.is2ttiming;
+
+ tristatemodeca = (uint16_t)((ckdisval_def << CSR_CKDISVAL_LSB) |
+ (ddr2tmode << CSR_DDR2TMODE_LSB) |
+ (disdynadrtri << CSR_DISDYNADRTRI_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_TRISTATEMODECA_ADDR))),
+ tristatemodeca);
+}
+
+/*
+ * Program DfiXlat based on Pll Bypass Input
+ * - Dependencies:
+ * - user_input_basic.frequency
+ * - user_input_basic.pllbypass
+ */
+static void dfixlat_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t loopvector;
+ uint16_t pllbypass_dat = 0U;
+ uint16_t skipddc_dat = 0U; /*
+ * Set to vector offset based on frequency to disable dram
+ * drift compensation.
+ */
+
+ pllbypass_dat |= (uint16_t)config->uib.pllbypass;
+
+ if (config->uib.frequency < 333U) {
+ skipddc_dat |= 0x5U;
+ }
+
+ for (loopvector = 0U; loopvector < 8U; loopvector++) {
+ uint16_t dfifreqxlat_dat;
+ uintptr_t reg = (uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER |
+ (CSR_DFIFREQXLAT0_ADDR +
+ loopvector))));
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if (loopvector == 0U) {
+ /*
+ * Relock DfiFreq = 00,01,02,03) Use StartVec 5 (pll_enabled) or
+ * StartVec 6 (pll_bypassed).
+ */
+ dfifreqxlat_dat = pllbypass_dat + 0x5555U;
+
+ mmio_write_16(reg, dfifreqxlat_dat);
+ } else if (loopvector == 7U) {
+ /* LP3-entry DfiFreq = 1F */
+ mmio_write_16(reg, 0xF000U);
+ } else {
+ /*
+ * Everything else = skip retrain (could also map to 0000 since retrain
+ * code is excluded, but this is cleaner).
+ */
+ mmio_write_16(reg, 0x5555U);
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ if (loopvector == 0U) {
+ /*
+ * Retrain & Relock DfiFreq = 00,01,02,03) Use StartVec 0 (pll_enabled) or
+ * StartVec 1 (pll_bypassed).
+ */
+ dfifreqxlat_dat = pllbypass_dat + skipddc_dat;
+ mmio_write_16(reg, dfifreqxlat_dat);
+ } else if (loopvector == 2U) {
+ /*
+ * Retrain only DfiFreq = 08,09,0A,0B) Use StartVec 4 (1, and maybe 2,3,
+ * used by verif).
+ */
+ mmio_write_16(reg, 0x4444U);
+ } else if (loopvector == 3U) {
+ /* Phymstr type state change, StartVec 8 */
+ mmio_write_16(reg, 0x8888U);
+ } else if (loopvector == 4U) {
+ /*
+ * Relock only DfiFreq = 10,11,12,13 Use StartVec 5 (pll_enabled) or
+ * StartVec 6 (pll_bypassed).
+ */
+ dfifreqxlat_dat = pllbypass_dat + 0x5555U;
+ mmio_write_16(reg, dfifreqxlat_dat);
+ } else if (loopvector == 7U) {
+ /* LP3-entry DfiFreq = 1F */
+ mmio_write_16(reg, 0xF000U);
+ } else {
+ /* Everything else */
+ mmio_write_16(reg, 0x0000U);
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ }
+}
+
+/*
+ * Program dqdqsrcvcntrl1 (Receiver Powerdown) and DbyteMiscMode
+ * - see function ddrphy_phyinit_isdbytedisabled() to determine
+ * which DBytes are turned off completely based on PHY configuration.
+ * - Fields:
+ * - DByteDisable
+ * - PowerDownRcvr
+ * - PowerDownRcvrDqs
+ * - RxPadStandbyEn
+ * - Dependencies:
+ * - user_input_basic.numdbyte
+ * - user_input_basic.dramdatawidth (DDR3/DDR4)
+ * - mb_ddr_1d->mr5 (DDR4)
+ * - user_input_advanced.lp4dbird (LPDDR4)
+ */
+static void dqdqsrcvcntrl1_program(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ uint32_t d;
+ uint16_t mr5 __maybe_unused;
+ uint16_t regdata;
+ uint16_t regdata1;
+ uint16_t regdata2; /* Turn off Rx of DBI lane */
+
+ regdata = 0x1U << CSR_DBYTEDISABLE_LSB;
+
+ regdata1 = (0x1FFU << CSR_POWERDOWNRCVR_LSB) |
+ (0x1U << CSR_POWERDOWNRCVRDQS_LSB) |
+ (0x1U << CSR_RXPADSTANDBYEN_LSB);
+
+ regdata2 = (0x100U << CSR_POWERDOWNRCVR_LSB) | CSR_RXPADSTANDBYEN_MASK;
+
+#if STM32MP_DDR4_TYPE
+ /* OR all mr4 masked values, to help check in next loop */
+ mr5 = (mb_ddr_1d->mr5 >> 12) & 0x1U;
+#endif /* STM32MP_DDR4_TYPE */
+
+ for (d = 0U; d < config->uib.numdbyte; d++) {
+ uint32_t c_addr;
+
+ c_addr = d * C1;
+ if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, d) != 0) {
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_DBYTEMISCMODE_ADDR))),
+ regdata);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_DQDQSRCVCNTRL1_ADDR))),
+ regdata1);
+ } else {
+ /* Disable RDBI lane if not used. */
+#if STM32MP_DDR3_TYPE
+ if (config->uib.dramdatawidth != 4U) {
+#elif STM32MP_DDR4_TYPE
+ if ((config->uib.dramdatawidth != 4U) && (mr5 == 0U)) {
+#else /* STM32MP_LPDDR4_TYPE */
+ if (config->uia.lp4dbird == 0U) {
+#endif /* STM32MP_DDR3_TYPE */
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_DQDQSRCVCNTRL1_ADDR))),
+ regdata2);
+ }
+ }
+ }
+}
+
+/*
+ * Program masterx4config
+ * - Fields:
+ * - x4tg
+ * - masterx4config
+ * - Dependencies:
+ * - user_input_basic.dramdatawidth
+ *
+ * \note PHY does not support mixed dram device data width
+ */
+static void masterx4config_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t x4tg = 0U;
+ uint16_t masterx4config;
+
+ if (config->uib.dramdatawidth == 4U) {
+ x4tg = 0xFU;
+ }
+
+ masterx4config = (uint16_t)(x4tg << CSR_X4TG_LSB);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MASTERX4CONFIG_ADDR))),
+ masterx4config);
+}
+
+#if !STM32MP_DDR3_TYPE
+/*
+ * Program dmipinpresent based on dramtype and Read-DBI enable
+ * - Fields:
+ * - RdDbiEnabled
+ * - Dependencies:
+ * - mb_ddr_1d->mr5 (DDR4)
+ * - user_input_advanced.lp4dbird (LPDDR4)
+ */
+static void dmipinpresent_program(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ uint16_t dmipinpresent;
+
+#if STM32MP_DDR4_TYPE
+ /* For DDR4, Read DBI is enabled in mr5-A12 */
+ dmipinpresent = (mb_ddr_1d->mr5 >> 12) & 0x1U;
+#else /* STM32MP_LPDDR4_TYPE */
+ dmipinpresent = (uint16_t)config->uia.lp4dbird;
+#endif /* STM32MP_DDR4_TYPE */
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DMIPINPRESENT_ADDR))),
+ dmipinpresent);
+}
+#endif /* !STM32MP_DDR3_TYPE */
+
+/*
+ * Program aforcetricont and acx4anibdis
+ * - Fields:
+ * - aforcetricont
+ * - acx4anibdis
+ * - Dependencies:
+ * - user_input_basic.numrank_dfi0
+ * - user_input_basic.numrank_dfi1
+ * - user_input_basic.numanib
+ * - user_input_advanced.disableunusedaddrlns
+ */
+static void aforcetricont_acx4anibdis_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t anib;
+ uint16_t acx4anibdis = 0x0U;
+
+ for (anib = 0U; (anib < config->uib.numanib) && (config->uia.disableunusedaddrlns != 0U);
+ anib++) {
+ uint32_t c_addr;
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ uint32_t numrank = config->uib.numrank_dfi0 + config->uib.numrank_dfi1;
+#else /* STM32MP_LPDDR4_TYPE */
+ uint32_t numrank0 = config->uib.numrank_dfi0;
+ uint32_t numrank1 = config->uib.numrank_dfi1;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ uint16_t aforcetricont = 0x0U;
+
+ c_addr = anib << 12;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if ((anib == 0U) && (numrank == 1U)) {
+ aforcetricont = 0x2U;
+ } else if ((anib == 1U) && (numrank == 1U)) {
+ aforcetricont = 0xCU;
+ } else if (anib == 6U) {
+ aforcetricont = 0x1U;
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ if ((anib == 0U) && (numrank0 == 0U)) {
+ aforcetricont = 0xFU;
+ } else if ((anib == 0U) && (numrank0 == 1U)) {
+ aforcetricont = 0x2U;
+ } else if ((anib == 1U) && (numrank0 == 0U)) {
+ aforcetricont = 0xFU;
+ } else if ((anib == 1U) && (numrank0 == 1U)) {
+ aforcetricont = 0x8U;
+ } else if ((anib == 2U) && (numrank0 == 0U)) {
+ aforcetricont = 0xFU;
+ } else if ((anib == 3U) && (numrank1 == 0U)) {
+ aforcetricont = 0xFU;
+ } else if ((anib == 3U) && (numrank1 == 1U)) {
+ aforcetricont = 0x2U;
+ } else if ((anib == 4U) && (numrank1 == 0U)) {
+ aforcetricont = 0xFU;
+ } else if ((anib == 4U) && (numrank1 == 1U)) {
+ aforcetricont = 0x8U;
+ } else if ((anib == 5U) && (numrank1 == 0U)) {
+ aforcetricont = 0xFU;
+ } else if (anib == 6U) {
+ aforcetricont = 0xFU;
+ } else if (anib == 7U) {
+ aforcetricont = 0xFU;
+ }
+
+ /*
+ * If all the lanes can be disabled, and Anib is not the first or last disable
+ * entire chiplet
+ */
+ if ((aforcetricont == 0xFU) && (anib != 0U) &&
+ (anib != (config->uib.numanib - 1U))) {
+ acx4anibdis = acx4anibdis | (0x1U << anib);
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr |
+ CSR_AFORCETRICONT_ADDR))),
+ aforcetricont);
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_ACX4ANIBDIS_ADDR))),
+ acx4anibdis);
+}
+
+/*
+ * Implements Step C of initialization sequence
+ *
+ * This function programs majority of PHY configuration registers based
+ * on data input into PhyInit data structures.
+ *
+ * This function programs PHY configuration registers based on information
+ * provided in the PhyInit data structures (config->uib, config->uia).
+ * The user can overwrite the programming of this function by modifying
+ * ddrphy_phyinit_usercustom_custompretrain(). Please see
+ * ddrphy_phyinit_struct.h for PhyInit data structure definition.
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t *ardptrinitval)
+{
+ uint32_t twotckrxdqspre;
+ int ret;
+
+ /*
+ * Step (C) Initialize PHY Configuration
+ * Load the required PHY configuration registers for the appropriate mode and memory
+ * configuration.
+ */
+
+ txslewrate_program(config);
+
+ atxslewrate_program(config);
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ dfidatacsdestmap_program(mb_ddr_1d);
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ pllctrl2_program(config);
+
+ ardptrinitval_program(config, ardptrinitval);
+
+#if STM32MP_LPDDR4_TYPE
+ procodtctl_program();
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ dbytedllmodecntrl_program(config, &twotckrxdqspre);
+
+ procodttimectl_program(config, twotckrxdqspre);
+
+ ret = txodtdrvstren_program(config);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = tximpedancectrl1_program(config);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = atximpedance_program(config);
+ if (ret != 0) {
+ return ret;
+ }
+
+ dfimode_program(config);
+
+ dficamode_program();
+
+ caldrvstr0_program(config);
+
+ caluclkinfo_program(config);
+
+ calibration_program(config);
+
+ vrefinglobal_program(config, mb_ddr_1d);
+
+ dfifreqratio_program(config);
+
+ tristatemodeca_program(config);
+
+ dfixlat_program(config);
+
+ dqdqsrcvcntrl1_program(config, mb_ddr_1d);
+
+ masterx4config_program(config);
+
+#if !STM32MP_DDR3_TYPE
+ dmipinpresent_program(config, mb_ddr_1d);
+
+#if STM32MP_LPDDR4_TYPE
+ /*
+ * Program DFIPHYUPD
+ * - Fields:
+ * - DFIPHYUPDMODE
+ * - DFIPHYUPDCNT
+ * - Dependencies:
+ * - user_input_advanced.disablephyupdate
+ */
+ if (config->uia.disablephyupdate != 0U) {
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFIPHYUPD_ADDR))),
+ 0x0U);
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+#endif /* !STM32MP_DDR3_TYPE */
+
+ aforcetricont_acx4anibdis_program(config);
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c
new file mode 100644
index 0000000..c5fa5f1
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+/*
+ * Reads PhyInit inputs structures and sets relevant message block
+ * parameters.
+ *
+ * This function sets Message Block parameters based on user_input_basic and
+ * user_input_advanced. user changes in these files takes precedence
+ * over this function call.
+ *
+ * MessageBlock fields set :
+ * - dramtype
+ * - pstate
+ * - dramfreq
+ * - pllbypassen
+ * - dfifreqratio
+ * - phyodtimpedance
+ * - phydrvimpedance
+ * - bpznresval
+ * - enableddqscha (LPDDR4)
+ * - cspresentcha (LPDDR4)
+ * - enableddqsChb (LPDDR4)
+ * - cspresentchb (LPDDR4)
+ * - enableddqs (DDR3/DDR4)
+ * - phycfg (DDR3/DDR4)
+ * - x16present (DDR4)
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ uint32_t nad0 = config->uib.numactivedbytedfi0;
+ uint32_t nad1 = 0;
+ uint16_t mr4 __maybe_unused;
+ uint16_t disableddbyte __maybe_unused;
+ uint32_t dbyte __maybe_unused;
+ int ret;
+
+#if STM32MP_LPDDR4_TYPE
+ nad1 = config->uib.numactivedbytedfi1;
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ /* A few checks to make sure valid programming */
+ if ((nad0 == 0U) || (config->uib.numdbyte == 0U)) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s numactivedbytedfi0, numactivedbytedfi0, NumByte out of range.\n",
+ __func__);
+ return -1;
+ }
+
+ if ((nad0 + nad1) > config->uib.numdbyte) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s numactivedbytedfi0+numactivedbytedfi1 is larger than numdbyteDfi0\n",
+ __func__);
+ return -1;
+ }
+
+ if ((config->uib.dfi1exists == 0U) && (nad1 != 0U)) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s dfi1exists==0 but numdbyteDfi0 != 0\n", __func__);
+ return -1;
+ }
+
+#if STM32MP_DDR4_TYPE
+ /* OR all mr4 masked values, to help check in next loop */
+ mr4 = mb_ddr_1d->mr4 & 0x1C0U;
+
+ /* 1D message block defaults */
+ if (mr4 != 0x0U) {
+ ERROR("mr4 != 0x0\n");
+ VERBOSE("%s Setting DRAM CAL mode is not supported by the PHY.\n", __func__);
+ VERBOSE("Memory controller may set CAL mode after PHY has entered mission\n");
+ VERBOSE("mode. Please check value programmed in mb_ddr_1d[*].mr4\n");
+ VERBOSE("and unset A8:6\n");
+ return -1;
+ }
+#endif /* STM32MP_DDR4_TYPE */
+
+#if STM32MP_DDR3_TYPE
+ if (config->uib.dimmtype == DDR_DIMMTYPE_NODIMM) {
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMTYPE, 0x1U);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+#elif STM32MP_DDR4_TYPE
+ if (config->uib.dimmtype == DDR_DIMMTYPE_NODIMM) {
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMTYPE, 0x2U);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ /* Nothing to do */
+#endif /* STM32MP_DDR3_TYPE */
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PSTATE, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMFREQ, config->uib.frequency * 2U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PLLBYPASSEN, config->uib.pllbypass);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (config->uib.dfifreqratio == 1U) {
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DFIFREQRATIO, 0x2U);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYODTIMPEDANCE, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYDRVIMPEDANCE, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_BPZNRESVAL, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_ENABLEDDQS, nad0 * 8U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ disableddbyte = 0x0U;
+
+ for (dbyte = 0U; (dbyte < config->uib.numdbyte) && (dbyte < 8U); dbyte++) {
+ if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, dbyte) != 0) {
+ disableddbyte |= 0x1U << dbyte;
+ }
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DISABLEDDBYTE, disableddbyte);
+ if (ret != 0) {
+ return ret;
+ }
+
+#if STM32MP_DDR3_TYPE
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYCFG, config->uia.is2ttiming);
+ if (ret != 0) {
+ return ret;
+ }
+#else /* STM32MP_DDR4_TYPE */
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYCFG,
+ ((mb_ddr_1d->mr3 & 0x8U) != 0U) ?
+ 0U : config->uia.is2ttiming);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_X16PRESENT,
+ (config->uib.dramdatawidth == 0x10U) ?
+ mb_ddr_1d->cspresent : 0x0U);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_DDR3_TYPE */
+#else /* STM32MP_LPDDR4_TYPE */
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_ENABLEDDQSCHA, nad0 * 8U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_CSPRESENTCHA,
+ (config->uib.numrank_dfi0 == 2U) ?
+ 0x3U : config->uib.numrank_dfi0);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_ENABLEDDQSCHB, nad1 * 8U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_CSPRESENTCHB,
+ (config->uib.numrank_dfi1 == 2U) ?
+ 0x3U : config->uib.numrank_dfi1);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c
new file mode 100644
index 0000000..8bec30b
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*
+ * This function loads the training firmware IMEM image into the PHY.
+ *
+ * This function reads the DDR firmware source memory area to generate a
+ * set of apb writes to load IMEM image into the PHY. The exact steps in this
+ * function are as follows:
+ *
+ * -# Ensure DRAM is in reset.
+ * -# Load the microcontroller memory with the provided training firmware
+ * -# Initialize the firmware mailbox structures to be able to communicate with
+ * the firmware.
+ *
+ * \return void
+ */
+void ddrphy_phyinit_d_loadimem(void)
+{
+ uint16_t memresetl;
+ uint32_t *ptr32;
+
+ /* Set memresetl to avoid glitch on BP_MemReset_L during training */
+ memresetl = CSR_PROTECTMEMRESET_MASK;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MEMRESETL_ADDR))), memresetl);
+
+ ptr32 = (uint32_t *)(STM32MP_DDR_FW_BASE + STM32MP_DDR_FW_IMEM_OFFSET);
+ ddrphy_phyinit_writeoutmem(ptr32, IMEM_ST_ADDR, IMEM_SIZE);
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c
new file mode 100644
index 0000000..3c6c87f
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <platform_def.h>
+
+/*
+ * This function loads the training firmware DMEM image and write the
+ * Message Block parameters for the training firmware into the PHY.
+ *
+ * This function performs the following tasks:
+ *
+ * -# Load the firmware DMEM segment to initialize the data structures from the
+ * DDR firmware source memory area.
+ * -# Write the Firmware Message Block with the required contents detailing the training parameters.
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ uint32_t sizeofmsgblk;
+ uint16_t *ptr16;
+ uint32_t *ptr32;
+
+ /* Some basic checks on MessageBlock */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if ((mb_ddr_1d->enableddqs > (8U * (uint8_t)config->uib.numactivedbytedfi0)) ||
+ (mb_ddr_1d->enableddqs <= 0U)) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s enableddqs is Zero or greater than NumActiveDbytes for Dfi0\n",
+ __func__);
+ return -1;
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ if (((mb_ddr_1d->enableddqscha % 16U) != 0U) || ((mb_ddr_1d->enableddqschb % 16U) != 0U)) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s Lp3/Lp4 - Number of Dq's Enabled per Channel much be multipe of 16\n",
+ __func__);
+ return -1;
+ }
+
+ if ((mb_ddr_1d->enableddqscha > (uint8_t)(8U * config->uib.numactivedbytedfi0)) ||
+ (mb_ddr_1d->enableddqschb > (uint8_t)(8U * config->uib.numactivedbytedfi1)) ||
+ ((mb_ddr_1d->enableddqscha == 0U) && (mb_ddr_1d->enableddqschb == 0U))) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s EnabledDqsChA/B are not set correctly./1\n", __func__);
+ return -1;
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ sizeofmsgblk = sizeof(struct pmu_smb_ddr_1d);
+
+ ptr16 = (uint16_t *)mb_ddr_1d;
+ ddrphy_phyinit_writeoutmsgblk(ptr16, DMEM_ST_ADDR, sizeofmsgblk);
+
+ ptr32 = (uint32_t *)(STM32MP_DDR_FW_BASE + STM32MP_DDR_FW_DMEM_OFFSET);
+ ddrphy_phyinit_writeoutmem(ptr32, DMEM_ST_ADDR + DMEM_BIN_OFFSET,
+ DMEM_SIZE - STM32MP_DDR_FW_DMEM_OFFSET);
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c
new file mode 100644
index 0000000..0c11594
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*
+ * Execute the Training Firmware
+ *
+ * The training firmware is executed with the procedure:
+ *
+ * -# Reset the firmware microcontroller by writing the MicroReset register to
+ * set the StallToMicro and ResetToMicro fields to 1 (all other fields should be
+ * zero). Then rewrite the registers so that only the StallToMicro remains set
+ * (all other fields should be zero).
+ * -# Begin execution of the training firmware by setting the MicroReset
+ * register to 0.
+ * -# Wait for the training firmware to complete by following the procedure implemented in
+ * ddrphy_phyinit_usercustom_g_waitfwdone() function.
+ * -# Halt the microcontroller.
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_g_execfw(void)
+{
+ int ret;
+
+ /*
+ * 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the
+ * StallToMicro and ResetToMicro fields to 1 (all other fields should be zero).
+ * Then rewrite the CSR so that only the StallToMicro remains set (all other fields should
+ * be zero).
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ CSR_STALLTOMICRO_MASK);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))),
+ CSR_RESETTOMICRO_MASK | CSR_STALLTOMICRO_MASK);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))),
+ CSR_STALLTOMICRO_MASK);
+
+ /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 0 */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 0x0U);
+
+ /*
+ * 3. Wait for the training firmware to complete by following the procedure
+ * implemented in ddrphy_phyinit_usercustom_g_waitfwdone() function.
+ */
+ ret = ddrphy_phyinit_usercustom_g_waitfwdone();
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* 4. Halt the microcontroller */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))),
+ CSR_STALLTOMICRO_MASK);
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c
new file mode 100644
index 0000000..6ca0ddc
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c
@@ -0,0 +1,394 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#if STM32MP_LPDDR4_TYPE
+/*
+ * Program DfiWrRdDataCsConfig
+ * - Fields:
+ * - dfiwrdatacspolarity
+ * - dfirddatacspolarity
+ */
+static void dfiwrrddatacsconfig_program(void)
+{
+ uint16_t dfiwrdatacspolarity;
+ uint16_t dfirddatacspolarity;
+
+ /*
+ * DfiWrRdDataCsConfig : dfiwrdatacspolarity=0x1 and dfirddatacspolarity=0x1.
+ * Set DataCsPolarity bits to enable active high
+ */
+ dfiwrdatacspolarity = 0x1U;
+ dfirddatacspolarity = 0x1U;
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | C0 |
+ CSR_DFIWRRDDATACSCONFIG_ADDR))),
+ (dfiwrdatacspolarity << CSR_DFIWRDATACSPOLARITY_LSB) |
+ (dfirddatacspolarity << CSR_DFIRDDATACSPOLARITY_LSB));
+}
+#endif /* STM32MP_LPDDR4_TYPE */
+
+/*
+ * Registers: Seq0BDLY0, Seq0BDLY1, Seq0BDLY2, Seq0BDLY3
+ * - Program PIE instruction delays
+ * - Dependencies:
+ * - user_input_basic.frequency
+ */
+static void seq0bdly_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t lowfreqopt __unused;
+ uint16_t dfifrq_x10;
+ uint16_t pscount_ref;
+ uint16_t pscount[4]; /* Need delays for 0.5us, 1us, 10us, and 25us */
+
+ /*
+ * Calculate the counts to obtain the correct delay for each frequency
+ * Need to divide by 4 since the delay value are specified in units of
+ * 4 clocks.
+ */
+ dfifrq_x10 = (10U * (uint16_t)config->uib.frequency) / 2U;
+ pscount_ref = dfifrq_x10 / 4U;
+ pscount[0] = pscount_ref / (2U * 10U);
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if (config->uib.frequency < 400U) {
+ lowfreqopt = 3U;
+ } else if (config->uib.frequency < 533U) {
+ lowfreqopt = 11U;
+ } else {
+ lowfreqopt = 0U;
+ }
+
+ pscount[1] = (pscount_ref / 10U) - lowfreqopt;
+#else /* STM32MP_LPDDR4_TYPE */
+ pscount[1] = pscount_ref / 10U;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ pscount[2] = pscount_ref;
+
+ if (dfifrq_x10 > 2665U) {
+ pscount[3] = 44U;
+ } else if ((dfifrq_x10 <= 2665U) && (dfifrq_x10 > 2000U)) {
+ pscount[3] = 33U;
+ } else {
+ pscount[3] = 16U;
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY0_ADDR))),
+ pscount[0]);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY1_ADDR))),
+ pscount[1]);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY2_ADDR))),
+ pscount[2]);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY3_ADDR))),
+ pscount[3]);
+}
+
+/*
+ * Registers: Seq0BDisableFlag0..7
+ * - Program PIE Instruction Disable Flags
+ * - Dependencies:
+ * - user_input_advanced.DisableRetraining (LPDDR4)
+ * - skip_training (LPDDR4)
+ * - user_input_basic.frequency (LPDDR4)
+ */
+static void seq0bdisableflag_program(struct stm32mp_ddr_config *config, bool skip_training)
+{
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG0_ADDR))),
+ 0x0000U);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG1_ADDR))),
+ 0x0173U);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG2_ADDR))),
+ 0x0060U);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG3_ADDR))),
+ 0x6110U);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG4_ADDR))),
+ 0x2152U);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG5_ADDR))),
+ 0xDFBDU);
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG6_ADDR))),
+ 0xFFFFU);
+#else /* STM32MP_LPDDR4_TYPE */
+ if (skip_training || (config->uia.disableretraining != 0U) ||
+ (config->uib.frequency < 333U)) {
+ /* Disabling DRAM drift compensation */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG |
+ CSR_SEQ0BDISABLEFLAG6_ADDR))),
+ 0xFFFFU);
+ } else {
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG |
+ CSR_SEQ0BDISABLEFLAG6_ADDR))),
+ 0x2060U);
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ /*
+ * - Register: Seq0BGPR7
+ * - Program active CSx for MRS7 during D4 RDIMM frequency change
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG7_ADDR))),
+ 0x6152U);
+}
+
+#if STM32MP_LPDDR4_TYPE
+/*
+ * Registers: ppttrainsetup and ppttrainsetup2
+ * - Related to DFI PHY Master Interface (PMI).
+ * - Enable DFI PMI if training firmware was run
+ * - Fields:
+ * - PhyMstrTrainInterval
+ * - PhyMstrMaxReqToAck
+ * - PhyMstrFreqOverride
+ * - Dependencies:
+ * - user_input_basic.frequency
+ * - user_input_advanced.PhyMstrTrainInterval
+ * - user_input_advanced.PhyMstrMaxReqToAck
+ */
+static void ppttrainsetup_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t ppttrainsetup;
+
+ /* Enabling Phy Master Interface for DRAM drift compensation */
+ if (config->uib.frequency >= 333U) {
+ ppttrainsetup = (uint16_t)((config->uia.phymstrtraininterval <<
+ CSR_PHYMSTRTRAININTERVAL_LSB) |
+ (config->uia.phymstrmaxreqtoack <<
+ CSR_PHYMSTRMAXREQTOACK_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PPTTRAINSETUP_ADDR))),
+ ppttrainsetup);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER |
+ CSR_PPTTRAINSETUP2_ADDR))),
+ 0x0003U);
+ }
+}
+
+/*
+ * Registers AcsmPlayback*x*
+ * - Program Address/Command Sequence Engine (ACSM) registers with
+ * required instructions for retraining algorithm.
+ */
+static void acsmplayback_program(void)
+{
+ uint32_t vec;
+
+ for (vec = 0U; vec < 3U; vec++) {
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TACSM | (CSR_ACSMPLAYBACK0X0_ADDR +
+ (vec * 2U))))),
+ 0xE0U);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TACSM | (CSR_ACSMPLAYBACK1X0_ADDR +
+ (vec * 2U))))),
+ 0x12U);
+ }
+}
+
+/*
+ * Program Training Hardware Registers for mission mode retraining
+ * and DRAM drift compensation algorithm.
+ */
+static void traininghwreg_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t byte;
+
+ /* Programing Training Hardware Registers for mission mode retraining */
+
+ /*
+ * - Register: AcsmCtrl13
+ * - Fields: AcsmCkeEnb
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL13_ADDR))),
+ 0xFU << CSR_ACSMCKEENB_LSB);
+
+ /*
+ * - Register: AcsmCtrl1
+ * - Fields: AcsmRepCnt
+ * Need 19 iterations @ 0.25ui increments to cover 4.5UI
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL1_ADDR))),
+ 0xEU << CSR_ACSMREPCNT_LSB);
+
+ /*
+ * - Register: TsmByte1, TsmByte2
+ * - Dependencies: config->uib.numdbyte
+ */
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t i_addr;
+ uint16_t regdata;
+ uint32_t vec;
+
+ c_addr = byte * C1;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_TSMBYTE1_ADDR))),
+ 0x1U); /* [15:8] gstep; [7:0]bstep; */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_TSMBYTE2_ADDR))),
+ 0x1U); /* [15:0] good_bar; */
+
+ regdata = (CSR_DTSMSTATICCMPR_MASK | CSR_DTSMSTATICCMPRVAL_MASK);
+
+ /*
+ * - Register: TsmByte3, TsmByte5
+ * - Fields:
+ * - DtsmStaticCmpr
+ * - DtsmStaticCmprVal
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_TSMBYTE3_ADDR))),
+ regdata);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_TSMBYTE5_ADDR))),
+ 0x1U); /* [15:0] bad_bar; */
+
+ /*
+ * - Register: TrainingParam
+ * - Fields:
+ * - EnDynRateReduction
+ * - RollIntoCoarse
+ * - IncDecRate
+ * - TrainEnRxEn
+ * - Dependencies:
+ * - user_input_advanced.DisableRetraining
+ */
+ regdata = (CSR_ENDYNRATEREDUCTION_MASK | CSR_ROLLINTOCOARSE_MASK |
+ (0x3U << CSR_INCDECRATE_LSB));
+ regdata = config->uia.disableretraining ?
+ regdata : (regdata | CSR_TRAINENRXEN_MASK);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_TRAININGPARAM_ADDR))),
+ regdata);
+
+ /*
+ * - Register: Tsm0
+ * - Fields:
+ * - DtsmEnb
+ */
+ regdata = (0x1U << CSR_DTSMENB_LSB);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | I0 | TDBYTE |
+ CSR_TSM0_ADDR))),
+ regdata);
+
+ /*
+ * - Register: Tsm2
+ * - Fields:
+ * - DtsmDisErrChk
+ */
+ regdata = (0x1U << CSR_DTSMDISERRCHK_LSB);
+ for (vec = 1U; vec <= I_MAX; vec++) {
+ i_addr = vec * I1;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | i_addr | TDBYTE |
+ CSR_TSM2_ADDR))),
+ regdata);
+ }
+ }
+}
+#endif /* STM32MP_LPDDR4_TYPE */
+
+/*
+ * - Register: calrate
+ * - Fields:
+ * - calOnce
+ * - calinterval
+ * - Dependencies
+ * - user_input_advanced.calinterval
+ * - user_input_advanced.calonce
+ */
+static void calrate_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t calinterval;
+ uint32_t calonce;
+ uint16_t calrate;
+
+ calinterval = config->uia.calinterval;
+ calonce = config->uia.calonce;
+
+ calrate = (uint16_t)((0x1U << CSR_CALRUN_LSB) | (calonce << CSR_CALONCE_LSB) |
+ (calinterval << CSR_CALINTERVAL_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALRATE_ADDR))), calrate);
+}
+
+/*
+ * Loads registers after training
+ *
+ * This function programs the PHY Initialization Engine (PIE) instructions and
+ * the associated registers.
+ * Training hardware registers are also programmed to for mission mode
+ * retraining. (LPDDR4)
+ *
+ * \return void
+ */
+void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training)
+{
+ /*
+ * Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+ * This allows the memory controller unrestricted access to the configuration CSRs.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x0U);
+
+ ddrphy_phyinit_loadpieprodcode();
+
+#if STM32MP_LPDDR4_TYPE
+ /*
+ * No user specified EnableDfiCsPolarityFix, running with new PUB with DFI CS polarity fix
+ * so program the data polarity CSR.
+ */
+ dfiwrrddatacsconfig_program();
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ seq0bdly_program(config);
+
+ seq0bdisableflag_program(config, skip_training);
+
+#if STM32MP_LPDDR4_TYPE
+ if (!skip_training) {
+ ppttrainsetup_program(config);
+ }
+
+ acsmplayback_program();
+
+ traininghwreg_program(config);
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ /*
+ * - Register: CalZap
+ * - Prepare the calibration controller for mission mode.
+ * Turn on calibration and hold idle until dfi_init_start is asserted sequence is
+ * triggered.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALZAP_ADDR))), 0x1U);
+
+ calrate_program(config);
+
+ /*
+ * At the end of this function, PHY Clk gating register UcclkHclkEnables is
+ * set for mission mode. Additionally APB access is Isolated by setting
+ * MicroContMuxSel.
+ */
+ /* Disabling Ucclk (PMU) and Hclk (training hardware) */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
+ 0x0U);
+
+ /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1 */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x1U);
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c
new file mode 100644
index 0000000..50a88be
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+/*
+ * This is used to initialize the PhyInit structures before user defaults and overrides are applied.
+ *
+ * @return Void
+ */
+void ddrphy_phyinit_initstruct(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ /*
+ * ##############################################################
+ * Basic Message Block Variables
+ * ##############################################################
+ */
+
+ uint8_t msgmisc = 0x00U; /* For fast simulation */
+ uint8_t reserved00 = 0x0U; /*
+ * Set reserved00[7] = 1 (If using T28 attenuated receivers)
+ * Set reserved00[6:0] = 0 (Reserved; must be set to 0)
+ */
+
+ uint8_t hdtctrl = 0xFFU;
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ uint8_t cspresent = 0x01U; /*
+ * Indicates presence of DRAM at each chip select for PHY.
+ *
+ * If the bit is set to 1, the CS is connected to DRAM.
+ * If the bit is set to 0, the CS is not connected to DRAM.
+ *
+ * Set cspresent[0] = 1 (if CS0 is populated with DRAM)
+ * Set cspresent[1] = 1 (if CS1 is populated with DRAM)
+ * Set cspresent[2] = 1 (if CS2 is populated with DRAM)
+ * Set cspresent[3] = 1 (if CS3 is populated with DRAM)
+ * Set cspresent[7:4] = 0 (Reserved; must be set to 0)
+ */
+ uint8_t dfimrlmargin = 0x01U; /* 1 is typically good in DDR3 */
+#if STM32MP_DDR3_TYPE
+ uint8_t addrmirror = 0x00U; /*
+ * Set addrmirror if CS is mirrored.
+ * (typically odd CS are mirroed in DIMMs)
+ */
+#else /* STM32MP_DDR4_TYPE */
+ uint8_t addrmirror = 0xAAU;
+#endif /* STM32MP_DDR3_TYPE */
+ uint8_t wrodtpat_rank0 = 0x01U; /*
+ * When Writing Rank0 : Bits[3:0] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+ uint8_t wrodtpat_rank1 = 0x02U; /*
+ * When Writing Rank1 : Bits[3:0] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+#if STM32MP_DDR3_TYPE
+ uint8_t wrodtpat_rank2 = 0x04U; /*
+ * When Writing Rank2 : Bits[3:0] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+ uint8_t wrodtpat_rank3 = 0x08U; /*
+ * When Writing Rank3 : Bits[3:0] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+#else /* STM32MP_DDR4_TYPE */
+ uint8_t wrodtpat_rank2 = 0x00U;
+ uint8_t wrodtpat_rank3 = 0x00U;
+#endif /* STM32MP_DDR3_TYPE */
+ uint8_t rdodtpat_rank0 = 0x20U; /*
+ * When Reading Rank0 : Bits[7:4] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+ uint8_t rdodtpat_rank1 = 0x10U; /*
+ * When Reading Rank1 : Bits[7:4] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+#if STM32MP_DDR3_TYPE
+ uint8_t rdodtpat_rank2 = 0x80U; /*
+ * When Reading Rank2 : Bits[7:4] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+ uint8_t rdodtpat_rank3 = 0x40U; /*
+ * When Reading Rank3 : Bits[7:4] should be set to the
+ * desired setting of ODT[3:0] to the DRAM
+ */
+#else /* STM32MP_DDR4_TYPE */
+ uint8_t rdodtpat_rank2 = 0x00U;
+ uint8_t rdodtpat_rank3 = 0x00U;
+
+ uint8_t d4misc = 0x1U; /*
+ * Protect memory reset:
+ * 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to
+ * devices after training.
+ * 0x0 = dfi_resert_n can control BP_MEMRESERT_L to
+ * devices after training.
+ */
+#endif /* STM32MP_DDR3_TYPE */
+#else /* STM32MP_LPDDR4_TYPE */
+ uint8_t caterminatingrankcha = 0x00U; /* Usually Rank0 is terminating rank */
+ uint8_t caterminatingrankchb = 0x00U; /* Usually Rank0 is terminating rank */
+ uint8_t dfimrlmargin = 0x02U; /* This needs to be large enough for max tDQSCK variation */
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+#if STM32MP_DDR3_TYPE
+ uint8_t share2dvrefresult = 0x0U; /*
+ * Bitmap that controls which vref generator the
+ * phy will use per pstate
+ * If share2dvrefresult[x] = 1, pstate x will
+ * use the per-lane VrefDAC0/1 CSRs which can be
+ * trained by 2d training. If 2D has not run
+ * yet, VrefDAC0/1 will default to pstate 0's
+ * 1D phyVref messageBlock setting.
+ * If share2dvrefresult[x] = 0, pstate x will
+ * use the per-phy VrefInGlobal CSR, which are
+ * set to pstate x's 1D phyVref messageBlock
+ * setting.
+ */
+#elif STM32MP_DDR4_TYPE
+ uint8_t share2dvrefresult = 0x1U;
+#else /* STM32MP_LPDDR4_TYPE */
+ uint8_t share2dvrefresult = 0x1U;
+ uint8_t usebroadcastmr = 0x00U;
+#endif /* STM32MP_DDR3_TYPE */
+
+ /* 1D message block defaults */
+ memset((void *)mb_ddr_1d, 0, sizeof(struct pmu_smb_ddr_1d));
+
+ mb_ddr_1d->pstate = 0U;
+ mb_ddr_1d->sequencectrl = (uint16_t)config->uia.sequencectrl;
+ mb_ddr_1d->phyconfigoverride = 0x0U;
+ mb_ddr_1d->hdtctrl = hdtctrl;
+ mb_ddr_1d->msgmisc = msgmisc;
+ mb_ddr_1d->reserved00 = reserved00;
+ mb_ddr_1d->dfimrlmargin = dfimrlmargin;
+ mb_ddr_1d->phyvref = (uint8_t)config->uia.phyvref;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ mb_ddr_1d->cspresent = cspresent;
+ mb_ddr_1d->cspresentd0 = cspresent;
+ /* mb_ddr_1d->cspresentd1 = 0x0U; Unused */
+ mb_ddr_1d->addrmirror = addrmirror;
+
+ mb_ddr_1d->acsmodtctrl0 = wrodtpat_rank0 | rdodtpat_rank0;
+ mb_ddr_1d->acsmodtctrl1 = wrodtpat_rank1 | rdodtpat_rank1;
+ mb_ddr_1d->acsmodtctrl2 = wrodtpat_rank2 | rdodtpat_rank2;
+ mb_ddr_1d->acsmodtctrl3 = wrodtpat_rank3 | rdodtpat_rank3;
+
+ /* mb_ddr_1d->acsmodtctrl4 = 0x0U; Unused */
+ /* mb_ddr_1d->acsmodtctrl5 = 0x0U; Unused */
+ /* mb_ddr_1d->acsmodtctrl6 = 0x0U; Unused */
+ /* mb_ddr_1d->acsmodtctrl7 = 0x0U; Unused */
+ mb_ddr_1d->enableddqs = (uint8_t)((config->uib.numactivedbytedfi0 +
+ config->uib.numactivedbytedfi1) * 8U);
+#if STM32MP_DDR3_TYPE
+ mb_ddr_1d->phycfg = (uint8_t)config->uia.is2ttiming;
+#else /* STM32MP_DDR4_TYPE */
+ mb_ddr_1d->phycfg = ((config->uim.mr3 & 0x8U) == 0x8U) ?
+ 0U : (uint8_t)config->uia.is2ttiming;
+ mb_ddr_1d->x16present = (config->uib.dramdatawidth == 0x10) ?
+ mb_ddr_1d->cspresent : 0x0U;
+ mb_ddr_1d->d4misc = d4misc;
+ mb_ddr_1d->cssetupgddec = 0x1U; /* If Geardown is chosen, dynamically modify CS timing */
+
+ /*
+ * Outputs - just initialize these to zero
+ * mb_ddr_1d->rtt_nom_wr_park<0..7>
+ */
+#endif /* STM32MP_DDR3_TYPE */
+
+ mb_ddr_1d->mr0 = (uint16_t)config->uim.mr0;
+ mb_ddr_1d->mr1 = (uint16_t)config->uim.mr1;
+ mb_ddr_1d->mr2 = (uint16_t)config->uim.mr2;
+#if STM32MP_DDR4_TYPE
+ mb_ddr_1d->mr3 = (uint16_t)config->uim.mr3;
+ mb_ddr_1d->mr4 = (uint16_t)config->uim.mr4;
+ mb_ddr_1d->mr5 = (uint16_t)config->uim.mr5;
+ mb_ddr_1d->mr6 = (uint16_t)config->uim.mr6;
+
+ mb_ddr_1d->alt_cas_l = 0x0U;
+ mb_ddr_1d->alt_wcas_l = 0x0U;
+
+ /*
+ * Outputs - just initialize these to zero
+ * mb_ddr_1d->vrefdqr<0..3>nib<0..19>
+ */
+#endif /* STM32MP_DDR4_TYPE */
+#else /* STM32MP_LPDDR4_TYPE */
+ mb_ddr_1d->enableddqscha = (uint8_t)(config->uib.numactivedbytedfi0 * 8U);
+ mb_ddr_1d->cspresentcha = (config->uib.numrank_dfi0 == 2U) ?
+ 0x3U : (uint8_t)config->uib.numrank_dfi0;
+ mb_ddr_1d->enableddqschb = (uint8_t)(config->uib.numactivedbytedfi1 * 8U);
+ mb_ddr_1d->cspresentchb = (config->uib.numrank_dfi1 == 2U) ?
+ 0x3U : (uint8_t)config->uib.numrank_dfi1;
+ mb_ddr_1d->usebroadcastmr = usebroadcastmr;
+
+ mb_ddr_1d->lp4misc = 0x00U;
+ mb_ddr_1d->caterminatingrankcha = caterminatingrankcha;
+ mb_ddr_1d->caterminatingrankchb = caterminatingrankchb;
+ mb_ddr_1d->lp4quickboot = 0x00U;
+ mb_ddr_1d->catrainopt = 0x00U;
+ mb_ddr_1d->x8mode = 0x00U;
+
+ mb_ddr_1d->mr1_a0 = (uint8_t)config->uim.mr1;
+ mb_ddr_1d->mr2_a0 = (uint8_t)config->uim.mr2;
+ mb_ddr_1d->mr3_a0 = (uint8_t)config->uim.mr3;
+ mb_ddr_1d->mr4_a0 = (uint8_t)config->uim.mr4;
+ mb_ddr_1d->mr11_a0 = (uint8_t)config->uim.mr11;
+ mb_ddr_1d->mr12_a0 = (uint8_t)config->uim.mr12;
+ mb_ddr_1d->mr13_a0 = (uint8_t)config->uim.mr13;
+ mb_ddr_1d->mr14_a0 = (uint8_t)config->uim.mr14;
+ mb_ddr_1d->mr16_a0 = 0x00U;
+ mb_ddr_1d->mr17_a0 = 0x00U;
+ mb_ddr_1d->mr22_a0 = (uint8_t)config->uim.mr22;
+ mb_ddr_1d->mr24_a0 = 0x00U;
+ mb_ddr_1d->mr1_a1 = (uint8_t)config->uim.mr1;
+ mb_ddr_1d->mr2_a1 = (uint8_t)config->uim.mr2;
+ mb_ddr_1d->mr3_a1 = (uint8_t)config->uim.mr3;
+ mb_ddr_1d->mr4_a1 = (uint8_t)config->uim.mr4;
+ mb_ddr_1d->mr11_a1 = (uint8_t)config->uim.mr11;
+ mb_ddr_1d->mr12_a1 = (uint8_t)config->uim.mr12;
+ mb_ddr_1d->mr13_a1 = (uint8_t)config->uim.mr13;
+ mb_ddr_1d->mr14_a1 = (uint8_t)config->uim.mr14;
+ mb_ddr_1d->mr16_a1 = 0x00U;
+ mb_ddr_1d->mr17_a1 = 0x00U;
+ mb_ddr_1d->mr22_a1 = (uint8_t)config->uim.mr22;
+ mb_ddr_1d->mr24_a1 = 0x00U;
+
+ mb_ddr_1d->mr1_b0 = (uint8_t)config->uim.mr1;
+ mb_ddr_1d->mr2_b0 = (uint8_t)config->uim.mr2;
+ mb_ddr_1d->mr3_b0 = (uint8_t)config->uim.mr3;
+ mb_ddr_1d->mr4_b0 = (uint8_t)config->uim.mr4;
+ mb_ddr_1d->mr11_b0 = (uint8_t)config->uim.mr11;
+ mb_ddr_1d->mr12_b0 = (uint8_t)config->uim.mr12;
+ mb_ddr_1d->mr13_b0 = (uint8_t)config->uim.mr13;
+ mb_ddr_1d->mr14_b0 = (uint8_t)config->uim.mr14;
+ mb_ddr_1d->mr16_b0 = 0x00U;
+ mb_ddr_1d->mr17_b0 = 0x00U;
+ mb_ddr_1d->mr22_b0 = (uint8_t)config->uim.mr22;
+ mb_ddr_1d->mr24_b0 = 0x00U;
+ mb_ddr_1d->mr1_b1 = (uint8_t)config->uim.mr1;
+ mb_ddr_1d->mr2_b1 = (uint8_t)config->uim.mr2;
+ mb_ddr_1d->mr3_b1 = (uint8_t)config->uim.mr3;
+ mb_ddr_1d->mr4_b1 = (uint8_t)config->uim.mr4;
+ mb_ddr_1d->mr11_b1 = (uint8_t)config->uim.mr11;
+ mb_ddr_1d->mr12_b1 = (uint8_t)config->uim.mr12;
+ mb_ddr_1d->mr13_b1 = (uint8_t)config->uim.mr13;
+ mb_ddr_1d->mr14_b1 = (uint8_t)config->uim.mr14;
+ mb_ddr_1d->mr16_b1 = 0x00U;
+ mb_ddr_1d->mr17_b1 = 0x00U;
+ mb_ddr_1d->mr22_b1 = (uint8_t)config->uim.mr22;
+ mb_ddr_1d->mr24_b1 = 0x00U;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ mb_ddr_1d->share2dvrefresult = share2dvrefresult;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c
new file mode 100644
index 0000000..4daf2bb
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+#include <ddrphy_wrapper.h>
+
+/*
+ * Helper function to determine if a given DByte is Disabled given PhyInit inputs.
+ * @return 1 if disabled, 0 if enabled.
+ */
+int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t dbytenumber)
+{
+ int disabledbyte;
+ uint32_t nad0 __maybe_unused;
+ uint32_t nad1 __maybe_unused;
+
+ disabledbyte = 0; /* Default assume Dbyte is Enabled */
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? 1 : 0;
+#else /* STM32MP_LPDDR4_TYPE */
+ nad0 = config->uib.numactivedbytedfi0;
+ nad1 = config->uib.numactivedbytedfi1;
+
+ if ((nad0 + nad1) > config->uib.numdbyte) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s invalid PHY configuration:\n", __func__);
+ VERBOSE("numactivedbytedfi0(%u)+numactivedbytedfi1(%u)>numdbytes(%u).\n",
+ nad0, nad1, config->uib.numdbyte);
+ }
+
+ if (config->uib.dfi1exists != 0U) {
+ if (config->uib.numactivedbytedfi1 == 0U) {
+ /* Only dfi0 (ChA) is enabled, dfi1 (ChB) disabled */
+ disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ?
+ 1 : 0;
+ } else {
+ /* DFI1 enabled */
+ disabledbyte = (((config->uib.numactivedbytedfi0 - 1U) < dbytenumber) &&
+ (dbytenumber < (config->uib.numdbyte / 2U))) ?
+ 1 : (dbytenumber >
+ ((config->uib.numdbyte / 2U) +
+ config->uib.numactivedbytedfi1 - 1U)) ? 1 : 0;
+ }
+ } else {
+ disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? 1 : 0;
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ /* Qualify results against MessageBlock */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if ((mb_ddr_1d->enableddqs < 1U) ||
+ (mb_ddr_1d->enableddqs > (uint8_t)(8U * config->uib.numactivedbytedfi0))) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s enableddqs(%u)\n", __func__, mb_ddr_1d->enableddqs);
+ VERBOSE("Value must be 0 < enableddqs < config->uib.numactivedbytedfi0 * 8.\n");
+ }
+
+ if (dbytenumber < 8) {
+ disabledbyte |= (int)mb_ddr_1d->disableddbyte & (0x1 << dbytenumber);
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ if ((mb_ddr_1d->enableddqscha < 1U) ||
+ (mb_ddr_1d->enableddqscha > (uint8_t)(8U * config->uib.numactivedbytedfi0))) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s enableddqscha(%u)\n", __func__, mb_ddr_1d->enableddqscha);
+ VERBOSE("Value must be 0 < enableddqscha < config->uib.numactivedbytedfi0*8\n");
+ }
+
+ if ((config->uib.dfi1exists != 0U) && (config->uib.numactivedbytedfi1 > 0U) &&
+ ((mb_ddr_1d->enableddqschb < 1U) ||
+ (mb_ddr_1d->enableddqschb > (uint8_t)(8U * config->uib.numactivedbytedfi1)))) {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s enableddqschb(%u)\n", __func__, mb_ddr_1d->enableddqschb);
+ VERBOSE("Value must be 0 < enableddqschb < config->uib.numactivedbytedfi1*8\n");
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+ return disabledbyte;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c
new file mode 100644
index 0000000..2843b10
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+#define PRODCODE_SIZE 177
+
+static const uint32_t prodcode_addr[PRODCODE_SIZE] = {
+ 0x90000U, 0x90001U, 0x90002U, 0x90003U, 0x90004U, 0x90005U, 0x90029U, 0x9002AU, 0x9002BU,
+ 0x9002CU, 0x9002DU, 0x9002EU, 0x9002FU, 0x90030U, 0x90031U, 0x90032U, 0x90033U, 0x90034U,
+ 0x90035U, 0x90036U, 0x90037U, 0x90038U, 0x90039U, 0x9003AU, 0x9003BU, 0x9003CU, 0x9003DU,
+ 0x9003EU, 0x9003FU, 0x90040U, 0x90041U, 0x90042U, 0x90043U, 0x90044U, 0x90045U, 0x90046U,
+ 0x90047U, 0x90048U, 0x90049U, 0x9004AU, 0x9004BU, 0x9004CU, 0x9004DU, 0x9004EU, 0x9004FU,
+ 0x90050U, 0x90051U, 0x90052U, 0x90053U, 0x90054U, 0x90055U, 0x90056U, 0x90057U, 0x90058U,
+ 0x90059U, 0x9005AU, 0x9005BU, 0x9005CU, 0x9005DU, 0x9005EU, 0x9005FU, 0x90060U, 0x90061U,
+ 0x90062U, 0x90063U, 0x90064U, 0x90065U, 0x90066U, 0x90067U, 0x90068U, 0x90069U, 0x9006AU,
+ 0x9006BU, 0x9006CU, 0x9006DU, 0x9006EU, 0x9006FU, 0x90070U, 0x90071U, 0x90072U, 0x90073U,
+ 0x90074U, 0x90075U, 0x90076U, 0x90077U, 0x90078U, 0x90079U, 0x9007AU, 0x9007BU, 0x9007CU,
+ 0x9007DU, 0x9007EU, 0x9007FU, 0x90080U, 0x90081U, 0x90082U, 0x90083U, 0x90084U, 0x90085U,
+ 0x90086U, 0x90087U, 0x90088U, 0x90089U, 0x9008AU, 0x9008BU, 0x9008CU, 0x9008DU, 0x9008EU,
+ 0x9008FU, 0x90090U, 0x90091U, 0x90092U, 0x90093U, 0x90094U, 0x90095U, 0x90096U, 0x90097U,
+ 0x90098U, 0x90099U, 0x9009AU, 0x9009BU, 0x9009CU, 0x9009DU, 0x9009EU, 0x9009FU, 0x900A0U,
+ 0x900A1U, 0x900A2U, 0x900A3U, 0x900A4U, 0x900A5U, 0x900A6U, 0x900A7U, 0x900A8U, 0x900A9U,
+ 0x900AAU, 0x900ABU, 0x900ACU, 0x900ADU, 0x900AEU, 0x900AFU, 0x900B0U, 0x900B1U, 0x900B2U,
+ 0x900B3U, 0x900B4U, 0x900B5U, 0x900B6U, 0x900B7U, 0x900B8U, 0x900B9U, 0x900BAU, 0x900BBU,
+ 0x900BCU, 0x900BDU, 0x900BEU, 0x900BFU, 0x900C0U, 0x900C1U, 0x900C2U, 0x900C3U, 0x900C4U,
+ 0x900C5U, 0x900C6U, 0x900C7U, 0x900C8U, 0x900C9U, 0x900CAU, 0x90006U, 0x90007U, 0x90008U,
+ 0x90009U, 0x9000AU, 0x9000BU, 0xD00E7U, 0x90017U, 0x90026U,
+};
+
+static const uint16_t prodcode_data[PRODCODE_SIZE] = {
+ 0x0010U, 0x0400U, 0x010EU, 0x0000U, 0x0000U, 0x0008U, 0x000BU, 0x0480U, 0x0109U, 0x0008U,
+ 0x0448U, 0x0139U, 0x0008U, 0x0478U, 0x0109U, 0x0002U, 0x0010U, 0x0139U, 0x000BU, 0x07C0U,
+ 0x0139U, 0x0044U, 0x0633U, 0x0159U, 0x014FU, 0x0630U, 0x0159U, 0x0047U, 0x0633U, 0x0149U,
+ 0x004FU, 0x0633U, 0x0179U, 0x0008U, 0x00E0U, 0x0109U, 0x0000U, 0x07C8U, 0x0109U, 0x0000U,
+ 0x0001U, 0x0008U, 0x0030U, 0x065AU, 0x0009U, 0x0000U, 0x045AU, 0x0009U, 0x0000U, 0x0448U,
+ 0x0109U, 0x0040U, 0x0633U, 0x0179U, 0x0001U, 0x0618U, 0x0109U, 0x40C0U, 0x0633U, 0x0149U,
+ 0x0008U, 0x0004U, 0x0048U, 0x4040U, 0x0633U, 0x0149U, 0x0000U, 0x0004U, 0x0048U, 0x0040U,
+ 0x0633U, 0x0149U, 0x0000U, 0x0658U, 0x0109U, 0x0010U, 0x0004U, 0x0018U, 0x0000U, 0x0004U,
+ 0x0078U, 0x0549U, 0x0633U, 0x0159U, 0x0D49U, 0x0633U, 0x0159U, 0x094AU, 0x0633U, 0x0159U,
+ 0x0441U, 0x0633U, 0x0149U, 0x0042U, 0x0633U, 0x0149U, 0x0001U, 0x0633U, 0x0149U, 0x0000U,
+ 0x00E0U, 0x0109U, 0x000AU, 0x0010U, 0x0109U, 0x0009U, 0x03C0U, 0x0149U, 0x0009U, 0x03C0U,
+ 0x0159U, 0x0018U, 0x0010U, 0x0109U, 0x0000U, 0x03C0U, 0x0109U, 0x0018U, 0x0004U, 0x0048U,
+ 0x0018U, 0x0004U, 0x0058U, 0x000BU, 0x0010U, 0x0109U, 0x0001U, 0x0010U, 0x0109U, 0x0005U,
+ 0x07C0U, 0x0109U, 0x0000U, 0x8140U, 0x010CU, 0x0010U, 0x8138U, 0x0104U, 0x0008U, 0x0448U,
+ 0x0109U, 0x000FU, 0x07C0U, 0x0109U, 0x0047U, 0x0630U, 0x0109U, 0x0008U, 0x0618U, 0x0109U,
+ 0x0008U, 0x00E0U, 0x0109U, 0x0000U, 0x07C8U, 0x0109U, 0x0008U, 0x8140U, 0x010CU, 0x0000U,
+ 0x0478U, 0x0109U, 0x0000U, 0x0001U, 0x0008U, 0x0008U, 0x0004U, 0x0000U, 0x0008U, 0x07C8U,
+ 0x0109U, 0x0000U, 0x0400U, 0x0106U, 0x0400U, 0x0000U, 0x002CU,
+ };
+
+#else /* STM32MP_LPDDR4_TYPE */
+#define PRODCODE_SIZE 481
+
+static const uint32_t prodcode_addr[PRODCODE_SIZE] = {
+ 0x90000U, 0x90001U, 0x90002U, 0x90003U, 0x90004U, 0x90005U, 0x90029U, 0x9002AU, 0x9002BU,
+ 0x9002CU, 0x9002DU, 0x9002EU, 0x9002FU, 0x90030U, 0x90031U, 0x90032U, 0x90033U, 0x90034U,
+ 0x90035U, 0x90036U, 0x90037U, 0x90038U, 0x90039U, 0x9003AU, 0x9003BU, 0x9003CU, 0x9003DU,
+ 0x9003EU, 0x9003FU, 0x90040U, 0x90041U, 0x90042U, 0x90043U, 0x90044U, 0x90045U, 0x90046U,
+ 0x90047U, 0x90048U, 0x90049U, 0x9004AU, 0x9004BU, 0x9004CU, 0x9004DU, 0x9004EU, 0x9004FU,
+ 0x90050U, 0x90051U, 0x90052U, 0x90053U, 0x90054U, 0x90055U, 0x90056U, 0x90057U, 0x90058U,
+ 0x90059U, 0x9005AU, 0x9005BU, 0x9005CU, 0x9005DU, 0x9005EU, 0x9005FU, 0x90060U, 0x90061U,
+ 0x90062U, 0x90063U, 0x90064U, 0x90065U, 0x90066U, 0x90067U, 0x90068U, 0x90069U, 0x9006AU,
+ 0x9006BU, 0x9006CU, 0x9006DU, 0x9006EU, 0x9006FU, 0x90070U, 0x90071U, 0x90072U, 0x90073U,
+ 0x90074U, 0x90075U, 0x90076U, 0x90077U, 0x90078U, 0x90079U, 0x9007AU, 0x9007BU, 0x9007CU,
+ 0x9007DU, 0x9007EU, 0x9007FU, 0x90080U, 0x90081U, 0x90082U, 0x90083U, 0x90084U, 0x90085U,
+ 0x90086U, 0x90087U, 0x90088U, 0x90089U, 0x9008AU, 0x9008BU, 0x9008CU, 0x9008DU, 0x9008EU,
+ 0x9008FU, 0x90090U, 0x90091U, 0x90092U, 0x90093U, 0x90094U, 0x90095U, 0x90096U, 0x90097U,
+ 0x90098U, 0x90099U, 0x9009AU, 0x9009BU, 0x9009CU, 0x9009DU, 0x9009EU, 0x9009FU, 0x900A0U,
+ 0x900A1U, 0x900A2U, 0x900A3U, 0x900A4U, 0x900A5U, 0x900A6U, 0x900A7U, 0x900A8U, 0x900A9U,
+ 0x40000U, 0x40020U, 0x40040U, 0x40060U, 0x40001U, 0x40021U, 0x40041U, 0x40061U, 0x40002U,
+ 0x40022U, 0x40042U, 0x40062U, 0x40003U, 0x40023U, 0x40043U, 0x40063U, 0x40004U, 0x40024U,
+ 0x40044U, 0x40064U, 0x40005U, 0x40025U, 0x40045U, 0x40065U, 0x40006U, 0x40026U, 0x40046U,
+ 0x40066U, 0x40007U, 0x40027U, 0x40047U, 0x40067U, 0x40008U, 0x40028U, 0x40048U, 0x40068U,
+ 0x40009U, 0x40029U, 0x40049U, 0x40069U, 0x4000AU, 0x4002AU, 0x4004AU, 0x4006AU, 0x4000BU,
+ 0x4002BU, 0x4004BU, 0x4006BU, 0x4000CU, 0x4002CU, 0x4004CU, 0x4006CU, 0x4000DU, 0x4002DU,
+ 0x4004DU, 0x4006DU, 0x4000EU, 0x4002EU, 0x4004EU, 0x4006EU, 0x4000FU, 0x4002FU, 0x4004FU,
+ 0x4006FU, 0x40010U, 0x40030U, 0x40050U, 0x40070U, 0x40011U, 0x40031U, 0x40051U, 0x40071U,
+ 0x40012U, 0x40032U, 0x40052U, 0x40072U, 0x40013U, 0x40033U, 0x40053U, 0x40073U, 0x40014U,
+ 0x40034U, 0x40054U, 0x40074U, 0x40015U, 0x40035U, 0x40055U, 0x40075U, 0x40016U, 0x40036U,
+ 0x40056U, 0x40076U, 0x40017U, 0x40037U, 0x40057U, 0x40077U, 0x40018U, 0x40038U, 0x40058U,
+ 0x40078U, 0x40019U, 0x40039U, 0x40059U, 0x40079U, 0x4001AU, 0x4003AU, 0x4005AU, 0x4007AU,
+ 0x900AAU, 0x900ABU, 0x900ACU, 0x900ADU, 0x900AEU, 0x900AFU, 0x900B0U, 0x900B1U, 0x900B2U,
+ 0x900B3U, 0x900B4U, 0x900B5U, 0x900B6U, 0x900B7U, 0x900B8U, 0x900B9U, 0x900BAU, 0x900BBU,
+ 0x900BCU, 0x900BDU, 0x900BEU, 0x900BFU, 0x900C0U, 0x900C1U, 0x900C2U, 0x900C3U, 0x900C4U,
+ 0x900C5U, 0x900C6U, 0x900C7U, 0x900C8U, 0x900C9U, 0x900CAU, 0x900CBU, 0x900CCU, 0x900CDU,
+ 0x900CEU, 0x900CFU, 0x900D0U, 0x900D1U, 0x900D2U, 0x900D3U, 0x900D4U, 0x900D5U, 0x900D6U,
+ 0x900D7U, 0x900D8U, 0x900D9U, 0x900DAU, 0x900DBU, 0x900DCU, 0x900DDU, 0x900DEU, 0x900DFU,
+ 0x900E0U, 0x900E1U, 0x900E2U, 0x900E3U, 0x900E4U, 0x900E5U, 0x900E6U, 0x900E7U, 0x900E8U,
+ 0x900E9U, 0x900EAU, 0x900EBU, 0x900ECU, 0x900EDU, 0x900EEU, 0x900EFU, 0x900F0U, 0x900F1U,
+ 0x900F2U, 0x900F3U, 0x900F4U, 0x900F5U, 0x900F6U, 0x900F7U, 0x900F8U, 0x900F9U, 0x900FAU,
+ 0x900FBU, 0x900FCU, 0x900FDU, 0x900FEU, 0x900FFU, 0x90100U, 0x90101U, 0x90102U, 0x90103U,
+ 0x90104U, 0x90105U, 0x90106U, 0x90107U, 0x90108U, 0x90109U, 0x9010AU, 0x9010BU, 0x9010CU,
+ 0x9010DU, 0x9010EU, 0x9010FU, 0x90110U, 0x90111U, 0x90112U, 0x90113U, 0x90114U, 0x90115U,
+ 0x90116U, 0x90117U, 0x90118U, 0x90119U, 0x9011AU, 0x9011BU, 0x9011CU, 0x9011DU, 0x9011EU,
+ 0x9011FU, 0x90120U, 0x90121U, 0x90122U, 0x90123U, 0x90124U, 0x90125U, 0x90126U, 0x90127U,
+ 0x90128U, 0x90129U, 0x9012AU, 0x9012BU, 0x9012CU, 0x9012DU, 0x9012EU, 0x9012FU, 0x90130U,
+ 0x90131U, 0x90132U, 0x90133U, 0x90134U, 0x90135U, 0x90136U, 0x90137U, 0x90138U, 0x90139U,
+ 0x9013AU, 0x9013BU, 0x9013CU, 0x9013DU, 0x9013EU, 0x9013FU, 0x90140U, 0x90141U, 0x90142U,
+ 0x90143U, 0x90144U, 0x90145U, 0x90146U, 0x90147U, 0x90148U, 0x90149U, 0x9014AU, 0x9014BU,
+ 0x9014CU, 0x9014DU, 0x9014EU, 0x9014FU, 0x90150U, 0x90151U, 0x90152U, 0x90153U, 0x90154U,
+ 0x90155U, 0x90156U, 0x90157U, 0x90158U, 0x90159U, 0x9015AU, 0x9015BU, 0x9015CU, 0x9015DU,
+ 0x9015EU, 0x9015FU, 0x90160U, 0x90161U, 0x90162U, 0x90163U, 0x90164U, 0x90165U, 0x90166U,
+ 0x90167U, 0x90168U, 0x90169U, 0x9016AU, 0x9016BU, 0x9016CU, 0x9016DU, 0x9016EU, 0x9016FU,
+ 0x90170U, 0x90171U, 0x90172U, 0x90173U, 0x90174U, 0x90175U, 0x90176U, 0x90177U, 0x90178U,
+ 0x90179U, 0x9017AU, 0x9017BU, 0x9017CU, 0x9017DU, 0x9017EU, 0x9017FU, 0x90180U, 0x90181U,
+ 0x90182U, 0x90183U, 0x90184U, 0x90006U, 0x90007U, 0x90008U, 0x90009U, 0x9000AU, 0x9000BU,
+ 0xD00E7U, 0x90017U, 0x9001FU, 0x90026U, 0x400D0U, 0x400D1U, 0x400D2U, 0x400D3U, 0x400D4U,
+ 0x400D5U, 0x400D6U, 0x400D7U, 0x2003AU,
+ };
+
+static const uint16_t prodcode_data[PRODCODE_SIZE] = {
+ 0x0010U, 0x0400U, 0x010EU, 0x0000U, 0x0000U, 0x0008U, 0x000BU, 0x0480U, 0x0109U, 0x0008U,
+ 0x0448U, 0x0139U, 0x0008U, 0x0478U, 0x0109U, 0x0000U, 0x00E8U, 0x0109U, 0x0002U, 0x0010U,
+ 0x0139U, 0x000BU, 0x07C0U, 0x0139U, 0x0044U, 0x0633U, 0x0159U, 0x014FU, 0x0630U, 0x0159U,
+ 0x0047U, 0x0633U, 0x0149U, 0x004FU, 0x0633U, 0x0179U, 0x0008U, 0x00E0U, 0x0109U, 0x0000U,
+ 0x07C8U, 0x0109U, 0x0000U, 0x0001U, 0x0008U, 0x0030U, 0x065AU, 0x0009U, 0x0000U, 0x045AU,
+ 0x0009U, 0x0000U, 0x0448U, 0x0109U, 0x0040U, 0x0633U, 0x0179U, 0x0001U, 0x0618U, 0x0109U,
+ 0x40C0U, 0x0633U, 0x0149U, 0x0008U, 0x0004U, 0x0048U, 0x4040U, 0x0633U, 0x0149U, 0x0000U,
+ 0x0004U, 0x0048U, 0x0040U, 0x0633U, 0x0149U, 0x0000U, 0x0658U, 0x0109U, 0x0010U, 0x0004U,
+ 0x0018U, 0x0000U, 0x0004U, 0x0078U, 0x0549U, 0x0633U, 0x0159U, 0x0D49U, 0x0633U, 0x0159U,
+ 0x094AU, 0x0633U, 0x0159U, 0x0441U, 0x0633U, 0x0149U, 0x0042U, 0x0633U, 0x0149U, 0x0001U,
+ 0x0633U, 0x0149U, 0x0000U, 0x00E0U, 0x0109U, 0x000AU, 0x0010U, 0x0109U, 0x0009U, 0x03C0U,
+ 0x0149U, 0x0009U, 0x03C0U, 0x0159U, 0x0018U, 0x0010U, 0x0109U, 0x0000U, 0x03C0U, 0x0109U,
+ 0x0018U, 0x0004U, 0x0048U, 0x0018U, 0x0004U, 0x0058U, 0x000BU, 0x0010U, 0x0109U, 0x0001U,
+ 0x0010U, 0x0109U, 0x0005U, 0x07C0U, 0x0109U, 0x0811U, 0x0880U, 0x0000U, 0x0000U, 0x4008U,
+ 0x0083U, 0x004FU, 0x0000U, 0x4040U, 0x0083U, 0x0051U, 0x0000U, 0x0811U, 0x0880U, 0x0000U,
+ 0x0000U, 0x0720U, 0x000FU, 0x1740U, 0x0000U, 0x0016U, 0x0083U, 0x004BU, 0x0000U, 0x0716U,
+ 0x000FU, 0x2001U, 0x0000U, 0x0716U, 0x000FU, 0x2800U, 0x0000U, 0x0716U, 0x000FU, 0x0F00U,
+ 0x0000U, 0x0720U, 0x000FU, 0x1400U, 0x0000U, 0x0E08U, 0x0C15U, 0x0000U, 0x0000U, 0x0625U,
+ 0x0015U, 0x0000U, 0x0000U, 0x4028U, 0x0080U, 0x0000U, 0x0000U, 0x0E08U, 0x0C1AU, 0x0000U,
+ 0x0000U, 0x0625U, 0x001AU, 0x0000U, 0x0000U, 0x4040U, 0x0080U, 0x0000U, 0x0000U, 0x2604U,
+ 0x0015U, 0x0000U, 0x0000U, 0x0708U, 0x0005U, 0x0000U, 0x2002U, 0x0008U, 0x0080U, 0x0000U,
+ 0x0000U, 0x2604U, 0x001AU, 0x0000U, 0x0000U, 0x0708U, 0x000AU, 0x0000U, 0x2002U, 0x4040U,
+ 0x0080U, 0x0000U, 0x0000U, 0x060AU, 0x0015U, 0x1200U, 0x0000U, 0x061AU, 0x0015U, 0x1300U,
+ 0x0000U, 0x060AU, 0x001AU, 0x1200U, 0x0000U, 0x0642U, 0x001AU, 0x1300U, 0x0000U, 0x4808U,
+ 0x0880U, 0x0000U, 0x0000U, 0x0000U, 0x0790U, 0x011AU, 0x0008U, 0x07AAU, 0x002AU, 0x0010U,
+ 0x07B2U, 0x002AU, 0x0000U, 0x07C8U, 0x0109U, 0x0010U, 0x0010U, 0x0109U, 0x0010U, 0x02A8U,
+ 0x0129U, 0x0008U, 0x0370U, 0x0129U, 0x000AU, 0x03C8U, 0x01A9U, 0x000CU, 0x0408U, 0x0199U,
+ 0x0014U, 0x0790U, 0x011AU, 0x0008U, 0x0004U, 0x0018U, 0x000EU, 0x0408U, 0x0199U, 0x0008U,
+ 0x8568U, 0x0108U, 0x0018U, 0x0790U, 0x016AU, 0x0008U, 0x01D8U, 0x0169U, 0x0010U, 0x8558U,
+ 0x0168U, 0x1FF8U, 0x85A8U, 0x01E8U, 0x0050U, 0x0798U, 0x016AU, 0x0060U, 0x07A0U, 0x016AU,
+ 0x0008U, 0x8310U, 0x0168U, 0x0008U, 0xA310U, 0x0168U, 0x000AU, 0x0408U, 0x0169U, 0x006EU,
+ 0x0000U, 0x0068U, 0x0000U, 0x0408U, 0x0169U, 0x0000U, 0x8310U, 0x0168U, 0x0000U, 0xA310U,
+ 0x0168U, 0x1FF8U, 0x85A8U, 0x01E8U, 0x0068U, 0x0798U, 0x016AU, 0x0078U, 0x07A0U, 0x016AU,
+ 0x0068U, 0x0790U, 0x016AU, 0x0008U, 0x8B10U, 0x0168U, 0x0008U, 0xAB10U, 0x0168U, 0x000AU,
+ 0x0408U, 0x0169U, 0x0058U, 0x0000U, 0x0068U, 0x0000U, 0x0408U, 0x0169U, 0x0000U, 0x8B10U,
+ 0x0168U, 0x0001U, 0xAB10U, 0x0168U, 0x0000U, 0x01D8U, 0x0169U, 0x0080U, 0x0790U, 0x016AU,
+ 0x0018U, 0x07AAU, 0x006AU, 0x000AU, 0x0000U, 0x01E9U, 0x0008U, 0x8080U, 0x0108U, 0x000FU,
+ 0x0408U, 0x0169U, 0x000CU, 0x0000U, 0x0068U, 0x0009U, 0x0000U, 0x01A9U, 0x0000U, 0x0408U,
+ 0x0169U, 0x0000U, 0x8080U, 0x0108U, 0x0008U, 0x07AAU, 0x006AU, 0x0000U, 0x8568U, 0x0108U,
+ 0x00B7U, 0x0790U, 0x016AU, 0x001FU, 0x0000U, 0x0068U, 0x0008U, 0x8558U, 0x0168U, 0x000FU,
+ 0x0408U, 0x0169U, 0x000DU, 0x0000U, 0x0068U, 0x0000U, 0x0408U, 0x0169U, 0x0000U, 0x8558U,
+ 0x0168U, 0x0008U, 0x03C8U, 0x01A9U, 0x0003U, 0x0370U, 0x0129U, 0x0020U, 0x02AAU, 0x0009U,
+ 0x0008U, 0x00E8U, 0x0109U, 0x0000U, 0x8140U, 0x010CU, 0x0010U, 0x8138U, 0x0104U, 0x0008U,
+ 0x0448U, 0x0109U, 0x000FU, 0x07C0U, 0x0109U, 0x0000U, 0x00E8U, 0x0109U, 0x0047U, 0x0630U,
+ 0x0109U, 0x0008U, 0x0618U, 0x0109U, 0x0008U, 0x00E0U, 0x0109U, 0x0000U, 0x07C8U, 0x0109U,
+ 0x0008U, 0x8140U, 0x010CU, 0x0000U, 0x0478U, 0x0109U, 0x0000U, 0x0001U, 0x0008U, 0x0008U,
+ 0x0004U, 0x0000U, 0x0008U, 0x07C8U, 0x0109U, 0x0000U, 0x0400U, 0x0106U, 0x0400U, 0x0000U,
+ 0x002BU, 0x0069U, 0x0000U, 0x0101U, 0x0105U, 0x0107U, 0x010FU, 0x0202U, 0x020AU, 0x020BU,
+ 0x0002U,
+ };
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+/*
+ * Loads PIE instruction sequence PHY registers
+ * @returns void
+ */
+void ddrphy_phyinit_loadpieprodcode(void)
+{
+ int i;
+
+ for (i = 0; i < PRODCODE_SIZE; i++) {
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * prodcode_addr[i])),
+ prodcode_data[i]);
+ }
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c
new file mode 100644
index 0000000..f1eeb82
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+/*
+ * Maps impedance values to register settings
+ *
+ * Reads the pull-up/pull-down driver impedance from drvstren_ohm input
+ * and encodes that value for the CSR field specified in targetcsr input,
+ * based on DDR protocol.
+ *
+ * @param[in] drvstren_ohm drive strenght / ODT impedance in Ohms
+ *
+ * @param[in] targetcsr Target CSR for the impedance value. on of following
+ * enum drvtype:
+ * - DRVSTRENFSDQP
+ * - DRVSTRENFSDQN
+ * - ODTSTRENP
+ * - ODTSTRENN
+ * - ADRVSTRENP
+ * - ADRVSTRENN
+ *
+ * \return >=0 value on success, else negative.
+ */
+int ddrphy_phyinit_mapdrvstren(uint32_t drvstren_ohm, enum drvtype targetcsr)
+{
+ int stren_setting = -1;
+
+ if ((targetcsr == DRVSTRENFSDQP) || (targetcsr == DRVSTRENFSDQN)) {
+ if (drvstren_ohm == 0U) {
+ stren_setting = 0x00; /* High-impedance */
+ } else if (drvstren_ohm < 29U) {
+ stren_setting = 0x3f;
+ } else if (drvstren_ohm < 31U) {
+ stren_setting = 0x3e;
+ } else if (drvstren_ohm < 33U) {
+ stren_setting = 0x3b;
+ } else if (drvstren_ohm < 35U) {
+ stren_setting = 0x3a;
+ } else if (drvstren_ohm < 38U) {
+ stren_setting = 0x39;
+ } else if (drvstren_ohm < 41U) {
+ stren_setting = 0x38;
+ } else if (drvstren_ohm < 45U) {
+ stren_setting = 0x1b;
+ } else if (drvstren_ohm < 50U) {
+ stren_setting = 0x1a;
+ } else if (drvstren_ohm < 56U) {
+ stren_setting = 0x19;
+ } else if (drvstren_ohm < 64U) {
+ stren_setting = 0x18;
+ } else if (drvstren_ohm < 74U) {
+ stren_setting = 0x0b;
+ } else if (drvstren_ohm < 88U) {
+ stren_setting = 0x0a;
+ } else if (drvstren_ohm < 108U) {
+ stren_setting = 0x09;
+ } else if (drvstren_ohm < 140U) {
+ stren_setting = 0x08;
+ } else if (drvstren_ohm < 200U) {
+ stren_setting = 0x03;
+ } else if (drvstren_ohm < 360U) {
+ stren_setting = 0x02;
+ } else if (drvstren_ohm < 481U) {
+ stren_setting = 0x01;
+ } else {
+ stren_setting = 0x00; /* High-impedance */
+ }
+ } else if (targetcsr == ODTSTRENP) {
+#if STM32MP_DDR3_TYPE
+ /*
+ * DDR3 - P and N has the same impedance and non-zero.
+ * user input is half the individual pull-up and pull-down impedances values
+ * because of parallel between them.
+ */
+ if (drvstren_ohm == 0U) {
+ stren_setting = 0x00; /* High-impedance */
+ } else if (drvstren_ohm < 15U) {
+ stren_setting = 0x3f;
+ } else if (drvstren_ohm < 16U) {
+ stren_setting = 0x3e;
+ } else if (drvstren_ohm < 17U) {
+ stren_setting = 0x3b;
+ } else if (drvstren_ohm < 18U) {
+ stren_setting = 0x3a;
+ } else if (drvstren_ohm < 20U) {
+ stren_setting = 0x39;
+ } else if (drvstren_ohm < 21U) {
+ stren_setting = 0x38;
+ } else if (drvstren_ohm < 23U) {
+ stren_setting = 0x1b;
+ } else if (drvstren_ohm < 26U) {
+ stren_setting = 0x1a;
+ } else if (drvstren_ohm < 29U) {
+ stren_setting = 0x19;
+ } else if (drvstren_ohm < 33U) {
+ stren_setting = 0x18;
+ } else if (drvstren_ohm < 38U) {
+ stren_setting = 0x0b;
+ } else if (drvstren_ohm < 45U) {
+ stren_setting = 0x0a;
+ } else if (drvstren_ohm < 55U) {
+ stren_setting = 0x09;
+ } else if (drvstren_ohm < 71U) {
+ stren_setting = 0x08;
+ } else if (drvstren_ohm < 101U) {
+ stren_setting = 0x03;
+ } else if (drvstren_ohm < 181U) {
+ stren_setting = 0x02;
+ } else if (drvstren_ohm < 241U) {
+ stren_setting = 0x01;
+ } else {
+ stren_setting = 0x00; /* High-impedance */
+ }
+#elif STM32MP_DDR4_TYPE
+ /* DDR4 - P is non-zero */
+ if (drvstren_ohm == 0U) {
+ stren_setting = 0x00; /* High-impedance */
+ } else if (drvstren_ohm < 29U) {
+ stren_setting = 0x3f;
+ } else if (drvstren_ohm < 31U) {
+ stren_setting = 0x3e;
+ } else if (drvstren_ohm < 33U) {
+ stren_setting = 0x3b;
+ } else if (drvstren_ohm < 35U) {
+ stren_setting = 0x3a;
+ } else if (drvstren_ohm < 38U) {
+ stren_setting = 0x39;
+ } else if (drvstren_ohm < 41U) {
+ stren_setting = 0x38;
+ } else if (drvstren_ohm < 45U) {
+ stren_setting = 0x1b;
+ } else if (drvstren_ohm < 50U) {
+ stren_setting = 0x1a;
+ } else if (drvstren_ohm < 56U) {
+ stren_setting = 0x19;
+ } else if (drvstren_ohm < 64U) {
+ stren_setting = 0x18;
+ } else if (drvstren_ohm < 74U) {
+ stren_setting = 0x0b;
+ } else if (drvstren_ohm < 88U) {
+ stren_setting = 0x0a;
+ } else if (drvstren_ohm < 108U) {
+ stren_setting = 0x09;
+ } else if (drvstren_ohm < 140U) {
+ stren_setting = 0x08;
+ } else if (drvstren_ohm < 200U) {
+ stren_setting = 0x03;
+ } else if (drvstren_ohm < 360U) {
+ stren_setting = 0x02;
+ } else if (drvstren_ohm < 481U) {
+ stren_setting = 0x01;
+ } else {
+ stren_setting = 0x00; /* High-impedance */
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ /* LPDDR4 - P is high-Z */
+ stren_setting = 0x00; /* High-impedance */
+#endif /* STM32MP_DDR3_TYPE */
+ } else if (targetcsr == ODTSTRENN) {
+#if STM32MP_DDR3_TYPE
+ /*
+ * DDR3 - P and N has the same impedance and non-zero.
+ * Times 2 of user input because of parallel pull-up and pull-down termination.
+ */
+ if (drvstren_ohm == 0U) {
+ stren_setting = 0x00; /* High-impedance */
+ } else if (drvstren_ohm < 15U) {
+ stren_setting = 0x3f;
+ } else if (drvstren_ohm < 16U) {
+ stren_setting = 0x3e;
+ } else if (drvstren_ohm < 17U) {
+ stren_setting = 0x3b;
+ } else if (drvstren_ohm < 18U) {
+ stren_setting = 0x3a;
+ } else if (drvstren_ohm < 20U) {
+ stren_setting = 0x39;
+ } else if (drvstren_ohm < 21U) {
+ stren_setting = 0x38;
+ } else if (drvstren_ohm < 23U) {
+ stren_setting = 0x1b;
+ } else if (drvstren_ohm < 26U) {
+ stren_setting = 0x1a;
+ } else if (drvstren_ohm < 29U) {
+ stren_setting = 0x19;
+ } else if (drvstren_ohm < 33U) {
+ stren_setting = 0x18;
+ } else if (drvstren_ohm < 38U) {
+ stren_setting = 0x0b;
+ } else if (drvstren_ohm < 45U) {
+ stren_setting = 0x0a;
+ } else if (drvstren_ohm < 55U) {
+ stren_setting = 0x09;
+ } else if (drvstren_ohm < 71U) {
+ stren_setting = 0x08;
+ } else if (drvstren_ohm < 101U) {
+ stren_setting = 0x03;
+ } else if (drvstren_ohm < 181U) {
+ stren_setting = 0x02;
+ } else if (drvstren_ohm < 241U) {
+ stren_setting = 0x01;
+ } else {
+ stren_setting = 0x00; /* High-impedance */
+ }
+#elif STM32MP_DDR4_TYPE
+ /* DDR4 - N is high-Z */
+ stren_setting = 0x00; /* High-impedance */
+#else /* STM32MP_LPDDR4_TYPE */
+ /* LPDDR4 - N is non-zero */
+ if (drvstren_ohm == 0U) {
+ stren_setting = 0x00; /* High-impedance */
+ } else if (drvstren_ohm < 29U) {
+ stren_setting = 0x3f;
+ } else if (drvstren_ohm < 31U) {
+ stren_setting = 0x3e;
+ } else if (drvstren_ohm < 33U) {
+ stren_setting = 0x3b;
+ } else if (drvstren_ohm < 35U) {
+ stren_setting = 0x3a;
+ } else if (drvstren_ohm < 38U) {
+ stren_setting = 0x39;
+ } else if (drvstren_ohm < 41U) {
+ stren_setting = 0x38;
+ } else if (drvstren_ohm < 45U) {
+ stren_setting = 0x1b;
+ } else if (drvstren_ohm < 50U) {
+ stren_setting = 0x1a;
+ } else if (drvstren_ohm < 56U) {
+ stren_setting = 0x19;
+ } else if (drvstren_ohm < 64U) {
+ stren_setting = 0x18;
+ } else if (drvstren_ohm < 74U) {
+ stren_setting = 0x0b;
+ } else if (drvstren_ohm < 88U) {
+ stren_setting = 0x0a;
+ } else if (drvstren_ohm < 108U) {
+ stren_setting = 0x09;
+ } else if (drvstren_ohm < 140U) {
+ stren_setting = 0x08;
+ } else if (drvstren_ohm < 200U) {
+ stren_setting = 0x03;
+ } else if (drvstren_ohm < 360U) {
+ stren_setting = 0x02;
+ } else if (drvstren_ohm < 481U) {
+ stren_setting = 0x01;
+ } else {
+ stren_setting = 0x00; /* High-impedance */
+ }
+#endif /* STM32MP_DDR3_TYPE */
+ } else {
+ /* if ((targetcsr == ADRVSTRENP) || (targetcsr == ADRVSTRENN)) */
+ if (drvstren_ohm == 120U) {
+ stren_setting = 0x00;
+ } else if (drvstren_ohm == 60U) {
+ stren_setting = 0x01;
+ } else if (drvstren_ohm == 40U) {
+ stren_setting = 0x03;
+ } else if (drvstren_ohm == 30U) {
+ stren_setting = 0x07;
+ } else if (drvstren_ohm == 24U) {
+ stren_setting = 0x0F;
+ } else if (drvstren_ohm == 20U) {
+ stren_setting = 0x1F;
+ } else {
+ ERROR("%s %d\n", __func__, __LINE__);
+ VERBOSE("%s userinputadvanced.atximpedance %u Ohms value is not valid.\n",
+ __func__, drvstren_ohm);
+ VERBOSE("Valid values are: 20, 24, 30, 40, 60 and 120 Ohms.\n");
+ }
+ }
+
+ return stren_setting;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c
new file mode 100644
index 0000000..c9a71f4
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c
@@ -0,0 +1,893 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+#include <ddrphy_wrapper.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+struct phyinit_timings {
+ int tstaoff;
+ int tpdm;
+ int tcasl_add;
+};
+
+static struct phyinit_timings timings;
+
+/*
+ * Program dfimrl according to this formula:
+ *
+ * dfimrl = ceiling( (ARdPtrinitval*UI + phy_tx_insertion_dly +
+ * phy_rx_insertion_dly + PHY_Rx_Fifo_dly + tDQSCK + tstaoff) /
+ * dficlk_period)
+ *
+ * All terms in above equation specified in ps
+ * tDQSCK - determine from memory model
+ * tstaoff - determine from memory model
+ * phy_tx_insertion_dly = 200ps
+ * phy_rx_insertion_dly = 200ps
+ * phy_rx_fifo_dly = 200ps + 4UI
+ */
+static void dfimrl_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d,
+ int ardptrinitval)
+{
+ uint32_t byte;
+ int dfimrl_in_dficlk;
+ int phy_rx_fifo_dly;
+ int phy_rx_insertion_dly = 200;
+ int phy_tx_insertion_dly = 200;
+ long long dficlk_period_x1000;
+ long long dfimrl_in_fs;
+ long long uifs;
+ uint16_t dfimrl;
+
+ uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
+ dficlk_period_x1000 = 4 * uifs;
+
+ phy_rx_fifo_dly = (int)(((200 * 1000) + (4 * uifs)) / 1000);
+
+ dfimrl_in_fs = (ardptrinitval * uifs) +
+ ((phy_tx_insertion_dly + phy_rx_insertion_dly + phy_rx_fifo_dly +
+ timings.tstaoff + timings.tcasl_add + timings.tpdm) * 1000);
+
+ dfimrl_in_dficlk = (int)(dfimrl_in_fs / dficlk_period_x1000);
+ if ((dfimrl_in_fs % dficlk_period_x1000) != 0) {
+ dfimrl_in_dficlk++;
+ }
+ dfimrl = (uint16_t)(dfimrl_in_dficlk + mb_ddr_1d->dfimrlmargin);
+
+ /*
+ * mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | CBRD | CSR_DFIMRL_ADDR))),
+ * dfimrl);
+ */
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+
+ c_addr = byte << 12;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr |
+ CSR_DFIMRL_ADDR))),
+ dfimrl);
+ }
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTMRL_ADDR))), dfimrl);
+}
+
+/*
+ * Program txdqsdlytg0/1[9:0]:
+ *
+ * txdqsdlytg*[9:6] = floor( (4*UI + tstaoff) / UI)
+ * txdqsdlytg*[5:0] = ceiling( (tstaoff%UI / UI) * 32)
+ *
+ * tstaoff and UI expressed in ps
+ *
+ * For HMD and LPDDR4X and MEMCLK <= 533 mhz:
+ * txdqsdlytg*[9:6] = 0x5
+ *
+ * For other dimm types, leave TDqsDlyTg*[9:0] at default 0x100
+ *
+ * ppp_0001_cccc_uuuu_1101_0000
+ *
+ * if DDR3 or DDR4
+ * num_timingroup = numrank_dfi0;
+ * else
+ * num_timingroup = numrank_dfi0 + numrank_dfi1 * dfi1exists;
+ */
+static void txdqsdlytg_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d,
+ uint16_t *txdqsdly)
+{
+ uint32_t byte;
+ int txdqsdlytg_5to0; /* Fine delay - 1/32UI per increment */
+ int txdqsdlytg_9to6; /* Coarse delay - 1UI per increment */
+ int txdqsdlytg_fine_default = 0;
+ int txdqsdlytg_coarse_default = 4;
+ long long tmp_value;
+ long long uifs;
+
+ uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
+
+ txdqsdlytg_9to6 = (int)(((int)((txdqsdlytg_coarse_default * uifs) / 1000) +
+ timings.tstaoff + timings.tcasl_add
+ - timings.tpdm) / (int)(uifs / 1000));
+
+ tmp_value = fmodll(((txdqsdlytg_fine_default * uifs / 32) +
+ ((timings.tstaoff + timings.tcasl_add) * 1000) -
+ (timings.tpdm * 1000)),
+ uifs);
+ txdqsdlytg_5to0 = (int)(tmp_value / uifs * 32);
+ if ((tmp_value % uifs) != 0) {
+ txdqsdlytg_5to0++;
+ }
+
+ /* Bit-5 of LCDL is no longer used, so bumping bit-5 of fine_dly up to coarse_dly */
+ if (txdqsdlytg_5to0 >= 32) {
+ txdqsdlytg_9to6 = txdqsdlytg_9to6 + 1;
+ txdqsdlytg_5to0 = txdqsdlytg_5to0 - 32;
+ }
+
+ *txdqsdly = (uint16_t)((txdqsdlytg_9to6 << 6) | txdqsdlytg_5to0);
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t nibble;
+
+ c_addr = byte << 12;
+ for (nibble = 0U; nibble < 2U; nibble++) {
+ uint32_t u_addr;
+
+ if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) {
+ continue;
+ }
+
+ u_addr = nibble << 8;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if ((mb_ddr_1d->cspresent & 0x1U) != 0U) {
+#else /* STM32MP_LPDDR4_TYPE */
+ if (((mb_ddr_1d->cspresentcha & 0x1U) |
+ (mb_ddr_1d->cspresentchb & 0x1U)) != 0U) {
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr |
+ CSR_TXDQSDLYTG0_ADDR))),
+ *txdqsdly);
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ if ((((mb_ddr_1d->cspresentcha & 0x2U) >> 1) |
+ ((mb_ddr_1d->cspresentchb & 0x2U) >> 1)) != 0U) {
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr |
+ CSR_TXDQSDLYTG1_ADDR))),
+ *txdqsdly);
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+ }
+}
+
+/*
+ * ##############################################################
+ *
+ * Program txdqdlyTg0/1[8:0]:
+ *
+ * txdqdlyTg*[8:6] = floor( (txdqsdlytg*[5:0]*UI/32 + tDQS2DQ + 0.5UI) / UI)
+ * txdqdlyTg*[5:0] = ceil( ((txdqsdlytg*[5:0]*UI/32 + tDQS2DQ + 0.5UI)%UI / UI) * 32)
+ *
+ * ##############################################################
+ */
+static void txdqdlytg_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d,
+ uint16_t txdqsdly)
+{
+ uint32_t byte;
+ int txdqdly_5to0; /* Fine delay - 1/32UI per increment */
+ int txdqdly_8to6; /* Coarse delay - 1UI per increment */
+ int txdqsdlytg_5to0; /* Fine delay - 1/32UI per increment */
+ long long tmp_value;
+ long long uifs;
+ uint16_t txdqdly;
+
+ uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
+
+ txdqsdlytg_5to0 = (int)txdqsdly & 0x3F;
+
+ txdqdly_8to6 = (int)(((txdqsdlytg_5to0 * uifs / 32) + (uifs / 2)) / uifs);
+ tmp_value = fmodll(((txdqsdlytg_5to0 * uifs / 32) + (uifs / 2)), uifs);
+ txdqdly_5to0 = (int)(((tmp_value * 32) / uifs));
+ if ((tmp_value % uifs) != 0) {
+ txdqdly_5to0++;
+ }
+
+ /* Bit-5 of LCDL is no longer used, so bumping bit-5 of fine_dly up to coarse_dly */
+ if (txdqdly_5to0 >= 32) {
+ txdqdly_8to6 = txdqdly_8to6 + 1;
+ txdqdly_5to0 = txdqdly_5to0 - 32;
+ }
+
+ txdqdly = (uint16_t)((txdqdly_8to6 << 6) | txdqdly_5to0);
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t lane;
+
+ c_addr = byte << 12;
+ for (lane = 0U; lane < 9U; lane++) {
+ uint32_t r_addr;
+
+ if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) {
+ continue;
+ }
+
+ r_addr = lane << 8;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if ((mb_ddr_1d->cspresent & 0x1U) != 0U) {
+#else /* STM32MP_LPDDR4_TYPE */
+ if (((mb_ddr_1d->cspresentcha & 0x1U) |
+ (mb_ddr_1d->cspresentchb & 0x1U)) != 0U) {
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | r_addr |
+ CSR_TXDQDLYTG0_ADDR))),
+ txdqdly);
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ if ((((mb_ddr_1d->cspresentcha & 0x2U) >> 1) |
+ ((mb_ddr_1d->cspresentchb & 0x2U) >> 1)) != 0U) {
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | r_addr |
+ CSR_TXDQDLYTG1_ADDR))),
+ txdqdly);
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+ }
+}
+
+/*
+ * Program rxendly0/1[10:0]:
+ *
+ * rxendly[10:6] = floor( (4*UI + tDQSCK + tstaoff) / UI)
+ * rxendly[5:0] = ceil( ((tDQSCK + tstaoff) % UI) * 32)
+ *
+ * tDQSCK, tstaoff and UI expressed in ps
+ */
+static void rxendly_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d)
+{
+ int rxendly_coarse_default = 4;
+ int rxendly_fine_default = 0;
+
+ int backoff_x1000 __maybe_unused;
+ int zerobackoff_x1000 __maybe_unused;
+ uint32_t byte;
+ int rxendly_10to6; /* Coarse delay - 1UI per increment */
+ int rxendly_5to0; /* Fine delay - 1/32UI per increment */
+ int totfinestep;
+ long long finestepfs; /* Fine steps in fs */
+ long long rxendly_offset_x1000000 = 0; /* 0 Offset is 1UI before the first DQS. */
+ long long totfs;
+ long long uifs;
+ uint16_t rxendly;
+
+ uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
+
+#if STM32MP_LPDDR4_TYPE
+ /* Compensate for pptenrxenbackoff */
+ zerobackoff_x1000 = (1000 * 24) / 32;
+ if (config->uia.lp4rxpreamblemode == 1U) {
+ backoff_x1000 = 1000 - ((1000 * 2) / 32);
+ } else {
+ backoff_x1000 = (1000 * (int)config->uia.rxenbackoff) - ((1000 * 2) / 32);
+ }
+
+ if (config->uia.disableretraining == 0U) {
+ rxendly_offset_x1000000 = config->uib.frequency < 333U ?
+ backoff_x1000 * uifs : zerobackoff_x1000 * uifs;
+ } else {
+ rxendly_offset_x1000000 = zerobackoff_x1000 * uifs;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ finestepfs = uifs / 32;
+ totfs = ((32 * rxendly_coarse_default * finestepfs) +
+ (rxendly_fine_default * finestepfs) +
+ ((timings.tstaoff + timings.tcasl_add +
+ timings.tpdm) * 1000) + (rxendly_offset_x1000000 / 1000));
+ totfinestep = totfs / finestepfs;
+
+ rxendly_10to6 = totfinestep / 32;
+ rxendly_5to0 = fmodi(totfinestep, 32);
+
+ /* Bit-5 of LCDL is no longer used, so bumping bit-5 of fine_dly up to coarse_dly */
+ if (rxendly_5to0 >= 32) {
+ rxendly_10to6 = rxendly_10to6 + 1;
+ rxendly_5to0 = rxendly_5to0 - 32;
+ }
+
+ rxendly = (uint16_t)((rxendly_10to6 << 6) | rxendly_5to0);
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint32_t nibble;
+
+ c_addr = byte << 12;
+ for (nibble = 0U; nibble < 2U; nibble++) {
+ uint32_t u_addr;
+
+ if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) {
+ continue;
+ }
+
+ u_addr = nibble << 8;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ if ((mb_ddr_1d->cspresent & 0x1U) != 0) {
+#else /* STM32MP_LPDDR4_TYPE */
+ if (((mb_ddr_1d->cspresentcha & 0x1U) |
+ (mb_ddr_1d->cspresentchb & 0x1U)) != 0U) {
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr |
+ CSR_RXENDLYTG0_ADDR))),
+ rxendly);
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ if ((((mb_ddr_1d->cspresentcha & 0x2U) >> 1) |
+ ((mb_ddr_1d->cspresentchb & 0x2U) >> 1)) != 0U) {
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr |
+ CSR_RXENDLYTG1_ADDR))),
+ rxendly);
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+ }
+}
+
+#if STM32MP_LPDDR4_TYPE
+/*
+ * Programming Seq0BGPR1/2/3 for LPDDR4
+ */
+static void seq0bgpr_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t extradly = 3U;
+ uint32_t rl = 0U; /* Computed read latency */
+ uint32_t wl = 0U; /* Computed write latency */
+ uint16_t mr_dbi_rd; /* Extracted field from MR */
+ uint16_t mr_rl;
+ uint16_t mr_wl;
+ uint16_t mr_wls;
+ uint16_t regdata;
+
+ mr_rl = (uint16_t)config->uia.lp4rl; /* RL[2:0] */
+ mr_wl = (uint16_t)config->uia.lp4wl; /* WL[5:3] */
+ mr_wls = (uint16_t)config->uia.lp4wls; /* WLS */
+ mr_dbi_rd = (uint16_t)config->uia.lp4dbird; /* DBI-RD */
+
+ switch ((mr_dbi_rd << 3) | mr_rl) {
+ /* DBI-RD Disabled */
+ case 0U:
+ rl = 6U;
+ break;
+ case 1U:
+ rl = 10U;
+ break;
+ case 2U:
+ rl = 14U;
+ break;
+ case 3U:
+ rl = 20U;
+ break;
+ case 4U:
+ rl = 24U;
+ break;
+ case 5U:
+ rl = 28U;
+ break;
+ case 6U:
+ rl = 32U;
+ break;
+ case 7U:
+ rl = 36U;
+ break;
+ /* DBI-RD Enabled */
+ case 8U:
+ rl = 6U;
+ break;
+ case 9U:
+ rl = 12U;
+ break;
+ case 10U:
+ rl = 16U;
+ break;
+ case 11U:
+ rl = 22U;
+ break;
+ case 12U:
+ rl = 28U;
+ break;
+ case 13U:
+ rl = 32U;
+ break;
+ case 14U:
+ rl = 36U;
+ break;
+ case 15U:
+ rl = 40U;
+ break;
+ default:
+ rl = 6U;
+ break;
+ }
+
+ switch ((mr_wls << 3) | mr_wl) {
+ /* DBI-RD Disabled */
+ case 0U:
+ wl = 4U;
+ break;
+ case 1U:
+ wl = 6U;
+ break;
+ case 2U:
+ wl = 8U;
+ break;
+ case 3U:
+ wl = 10U;
+ break;
+ case 4U:
+ wl = 12U;
+ break;
+ case 5U:
+ wl = 14U;
+ break;
+ case 6U:
+ wl = 16U;
+ break;
+ case 7U:
+ wl = 18U;
+ break;
+ /* DBI-RD Enabled */
+ case 8U:
+ wl = 4U;
+ break;
+ case 9U:
+ wl = 8U;
+ break;
+ case 10U:
+ wl = 12U;
+ break;
+ case 11U:
+ wl = 18U;
+ break;
+ case 12U:
+ wl = 22U;
+ break;
+ case 13U:
+ wl = 26U;
+ break;
+ case 14U:
+ wl = 30U;
+ break;
+ case 15U:
+ wl = 34U;
+ break;
+ default:
+ wl = 4U;
+ break;
+ }
+
+ /* Program Seq0b_GPRx */
+ regdata = (uint16_t)((rl - 5U + extradly) << CSR_ACSMRCASLAT_LSB);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
+ CSR_SEQ0BGPR1_ADDR))),
+ regdata);
+
+ regdata = (uint16_t)((wl - 5U + extradly) << CSR_ACSMWCASLAT_LSB);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
+ CSR_SEQ0BGPR2_ADDR))),
+ regdata);
+
+ regdata = (uint16_t)((rl - 5U + extradly + 4U + 8U) << CSR_ACSMRCASLAT_LSB);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
+ CSR_SEQ0BGPR3_ADDR))),
+ regdata);
+}
+
+/*
+ * Program hwtlpcsena and hwtlpcsenb based on number of ranks per channel
+ * Applicable only for LPDDR4. These CSRs have no effect for DDR3/4.
+ *
+ * CSRs to program:
+ * hwtlpcsena
+ * hwtlpcsenb
+ *
+ * User input dependencies:
+ * config->uib.numrank_dfi0
+ * config->uib.numrank_dfi1
+ * config->uib.dfi1exists
+ * config->uib.numactivedbytedfi1
+ */
+static void hwtlpcsen_program(struct stm32mp_ddr_config *config)
+{
+ uint16_t hwtlpcsena;
+ uint16_t hwtlpcsenb;
+
+ /* Channel A - 1'b01 if signal-rank, 2'b11 if dual-rank */
+ hwtlpcsena = (uint16_t)config->uib.numrank_dfi0 | 0x1U;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENA_ADDR))),
+ hwtlpcsena);
+
+ /*
+ * Channel B - 1'b01 if signal-rank, 2'b11 if dual-rank
+ * If DFI1 exists but disabled, numrank_dfi0 is used to program CsEnB
+ */
+ if ((config->uib.dfi1exists != 0U) && (config->uib.numactivedbytedfi1 == 0U)) {
+ hwtlpcsenb = (uint16_t)config->uib.numrank_dfi0 | 0x1U;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENB_ADDR))),
+ hwtlpcsenb);
+ } else if ((config->uib.dfi1exists != 0U) && (config->uib.numactivedbytedfi1 > 0U)) {
+ hwtlpcsenb = (uint16_t)config->uib.numrank_dfi1 | 0x1U;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENB_ADDR))),
+ hwtlpcsenb);
+ } else {
+ /* Disable Channel B */
+ hwtlpcsenb = 0x0U;
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENB_ADDR))),
+ hwtlpcsenb);
+ }
+}
+
+/*
+ * Program pptdqscntinvtrntg0 and pptdqscntinvtrntg1
+ * Calculated based on tDQS2DQ and Frequencey
+ * Applicable to LPDDR4 only
+ *
+ * 65536*(tdqs2dq_value_rank<rank>_chan<chan>*2)/(2*2048*UI(ps)_int)
+ *
+ * CSRs to program:
+ * pptdqscntinvtrntg0
+ * pptdqscntinvtrntg1
+ *
+ * User input dependencies:
+ * config->uib.numrank_dfi0
+ * config->uib.numrank_dfi1
+ * config->uib.dfi1exists
+ * config->uib.numdbyte
+ */
+static void pptdqscntinvtrntg_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t numrank_total = config->uib.numrank_dfi0;
+ uint32_t rank;
+
+ /* Calculate total number of timing groups (ranks) */
+ if (config->uib.dfi1exists != 0U) {
+ numrank_total += config->uib.numrank_dfi1;
+ }
+
+ /* Set per timing group */
+ for (rank = 0U; rank < numrank_total; rank++) {
+ uint32_t byte;
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+
+ c_addr = byte << 12;
+ if (rank == 0U) {
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr |
+ CSR_PPTDQSCNTINVTRNTG0_ADDR))),
+ 0U);
+ } else if (rank == 1U) {
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * (TDBYTE | c_addr |
+ CSR_PPTDQSCNTINVTRNTG1_ADDR))),
+ 0U);
+ }
+ }
+ }
+}
+
+/*
+ * CSRs to program:
+ * PptCtlStatic:: DOCByteSelTg0/1
+ * :: pptenrxenbackoff
+ *
+ * User input dependencies::
+ * config->uib.numdbyte
+ * config->uib.numrank_dfi0
+ * config->uib.numrank_dfi1
+ * config->uia.lp4rxpreamblemode
+ * config->uia.rxenbackoff
+ * config->uia.drambyteswap
+ */
+static void pptctlstatic_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t byte;
+ uint32_t pptenrxenbackoff;
+
+ /*
+ * The customer will setup some fields in this csr so the fw needs to do a
+ * read-modify-write here.
+ */
+
+ if (config->uia.lp4rxpreamblemode == 1U) {
+ /* Rx-preamble mode for PS0 */
+ /* Programming PptCtlStatic detected toggling preamble */
+ pptenrxenbackoff = 0x1U; /* Toggling RD_PRE */
+ } else {
+ pptenrxenbackoff = config->uia.rxenbackoff; /* Static RD_PRE */
+ }
+
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ uint32_t c_addr;
+ uint16_t regdata;
+ uint8_t pptentg1;
+ uint32_t docbytetg0;
+ uint32_t docbytetg1;
+
+ /* Each Dbyte could have a different configuration */
+ c_addr = byte * C1;
+ if ((byte % 2) == 0) {
+ docbytetg0 = 0x1U & (config->uia.drambyteswap >> byte);
+ docbytetg1 = 0x1U & (config->uia.drambyteswap >> byte);
+ } else {
+ docbytetg0 = 0x1U & (~(config->uia.drambyteswap >> byte));
+ docbytetg1 = 0x1U & (~(config->uia.drambyteswap >> byte));
+ }
+
+ pptentg1 = ((config->uib.numrank_dfi0 == 2U) || (config->uib.numrank_dfi1 == 2U)) ?
+ 0x1U : 0x0U;
+ regdata = (uint16_t)((0x1U << CSR_PPTENDQS2DQTG0_LSB) |
+ (pptentg1 << CSR_PPTENDQS2DQTG1_LSB) |
+ (0x1U << CSR_PPTENRXENDLYTG0_LSB) |
+ (pptentg1 << CSR_PPTENRXENDLYTG1_LSB) |
+ (pptenrxenbackoff << CSR_PPTENRXENBACKOFF_LSB) |
+ (docbytetg0 << CSR_DOCBYTESELTG0_LSB) |
+ (docbytetg1 << CSR_DOCBYTESELTG1_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE |
+ CSR_PPTCTLSTATIC_ADDR))),
+ regdata);
+ }
+}
+#endif /* STM32MP_LPDDR4_TYPE */
+
+/*
+ * Program hwtcamode based on dram type
+ *
+ * CSRs to program:
+ * hwtcamode::hwtlp3camode
+ * ::hwtd4camode
+ * ::hwtlp4camode
+ * ::hwtd4altcamode
+ * ::hwtcsinvert
+ * ::hwtdbiinvert
+ */
+static void hwtcamode_program(void)
+{
+ uint32_t hwtlp3camode = 0U;
+ uint32_t hwtd4camode = 0U;
+ uint32_t hwtlp4camode = 0U;
+ uint32_t hwtd4altcamode = 0U;
+ uint32_t hwtcsinvert = 0U;
+ uint32_t hwtdbiinvert = 0U;
+ uint16_t hwtcamode;
+
+#if STM32MP_DDR4_TYPE
+ hwtd4camode = 1U;
+#elif STM32MP_LPDDR4_TYPE
+ hwtlp4camode = 1U;
+ hwtcsinvert = 1U;
+ hwtdbiinvert = 1U;
+#else /* STM32MP_DDR3_TYPE */
+ /* Nothing to declare */
+#endif /* STM32MP_DDR4_TYPE */
+
+ hwtcamode = (uint16_t)((hwtdbiinvert << CSR_HWTDBIINVERT_LSB) |
+ (hwtcsinvert << CSR_HWTCSINVERT_LSB) |
+ (hwtd4altcamode << CSR_HWTD4ALTCAMODE_LSB) |
+ (hwtlp4camode << CSR_HWTLP4CAMODE_LSB) |
+ (hwtd4camode << CSR_HWTD4CAMODE_LSB) |
+ (hwtlp3camode << CSR_HWTLP3CAMODE_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTCAMODE_ADDR))), hwtcamode);
+}
+
+/*
+ * Program DllGainCtl and DllLockParam based on frequency
+ */
+static void dllgainctl_dlllockparam_program(struct stm32mp_ddr_config *config)
+{
+ uint32_t dllgainiv;
+ uint32_t dllgaintv;
+ uint32_t lcdlseed;
+ uint32_t memck_freq;
+ uint32_t stepsize_x10 = 47U; /*
+ * Nominal stepsize, in units of tenths of a ps,
+ * if nominal=4.7ps use 47
+ */
+ uint16_t wddllgainctl;
+ uint16_t wddlllockparam;
+
+ memck_freq = config->uib.frequency;
+
+ /*
+ * lcdlseed = ((1000000/memck_freq)/2)/lcdl_stepsize ...
+ * where default lcdl_stepsize=4.7 in simulation.
+ */
+ if (memck_freq >= 1200U) {
+ dllgainiv = 0x04U;
+ dllgaintv = 0x05U;
+ } else if (memck_freq >= 800U) {
+ dllgainiv = 0x03U;
+ dllgaintv = 0x05U;
+ } else if (memck_freq >= 532U) {
+ dllgainiv = 0x02U;
+ dllgaintv = 0x04U;
+ } else if (memck_freq >= 332U) {
+ dllgainiv = 0x01U;
+ dllgaintv = 0x03U;
+ } else {
+ dllgainiv = 0x00U;
+ dllgaintv = 0x02U;
+ }
+
+ /*
+ * lcdlseed= (1000000/(2*memck_freq)) * (100/(120*(stepsize_nominal)));
+ * *100/105 is to bias the seed low.
+ */
+ lcdlseed = (1000000U * 10U * 100U) / (2U * memck_freq * stepsize_x10 * 105U);
+
+ if (lcdlseed > (511U - 32U)) {
+ lcdlseed = 511U - 32U;
+ }
+
+ if (lcdlseed < 32U) {
+ lcdlseed = 32U;
+ }
+
+ wddllgainctl = (uint16_t)((CSR_DLLGAINTV_MASK & (dllgaintv << CSR_DLLGAINTV_LSB)) |
+ (CSR_DLLGAINIV_MASK & (dllgainiv << CSR_DLLGAINIV_LSB)));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLGAINCTL_ADDR))),
+ wddllgainctl);
+
+ wddlllockparam = (uint16_t)((CSR_LCDLSEED0_MASK & (lcdlseed << CSR_LCDLSEED0_LSB)) |
+ (CSR_DISDLLGAINIVSEED_MASK & 0xFFFFU));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLLOCKPARAM_ADDR))),
+ wddlllockparam);
+}
+
+/*
+ * Program AcsmCtrl23 for Fw and Ppt.
+ *
+ * CSRs to program:
+ * AcsmCtrl23::AcsmCsMask
+ * AcsmCsMode
+ */
+static void acsmctrl23_program(void)
+{
+ uint16_t regdata;
+
+ regdata = (0x0FU << CSR_ACSMCSMASK_LSB) | (0x1U << CSR_ACSMCSMODE_LSB);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL23_ADDR))),
+ regdata);
+}
+
+/*
+ * Set PllForceCal to 1 and PllDacValIn to some arbitrary value
+ */
+static void pllforcecal_plldacvalin_program(void)
+{
+ uint32_t dacval_in = 0x10U;
+ uint32_t force_cal = 0x1U;
+ uint32_t pllencal = 0x1U;
+ uint32_t maxrange = 0x1FU;
+ uint16_t pllctrl3_gpr;
+ uint16_t pllctrl3_startup;
+
+ pllctrl3_startup = (uint16_t)((dacval_in << CSR_PLLDACVALIN_LSB) |
+ (maxrange << CSR_PLLMAXRANGE_LSB));
+ pllctrl3_gpr = pllctrl3_startup | (uint16_t)((force_cal << CSR_PLLFORCECAL_LSB) |
+ (pllencal << CSR_PLLENCAL_LSB));
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PLLCTRL3_ADDR))),
+ pllctrl3_startup);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BGPR6_ADDR))),
+ pllctrl3_gpr);
+}
+
+/*
+ * This function programs registers that are normally set by training
+ * firmware.
+ *
+ * This function is used in place of running 1D or 1D training steps. PhyInit
+ * calls this function when skip_train = true. In that case, PhyInit does not
+ * execute training firmware and this function is called instead to program
+ * PHY registers according to DRAM timing parameters specified in userInput
+ * data structure. See documentation of ddrphy_phyinit_struct.h file
+ * details of timing parameters available in skip training.
+ *
+ * \warning ddrphy_phyinit_progcsrskiptrain() only supports zero board
+ * delay model. If system board delays are set or randomized, full 1D or 1D
+ * initialization flow must be executed.
+ *
+ * This function replaces these steps in the PHY Initialization sequence:
+ * - (E) Set the PHY input clocks to the desired frequency
+ * - (F) Write the Message Block parameters for the training firmware
+ * - (G) Execute the Training Firmware
+ * - (H) Read the Message Block results
+ *
+ * \returns \c void
+ */
+void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config,
+ struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t ardptrinitval)
+{
+ uint16_t txdqsdly;
+
+ /*
+ * Program ATxDlY
+ * For DDR4, DDR3 and LPDDR4, leave AtxDly[6:0] at default (0x0)
+ */
+
+ dfimrl_program(config, mb_ddr_1d, ardptrinitval);
+
+ txdqsdlytg_program(config, mb_ddr_1d, &txdqsdly);
+
+ txdqdlytg_program(config, mb_ddr_1d, txdqsdly);
+
+ rxendly_program(config, mb_ddr_1d);
+
+#if STM32MP_LPDDR4_TYPE
+ seq0bgpr_program(config);
+
+ hwtlpcsen_program(config);
+
+ pptdqscntinvtrntg_program(config);
+
+ pptctlstatic_program(config);
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ hwtcamode_program();
+
+ dllgainctl_dlllockparam_program(config);
+
+ acsmctrl23_program();
+
+ pllforcecal_plldacvalin_program();
+
+ /*
+ * ##############################################################
+ *
+ * Setting PhyInLP3 to 0 to cause PIE to execute LP2 sequence instead of INIT on first
+ * dfi_init_start.
+ * This prevents any DRAM commands before DRAM is initialized, which is the case for
+ * skip_train.
+ *
+ * Moved to here from dddrphy_phyinit_I_loadPIEImage()
+ * These should not be needed on S3-exit
+ *
+ * Note this executes for SkipTrain only, *not* DevInit+SkipTrain
+ * DevInit+SkipTrain already initializes DRAM and thus don't need to avoid DRAM commands
+ *
+ * ##############################################################
+ */
+
+ /*
+ * Special skipTraining configuration to Prevent DRAM Commands on the first dfi
+ * status interface handshake. In order to see this behavior, the first dfi_freq
+ * should be in the range of 0x0f < dfi_freq_sel[4:0] < 0x14.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_PHYINLP3_ADDR))), 0x0U);
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c
new file mode 100644
index 0000000..21400f7
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * This file provides a group of functions that are used to track PHY register
+ * writes by intercepting io_write16 function calls. Once the registers are
+ * tracked, their value can be saved at a given time spot, and restored later
+ * as required. This implementation is useful to capture any PHY register
+ * programing in any function during PHY initialization.
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*
+ * MAX_NUM_RET_REGS default Max number of retention registers.
+ *
+ * This define is only used by the PhyInit Register interface to define the max
+ * amount of registered that can be saved. The user may increase this variable
+ * as desired if a larger number of registers need to be restored.
+ */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+#define MAX_NUM_RET_REGS 129
+#else /* STM32MP_LPDDR4_TYPE */
+#define MAX_NUM_RET_REGS 283
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
+/*
+ * Array of Address/value pairs used to store register values for the purpose
+ * of retention restore.
+ */
+#define RETREG_AREA (MAX_NUM_RET_REGS + 1) * sizeof(struct reg_addr_val)
+#define RETREG_BASE RETRAM_BASE + RETRAM_SIZE - RETREG_AREA
+
+static int *retregsize = (int *)(RETREG_BASE);
+static struct reg_addr_val *retreglist = (struct reg_addr_val *)(RETREG_BASE + sizeof(int));
+
+static int numregsaved; /* Current Number of registers saved. */
+static int tracken = 1; /* Enabled tracking of registers */
+
+/*
+ * Tags a register if tracking is enabled in the register
+ * interface.
+ *
+ * During PhyInit registers writes, keeps track of address
+ * for the purpose of restoring the PHY register state during PHY
+ * retention exit process. Tracking can be turned on/off via the
+ * ddrphy_phyinit_reginterface STARTTRACK, STOPTRACK instructions. By
+ * default tracking is always turned on.
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_trackreg(uint32_t adr)
+{
+ int regindx = 0;
+
+ /* Return if tracking is disabled */
+ if (tracken == 0) {
+ return 0;
+ }
+
+ /* Search register address within the array */
+ for (regindx = 0; regindx < numregsaved; regindx++) {
+ if (retreglist[regindx].address == adr) {
+ /* Register found */
+ return 0;
+ }
+ }
+
+ /* Register not found, so add it */
+ if (numregsaved > MAX_NUM_RET_REGS) {
+ ERROR("numregsaved > MAX_NUM_RET_REGS\n");
+ VERBOSE("[ddrphy_phyinit_reginterface:%s]\n", __func__);
+ VERBOSE("Max Number of Restore Registers reached: %d.\n", numregsaved);
+ VERBOSE("Please recompile PhyInit with larger MAX_NUM_RET_REG value.\n");
+ return -1;
+ }
+
+ retreglist[regindx].address = adr;
+ numregsaved++;
+
+ return 0;
+}
+
+/*
+ * Register interface function used to track, save and restore retention registers.
+ *
+ * ### Usage
+ * Register tracking is enabled by calling:
+ *
+ * \code
+ * ddrphy_phyinit_reginterface(STARTTRACK,0,0);
+ * \endcode
+ *
+ * from this point on any call to mmio_write_16() in
+ * return will be capture by the register interface via a call to
+ * ddrphy_phyinit_trackreg(). Tracking is disabled by calling:
+ *
+ * \code
+ * ddrphy_phyinit_reginterface(STOPTRACK,0,0);
+ * \endcode
+ *
+ * On calling this function, register write via mmio_write_16 are no longer tracked until a
+ * STARTTRACK call is made. Once all the register write are complete, SAVEREGS
+ * command can be issue to save register values into the internal data array of
+ * the register interface. Upon retention exit RESTOREREGS are command can be
+ * used to issue register write commands to the PHY based on values stored in
+ * the array.
+ * \code
+ * ddrphy_phyinit_reginterface(SAVEREGS,0,0);
+ * ddrphy_phyinit_reginterface(RESTOREREGS,0,0);
+ * \endcode
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_reginterface(enum reginstr myreginstr, uint32_t adr, uint16_t dat)
+{
+ if (myreginstr == SAVEREGS) {
+ int regindx;
+
+ /*
+ * Go through all the tracked registers, issue a register read and place
+ * the result in the data structure for future recovery.
+ */
+ for (regindx = 0; regindx < numregsaved; regindx++) {
+ uint16_t data;
+
+ data = mmio_read_16((uintptr_t)(DDRPHYC_BASE +
+ (4U * retreglist[regindx].address)));
+ retreglist[regindx].value = data;
+ }
+
+ *retregsize = numregsaved;
+
+ return 0;
+ } else if (myreginstr == RESTOREREGS) {
+ int regindx;
+
+ /*
+ * Write PHY registers based on Address, Data value pairs stores in
+ * retreglist.
+ */
+ for (regindx = 0; regindx < *retregsize; regindx++) {
+ mmio_write_16((uintptr_t)
+ (DDRPHYC_BASE + (4U * retreglist[regindx].address)),
+ retreglist[regindx].value);
+ }
+
+ return 0;
+ } else if (myreginstr == STARTTRACK) {
+ /* Enable tracking */
+ tracken = 1;
+ return 0;
+ } else if (myreginstr == STOPTRACK) {
+ /* Disable tracking */
+ tracken = 0;
+ return 0;
+ } else {
+ return -1;
+ }
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c
new file mode 100644
index 0000000..cddb955
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*
+ * This function implements the register restore portion of S3/IO
+ * retention sequence.
+ *
+ * \note This function requiers the runtime_config.reten=1 to enable PhyInit exit retention feature.
+ * This variable can be set as in
+ * \return 0 on completion of the sequence, EXIT_FAILURE on error.
+ */
+int ddrphy_phyinit_restore_sequence(void)
+{
+ int ret;
+
+ /*
+ * Before you call this functions perform the following:
+ * --------------------------------------------------------------------------
+ * -# Bring up VDD, VDDQ should already be up
+ * -# Since the CKE* and MEMRESET pin state must be protected, special care
+ * must be taken to ensure that the following signals
+ * - atpg_mode = 1'b0
+ * - PwrOkIn = 1'b0
+ *
+ * -# The {BypassModeEn*, WRSTN} signals may be defined at VDD power-on, but
+ * must be driven to ZERO at least 10ns prior to the asserting edge of PwrOkIn.
+ *
+ * -# Start Clocks and Reset the PHY
+ * This step is identical to ddrphy_phyinit_usercustom_b_startclockresetphy()
+ */
+
+ /* Write the MicroContMuxSel CSR to 0x0 to allow access to the internal CSRs */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x0U);
+
+ /*
+ * Write the UcclkHclkEnables CSR to 0x3 to enable all the clocks so the reads can
+ * complete.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
+ 0x3U);
+
+ /*
+ * Assert CalZap to force impedance calibration FSM to idle.
+ * De-asserted as part of dfi_init_start/complete handshake by the PIE when DfiClk is valid.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALZAP_ADDR))), 0x1U);
+
+ /* Issue register writes to restore registers values */
+ ret = ddrphy_phyinit_reginterface(RESTOREREGS, 0U, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /*
+ * Write the UcclkHclkEnables CSR to disable the appropriate clocks after all reads done.
+ * Disabling Ucclk (PMU) and Hclk (training hardware).
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
+ 0x0U);
+
+ /* Write the MicroContMuxSel CSR to 0x1 to isolate the internal CSRs during mission mode */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x1U);
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c
new file mode 100644
index 0000000..adc4377
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+/*
+ * This function implements the flow of PhyInit software to initialize the PHY.
+ *
+ * The execution sequence follows the overview figure provided in the Reference Manual.
+ *
+ * \returns 0 on completion of the sequence, EXIT_FAILURE on error.
+ */
+int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten)
+{
+ int ret;
+ uint32_t ardptrinitval; /*
+ * Represents the value stored in Step C into the register with the
+ * same name. Defined as a global variable so that implementation
+ * of ddrphy_phyinit_progcsrskiptrain() function does not require
+ * a PHY read register implementation.
+ */
+ struct pmu_smb_ddr_1d mb_ddr_1d; /* Firmware 1D Message Block structure */
+
+ /* Check user input pstate number consistency vs. SW capabilities */
+ if (config->uib.numpstates > 1U) {
+ return -1;
+ }
+
+ /* Initialize structures */
+ ddrphy_phyinit_initstruct(config, &mb_ddr_1d);
+
+ /* Re-calculate Firmware Message Block input based on final user input */
+ ret = ddrphy_phyinit_calcmb(config, &mb_ddr_1d);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* (A) Bring up VDD, VDDQ, and VAA */
+ /* ddrphy_phyinit_usercustom_a_bringuppower(); */
+
+ /* (B) Start Clocks and Reset the PHY */
+ /* ddrphy_phyinit_usercustom_b_startclockresetphy(); */
+
+ /* (C) Initialize PHY Configuration */
+ ret = ddrphy_phyinit_c_initphyconfig(config, &mb_ddr_1d, &ardptrinitval);
+ if (ret != 0) {
+ return ret;
+ }
+ /*
+ * Customize any register write desired; This can include any CSR not covered by PhyInit
+ * or user wish to override values calculated in step_C.
+ */
+ ddrphy_phyinit_usercustom_custompretrain(config);
+
+ /* Stop retention register tracking for training firmware related registers */
+ ret = ddrphy_phyinit_reginterface(STOPTRACK, 0U, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (skip_training) {
+ /* Skip running training firmware entirely */
+ ddrphy_phyinit_progcsrskiptrain(config, &mb_ddr_1d, ardptrinitval);
+ } else {
+ /* (D) Load the IMEM Memory for 1D training */
+ ddrphy_phyinit_d_loadimem();
+
+ /* (E) Set the PHY input clocks to the desired frequency */
+ /* ddrphy_phyinit_usercustom_e_setdficlk(pstate); */
+
+ /* (F) Write the Message Block parameters for the training firmware */
+ ret = ddrphy_phyinit_f_loaddmem(config, &mb_ddr_1d);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* (G) Execute the Training Firmware */
+ ret = ddrphy_phyinit_g_execfw();
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* (H) Read the Message Block results */
+ /* ddrphy_phyinit_h_readmsgblock(); */
+ }
+
+ /* Start retention register tracking for training firmware related registers */
+ ret = ddrphy_phyinit_reginterface(STARTTRACK, 0U, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* (I) Load PHY Init Engine Image */
+ ddrphy_phyinit_i_loadpieimage(config, skip_training);
+
+ /*
+ * Customize any CSR write desired to override values programmed by firmware or
+ * ddrphy_phyinit_i_loadpieimage()
+ */
+ /* ddrphy_phyinit_usercustom_customposttrain(); */
+
+ if (reten) {
+ /* Save value of tracked registers for retention restore sequence. */
+ ret = ddrphy_phyinit_usercustom_saveretregs(config);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ /* (J) Initialize the PHY to Mission Mode through DFI Initialization */
+ /* ddrphy_phyinit_usercustom_j_entermissionmode(); */
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c
new file mode 100644
index 0000000..86b084d
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+/*
+ * Set messageBlock variable only if not set by user
+ *
+ * This function is used by ddrphy_phyinit_calcmb() to set calculated
+ * messageBlock variables only when the user has not directly programmed them.
+ *
+ * @param[in] field A string representing the messageBlock field to be programed.
+ * @param[in] value filed value
+ *
+ * @return 0 on success.
+ * On error returns the following values based on error:
+ * - -1 : message block field specified by the input \c field string is not
+ * found in the message block data structure.
+ */
+int ddrphy_phyinit_softsetmb(struct pmu_smb_ddr_1d *mb_ddr_1d, enum message_block_field field,
+ uint32_t value)
+{
+ int ret = 0;
+
+ if (field == MB_FIELD_DRAMFREQ) {
+ assert(value <= UINT16_MAX);
+ } else {
+ assert(value <= UINT8_MAX);
+ }
+
+ switch (field) {
+ case MB_FIELD_PSTATE:
+ mb_ddr_1d->pstate = (uint8_t)value;
+ break;
+ case MB_FIELD_PLLBYPASSEN:
+ mb_ddr_1d->pllbypassen = (uint8_t)value;
+ break;
+ case MB_FIELD_DRAMFREQ:
+ mb_ddr_1d->dramfreq = (uint16_t)value;
+ break;
+ case MB_FIELD_DFIFREQRATIO:
+ mb_ddr_1d->dfifreqratio = (uint8_t)value;
+ break;
+ case MB_FIELD_BPZNRESVAL:
+ mb_ddr_1d->bpznresval = (uint8_t)value;
+ break;
+ case MB_FIELD_PHYODTIMPEDANCE:
+ mb_ddr_1d->phyodtimpedance = (uint8_t)value;
+ break;
+ case MB_FIELD_PHYDRVIMPEDANCE:
+ mb_ddr_1d->phydrvimpedance = (uint8_t)value;
+ break;
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ case MB_FIELD_DRAMTYPE:
+ mb_ddr_1d->dramtype = (uint8_t)value;
+ break;
+ case MB_FIELD_DISABLEDDBYTE:
+ mb_ddr_1d->disableddbyte = (uint8_t)value;
+ break;
+ case MB_FIELD_ENABLEDDQS:
+ mb_ddr_1d->enableddqs = (uint8_t)value;
+ break;
+ case MB_FIELD_PHYCFG:
+ mb_ddr_1d->phycfg = (uint8_t)value;
+ break;
+#if STM32MP_DDR4_TYPE
+ case MB_FIELD_X16PRESENT:
+ mb_ddr_1d->x16present = (uint8_t)value;
+ break;
+#endif /* STM32MP_DDR4_TYPE */
+#else /* STM32MP_LPDDR4_TYPE */
+ case MB_FIELD_ENABLEDDQSCHA:
+ mb_ddr_1d->enableddqscha = (uint8_t)value;
+ break;
+ case MB_FIELD_CSPRESENTCHA:
+ mb_ddr_1d->cspresentcha = (uint8_t)value;
+ break;
+ case MB_FIELD_ENABLEDDQSCHB:
+ mb_ddr_1d->enableddqschb = (uint8_t)value;
+ break;
+ case MB_FIELD_CSPRESENTCHB:
+ mb_ddr_1d->cspresentchb = (uint8_t)value;
+ break;
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ default:
+ ERROR("unknown message block field %u\n", field);
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c
new file mode 100644
index 0000000..868800e
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*
+ * Writes local memory content into the SRAM via APB interface.
+ *
+ * This function issued APB writes commands to SRAM address based on values
+ * stored in a local PhyInit array that contains consolidated IMEM and DMEM
+ * data.
+ * @param[in] mem[] Local memory array.
+ * @param[in] mem_offset offset index. if provided, skips to the offset index
+ * from the local array and issues APB commands from mem_offset to mem_size.
+ * @param[in] mem_size size of the memroy (in mem array index)
+ * @returns void
+ */
+void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size)
+{
+ uint32_t index;
+
+ /*
+ * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+ * This allows the memory controller unrestricted access to the configuration CSRs.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x0U);
+
+ for (index = 0U; index < mem_size / sizeof(uint32_t); index++) {
+ uint32_t data = mem[index];
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + mem_offset))),
+ data & 0xFFFFU);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + 1 + mem_offset))),
+ (data >> 16) & 0xFFFFU);
+ }
+
+ /*
+ * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+ * This allows the firmware unrestricted access to the configuration CSRs.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x1U);
+}
+
+/* Similar function for message block */
+void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size)
+{
+ uint32_t index;
+
+ /*
+ * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+ * This allows the memory controller unrestricted access to the configuration CSRs.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x0U);
+
+ for (index = 0U; index < mem_size / sizeof(uint16_t); index++) {
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (index + mem_offset))), mem[index]);
+ }
+
+ /*
+ * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+ * This allows the firmware unrestricted access to the configuration CSRs.
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x1U);
+}
diff --git a/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c
new file mode 100644
index 0000000..6a20013
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/* DDRDBG registers */
+#define DDRDBG_DDR34_AC_SWIZZLE_ADD3_0 U(0x100)
+
+/*
+ * This function is called before training firmware is executed. Any
+ * register override in this function might affect the firmware training
+ * results.
+ *
+ * This function is executed before firmware execution loop. Thus this function
+ * should be used only for the following:
+ *
+ * - Override PHY register values written by
+ * ddrphy_phyinit_c_initphyconfig. An example use case is when this
+ * function does not perform the exact programing desired by the user.
+ * - Write custom PHY registers that need to take effect before training
+ * firmware execution.
+ *
+ * User shall use mmio_write_16 to write PHY registers in order for the register
+ * to be tracked by PhyInit for retention restore.
+ *
+ * To override settings in the message block, users can assign values to the
+ * fields in the message block data structure directly.
+ *
+ * \ref examples/simple/ddrphy_phyinit_usercustom_custompretrain.c example of this function.
+ *
+ * @return Void
+ */
+void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config)
+{
+ uint32_t byte __unused;
+ uint32_t i = 0U;
+ uint32_t j;
+ uintptr_t base;
+
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ base = (uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTSWIZZLEHWTADDRESS0_ADDR)));
+
+ for (i = 0U; i < NB_HWT_SWIZZLE; i++) {
+ mmio_write_16(base + (i * sizeof(uint32_t)),
+ (uint16_t)config->uis.swizzle[i]);
+ }
+
+ base = (uintptr_t)(stm32_ddrdbg_get_base() + DDRDBG_DDR34_AC_SWIZZLE_ADD3_0);
+
+ for (j = 0U; j < NB_AC_SWIZZLE; j++, i++) {
+ mmio_write_32(base + (j * sizeof(uint32_t)), config->uis.swizzle[i]);
+ }
+#else /* STM32MP_LPDDR4_TYPE */
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ base = (uintptr_t)(DDRPHYC_BASE + (4U *
+ ((byte << 12) | TDBYTE | CSR_DQ0LNSEL_ADDR)));
+
+ for (j = 0U; j < NB_DQLNSEL_SWIZZLE_PER_BYTE; j++, i++) {
+ mmio_write_16(base + (j * sizeof(uint32_t)),
+ (uint16_t)config->uis.swizzle[i]);
+ }
+ }
+
+ base = (uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MAPCAA0TODFI_ADDR)));
+
+ for (j = 0U; j < NB_MAPCAATODFI_SWIZZLE; j++, i++) {
+ mmio_write_16(base + (j * sizeof(uint32_t)),
+ (uint16_t)config->uis.swizzle[i]);
+ }
+
+ base = (uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MAPCAB0TODFI_ADDR)));
+
+ for (j = 0U; j < NB_MAPCABTODFI_SWIZZLE; j++, i++) {
+ mmio_write_16(base + (j * sizeof(uint32_t)),
+ (uint16_t)config->uis.swizzle[i]);
+ }
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+}
diff --git a/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
new file mode 100644
index 0000000..3d00d3d
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <drivers/delay_timer.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/* Firmware major messages */
+#define FW_MAJ_MSG_TRAINING_SUCCESS 0x0000007U
+#define FW_MAJ_MSG_START_STREAMING 0x0000008U
+#define FW_MAJ_MSG_TRAINING_FAILED 0x00000FFU
+
+#define PHYINIT_DELAY_1US 1U
+#define PHYINIT_DELAY_10US 10U
+#define PHYINIT_TIMEOUT_US_1S 1000000U
+
+static int wait_uctwriteprotshadow(bool state)
+{
+ uint64_t timeout;
+ uint16_t read_data;
+ uint16_t value = state ? BIT(0) : 0U;
+
+ timeout = timeout_init_us(PHYINIT_TIMEOUT_US_1S);
+
+ do {
+ read_data = mmio_read_16((uintptr_t)(DDRPHYC_BASE +
+ (4U * (TAPBONLY | CSR_UCTSHADOWREGS_ADDR))));
+ udelay(PHYINIT_DELAY_1US);
+ if (timeout_elapsed(timeout)) {
+ return -1;
+ }
+ } while ((read_data & BIT(0)) != value);
+
+ return 0;
+}
+
+static int ack_message_receipt(void)
+{
+ int ret;
+
+ /* Acknowledge the receipt of the message */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_DCTWRITEPROT_ADDR))), 0U);
+
+ udelay(PHYINIT_DELAY_1US);
+
+ ret = wait_uctwriteprotshadow(true);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Complete the 4-phase protocol */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_DCTWRITEPROT_ADDR))), 1U);
+
+ udelay(PHYINIT_DELAY_1US);
+
+ return 0;
+}
+
+static int get_major_message(uint32_t *msg)
+{
+ uint16_t message_number;
+ int ret;
+
+ ret = wait_uctwriteprotshadow(false);
+ if (ret != 0) {
+ return ret;
+ }
+
+ message_number = mmio_read_16((uintptr_t)(DDRPHYC_BASE +
+ (4U * (TAPBONLY |
+ CSR_UCTWRITEONLYSHADOW_ADDR))));
+
+ ret = ack_message_receipt();
+ if (ret != 0) {
+ return ret;
+ }
+
+ *msg = (uint32_t)message_number;
+
+ return 0;
+}
+
+static int get_streaming_message(uint32_t *msg)
+{
+ uint16_t stream_word_lower_part;
+ uint16_t stream_word_upper_part;
+ int ret;
+
+ ret = wait_uctwriteprotshadow(false);
+ if (ret != 0) {
+ return ret;
+ }
+
+ stream_word_lower_part = mmio_read_16((uintptr_t)(DDRPHYC_BASE +
+ (4U * (TAPBONLY |
+ CSR_UCTWRITEONLYSHADOW_ADDR))));
+
+ stream_word_upper_part = mmio_read_16((uintptr_t)(DDRPHYC_BASE +
+ (4U * (TAPBONLY |
+ CSR_UCTDATWRITEONLYSHADOW_ADDR))));
+
+ ret = ack_message_receipt();
+ if (ret != 0) {
+ return ret;
+ }
+
+ *msg = (uint32_t)stream_word_lower_part | ((uint32_t)stream_word_upper_part << 16);
+
+ return 0;
+}
+
+/*
+ * Implements the mechanism to wait for completion of training firmware execution.
+ *
+ * The purpose of user this function is to wait for firmware to finish training.
+ * The user can either implement a counter to wait or implement the polling
+ * mechanism (our choice here). The wait time is highly dependent on the training features
+ * enabled via sequencectrl input to the message block.
+ *
+ * The default behavior of this function is to print comments relating to this
+ * process. A function call of the same name will be printed in the output text
+ * file.
+ *
+ * The user can choose to leave this function as is, or implement mechanism to
+ * trigger mailbox poling event in simulation.
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_usercustom_g_waitfwdone(void)
+{
+ uint32_t fw_major_message;
+ int ret;
+
+ do {
+ ret = get_major_message(&fw_major_message);
+ if (ret != 0) {
+ return ret;
+ }
+
+ VERBOSE("fw_major_message = %x\n", (unsigned int)fw_major_message);
+
+ if (fw_major_message == FW_MAJ_MSG_START_STREAMING) {
+ uint32_t i;
+ uint32_t read_data;
+ uint32_t stream_len;
+
+ ret = get_streaming_message(&read_data);
+ if (ret != 0) {
+ return ret;
+ }
+
+ stream_len = read_data & 0xFFFFU;
+
+ for (i = 0U; i < stream_len; i++) {
+ ret = get_streaming_message(&read_data);
+ if (ret != 0) {
+ return ret;
+ }
+
+ VERBOSE("streaming message = %x\n", (unsigned int)read_data);
+ }
+ }
+ } while ((fw_major_message != FW_MAJ_MSG_TRAINING_SUCCESS) &&
+ (fw_major_message != FW_MAJ_MSG_TRAINING_FAILED));
+
+ udelay(PHYINIT_DELAY_10US);
+
+ if (fw_major_message == FW_MAJ_MSG_TRAINING_FAILED) {
+ ERROR("%s Training has failed.\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
new file mode 100644
index 0000000..b573de3
--- /dev/null
+++ b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
@@ -0,0 +1,399 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*
+ * This function can be used to implement saving of PHY registers to be
+ * restored on retention exit.
+ *
+ * The requirement of this function is to issue register reads and store the
+ * value to be recovered on retention exit. The following is an example
+ * implementation and the user may implement alternate methods that suit their
+ * specific SoC system needs.
+ *
+ * In this implementation PhyInit saves register values in an internal C array.
+ * During retention exit it restores register values from the array. The exact
+ * list of registers to save and later restore can be seen in the output txt
+ * file with an associated calls to mmio_read_16().
+ *
+ * PhyInit provides a register interface and a tracking mechanism to minimize
+ * the number registers needing restore. Refer to source code for
+ * ddrphy_phyinit_reginterface() for detailed implementation of tracking
+ * mechanism. Tracking is disabled from step D to Step H as these involve
+ * loading, executing and checking the state of training firmware execution
+ * which are not required to implement the retention exit sequence. The registers
+ * specified representing training results are also saved in addition to registers
+ * written by PhyInit during PHY initialization.
+ *
+ * \return 0 on success.
+ */
+int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config)
+{
+ uint32_t anib;
+ uint32_t byte;
+ uint32_t nibble;
+ uint32_t lane;
+ uint32_t c_addr;
+ uint32_t u_addr;
+ uint32_t b_addr;
+ uint32_t r_addr;
+ int ret;
+
+ /*
+ * --------------------------------------------------------------------------
+ * 1. Enable tracking of training firmware result registers
+ *
+ * \note The tagged registers in this step are in
+ * addition to what is automatically tagged during Steps C to I.
+ *
+ * --------------------------------------------------------------------------
+ */
+
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_PLLCTRL3_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Non-PState Dbyte Registers */
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ c_addr = byte << 12;
+
+ for (lane = 0U; lane <= R_MAX; lane++) {
+ r_addr = lane << 8;
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr |
+ CSR_RXPBDLYTG0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr |
+ CSR_RXPBDLYTG1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_PPTCTLSTATIC_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_TRAININGINCDECDTSMEN_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_TSMBYTE0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ0LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ1LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ2LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ3LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ4LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ5LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ6LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ7LNSEL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_VREFINGLOBAL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Anib Registers */
+ for (anib = 0U; anib < config->uib.numanib; anib++) {
+ c_addr = anib << 12;
+
+ ret = ddrphy_phyinit_trackreg(TANIB | c_addr | CSR_ATXDLY_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ /* Dbyte Registers */
+ for (byte = 0U; byte < config->uib.numdbyte; byte++) {
+ c_addr = byte << 12;
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DFIMRL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ for (nibble = 0U; nibble <= B_MAX; nibble++) {
+ b_addr = nibble << 8;
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | b_addr |
+ CSR_DQDQSRCVCNTRL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ for (nibble = 0U; nibble < 2U; nibble++) {
+ u_addr = nibble << 8;
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr |
+ CSR_RXENDLYTG0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr |
+ CSR_RXENDLYTG1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr |
+ CSR_TXDQSDLYTG0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr |
+ CSR_TXDQSDLYTG1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr |
+ CSR_RXCLKDLYTG0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr |
+ CSR_RXCLKDLYTG1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+
+ for (lane = R_MIN; lane <= R_MAX; lane++) {
+ r_addr = lane << 8;
+
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr |
+ CSR_TXDQDLYTG0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr |
+ CSR_TXDQDLYTG1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_PPTDQSCNTINVTRNTG0_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_PPTDQSCNTINVTRNTG1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+
+ /* PIE Registers */
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR1_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR2_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR3_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR4_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR5_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR6_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR7_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR8_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Master Registers */
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_DLLGAINCTL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_DLLLOCKPARAM_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTMRL_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* INITENG Registers */
+ ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BDISABLEFLAG6_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTCAMODE_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTLPCSENA_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTLPCSENB_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* ACSM registers */
+ ret = ddrphy_phyinit_trackreg(TACSM | CSR_ACSMCTRL13_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ddrphy_phyinit_trackreg(TACSM | CSR_ACSMCTRL23_ADDR);
+ if (ret != 0) {
+ return ret;
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ /*
+ * --------------------------------------------------------------------------
+ * 2. Track any additional registers
+ * Register writes made using the any of the PhyInit functions are
+ * automatically tracked using the call to ddrphy_phyinit_trackreg() in
+ * mmio_write_16(). Use this section to track additional registers.
+ * --------------------------------------------------------------------------
+ */
+
+ /*
+ * Example:
+ * ddrphy_phyinit_trackreg(<addr>);
+ */
+
+ /*
+ * --------------------------------------------------------------------------
+ * 3. Prepare for register reads
+ * - Write the MicroContMuxSel CSR to 0x0 to allow access to the internal CSRs
+ * - Write the UcclkHclkEnables CSR to 0x3 to enable all the clocks so the reads
+ * can complete.
+ * --------------------------------------------------------------------------
+ */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x0U);
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
+ 0x3U);
+
+ /*
+ * --------------------------------------------------------------------------
+ * / 4. Read and save all the registers
+ * / - The list of registers differ depending on protocol and 1D training.
+ * --------------------------------------------------------------------------
+ */
+
+ ret = ddrphy_phyinit_reginterface(SAVEREGS, 0U, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /*
+ * --------------------------------------------------------------------------
+ * 5. Prepare for mission mode
+ * - Write the UcclkHclkEnables CSR to disable the appropriate clocks after all reads done.
+ * - Write the MicroContMuxSel CSR to 0x1 to isolate the internal CSRs during mission mode.
+ * --------------------------------------------------------------------------
+ */
+
+ /* Disabling Ucclk (PMU) and Hclk (training hardware) */
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
+ 0x0U);
+
+ mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
+ 0x1U);
+
+ return 0;
+}
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index 27d8b2c..415d9e4 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -24,14 +24,12 @@
#define DDRCTL_REG(x, y) \
{ \
- .name = #x, \
.offset = offsetof(struct stm32mp_ddrctl, x), \
.par_offset = offsetof(struct y, x) \
}
#define DDRPHY_REG(x, y) \
{ \
- .name = #x, \
.offset = offsetof(struct stm32mp_ddrphy, x), \
.par_offset = offsetof(struct y, x) \
}
@@ -215,7 +213,7 @@
{
uint32_t pgsr;
int error = 0;
- uint64_t timeout = timeout_init_us(TIMEOUT_US_1S);
+ uint64_t timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
do {
pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
@@ -266,7 +264,7 @@
mmio_read_32((uintptr_t)&phy->pir));
/* Need to wait 10 configuration clock before start polling */
- udelay(10);
+ udelay(DDR_DELAY_10US);
/* Wait DRAM initialization and Gate Training Evaluation complete */
stm32mp1_ddrphy_idone_wait(phy);
@@ -279,7 +277,7 @@
uint32_t stat;
int break_loop = 0;
- timeout = timeout_init_us(TIMEOUT_US_1S);
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
for ( ; ; ) {
uint32_t operating_mode;
uint32_t selref_type;
@@ -508,8 +506,7 @@
#endif
/* 12. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
- mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl,
- DDRCTRL_PWRCTL_SELFREF_SW);
+ stm32mp_ddr_sw_selfref_exit(priv->ctl);
stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
/*
@@ -524,10 +521,7 @@
*/
/* 15. Write DBG1.dis_hif = 0 to re-enable reads and writes. */
- mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
- VERBOSE("[0x%lx] dbg1 = 0x%x\n",
- (uintptr_t)&priv->ctl->dbg1,
- mmio_read_32((uintptr_t)&priv->ctl->dbg1));
+ stm32mp_ddr_enable_host_interface(priv->ctl);
}
static void stm32mp1_refresh_disable(struct stm32mp_ddrctl *ctl)
@@ -614,7 +608,7 @@
mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
/* 1.4. wait 128 cycles to permit initialization of end logic */
- udelay(2);
+ udelay(DDR_DELAY_2US);
/* For PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
/* 1.5. initialize registers ddr_umctl2 */
diff --git a/drivers/st/ddr/stm32mp2_ddr.c b/drivers/st/ddr/stm32mp2_ddr.c
new file mode 100644
index 0000000..5193d11
--- /dev/null
+++ b/drivers/st/ddr/stm32mp2_ddr.c
@@ -0,0 +1,479 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <ddrphy_phyinit.h>
+
+#include <drivers/delay_timer.h>
+#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp2_ddr_regs.h>
+#include <drivers/st/stm32mp_ddr.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#define DDRDBG_FRAC_PLL_LOCK U(0x10)
+
+#define DDRCTL_REG(x, y, z) \
+ { \
+ .offset = offsetof(struct stm32mp_ddrctl, x), \
+ .par_offset = offsetof(struct y, x), \
+ .qd = z \
+ }
+
+/*
+ * PARAMETERS: value get from device tree :
+ * size / order need to be aligned with binding
+ * modification NOT ALLOWED !!!
+ */
+#define DDRCTL_REG_REG_SIZE 48 /* st,ctl-reg */
+#define DDRCTL_REG_TIMING_SIZE 20 /* st,ctl-timing */
+#define DDRCTL_REG_MAP_SIZE 12 /* st,ctl-map */
+#if STM32MP_DDR_DUAL_AXI_PORT
+#define DDRCTL_REG_PERF_SIZE 21 /* st,ctl-perf */
+#else /* !STM32MP_DDR_DUAL_AXI_PORT */
+#define DDRCTL_REG_PERF_SIZE 14 /* st,ctl-perf */
+#endif /* STM32MP_DDR_DUAL_AXI_PORT */
+
+#define DDRPHY_REG_REG_SIZE 0 /* st,phy-reg */
+#define DDRPHY_REG_TIMING_SIZE 0 /* st,phy-timing */
+
+#define DDRCTL_REG_REG(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_reg, z)
+static const struct stm32mp_ddr_reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
+ DDRCTL_REG_REG(mstr, true),
+ DDRCTL_REG_REG(mrctrl0, false),
+ DDRCTL_REG_REG(mrctrl1, false),
+ DDRCTL_REG_REG(mrctrl2, false),
+ DDRCTL_REG_REG(derateen, true),
+ DDRCTL_REG_REG(derateint, false),
+ DDRCTL_REG_REG(deratectl, false),
+ DDRCTL_REG_REG(pwrctl, false),
+ DDRCTL_REG_REG(pwrtmg, true),
+ DDRCTL_REG_REG(hwlpctl, true),
+ DDRCTL_REG_REG(rfshctl0, false),
+ DDRCTL_REG_REG(rfshctl1, false),
+ DDRCTL_REG_REG(rfshctl3, true),
+ DDRCTL_REG_REG(crcparctl0, false),
+ DDRCTL_REG_REG(crcparctl1, false),
+ DDRCTL_REG_REG(init0, true),
+ DDRCTL_REG_REG(init1, false),
+ DDRCTL_REG_REG(init2, false),
+ DDRCTL_REG_REG(init3, true),
+ DDRCTL_REG_REG(init4, true),
+ DDRCTL_REG_REG(init5, false),
+ DDRCTL_REG_REG(init6, true),
+ DDRCTL_REG_REG(init7, true),
+ DDRCTL_REG_REG(dimmctl, false),
+ DDRCTL_REG_REG(rankctl, true),
+ DDRCTL_REG_REG(rankctl1, true),
+ DDRCTL_REG_REG(zqctl0, true),
+ DDRCTL_REG_REG(zqctl1, false),
+ DDRCTL_REG_REG(zqctl2, false),
+ DDRCTL_REG_REG(dfitmg0, true),
+ DDRCTL_REG_REG(dfitmg1, true),
+ DDRCTL_REG_REG(dfilpcfg0, false),
+ DDRCTL_REG_REG(dfilpcfg1, false),
+ DDRCTL_REG_REG(dfiupd0, true),
+ DDRCTL_REG_REG(dfiupd1, false),
+ DDRCTL_REG_REG(dfiupd2, false),
+ DDRCTL_REG_REG(dfimisc, true),
+ DDRCTL_REG_REG(dfitmg2, true),
+ DDRCTL_REG_REG(dfitmg3, false),
+ DDRCTL_REG_REG(dbictl, true),
+ DDRCTL_REG_REG(dfiphymstr, false),
+ DDRCTL_REG_REG(dbg0, false),
+ DDRCTL_REG_REG(dbg1, false),
+ DDRCTL_REG_REG(dbgcmd, false),
+ DDRCTL_REG_REG(swctl, false), /* forced qd value */
+ DDRCTL_REG_REG(swctlstatic, false),
+ DDRCTL_REG_REG(poisoncfg, false),
+ DDRCTL_REG_REG(pccfg, false),
+};
+
+#define DDRCTL_REG_TIMING(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_timing, z)
+static const struct stm32mp_ddr_reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
+ DDRCTL_REG_TIMING(rfshtmg, false),
+ DDRCTL_REG_TIMING(rfshtmg1, false),
+ DDRCTL_REG_TIMING(dramtmg0, true),
+ DDRCTL_REG_TIMING(dramtmg1, true),
+ DDRCTL_REG_TIMING(dramtmg2, true),
+ DDRCTL_REG_TIMING(dramtmg3, true),
+ DDRCTL_REG_TIMING(dramtmg4, true),
+ DDRCTL_REG_TIMING(dramtmg5, true),
+ DDRCTL_REG_TIMING(dramtmg6, true),
+ DDRCTL_REG_TIMING(dramtmg7, true),
+ DDRCTL_REG_TIMING(dramtmg8, true),
+ DDRCTL_REG_TIMING(dramtmg9, true),
+ DDRCTL_REG_TIMING(dramtmg10, true),
+ DDRCTL_REG_TIMING(dramtmg11, true),
+ DDRCTL_REG_TIMING(dramtmg12, true),
+ DDRCTL_REG_TIMING(dramtmg13, true),
+ DDRCTL_REG_TIMING(dramtmg14, true),
+ DDRCTL_REG_TIMING(dramtmg15, true),
+ DDRCTL_REG_TIMING(odtcfg, true),
+ DDRCTL_REG_TIMING(odtmap, false),
+};
+
+#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp2_ddrctrl_map, false)
+static const struct stm32mp_ddr_reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
+ DDRCTL_REG_MAP(addrmap0),
+ DDRCTL_REG_MAP(addrmap1),
+ DDRCTL_REG_MAP(addrmap2),
+ DDRCTL_REG_MAP(addrmap3),
+ DDRCTL_REG_MAP(addrmap4),
+ DDRCTL_REG_MAP(addrmap5),
+ DDRCTL_REG_MAP(addrmap6),
+ DDRCTL_REG_MAP(addrmap7),
+ DDRCTL_REG_MAP(addrmap8),
+ DDRCTL_REG_MAP(addrmap9),
+ DDRCTL_REG_MAP(addrmap10),
+ DDRCTL_REG_MAP(addrmap11),
+};
+
+#define DDRCTL_REG_PERF(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_perf, z)
+static const struct stm32mp_ddr_reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
+ DDRCTL_REG_PERF(sched, true),
+ DDRCTL_REG_PERF(sched1, false),
+ DDRCTL_REG_PERF(perfhpr1, true),
+ DDRCTL_REG_PERF(perflpr1, true),
+ DDRCTL_REG_PERF(perfwr1, true),
+ DDRCTL_REG_PERF(sched3, false),
+ DDRCTL_REG_PERF(sched4, false),
+ DDRCTL_REG_PERF(pcfgr_0, false),
+ DDRCTL_REG_PERF(pcfgw_0, false),
+ DDRCTL_REG_PERF(pctrl_0, false),
+ DDRCTL_REG_PERF(pcfgqos0_0, true),
+ DDRCTL_REG_PERF(pcfgqos1_0, true),
+ DDRCTL_REG_PERF(pcfgwqos0_0, true),
+ DDRCTL_REG_PERF(pcfgwqos1_0, true),
+#if STM32MP_DDR_DUAL_AXI_PORT
+ DDRCTL_REG_PERF(pcfgr_1, false),
+ DDRCTL_REG_PERF(pcfgw_1, false),
+ DDRCTL_REG_PERF(pctrl_1, false),
+ DDRCTL_REG_PERF(pcfgqos0_1, true),
+ DDRCTL_REG_PERF(pcfgqos1_1, true),
+ DDRCTL_REG_PERF(pcfgwqos0_1, true),
+ DDRCTL_REG_PERF(pcfgwqos1_1, true),
+#endif /* STM32MP_DDR_DUAL_AXI_PORT */
+};
+
+static const struct stm32mp_ddr_reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {};
+
+static const struct stm32mp_ddr_reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {};
+
+/*
+ * REGISTERS ARRAY: used to parse device tree and interactive mode
+ */
+static const struct stm32mp_ddr_reg_info ddr_registers[REG_TYPE_NB] __unused = {
+ [REG_REG] = {
+ .name = "static",
+ .desc = ddr_reg,
+ .size = DDRCTL_REG_REG_SIZE,
+ .base = DDR_BASE
+ },
+ [REG_TIMING] = {
+ .name = "timing",
+ .desc = ddr_timing,
+ .size = DDRCTL_REG_TIMING_SIZE,
+ .base = DDR_BASE
+ },
+ [REG_PERF] = {
+ .name = "perf",
+ .desc = ddr_perf,
+ .size = DDRCTL_REG_PERF_SIZE,
+ .base = DDR_BASE
+ },
+ [REG_MAP] = {
+ .name = "map",
+ .desc = ddr_map,
+ .size = DDRCTL_REG_MAP_SIZE,
+ .base = DDR_BASE
+ },
+ [REGPHY_REG] = {
+ .name = "static",
+ .desc = ddrphy_reg,
+ .size = DDRPHY_REG_REG_SIZE,
+ .base = DDRPHY_BASE
+ },
+ [REGPHY_TIMING] = {
+ .name = "timing",
+ .desc = ddrphy_timing,
+ .size = DDRPHY_REG_TIMING_SIZE,
+ .base = DDRPHY_BASE
+ },
+};
+
+static void ddr_reset(struct stm32mp_ddr_priv *priv)
+{
+ udelay(DDR_DELAY_1US);
+
+ mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+ mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,
+ RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN |
+ RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
+ mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,
+ RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN |
+ RCC_DDRCAPBCFGR_DDRCAPBRST);
+ mmio_write_32(priv->rcc + RCC_DDRCFGR,
+ RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN | RCC_DDRCFGR_DDRCFGRST);
+
+ udelay(DDR_DELAY_1US);
+
+ mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+ mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,
+ RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN);
+ mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,
+ RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN);
+ mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN);
+
+ udelay(DDR_DELAY_1US);
+}
+
+static void ddr_standby_reset(struct stm32mp_ddr_priv *priv)
+{
+ udelay(DDR_DELAY_1US);
+
+ mmio_write_32(priv->rcc + RCC_DDRCPCFGR,
+ RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPRST);
+ mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+ mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,
+ RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN |
+ RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
+ mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,
+ RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN |
+ RCC_DDRCAPBCFGR_DDRCAPBRST);
+
+ mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);
+ mmio_setbits_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
+
+ udelay(DDR_DELAY_1US);
+}
+
+static void ddr_standby_reset_release(struct stm32mp_ddr_priv *priv)
+{
+ udelay(DDR_DELAY_1US);
+
+ mmio_write_32(priv->rcc + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);
+ mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+ mmio_clrbits_32(priv->rcc + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
+ mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN);
+
+ udelay(DDR_DELAY_1US);
+}
+
+static void ddr_sysconf_configuration(struct stm32mp_ddr_priv *priv,
+ struct stm32mp_ddr_config *config)
+{
+ mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE,
+ DDRDBG_LP_DISABLE_LPI_XPI_DISABLE | DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE);
+
+ mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_BYPASS_PCLKEN,
+ (uint32_t)config->uib.pllbypass);
+
+ mmio_write_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
+ mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+
+ udelay(DDR_DELAY_1US);
+}
+
+static void set_dfi_init_complete_en(struct stm32mp_ddrctl *ctl, bool phy_init_done)
+{
+ /*
+ * Manage quasi-dynamic registers modification
+ * dfimisc.dfi_init_complete_en : Group 3
+ */
+ stm32mp_ddr_set_qd3_update_conditions(ctl);
+
+ udelay(DDR_DELAY_1US);
+
+ if (phy_init_done) {
+ /* Indicates to controller that PHY has completed initialization */
+ mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ } else {
+ /* PHY not initialized yet, wait for completion */
+ mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ }
+
+ udelay(DDR_DELAY_1US);
+
+ stm32mp_ddr_unset_qd3_update_conditions(ctl);
+
+}
+
+static void disable_refresh(struct stm32mp_ddrctl *ctl)
+{
+ mmio_setbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+
+ stm32mp_ddr_wait_refresh_update_done_ack(ctl);
+
+ udelay(DDR_DELAY_1US);
+
+ mmio_clrbits_32((uintptr_t)&ctl->pwrctl,
+ DDRCTRL_PWRCTL_POWERDOWN_EN | DDRCTRL_PWRCTL_SELFREF_EN);
+
+ udelay(DDR_DELAY_1US);
+
+ set_dfi_init_complete_en(ctl, false);
+}
+
+static void restore_refresh(struct stm32mp_ddrctl *ctl, uint32_t rfshctl3, uint32_t pwrctl)
+{
+ if ((rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH) == 0U) {
+ mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+
+ stm32mp_ddr_wait_refresh_update_done_ack(ctl);
+
+ udelay(DDR_DELAY_1US);
+ }
+
+ if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_SW) != 0U) {
+ mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);
+
+ udelay(DDR_DELAY_1US);
+ }
+
+ if ((pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) != 0U) {
+ mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+
+ udelay(DDR_DELAY_1US);
+ }
+
+ if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) != 0U) {
+ mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
+
+ udelay(DDR_DELAY_1US);
+ }
+
+ set_dfi_init_complete_en(ctl, true);
+}
+
+void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv,
+ struct stm32mp_ddr_config *config)
+{
+ int ret = -EINVAL;
+ uint32_t ddr_retdis;
+ enum ddr_type ddr_type;
+
+ if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) {
+ ddr_type = STM32MP_DDR3;
+ } else if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR4) != 0U) {
+ ddr_type = STM32MP_DDR4;
+ } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR4) != 0U) {
+ ddr_type = STM32MP_LPDDR4;
+ } else {
+ ERROR("DDR type not supported\n");
+ panic();
+ }
+
+ VERBOSE("name = %s\n", config->info.name);
+ VERBOSE("speed = %u kHz\n", config->info.speed);
+ VERBOSE("size = 0x%zx\n", config->info.size);
+ if (config->self_refresh) {
+ VERBOSE("sel-refresh exit (zdata = 0x%x)\n", config->zdata);
+ }
+
+ /* Check DDR PHY pads retention */
+ ddr_retdis = mmio_read_32(priv->pwr + PWR_CR11) & PWR_CR11_DDRRETDIS;
+ if (config->self_refresh) {
+ if (ddr_retdis == PWR_CR11_DDRRETDIS) {
+ VERBOSE("self-refresh aborted: no retention\n");
+ config->self_refresh = false;
+ }
+ }
+
+ if (config->self_refresh) {
+ ddr_standby_reset(priv);
+
+ VERBOSE("disable DDR PHY retention\n");
+ mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS);
+
+ udelay(DDR_DELAY_1US);
+
+ mmio_clrbits_32(priv->rcc + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST);
+
+ udelay(DDR_DELAY_1US);
+
+ } else {
+ if (stm32mp_board_ddr_power_init(ddr_type) != 0) {
+ ERROR("DDR power init failed\n");
+ panic();
+ }
+
+ VERBOSE("disable DDR PHY retention\n");
+ mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS);
+
+ ddr_reset(priv);
+
+ ddr_sysconf_configuration(priv, config);
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ /*
+ * Enable PWRCTL.SELFREF_SW to ensure correct setting of PWRCTL.LPDDR4_SR_ALLOWED.
+ * Later disabled in restore_refresh().
+ */
+ config->c_reg.pwrctl |= DDRCTRL_PWRCTL_SELFREF_SW;
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers);
+ stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers);
+ stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers);
+ stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers);
+
+ if (!config->self_refresh) {
+ /* DDR core and PHY reset de-assert */
+ mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+
+ disable_refresh(priv->ctl);
+ }
+
+ if (config->self_refresh) {
+ ddr_standby_reset_release(priv);
+
+ /* Initialize DDR by skipping training and disabling result saving */
+ ret = ddrphy_phyinit_sequence(config, true, false);
+
+ if (ret == 0) {
+ ret = ddrphy_phyinit_restore_sequence();
+ }
+
+ /* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 0 */
+ ddr_wait_lp3_mode(false);
+ } else {
+ /* Initialize DDR including training and result saving */
+ ret = ddrphy_phyinit_sequence(config, false, true);
+ }
+
+ if (ret != 0) {
+ ERROR("DDR PHY init: Error %d\n", ret);
+ panic();
+ }
+
+ ddr_activate_controller(priv->ctl, false);
+
+ if (config->self_refresh) {
+ struct stm32mp_ddrctl *ctl = priv->ctl;
+
+ /* SW self refresh exit prequested */
+ mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);
+
+ if (ddr_sr_exit_loop() != 0) {
+ ERROR("DDR Standby exit error\n");
+ panic();
+ }
+
+ /* Re-enable DFI low-power interface */
+ mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);
+ } else {
+ restore_refresh(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl);
+ }
+
+ stm32mp_ddr_enable_axi_port(priv->ctl);
+}
diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
index e6be9dd..a2a4082 100644
--- a/drivers/st/ddr/stm32mp2_ddr_helpers.c
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c
@@ -4,12 +4,524 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <drivers/delay_timer.h>
+#include <drivers/st/stm32mp2_ddr.h>
+#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp2_ddr_regs.h>
+#include <drivers/st/stm32mp_ddr.h>
+
#include <lib/mmio.h>
#include <platform_def.h>
+/* HW idle period (unit: Multiples of 32 DFI clock cycles) */
+#define HW_IDLE_PERIOD 0x3U
+
+static enum stm32mp2_ddr_sr_mode saved_ddr_sr_mode;
+
+#pragma weak stm32_ddrdbg_get_base
+uintptr_t stm32_ddrdbg_get_base(void)
+{
+ return 0U;
+}
+
+static void set_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl)
+{
+ mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ);
+
+ stm32mp_ddr_set_qd3_update_conditions(ctl);
+}
+
+static void unset_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl)
+{
+ stm32mp_ddr_unset_qd3_update_conditions(ctl);
+
+ mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ);
+}
+
+static void wait_dfi_init_complete(struct stm32mp_ddrctl *ctl)
+{
+ uint64_t timeout;
+ uint32_t dfistat;
+
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ do {
+ dfistat = mmio_read_32((uintptr_t)&ctl->dfistat);
+ VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat);
+
+ if (timeout_elapsed(timeout)) {
+ panic();
+ }
+ } while ((dfistat & DDRCTRL_DFISTAT_DFI_INIT_COMPLETE) == 0U);
+
+ VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat);
+}
+
+static void disable_dfi_low_power_interface(struct stm32mp_ddrctl *ctl)
+{
+ uint64_t timeout;
+ uint32_t dfistat;
+ uint32_t stat;
+
+ mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);
+
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ do {
+ dfistat = mmio_read_32((uintptr_t)&ctl->dfistat);
+ stat = mmio_read_32((uintptr_t)&ctl->stat);
+ VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat);
+ VERBOSE("[0x%lx] stat = 0x%x ", (uintptr_t)&ctl->stat, stat);
+
+ if (timeout_elapsed(timeout)) {
+ panic();
+ }
+ } while (((dfistat & DDRCTRL_DFISTAT_DFI_LP_ACK) != 0U) ||
+ ((stat & DDRCTRL_STAT_OPERATING_MODE_MASK) == DDRCTRL_STAT_OPERATING_MODE_SR));
+
+ VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat);
+ VERBOSE("[0x%lx] stat = 0x%x\n", (uintptr_t)&ctl->stat, stat);
+}
+
+void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry)
+{
+ /*
+ * Manage quasi-dynamic registers modification
+ * dfimisc.dfi_frequency : Group 1
+ * dfimisc.dfi_init_complete_en and dfimisc.dfi_init_start : Group 3
+ */
+ set_qd1_qd3_update_conditions(ctl);
+
+ if (sr_entry) {
+ mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY);
+ } else {
+ mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY);
+ }
+
+ mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START);
+ mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START);
+
+ wait_dfi_init_complete(ctl);
+
+ udelay(DDR_DELAY_1US);
+
+ if (sr_entry) {
+ mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ } else {
+ mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ }
+
+ udelay(DDR_DELAY_1US);
+
+ unset_qd1_qd3_update_conditions(ctl);
+}
+
+#if STM32MP_LPDDR4_TYPE
+static void disable_phy_ddc(void)
+{
+ /* Enable APB access to internal CSR registers */
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, 0U);
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
+ DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN |
+ DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
+
+ /* Disable DRAM drift compensation */
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6, 0xFFFFU);
+
+ /* Disable APB access to internal CSR registers */
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
+ DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL,
+ DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL);
+}
+#endif /* STM32MP_LPDDR4_TYPE */
+
+void ddr_wait_lp3_mode(bool sr_entry)
+{
+ uint64_t timeout;
+ bool repeat_loop = false;
+
+ /* Enable APB access to internal CSR registers */
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, 0U);
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
+ DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN |
+ DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
+
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ do {
+ uint16_t phyinlpx = mmio_read_32(stm32mp_ddrphyc_base() +
+ DDRPHY_INITENG0_P0_PHYINLPX);
+
+ if (timeout_elapsed(timeout)) {
+ panic();
+ }
+
+ if (sr_entry) {
+ repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) == 0U;
+ } else {
+ repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) != 0U;
+ }
+ } while (repeat_loop);
+
+ /* Disable APB access to internal CSR registers */
+#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, 0U);
+#else /* STM32MP_LPDDR4_TYPE */
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
+ DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+ mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL,
+ DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL);
+}
+
+static int sr_loop(bool is_entry)
+{
+ uint32_t type;
+ uint32_t state __maybe_unused;
+ uint64_t timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ bool repeat_loop = false;
+
+ /*
+ * Wait for DDRCTRL to be out of or back to "normal/mission mode".
+ * Consider also SRPD mode for LPDDR4 only.
+ */
+ do {
+ type = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_STAT) &
+ DDRCTRL_STAT_SELFREF_TYPE_MASK;
+#if STM32MP_LPDDR4_TYPE
+ state = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_STAT) &
+ DDRCTRL_STAT_SELFREF_STATE_MASK;
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ if (timeout_elapsed(timeout)) {
+ return -ETIMEDOUT;
+ }
+
+ if (is_entry) {
+#if STM32MP_LPDDR4_TYPE
+ repeat_loop = (type == 0x0U) || (state != DDRCTRL_STAT_SELFREF_STATE_SRPD);
+#else /* !STM32MP_LPDDR4_TYPE */
+ repeat_loop = (type == 0x0U);
+#endif /* STM32MP_LPDDR4_TYPE */
+ } else {
+#if STM32MP_LPDDR4_TYPE
+ repeat_loop = (type != 0x0U) || (state != 0x0U);
+#else /* !STM32MP_LPDDR4_TYPE */
+ repeat_loop = (type != 0x0U);
+#endif /* STM32MP_LPDDR4_TYPE */
+ }
+ } while (repeat_loop);
+
+ return 0;
+}
+
+static int sr_entry_loop(void)
+{
+ return sr_loop(true);
+}
+
+int ddr_sr_exit_loop(void)
+{
+ return sr_loop(false);
+}
+
+static int sr_ssr_set(void)
+{
+ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
+
+ /*
+ * Disable Clock disable with LP modes
+ * (used in RUN mode for LPDDR2 with specific timing).
+ */
+ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
+
+ /* Disable automatic Self-Refresh mode */
+ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_EN);
+
+ mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE,
+ DDRDBG_LP_DISABLE_LPI_XPI_DISABLE | DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE);
+
+ return 0;
+}
+
+static int sr_ssr_entry(bool standby)
+{
+ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ if (stm32mp_ddr_disable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base) != 0) {
+ panic();
+ }
+
+#if STM32MP_LPDDR4_TYPE
+ if (standby) {
+ /* Disable DRAM drift compensation */
+ disable_phy_ddc();
+ }
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ disable_dfi_low_power_interface((struct stm32mp_ddrctl *)ddrctrl_base);
+
+ /* SW self refresh entry prequested */
+ mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
+#if STM32MP_LPDDR4_TYPE
+ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_STAY_IN_SELFREF);
+#endif /* STM32MP_LPDDR4_TYPE */
+
+ if (sr_entry_loop() != 0) {
+ return -1;
+ }
+
+ ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, true);
+
+ /* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 1 */
+ ddr_wait_lp3_mode(true);
+
+ if (standby) {
+ mmio_clrbits_32(stm32mp_pwr_base() + PWR_CR11, PWR_CR11_DDRRETDIS);
+ }
+
+ mmio_clrsetbits_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN,
+ RCC_DDRCPCFGR_DDRCPEN);
+ mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
+ mmio_setbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);
+
+ return 0;
+}
+
+static int sr_ssr_exit(void)
+{
+ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ mmio_setbits_32(rcc_base + RCC_DDRCPCFGR,
+ RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
+ mmio_clrbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);
+ mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
+
+ udelay(DDR_DELAY_1US);
+
+ ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, false);
+
+ /* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 0 */
+ ddr_wait_lp3_mode(false);
+
+ /* SW self refresh exit prequested */
+ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
+
+ if (ddr_sr_exit_loop() != 0) {
+ return -1;
+ }
+
+ /* Re-enable DFI low-power interface */
+ mmio_setbits_32(ddrctrl_base + DDRCTRL_DFILPCFG0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);
+
+ stm32mp_ddr_enable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base);
+
+ return 0;
+}
+
+static int sr_hsr_set(void)
+{
+ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
+
+ mmio_clrsetbits_32(stm32mp_rcc_base() + RCC_DDRITFCFGR,
+ RCC_DDRITFCFGR_DDRCKMOD_MASK, RCC_DDRITFCFGR_DDRCKMOD_HSR);
+
+ /*
+ * manage quasi-dynamic registers modification
+ * hwlpctl.hw_lp_en : Group 2
+ */
+ if (stm32mp_ddr_sw_selfref_entry((struct stm32mp_ddrctl *)ddrctrl_base) != 0) {
+ panic();
+ }
+ stm32mp_ddr_start_sw_done((struct stm32mp_ddrctl *)ddrctrl_base);
+
+ mmio_write_32(ddrctrl_base + DDRCTRL_HWLPCTL,
+ DDRCTRL_HWLPCTL_HW_LP_EN | DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN |
+ (HW_IDLE_PERIOD << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_SHIFT));
+
+ stm32mp_ddr_wait_sw_done_ack((struct stm32mp_ddrctl *)ddrctrl_base);
+ stm32mp_ddr_sw_selfref_exit((struct stm32mp_ddrctl *)ddrctrl_base);
+
+ return 0;
+}
+
+static int sr_hsr_entry(void)
+{
+ mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN);
+
+ return sr_entry_loop(); /* read_data should be equal to 0x223 */
+}
+
+static int sr_hsr_exit(void)
+{
+ mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
+ RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
+
+ /* TODO: check if ddr_sr_exit_loop() is needed here */
+
+ return 0;
+}
+
+static int sr_asr_set(void)
+{
+ mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE, 0U);
+
+ return 0;
+}
+
+static int sr_asr_entry(void)
+{
+ /*
+ * Automatically enter into self refresh when there is no ddr traffic
+ * for the delay programmed into SYSCONF_DDRC_AUTO_SR_DELAY register.
+ * Default value is 0x20 (unit: Multiples of 32 DFI clock cycles).
+ */
+ return sr_entry_loop();
+}
+
+static int sr_asr_exit(void)
+{
+ return ddr_sr_exit_loop();
+}
+
+uint32_t ddr_get_io_calibration_val(void)
+{
+ /* TODO create related service */
+
+ return 0U;
+}
+
+int ddr_sr_entry(bool standby)
+{
+ int ret = -EINVAL;
+
+ switch (saved_ddr_sr_mode) {
+ case DDR_SSR_MODE:
+ ret = sr_ssr_entry(standby);
+ break;
+ case DDR_HSR_MODE:
+ ret = sr_hsr_entry();
+ break;
+ case DDR_ASR_MODE:
+ ret = sr_asr_entry();
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+int ddr_sr_exit(void)
+{
+ int ret = -EINVAL;
+
+ switch (saved_ddr_sr_mode) {
+ case DDR_SSR_MODE:
+ ret = sr_ssr_exit();
+ break;
+ case DDR_HSR_MODE:
+ ret = sr_hsr_exit();
+ break;
+ case DDR_ASR_MODE:
+ ret = sr_asr_exit();
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void)
+{
+ uint32_t pwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL);
+ enum stm32mp2_ddr_sr_mode mode = DDR_SR_MODE_INVALID;
+
+ switch (pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
+ DDRCTRL_PWRCTL_SELFREF_EN)) {
+ case 0U:
+ mode = DDR_SSR_MODE;
+ break;
+ case DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE:
+ mode = DDR_HSR_MODE;
+ break;
+ case DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN:
+ mode = DDR_ASR_MODE;
+ break;
+ default:
+ break;
+ }
+
+ return mode;
+}
+
+void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode)
+{
+ int ret = -EINVAL;
+
+ if (mode == saved_ddr_sr_mode) {
+ return;
+ }
+
+ switch (mode) {
+ case DDR_SSR_MODE:
+ ret = sr_ssr_set();
+ break;
+ case DDR_HSR_MODE:
+ ret = sr_hsr_set();
+ break;
+ case DDR_ASR_MODE:
+ ret = sr_asr_set();
+ break;
+ default:
+ break;
+ }
+
+ if (ret != 0) {
+ ERROR("Unknown Self Refresh mode\n");
+ panic();
+ }
+
+ saved_ddr_sr_mode = mode;
+}
+
+void ddr_save_sr_mode(void)
+{
+ saved_ddr_sr_mode = ddr_read_sr_mode();
+}
+
+void ddr_restore_sr_mode(void)
+{
+ ddr_set_sr_mode(saved_ddr_sr_mode);
+}
+
void ddr_sub_system_clk_init(void)
{
mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);
}
+
+void ddr_sub_system_clk_off(void)
+{
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ /* Clear DDR IO retention */
+ mmio_clrbits_32(stm32mp_pwr_base() + PWR_CR11, PWR_CR11_DDRRETDIS);
+
+ /* Reset DDR sub system */
+ mmio_write_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPRST);
+ mmio_write_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
+ mmio_write_32(rcc_base + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
+ mmio_write_32(rcc_base + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST);
+
+ /* Deactivate clocks and PLL2 */
+ mmio_clrbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
+ mmio_clrbits_32(rcc_base + RCC_PLL2CFGR1, RCC_PLL2CFGR1_PLLEN);
+}
diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c
new file mode 100644
index 0000000..95f05e7
--- /dev/null
+++ b/drivers/st/ddr/stm32mp2_ram.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
+#include <drivers/st/stm32mp2_ddr.h>
+#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp2_ram.h>
+#include <drivers/st/stm32mp_ddr.h>
+#include <drivers/st/stm32mp_ddr_test.h>
+#include <drivers/st/stm32mp_ram.h>
+
+#include <lib/mmio.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+static struct stm32mp_ddr_priv ddr_priv_data;
+static bool ddr_self_refresh;
+
+static int ddr_dt_get_ui_param(void *fdt, int node, struct stm32mp_ddr_config *config)
+{
+ int ret;
+ uint32_t size;
+
+ size = sizeof(struct user_input_basic) / sizeof(int);
+ ret = fdt_read_uint32_array(fdt, node, "st,phy-basic", size, (uint32_t *)&config->uib);
+
+ VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-basic", size, ret);
+ if (ret != 0) {
+ ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-basic", ret);
+ return -EINVAL;
+ }
+
+ size = sizeof(struct user_input_advanced) / sizeof(int);
+ ret = fdt_read_uint32_array(fdt, node, "st,phy-advanced", size, (uint32_t *)&config->uia);
+
+ VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-advanced", size, ret);
+ if (ret != 0) {
+ ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-advanced", ret);
+ return -EINVAL;
+ }
+
+ size = sizeof(struct user_input_mode_register) / sizeof(int);
+ ret = fdt_read_uint32_array(fdt, node, "st,phy-mr", size, (uint32_t *)&config->uim);
+
+ VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-mr", size, ret);
+ if (ret != 0) {
+ ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-mr", ret);
+ return -EINVAL;
+ }
+
+ size = sizeof(struct user_input_swizzle) / sizeof(int);
+ ret = fdt_read_uint32_array(fdt, node, "st,phy-swizzle", size, (uint32_t *)&config->uis);
+
+ VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-swizzle", size, ret);
+ if (ret != 0) {
+ ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-swizzle", ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int stm32mp2_ddr_setup(void)
+{
+ struct stm32mp_ddr_priv *priv = &ddr_priv_data;
+ int ret;
+ struct stm32mp_ddr_config config;
+ int node;
+ uintptr_t uret;
+ void *fdt;
+
+ const struct stm32mp_ddr_param param[] = {
+ CTL_PARAM(reg),
+ CTL_PARAM(timing),
+ CTL_PARAM(map),
+ CTL_PARAM(perf)
+ };
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
+ if (node < 0) {
+ ERROR("%s: can't read DDR node in DT\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = stm32mp_ddr_dt_get_param(fdt, node, param, ARRAY_SIZE(param), (uintptr_t)&config);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = ddr_dt_get_ui_param(fdt, node, &config);
+ if (ret < 0) {
+ return ret;
+ }
+
+ config.self_refresh = false;
+
+ if (stm32mp_is_wakeup_from_standby()) {
+ config.self_refresh = true;
+ }
+
+ /* Map dynamically RETRAM area to save or restore PHY retention registers */
+ if (stm32mp_map_retram() != 0) {
+ panic();
+ }
+
+ stm32mp2_ddr_init(priv, &config);
+
+ /* Unmap RETRAM, no more used until next DDR initialization call */
+ if (stm32mp_unmap_retram() != 0) {
+ panic();
+ }
+
+ priv->info.size = config.info.size;
+
+ VERBOSE("%s : ram size(%lx, %lx)\n", __func__, priv->info.base, priv->info.size);
+
+ if (stm32mp_map_ddr_non_cacheable() != 0) {
+ panic();
+ }
+
+ if (config.self_refresh) {
+ uret = stm32mp_ddr_test_rw_access();
+ if (uret != 0UL) {
+ ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret);
+ panic();
+ }
+
+ /* TODO Restore area overwritten by training */
+ //stm32_restore_ddr_training_area();
+ } else {
+ size_t retsize;
+
+ uret = stm32mp_ddr_test_data_bus();
+ if (uret != 0UL) {
+ ERROR("DDR data bus test: can't access memory @ 0x%lx\n", uret);
+ panic();
+ }
+
+ uret = stm32mp_ddr_test_addr_bus(config.info.size);
+ if (uret != 0UL) {
+ ERROR("DDR addr bus test: can't access memory @ 0x%lx\n", uret);
+ panic();
+ }
+
+ retsize = stm32mp_ddr_check_size();
+ if (retsize < config.info.size) {
+ ERROR("DDR size: 0x%zx does not match DT config: 0x%zx\n",
+ retsize, config.info.size);
+ panic();
+ }
+
+ INFO("Memory size = 0x%zx (%zu MB)\n", retsize, retsize / (1024U * 1024U));
+ }
+
+ /*
+ * Initialization sequence has configured DDR registers with settings.
+ * The Self Refresh (SR) mode corresponding to these settings has now
+ * to be set.
+ */
+ ddr_set_sr_mode(ddr_read_sr_mode());
+
+ if (stm32mp_unmap_ddr() != 0) {
+ panic();
+ }
+
+ /* Save DDR self_refresh state */
+ ddr_self_refresh = config.self_refresh;
+
+ return 0;
+}
+
+bool stm32mp2_ddr_is_restored(void)
+{
+ return ddr_self_refresh;
+}
+
+int stm32mp2_ddr_probe(void)
+{
+ struct stm32mp_ddr_priv *priv = &ddr_priv_data;
+
+ VERBOSE("STM32MP DDR probe\n");
+
+ priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base();
+ priv->phy = (struct stm32mp_ddrphy *)stm32mp_ddrphyc_base();
+ priv->pwr = stm32mp_pwr_base();
+ priv->rcc = stm32mp_rcc_base();
+
+ priv->info.base = STM32MP_DDR_BASE;
+ priv->info.size = 0;
+
+ return stm32mp2_ddr_setup();
+}
diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c
index 6776e3b..98968d5 100644
--- a/drivers/st/ddr/stm32mp_ddr.c
+++ b/drivers/st/ddr/stm32mp_ddr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,13 +8,15 @@
#include <drivers/delay_timer.h>
#include <drivers/st/stm32mp_ddr.h>
#include <drivers/st/stm32mp_ddrctrl_regs.h>
-#include <drivers/st/stm32mp_pmic.h>
#include <lib/mmio.h>
#include <platform_def.h>
#define INVALID_OFFSET 0xFFU
+static bool axi_port_reenable_request;
+static bool host_interface_reenable_request;
+
static uintptr_t get_base_addr(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_base_type base)
{
if (base == DDRPHY_BASE) {
@@ -38,12 +40,23 @@
uintptr_t ptr = base_addr + desc[i].offset;
if (desc[i].par_offset == INVALID_OFFSET) {
- ERROR("invalid parameter offset for %s", desc[i].name);
+ ERROR("invalid parameter offset for %s - index %u",
+ ddr_registers[type].name, i);
panic();
} else {
+#if !STM32MP13 && !STM32MP15
+ if (desc[i].qd) {
+ stm32mp_ddr_start_sw_done(priv->ctl);
+ }
+#endif
value = *((uint32_t *)((uintptr_t)param +
desc[i].par_offset));
mmio_write_32(ptr, value);
+#if !STM32MP13 && !STM32MP15
+ if (desc[i].qd) {
+ stm32mp_ddr_wait_sw_done_ack(priv->ctl);
+ }
+#endif
}
}
}
@@ -66,7 +79,7 @@
VERBOSE("[0x%lx] swctl = 0x%x\n",
(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
- timeout = timeout_init_us(TIMEOUT_US_1S);
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
do {
swstat = mmio_read_32((uintptr_t)&ctl->swstat);
VERBOSE("[0x%lx] swstat = 0x%x ",
@@ -93,14 +106,194 @@
VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,
mmio_read_32((uintptr_t)&ctl->pctrl_1));
#endif
+}
+
+int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl)
+{
+ uint64_t timeout;
+ uint32_t pstat;
+
+ /* Disable uMCTL2 AXI port 0 */
+ mmio_clrbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
+ VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,
+ mmio_read_32((uintptr_t)&ctl->pctrl_0));
+
+#if STM32MP_DDR_DUAL_AXI_PORT
+ /* Disable uMCTL2 AXI port 1 */
+ mmio_clrbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
+ VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,
+ mmio_read_32((uintptr_t)&ctl->pctrl_1));
+#endif
+ /*
+ * Waits until all AXI ports are idle
+ * Poll PSTAT.rd_port_busy_n = 0
+ * Poll PSTAT.wr_port_busy_n = 0
+ */
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ do {
+ pstat = mmio_read_32((uintptr_t)&ctl->pstat);
+ VERBOSE("[0x%lx] pstat = 0x%x ",
+ (uintptr_t)&ctl->pstat, pstat);
+ if (timeout_elapsed(timeout)) {
+ return -1;
+ }
+ } while (pstat != 0U);
+
+ return 0;
+}
+
+static bool ddr_is_axi_port_enabled(struct stm32mp_ddrctl *ctl)
+{
+ return (mmio_read_32((uintptr_t)&ctl->pctrl_0) & DDRCTRL_PCTRL_N_PORT_EN) != 0U;
+}
+
+void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl)
+{
+ mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
+ VERBOSE("[0x%lx] dbg1 = 0x%x\n",
+ (uintptr_t)&ctl->dbg1,
+ mmio_read_32((uintptr_t)&ctl->dbg1));
+}
+
+void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl)
+{
+ uint64_t timeout;
+ uint32_t dbgcam;
+ int count = 0;
+
+ mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
+ VERBOSE("[0x%lx] dbg1 = 0x%x\n",
+ (uintptr_t)&ctl->dbg1,
+ mmio_read_32((uintptr_t)&ctl->dbg1));
+
+ /*
+ * Waits until all queues and pipelines are empty
+ * Poll DBGCAM.dbg_wr_q_empty = 1
+ * Poll DBGCAM.dbg_rd_q_empty = 1
+ * Poll DBGCAM.dbg_wr_data_pipeline_empty = 1
+ * Poll DBGCAM.dbg_rd_data_pipeline_empty = 1
+ *
+ * data_pipeline fields must be polled twice to ensure
+ * value propoagation, so count is added to loop condition.
+ */
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ do {
+ dbgcam = mmio_read_32((uintptr_t)&ctl->dbgcam);
+ VERBOSE("[0x%lx] dbgcam = 0x%x ",
+ (uintptr_t)&ctl->dbgcam, dbgcam);
+ if (timeout_elapsed(timeout)) {
+ panic();
+ }
+ count++;
+ } while (((dbgcam & DDRCTRL_DBG_Q_AND_DATA_PIPELINE_EMPTY) !=
+ DDRCTRL_DBG_Q_AND_DATA_PIPELINE_EMPTY) || (count < 2));
+}
+
+static bool ddr_is_host_interface_enabled(struct stm32mp_ddrctl *ctl)
+{
+ return (mmio_read_32((uintptr_t)&ctl->dbg1) & DDRCTRL_DBG1_DIS_HIF) == 0U;
+}
+
+int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl)
+{
+ uint64_t timeout;
+ uint32_t stat;
+ uint32_t operating_mode;
+ uint32_t selref_type;
+
+ mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);
+ VERBOSE("[0x%lx] pwrctl = 0x%x\n",
+ (uintptr_t)&ctl->pwrctl,
+ mmio_read_32((uintptr_t)&ctl->pwrctl));
+
+ /*
+ * Wait operating mode change in self-refresh mode
+ * with STAT.operating_mode[1:0]==11.
+ * Ensure transition to self-refresh was due to software
+ * by checking also that STAT.selfref_type[1:0]=2.
+ */
+ timeout = timeout_init_us(DDR_TIMEOUT_500US);
+ while (!timeout_elapsed(timeout)) {
+ stat = mmio_read_32((uintptr_t)&ctl->stat);
+ operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
+ selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
+
+ if ((operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) &&
+ (selref_type == DDRCTRL_STAT_SELFREF_TYPE_SR)) {
+ return 0;
+ }
+ }
+
+ return -1;
}
-int stm32mp_board_ddr_power_init(enum ddr_type ddr_type)
+void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl)
{
- if (dt_pmic_status() > 0) {
- return pmic_ddr_power_init(ddr_type);
+ mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);
+ VERBOSE("[0x%lx] pwrctl = 0x%x\n",
+ (uintptr_t)&ctl->pwrctl,
+ mmio_read_32((uintptr_t)&ctl->pwrctl));
+}
+
+void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl)
+{
+ if (ddr_is_axi_port_enabled(ctl)) {
+ if (stm32mp_ddr_disable_axi_port(ctl) != 0) {
+ panic();
+ }
+ axi_port_reenable_request = true;
}
- return 0;
+ if (ddr_is_host_interface_enabled(ctl)) {
+ stm32mp_ddr_disable_host_interface(ctl);
+ host_interface_reenable_request = true;
+ }
+
+ stm32mp_ddr_start_sw_done(ctl);
+}
+
+void stm32mp_ddr_unset_qd3_update_conditions(struct stm32mp_ddrctl *ctl)
+{
+ stm32mp_ddr_wait_sw_done_ack(ctl);
+
+ if (host_interface_reenable_request) {
+ stm32mp_ddr_enable_host_interface(ctl);
+ host_interface_reenable_request = false;
+ }
+
+ if (axi_port_reenable_request) {
+ stm32mp_ddr_enable_axi_port(ctl);
+ axi_port_reenable_request = false;
+ }
+}
+
+void stm32mp_ddr_wait_refresh_update_done_ack(struct stm32mp_ddrctl *ctl)
+{
+ uint64_t timeout;
+ uint32_t rfshctl3;
+ uint32_t refresh_update_level = DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL;
+
+ /* Toggle rfshctl3.refresh_update_level */
+ rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);
+ if ((rfshctl3 & refresh_update_level) == refresh_update_level) {
+ mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
+ } else {
+ mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
+ refresh_update_level = 0U;
+ }
+
+ VERBOSE("[0x%lx] rfshctl3 = 0x%x\n",
+ (uintptr_t)&ctl->rfshctl3, mmio_read_32((uintptr_t)&ctl->rfshctl3));
+
+ timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
+ do {
+ rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);
+ VERBOSE("[0x%lx] rfshctl3 = 0x%x ", (uintptr_t)&ctl->rfshctl3, rfshctl3);
+ if (timeout_elapsed(timeout)) {
+ panic();
+ }
+ } while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) != refresh_update_level);
+
+ VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);
}
diff --git a/drivers/st/ddr/stm32mp_ddr_test.c b/drivers/st/ddr/stm32mp_ddr_test.c
index 0f6aff1..707a6ff 100644
--- a/drivers/st/ddr/stm32mp_ddr_test.c
+++ b/drivers/st/ddr/stm32mp_ddr_test.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,8 +10,31 @@
#include <platform_def.h>
+#ifdef __aarch64__
+#define DDR_PATTERN 0xAAAAAAAAAAAAAAAAUL
+#define DDR_ANTIPATTERN 0x5555555555555555UL
+#else /* !__aarch64__ */
#define DDR_PATTERN 0xAAAAAAAAU
#define DDR_ANTIPATTERN 0x55555555U
+#endif /* __aarch64__ */
+
+static void mmio_write_pattern(uintptr_t addr, u_register_t value)
+{
+#ifdef __aarch64__
+ mmio_write_64(addr, (uint64_t)value);
+#else /* !__aarch64__ */
+ mmio_write_32(addr, (uint32_t)value);
+#endif /* __aarch64__ */
+}
+
+static u_register_t mmio_read_pattern(uintptr_t addr)
+{
+#ifdef __aarch64__
+ return (u_register_t)mmio_read_64(addr);
+#else /* !__aarch64__ */
+ return (u_register_t)mmio_read_32(addr);
+#endif /* __aarch64__ */
+}
/*******************************************************************************
* This function tests a simple read/write access to the DDR.
@@ -20,15 +43,15 @@
******************************************************************************/
uintptr_t stm32mp_ddr_test_rw_access(void)
{
- uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE);
+ u_register_t saved_value = mmio_read_pattern(STM32MP_DDR_BASE);
- mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE, DDR_PATTERN);
- if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) {
return STM32MP_DDR_BASE;
}
- mmio_write_32(STM32MP_DDR_BASE, saved_value);
+ mmio_write_pattern(STM32MP_DDR_BASE, saved_value);
return 0UL;
}
@@ -43,12 +66,12 @@
******************************************************************************/
uintptr_t stm32mp_ddr_test_data_bus(void)
{
- uint32_t pattern;
+ u_register_t pattern;
for (pattern = 1U; pattern != 0U; pattern <<= 1U) {
- mmio_write_32(STM32MP_DDR_BASE, pattern);
+ mmio_write_pattern(STM32MP_DDR_BASE, pattern);
- if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != pattern) {
return STM32MP_DDR_BASE;
}
}
@@ -72,41 +95,41 @@
size_t testoffset = 0U;
/* Write the default pattern at each of the power-of-two offsets. */
- for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
+ for (offset = sizeof(u_register_t); (offset & addressmask) != 0U;
offset <<= 1U) {
- mmio_write_32(STM32MP_DDR_BASE + offset, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + offset, DDR_PATTERN);
}
/* Check for address bits stuck high. */
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
- for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
+ for (offset = sizeof(u_register_t); (offset & addressmask) != 0U;
offset <<= 1U) {
- if (mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE + offset) != DDR_PATTERN) {
return STM32MP_DDR_BASE + offset;
}
}
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
/* Check for address bits stuck low or shorted. */
- for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
+ for (testoffset = sizeof(u_register_t); (testoffset & addressmask) != 0U;
testoffset <<= 1U) {
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
- if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) {
return STM32MP_DDR_BASE;
}
- for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
- offset <<= 1) {
- if ((mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) &&
+ for (offset = sizeof(u_register_t); (offset & addressmask) != 0U;
+ offset <<= 1U) {
+ if ((mmio_read_pattern(STM32MP_DDR_BASE + offset) != DDR_PATTERN) &&
(offset != testoffset)) {
return STM32MP_DDR_BASE + offset;
}
}
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
}
return 0UL;
@@ -121,15 +144,15 @@
******************************************************************************/
size_t stm32mp_ddr_check_size(void)
{
- size_t offset = sizeof(uint32_t);
+ size_t offset = sizeof(u_register_t);
- mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE, DDR_PATTERN);
while (offset < STM32MP_DDR_MAX_SIZE) {
- mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
dsb();
- if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) {
break;
}
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 1e16287..58f97b3 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -216,120 +216,6 @@
}
#endif
-int pmic_ddr_power_init(enum ddr_type ddr_type)
-{
- int status;
- uint16_t buck3_min_mv;
- struct rdev *buck2, *buck3, *vref;
- struct rdev *ldo3 __unused;
-
- buck2 = regulator_get_by_name("buck2");
- if (buck2 == NULL) {
- return -ENOENT;
- }
-
-#if STM32MP15
- ldo3 = regulator_get_by_name("ldo3");
- if (ldo3 == NULL) {
- return -ENOENT;
- }
-#endif
-
- vref = regulator_get_by_name("vref_ddr");
- if (vref == NULL) {
- return -ENOENT;
- }
-
- switch (ddr_type) {
- case STM32MP_DDR3:
-#if STM32MP15
- status = regulator_set_flag(ldo3, REGUL_SINK_SOURCE);
- if (status != 0) {
- return status;
- }
-#endif
-
- status = regulator_set_min_voltage(buck2);
- if (status != 0) {
- return status;
- }
-
- status = regulator_enable(buck2);
- if (status != 0) {
- return status;
- }
-
- status = regulator_enable(vref);
- if (status != 0) {
- return status;
- }
-
-#if STM32MP15
- status = regulator_enable(ldo3);
- if (status != 0) {
- return status;
- }
-#endif
- break;
-
- case STM32MP_LPDDR2:
- case STM32MP_LPDDR3:
- /*
- * Set LDO3 to 1.8V
- * Set LDO3 to bypass mode if BUCK3 = 1.8V
- * Set LDO3 to normal mode if BUCK3 != 1.8V
- */
- buck3 = regulator_get_by_name("buck3");
- if (buck3 == NULL) {
- return -ENOENT;
- }
-
- regulator_get_range(buck3, &buck3_min_mv, NULL);
-
-#if STM32MP15
- if (buck3_min_mv != 1800) {
- status = regulator_set_min_voltage(ldo3);
- if (status != 0) {
- return status;
- }
- } else {
- status = regulator_set_flag(ldo3, REGUL_ENABLE_BYPASS);
- if (status != 0) {
- return status;
- }
- }
-#endif
-
- status = regulator_set_min_voltage(buck2);
- if (status != 0) {
- return status;
- }
-
-#if STM32MP15
- status = regulator_enable(ldo3);
- if (status != 0) {
- return status;
- }
-#endif
-
- status = regulator_enable(buck2);
- if (status != 0) {
- return status;
- }
-
- status = regulator_enable(vref);
- if (status != 0) {
- return status;
- }
- break;
-
- default:
- break;
- };
-
- return 0;
-}
-
int pmic_voltages_init(void)
{
#if STM32MP13
diff --git a/drivers/st/pmic/stm32mp_pmic2.c b/drivers/st/pmic/stm32mp_pmic2.c
new file mode 100644
index 0000000..c19d36a
--- /dev/null
+++ b/drivers/st/pmic/stm32mp_pmic2.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/regulator.h>
+#include <drivers/st/stm32_i2c.h>
+#include <drivers/st/stm32mp_pmic2.h>
+#include <drivers/st/stpmic2.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+#include <lib/utils_def.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#define PMIC_NODE_NOT_FOUND 1
+
+struct regul_handle_s {
+ const uint32_t id;
+ uint16_t bypass_mv;
+};
+
+static struct pmic_handle_s pmic2_handle;
+static struct i2c_handle_s i2c_handle;
+
+/* This driver is monoinstance */
+static struct pmic_handle_s *pmic2;
+
+static int dt_get_pmic_node(void *fdt)
+{
+ static int node = -FDT_ERR_BADOFFSET;
+
+ if (node == -FDT_ERR_BADOFFSET) {
+ node = fdt_node_offset_by_compatible(fdt, -1, "st,stpmic2");
+ }
+
+ return node;
+}
+
+int dt_pmic_status(void)
+{
+ static int status = -FDT_ERR_BADVALUE;
+ int node;
+ void *fdt;
+
+ if (status != -FDT_ERR_BADVALUE) {
+ return status;
+ }
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = dt_get_pmic_node(fdt);
+ if (node <= 0) {
+ status = -FDT_ERR_NOTFOUND;
+
+ return status;
+ }
+
+ status = DT_SECURE;
+
+ return status;
+}
+
+/*
+ * Get PMIC and its I2C bus configuration from the device tree.
+ * Return 0 on success, negative on error, 1 if no PMIC node is defined.
+ */
+static int dt_pmic2_i2c_config(struct dt_node_info *i2c_info,
+ struct stm32_i2c_init_s *init,
+ uint32_t *i2c_addr)
+{
+ static int i2c_node = -FDT_ERR_NOTFOUND;
+ void *fdt;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ if (i2c_node == -FDT_ERR_NOTFOUND) {
+ int pmic_node;
+ const fdt32_t *cuint;
+
+ pmic_node = dt_get_pmic_node(fdt);
+ if (pmic_node < 0) {
+ return PMIC_NODE_NOT_FOUND;
+ }
+
+ cuint = fdt_getprop(fdt, pmic_node, "reg", NULL);
+ if (cuint == NULL) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ *i2c_addr = fdt32_to_cpu(*cuint) << 1;
+ if (*i2c_addr > UINT16_MAX) {
+ return -FDT_ERR_BADVALUE;
+ }
+
+ i2c_node = fdt_parent_offset(fdt, pmic_node);
+ if (i2c_node < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+ }
+
+ dt_fill_device_info(i2c_info, i2c_node);
+ if (i2c_info->base == 0U) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ i2c_info->status = DT_SECURE;
+
+ return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init);
+}
+
+bool initialize_pmic_i2c(void)
+{
+ int ret;
+ struct dt_node_info i2c_info;
+ struct i2c_handle_s *i2c = &i2c_handle;
+ uint32_t i2c_addr = 0U;
+ struct stm32_i2c_init_s i2c_init;
+
+ ret = dt_pmic2_i2c_config(&i2c_info, &i2c_init, &i2c_addr);
+ if (ret < 0) {
+ ERROR("I2C configuration failed %d\n", ret);
+ panic();
+ }
+
+ if (ret != 0) {
+ return false;
+ }
+
+ /* Initialize PMIC I2C */
+ i2c->i2c_base_addr = i2c_info.base;
+ i2c->dt_status = i2c_info.status;
+ i2c->clock = i2c_info.clock;
+ i2c->i2c_state = I2C_STATE_RESET;
+ i2c_init.own_address1 = i2c_addr;
+ i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
+ i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
+ i2c_init.own_address2 = 0;
+ i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK;
+ i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE;
+ i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE;
+ i2c_init.analog_filter = 1;
+ i2c_init.digital_filter_coef = 0;
+
+ ret = stm32_i2c_init(i2c, &i2c_init);
+ if (ret != 0) {
+ ERROR("Cannot initialize I2C %x (%d)\n",
+ i2c->i2c_base_addr, ret);
+ panic();
+ }
+
+ if (!stm32_i2c_is_device_ready(i2c, i2c_addr, 1,
+ I2C_TIMEOUT_BUSY_MS)) {
+ ERROR("I2C device not ready\n");
+ panic();
+ }
+
+ pmic2 = &pmic2_handle;
+ pmic2->i2c_handle = &i2c_handle;
+ pmic2->i2c_addr = i2c_addr;
+
+ return true;
+}
+
+static int pmic2_set_state(const struct regul_description *desc, bool enable)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: set state to %d\n", desc->node_name, enable);
+
+ return stpmic2_regulator_set_state(pmic2, regul->id, enable);
+}
+
+static int pmic2_get_state(const struct regul_description *desc)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ bool enabled;
+
+ VERBOSE("%s: get state\n", desc->node_name);
+
+ if (stpmic2_regulator_get_state(pmic2, regul->id, &enabled) < 0) {
+ panic();
+ }
+
+ return enabled;
+}
+
+static int pmic2_get_voltage(const struct regul_description *desc)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ uint16_t mv;
+
+ VERBOSE("%s: get volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ /* If the regul is in bypass mode, return bypass value */
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (ret == 1) {
+ return regul->bypass_mv;
+ }
+ };
+
+ if (stpmic2_regulator_get_voltage(pmic2, regul->id, &mv) < 0) {
+ panic();
+ }
+
+ return mv;
+}
+
+static int pmic2_set_voltage(const struct regul_description *desc, uint16_t mv)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: set volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ /* If the regul is in bypass mode, authorize bypass mV */
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if ((ret == 1) && (mv != regul->bypass_mv)) {
+ return -EPERM;
+ }
+ };
+
+ return stpmic2_regulator_set_voltage(pmic2, regul->id, mv);
+}
+
+static int pmic2_list_voltages(const struct regul_description *desc,
+ const uint16_t **levels, size_t *count)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: list volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* bypass is enabled, return a list with only bypass mV */
+ if (ret == 1) {
+ if (count != NULL) {
+ *count = 1U;
+ }
+ if (levels != NULL) {
+ *levels = ®ul->bypass_mv;
+ }
+ return 0;
+ }
+ };
+
+ return stpmic2_regulator_levels_mv(pmic2, regul->id, levels, count);
+}
+
+static int pmic2_set_flag(const struct regul_description *desc, uint16_t flag)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ uint32_t id = regul->id;
+ int ret = -EPERM;
+
+ VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag);
+
+ switch (flag) {
+ case REGUL_PULL_DOWN:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_PULL_DOWN, 1U);
+ break;
+ case REGUL_OCP:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_OCP, 1U);
+ break;
+ case REGUL_SINK_SOURCE:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_SINK_SOURCE, 1U);
+ break;
+ case REGUL_ENABLE_BYPASS:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_BYPASS, 1U);
+ break;
+ case REGUL_MASK_RESET:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_MASK_RESET, 1U);
+ break;
+ default:
+ ERROR("Invalid flag %u", flag);
+ panic();
+ }
+
+ if (ret != 0) {
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+int stpmic2_set_prop(const struct regul_description *desc, uint16_t prop, uint32_t value)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ int ret;
+
+ VERBOSE("%s: set_prop 0x%x val=%u\n", desc->node_name, prop, value);
+
+ ret = stpmic2_regulator_set_prop(pmic2, regul->id, prop, value);
+ if (ret != 0)
+ return -EPERM;
+
+ return 0;
+}
+
+static struct regul_ops pmic2_ops = {
+ .set_state = pmic2_set_state,
+ .get_state = pmic2_get_state,
+ .set_voltage = pmic2_set_voltage,
+ .get_voltage = pmic2_get_voltage,
+ .list_voltages = pmic2_list_voltages,
+ .set_flag = pmic2_set_flag,
+};
+
+#define DEFINE_PMIC_REGUL_HANDLE(rid) \
+[(rid)] = { \
+ .id = (rid), \
+}
+
+static struct regul_handle_s pmic2_regul_handles[STPMIC2_NB_REG] = {
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK1),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK2),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK3),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK4),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK5),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK6),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK7),
+
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO1),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO2),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO3),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO4),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO5),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO6),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO7),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO8),
+
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_REFDDR),
+};
+
+#define DEFINE_REGUL(rid, name) \
+[rid] = { \
+ .node_name = name, \
+ .ops = &pmic2_ops, \
+ .driver_data = &pmic2_regul_handles[rid], \
+}
+
+static const struct regul_description pmic2_descs[STPMIC2_NB_REG] = {
+ DEFINE_REGUL(STPMIC2_BUCK1, "buck1"),
+ DEFINE_REGUL(STPMIC2_BUCK2, "buck2"),
+ DEFINE_REGUL(STPMIC2_BUCK3, "buck3"),
+ DEFINE_REGUL(STPMIC2_BUCK4, "buck4"),
+ DEFINE_REGUL(STPMIC2_BUCK5, "buck5"),
+ DEFINE_REGUL(STPMIC2_BUCK6, "buck6"),
+ DEFINE_REGUL(STPMIC2_BUCK7, "buck7"),
+
+ DEFINE_REGUL(STPMIC2_LDO1, "ldo1"),
+ DEFINE_REGUL(STPMIC2_LDO2, "ldo2"),
+ DEFINE_REGUL(STPMIC2_LDO3, "ldo3"),
+ DEFINE_REGUL(STPMIC2_LDO4, "ldo4"),
+ DEFINE_REGUL(STPMIC2_LDO5, "ldo5"),
+ DEFINE_REGUL(STPMIC2_LDO6, "ldo6"),
+ DEFINE_REGUL(STPMIC2_LDO7, "ldo7"),
+ DEFINE_REGUL(STPMIC2_LDO8, "ldo8"),
+
+ DEFINE_REGUL(STPMIC2_REFDDR, "refddr"),
+};
+
+static int register_pmic2(void)
+{
+ void *fdt;
+ int pmic_node, regulators_node, subnode;
+
+ VERBOSE("Register pmic2\n");
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ pmic_node = dt_get_pmic_node(fdt);
+ if (pmic_node < 0) {
+ return pmic_node;
+ }
+
+ regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators");
+ if (regulators_node < 0) {
+ return -ENOENT;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, regulators_node) {
+ const char *reg_name = fdt_get_name(fdt, subnode, NULL);
+ const struct regul_description *desc;
+ unsigned int i;
+ int ret;
+ const fdt32_t *cuint;
+
+ for (i = 0; i < STPMIC2_NB_REG; i++) {
+ desc = &pmic2_descs[i];
+ if (strcmp(desc->node_name, reg_name) == 0) {
+ break;
+ }
+ }
+ assert(i < STPMIC2_NB_REG);
+
+ ret = regulator_register(desc, subnode);
+ if (ret != 0) {
+ WARN("%s:%d failed to register %s\n", __func__,
+ __LINE__, reg_name);
+ return ret;
+ }
+
+ cuint = fdt_getprop(fdt, subnode, "st,regulator-bypass-microvolt", NULL);
+ if (cuint != NULL) {
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ regul->bypass_mv = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U);
+ VERBOSE("%s: bypass voltage=%umV\n", desc->node_name,
+ regul->bypass_mv);
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,mask-reset", NULL) != NULL) {
+ VERBOSE("%s: set mask-reset\n", desc->node_name);
+ ret = pmic2_set_flag(desc, REGUL_MASK_RESET);
+ if (ret != 0) {
+ ERROR("set mask-reset failed\n");
+ return ret;
+ }
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,regulator-sink-source", NULL) != NULL) {
+ VERBOSE("%s: set regulator-sink-source\n", desc->node_name);
+ ret = pmic2_set_flag(desc, REGUL_SINK_SOURCE);
+ if (ret != 0) {
+ ERROR("set regulator-sink-source failed\n");
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+void initialize_pmic(void)
+{
+ int ret;
+ uint8_t val;
+
+ ret = initialize_pmic_i2c();
+ if (!ret) {
+ VERBOSE("No PMIC2\n");
+ return;
+ }
+
+ if (stpmic2_get_version(pmic2, &val) != 0) {
+ ERROR("Failed to access PMIC\n");
+ panic();
+ }
+ INFO("PMIC2 version = 0x%02x\n", val);
+
+ if (stpmic2_get_product_id(pmic2, &val) != 0) {
+ ERROR("Failed to access PMIC\n");
+ panic();
+ }
+ INFO("PMIC2 product ID = 0x%02x\n", val);
+
+ ret = register_pmic2();
+ if (ret < 0) {
+ ERROR("Register pmic2 failed\n");
+ panic();
+ }
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+ stpmic2_dump_regulators(pmic2);
+#endif
+}
diff --git a/drivers/st/pmic/stpmic2.c b/drivers/st/pmic/stpmic2.c
new file mode 100644
index 0000000..05a80ec
--- /dev/null
+++ b/drivers/st/pmic/stpmic2.c
@@ -0,0 +1,474 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/st/stpmic2.h>
+
+#define RET_SUCCESS 0
+#define RET_ERROR_NOT_SUPPORTED -1
+#define RET_ERROR_GENERIC -2
+#define RET_ERROR_BAD_PARAMETERS -3
+
+#define I2C_TIMEOUT_MS 25
+
+#define VOLTAGE_INDEX_INVALID ((size_t)~0U)
+
+struct regul_struct {
+ const char *name;
+ const uint16_t *volt_table;
+ uint8_t volt_table_size;
+ uint8_t volt_cr;
+ uint8_t volt_shift;
+ uint8_t en_cr;
+ uint8_t alt_en_cr;
+ uint8_t msrt_reg;
+ uint8_t msrt_mask;
+ uint8_t pd_reg;
+ uint8_t pd_val;
+ uint8_t ocp_reg;
+ uint8_t ocp_mask;
+};
+
+/* Voltage tables in mV */
+static const uint16_t buck1236_volt_table[] = {
+ 500U, 510U, 520U, 530U, 540U, 550U, 560U, 570U, 580U, 590U,
+ 600U, 610U, 620U, 630U, 640U, 650U, 660U, 670U, 680U, 690U,
+ 700U, 710U, 720U, 730U, 740U, 750U, 760U, 770U, 780U, 790U,
+ 800U, 810U, 820U, 830U, 840U, 850U, 860U, 870U, 880U, 890U,
+ 900U, 910U, 920U, 930U, 940U, 950U, 960U, 970U, 980U, 990U,
+ 1000U, 1010U, 1020U, 1030U, 1040U, 1050U, 1060U, 1070U, 1080U, 1090U,
+ 1100U, 1110U, 1120U, 1130U, 1140U, 1150U, 1160U, 1170U, 1180U, 1190U,
+ 1200U, 1210U, 1220U, 1230U, 1240U, 1250U, 1260U, 1270U, 1280U, 1290U,
+ 1300U, 1310U, 1320U, 1330U, 1340U, 1350U, 1360U, 1370U, 1380U, 1390U,
+ 1400U, 1410U, 1420U, 1430U, 1440U, 1450U, 1460U, 1470U, 1480U, 1490U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U
+};
+
+static const uint16_t buck457_volt_table[] = {
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1600U, 1700U, 1800U, 1900U, 2000U, 2100U, 2200U, 2300U, 2400U,
+ 2500U, 2600U, 2700U, 2800U, 2900U, 3000U, 3100U, 3200U, 3300U, 3400U,
+ 3500U, 3600U, 3700U, 3800U, 3900U, 4000U, 4100U, 4200U
+};
+
+static const uint16_t ldo235678_volt_table[] = {
+ 900U, 1000U, 1100U, 1200U, 1300U, 1400U, 1500U, 1600U, 1700U, 1800U,
+ 1900U, 2000U, 2100U, 2200U, 2300U, 2400U, 2500U, 2600U, 2700U, 2800U,
+ 2900U, 3000U, 3100U, 3200U, 3300U, 3400U, 3500U, 3600U, 3700U, 3800U,
+ 3900U, 4000U
+};
+
+static const uint16_t ldo1_volt_table[] = {
+ 1800U,
+};
+
+static const uint16_t ldo4_volt_table[] = {
+ 3300U,
+};
+
+static const uint16_t refddr_volt_table[] = {
+ 0,
+};
+
+#define DEFINE_BUCK(regu_name, ID, pd, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .en_cr = ID ## _MAIN_CR2, \
+ .volt_cr = ID ## _MAIN_CR1, \
+ .alt_en_cr = ID ## _ALT_CR2, \
+ .msrt_reg = BUCKS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = pd, \
+ .pd_val = ID ## _PD_FAST, \
+ .ocp_reg = FS_OCP_CR1, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+#define DEFINE_LDOx(regu_name, ID, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .volt_shift = LDO_VOLT_SHIFT, \
+ .en_cr = ID ## _MAIN_CR, \
+ .volt_cr = ID ## _MAIN_CR, \
+ .alt_en_cr = ID ## _ALT_CR, \
+ .msrt_reg = LDOS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = LDOS_PD_CR1, \
+ .pd_val = ID ## _PD, \
+ .ocp_reg = FS_OCP_CR2, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+#define DEFINE_REFDDR(regu_name, ID, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .en_cr = ID ## _MAIN_CR, \
+ .volt_cr = ID ## _MAIN_CR, \
+ .alt_en_cr = ID ## _ALT_CR, \
+ .msrt_reg = BUCKS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = LDOS_PD_CR2, \
+ .pd_val = ID ## _PD, \
+ .ocp_reg = FS_OCP_CR1, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+/* Table of Regulators in PMIC SoC */
+static const struct regul_struct regul_table[STPMIC2_NB_REG] = {
+ [STPMIC2_BUCK1] = DEFINE_BUCK("buck1", BUCK1, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK2] = DEFINE_BUCK("buck2", BUCK2, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK3] = DEFINE_BUCK("buck3", BUCK3, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK4] = DEFINE_BUCK("buck4", BUCK4, BUCKS_PD_CR1,
+ buck457_volt_table),
+ [STPMIC2_BUCK5] = DEFINE_BUCK("buck5", BUCK5, BUCKS_PD_CR2,
+ buck457_volt_table),
+ [STPMIC2_BUCK6] = DEFINE_BUCK("buck6", BUCK6, BUCKS_PD_CR2,
+ buck1236_volt_table),
+ [STPMIC2_BUCK7] = DEFINE_BUCK("buck7", BUCK7, BUCKS_PD_CR2,
+ buck457_volt_table),
+
+ [STPMIC2_REFDDR] = DEFINE_REFDDR("refddr", REFDDR, refddr_volt_table),
+
+ [STPMIC2_LDO1] = DEFINE_LDOx("ldo1", LDO1, ldo1_volt_table),
+ [STPMIC2_LDO2] = DEFINE_LDOx("ldo2", LDO2, ldo235678_volt_table),
+ [STPMIC2_LDO3] = DEFINE_LDOx("ldo3", LDO3, ldo235678_volt_table),
+ [STPMIC2_LDO4] = DEFINE_LDOx("ldo4", LDO4, ldo4_volt_table),
+ [STPMIC2_LDO5] = DEFINE_LDOx("ldo5", LDO5, ldo235678_volt_table),
+ [STPMIC2_LDO6] = DEFINE_LDOx("ldo6", LDO6, ldo235678_volt_table),
+ [STPMIC2_LDO7] = DEFINE_LDOx("ldo7", LDO7, ldo235678_volt_table),
+ [STPMIC2_LDO8] = DEFINE_LDOx("ldo8", LDO8, ldo235678_volt_table),
+
+};
+
+int stpmic2_register_read(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t *value)
+{
+ int ret = stm32_i2c_mem_read(pmic->i2c_handle,
+ pmic->i2c_addr,
+ (uint16_t)register_id,
+ I2C_MEMADD_SIZE_8BIT, value,
+ 1, I2C_TIMEOUT_MS);
+ if (ret != 0) {
+ ERROR("Failed to read reg:0x%x\n", register_id);
+ }
+
+ return ret;
+}
+
+int stpmic2_register_write(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value)
+{
+ uint8_t val = value;
+ int ret = stm32_i2c_mem_write(pmic->i2c_handle,
+ pmic->i2c_addr,
+ (uint16_t)register_id,
+ I2C_MEMADD_SIZE_8BIT, &val,
+ 1, I2C_TIMEOUT_MS);
+ if (ret != 0) {
+ ERROR("Failed to write reg:0x%x\n", register_id);
+ }
+
+ return ret;
+}
+
+int stpmic2_register_update(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value, uint8_t mask)
+{
+ int status;
+ uint8_t val = 0U;
+
+ status = stpmic2_register_read(pmic, register_id, &val);
+ if (status != 0) {
+ return status;
+ }
+
+ val = (val & ((uint8_t)~mask)) | (value & mask);
+
+ VERBOSE("REG:0x%x v=0x%x mask=0x%x -> 0x%x\n",
+ register_id, value, mask, val);
+
+ return stpmic2_register_write(pmic, register_id, val);
+}
+
+int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool enable)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (enable) {
+ return stpmic2_register_update(pmic, regul->en_cr, 1U, 1U);
+ } else {
+ return stpmic2_register_update(pmic, regul->en_cr, 0, 1U);
+ }
+}
+
+int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool *enabled)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t val;
+
+ if (stpmic2_register_read(pmic, regul->en_cr, &val) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ *enabled = (val & 1U) == 1U;
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
+ uint8_t id, const uint16_t **levels,
+ size_t *levels_count)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (regul == NULL) {
+ return RET_ERROR_BAD_PARAMETERS;
+ }
+
+ if (levels_count != NULL) {
+ *levels_count = regul->volt_table_size;
+ }
+ if (levels != NULL) {
+ *levels = regul->volt_table;
+ }
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t *val)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t value = 0U;
+ uint8_t mask;
+
+ if (regul->volt_table_size == 0U) {
+ return RET_ERROR_GENERIC;
+ }
+
+ mask = regul->volt_table_size - 1U;
+ if (mask != 0U) {
+ if (stpmic2_register_read(pmic, regul->volt_cr, &value) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ value = (value >> regul->volt_shift) & mask;
+ }
+
+ if (value > regul->volt_table_size) {
+ return RET_ERROR_GENERIC;
+ }
+
+ *val = regul->volt_table[value];
+
+ return RET_SUCCESS;
+}
+
+static size_t voltage_to_index(const struct regul_struct *regul,
+ uint16_t millivolts)
+{
+ unsigned int i;
+
+ assert(regul->volt_table);
+ for (i = 0U; i < regul->volt_table_size; i++) {
+ if (regul->volt_table[i] == millivolts) {
+ return i;
+ }
+ }
+
+ return VOLTAGE_INDEX_INVALID;
+}
+
+int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t millivolts)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ size_t index;
+ uint8_t mask;
+
+ if (!regul->volt_table_size) {
+ return RET_SUCCESS;
+ }
+
+ mask = regul->volt_table_size - 1U;
+
+ index = voltage_to_index(regul, millivolts);
+ if (index == VOLTAGE_INDEX_INVALID) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return stpmic2_register_update(pmic, regul->volt_cr,
+ index << regul->volt_shift,
+ mask << regul->volt_shift);
+}
+
+/* update both normal and alternate register */
+static int stpmic2_update_en_crs(struct pmic_handle_s *pmic, uint8_t id,
+ uint8_t value, uint8_t mask)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (stpmic2_register_update(pmic, regul->en_cr, value, mask) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ if (stpmic2_register_update(pmic, regul->alt_en_cr, value, mask) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t val;
+
+ VERBOSE("%s: get prop 0x%x\n", regul->name, prop);
+
+ switch (prop) {
+ case STPMIC2_BYPASS:
+ if ((id <= STPMIC2_BUCK7) || (id == STPMIC2_LDO1) ||
+ (id == STPMIC2_LDO4) || (id == STPMIC2_REFDDR)) {
+ return 0;
+ }
+
+ if (stpmic2_register_read(pmic, regul->en_cr, &val) != 0) {
+ return -EIO;
+ }
+
+ if ((val & LDO_BYPASS) != 0) {
+ return 1;
+ }
+
+ break;
+ default:
+ ERROR("Invalid prop %u\n", prop);
+ panic();
+ }
+
+ return 0;
+}
+
+int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop, uint32_t arg)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ VERBOSE("%s: set prop 0x%x arg=%u\n", regul->name, prop, arg);
+
+ switch (prop) {
+ case STPMIC2_PULL_DOWN:
+ return stpmic2_register_update(pmic, regul->pd_reg,
+ regul->pd_val,
+ regul->pd_val);
+ case STPMIC2_MASK_RESET:
+ if (!regul->msrt_mask) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+ /* enable mask reset */
+ return stpmic2_register_update(pmic, regul->msrt_reg,
+ regul->msrt_mask,
+ regul->msrt_mask);
+ case STPMIC2_BYPASS:
+ if ((id <= STPMIC2_BUCK7) || (id == STPMIC2_LDO1) ||
+ (id == STPMIC2_LDO4) || (id == STPMIC2_REFDDR)) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+
+ /* clear sink source mode */
+ if ((id == STPMIC2_LDO3) && (arg != 0U)) {
+ if (stpmic2_update_en_crs(pmic, id, 0, LDO3_SNK_SRC) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+ }
+
+ /* enable bypass mode */
+ return stpmic2_update_en_crs(pmic, id,
+ (arg != 0U) ? LDO_BYPASS : 0,
+ LDO_BYPASS);
+ case STPMIC2_SINK_SOURCE:
+ if (id != STPMIC2_LDO3) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+
+ /* clear bypass mode */
+ if (stpmic2_update_en_crs(pmic, id, 0, LDO_BYPASS) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return stpmic2_update_en_crs(pmic, id, LDO3_SNK_SRC,
+ LDO3_SNK_SRC);
+ case STPMIC2_OCP:
+ return stpmic2_register_update(pmic, regul->ocp_reg,
+ regul->ocp_mask,
+ regul->ocp_mask);
+ default:
+ ERROR("Invalid prop %u\n", prop);
+ panic();
+ }
+
+ return -EPERM;
+}
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+void stpmic2_dump_regulators(struct pmic_handle_s *pmic)
+{
+ size_t i;
+ char const *name;
+
+ for (i = 0U; i < ARRAY_SIZE(regul_table); i++) {
+ uint16_t val;
+ bool state;
+
+ if (!regul_table[i].volt_cr) {
+ continue;
+ }
+
+ stpmic2_regulator_get_voltage(pmic, i, &val);
+ stpmic2_regulator_get_state(pmic, i, &state);
+
+ name = regul_table[i].name;
+
+ VERBOSE("PMIC regul %s: %s, %dmV\n",
+ name, state ? "EN" : "DIS", val);
+ }
+}
+#endif
+
+int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val)
+{
+ return stpmic2_register_read(pmic, VERSION_SR, val);
+}
+
+int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val)
+{
+ return stpmic2_register_read(pmic, PRODUCT_ID, val);
+}
diff --git a/drivers/st/regulator/regulator_core.c b/drivers/st/regulator/regulator_core.c
index 2a5d0f7..b369acd 100644
--- a/drivers/st/regulator/regulator_core.c
+++ b/drivers/st/regulator/regulator_core.c
@@ -215,14 +215,18 @@
VERBOSE("%s: set mvolt\n", rdev->desc->node_name);
- if (rdev->desc->ops->set_voltage == NULL) {
- return -ENODEV;
- }
-
if ((mvolt < rdev->min_mv) || (mvolt > rdev->max_mv)) {
return -EPERM;
}
+ if (regulator_get_voltage(rdev) == mvolt) {
+ return 0U;
+ }
+
+ if (rdev->desc->ops->set_voltage == NULL) {
+ return -ENODEV;
+ }
+
lock_driver(rdev);
ret = rdev->desc->ops->set_voltage(rdev->desc, mvolt);
@@ -420,6 +424,7 @@
static int parse_properties(const void *fdt, struct rdev *rdev, int node)
{
+ const fdt32_t *cuint;
int ret;
if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) {
@@ -430,6 +435,13 @@
}
}
+ cuint = fdt_getprop(fdt, node, "regulator-enable-ramp-delay", NULL);
+ if (cuint != NULL) {
+ rdev->enable_ramp_delay = fdt32_to_cpu(*cuint);
+ VERBOSE("%s: enable_ramp_delay=%u\n", rdev->desc->node_name,
+ rdev->enable_ramp_delay);
+ }
+
return 0;
}
diff --git a/fdts/rd1ae.dts b/fdts/rd1ae.dts
new file mode 100644
index 0000000..3060b5a
--- /dev/null
+++ b/fdts/rd1ae.dts
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "RD-1 AE";
+ compatible = "arm,rd1ae", "arm,neoverse";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = &soc_serial0;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu1: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu2: cpu@20000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x20000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu3: cpu@30000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x30000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu4: cpu@40000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x40000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu5: cpu@50000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x50000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu6: cpu@60000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x60000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu7: cpu@70000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x70000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu8: cpu@80000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x80000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu9: cpu@90000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x90000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu10: cpu@a0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xa0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu11: cpu@b0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xb0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu12: cpu@c0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xc0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu13: cpu@d0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xd0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu14: cpu@e0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xe0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu15: cpu@f0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xf0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /*
+ * 0x7fc0 0000 - 0x7fff ffff : BL32
+ * 0x7fbf 0000 - 0x7fbf ffff : FFA_SHARED_MM_BUF
+ */
+ reg = <0x00000000 0x80000000 0 0x7fbf0000>,
+ <0x00000080 0x80000000 0 0x80000000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "refclk24mhz";
+ };
+
+ soc_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "refclk1mhz";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0 0x10000>, // GICD
+ <0x0 0x301c0000 0 0x8000000>; // GICR
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its1: msi-controller@30040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30040000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its2: msi-controller@30080000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30080000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its3: msi-controller@300c0000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x300c0000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its4: msi-controller@30100000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30100000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its5: msi-controller@30140000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30140000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its6: msi-controller@30180000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30180000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ soc_serial0: serial@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ watchdog@2a440000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x2a440000 0 0x1000>,
+ <0x0 0x2a450000 0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rtc@c170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0x0c170000 0x0 0x10000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ virtio-net@c150000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc150000 0x0 0x200>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio-block@c130000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc130000 0x0 0x200>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio-rng@c140000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc140000 0x0 0x200>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci@4000000000 {
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0x00 0x11>;
+ reg = <0x40 0x00 0x00 0x04000000>;
+ ranges = <0x43000000 0x40 0x40000000 0x40 0x40000000 0x10 0x00000000
+ 0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x08000000
+ 0x01000000 0x00 0x00 0x00 0x77800000 0x00 0x800000>;
+ msi-map = <0x00 &its1 0x40000 0x10000>;
+ iommu-map = <0x00 &smmu 0x40000 0x10000>;
+ dma-coherent;
+ };
+
+ smmu: iommu@280000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x2 0x80000000 0x0 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ interrupts = <1 210 1>,
+ <1 211 1>,
+ <1 212 1>,
+ <1 213 1>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ msi-parent = <&its1 0x10000>;
+ };
+
+ sysreg: sysreg@c010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ fixed_3v3: v2m-3v3@c011000 {
+ compatible = "regulator-fixed";
+ reg = <0x0 0xc011000 0x0 0x1000>;
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ mmci@c050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x0 0xc050000 0x0 0x1000>;
+ interrupts = <0 0x8B 0x4>,
+ <0 0x8C 0x4>;
+ cd-gpios = <&sysreg 0 0>;
+ wp-gpios = <&sysreg 1 0>;
+ bus-width = <8>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&fixed_3v3>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+};
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi
index e250e3f..e6662d0 100644
--- a/fdts/stm32mp25-bl2.dtsi
+++ b/fdts/stm32mp25-bl2.dtsi
@@ -31,6 +31,7 @@
bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
+ soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0";
tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
};
diff --git a/fdts/stm32mp25-bl31.dtsi b/fdts/stm32mp25-bl31.dtsi
new file mode 100644
index 0000000..fa63f63
--- /dev/null
+++ b/fdts/stm32mp25-bl31.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ */
+
+/ {
+ soc@0 {
+ rifsc@42080000 {
+ /delete-node/ mmc@48220000;
+ /delete-node/ mmc@48230000;
+ };
+ };
+};
diff --git a/fdts/stm32mp25-ddr.dtsi b/fdts/stm32mp25-ddr.dtsi
new file mode 100644
index 0000000..1fcd13d
--- /dev/null
+++ b/fdts/stm32mp25-ddr.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ */
+
+&ddr{
+ st,mem-name = DDR_MEM_NAME;
+ st,mem-speed = <DDR_MEM_SPEED>;
+ st,mem-size = <(DDR_MEM_SIZE >> 32) (DDR_MEM_SIZE & 0xFFFFFFFF)>;
+
+ st,ctl-reg = <
+ DDR_MSTR
+ DDR_MRCTRL0
+ DDR_MRCTRL1
+ DDR_MRCTRL2
+ DDR_DERATEEN
+ DDR_DERATEINT
+ DDR_DERATECTL
+ DDR_PWRCTL
+ DDR_PWRTMG
+ DDR_HWLPCTL
+ DDR_RFSHCTL0
+ DDR_RFSHCTL1
+ DDR_RFSHCTL3
+ DDR_CRCPARCTL0
+ DDR_CRCPARCTL1
+ DDR_INIT0
+ DDR_INIT1
+ DDR_INIT2
+ DDR_INIT3
+ DDR_INIT4
+ DDR_INIT5
+ DDR_INIT6
+ DDR_INIT7
+ DDR_DIMMCTL
+ DDR_RANKCTL
+ DDR_RANKCTL1
+ DDR_ZQCTL0
+ DDR_ZQCTL1
+ DDR_ZQCTL2
+ DDR_DFITMG0
+ DDR_DFITMG1
+ DDR_DFILPCFG0
+ DDR_DFILPCFG1
+ DDR_DFIUPD0
+ DDR_DFIUPD1
+ DDR_DFIUPD2
+ DDR_DFIMISC
+ DDR_DFITMG2
+ DDR_DFITMG3
+ DDR_DBICTL
+ DDR_DFIPHYMSTR
+ DDR_DBG0
+ DDR_DBG1
+ DDR_DBGCMD
+ DDR_SWCTL
+ DDR_SWCTLSTATIC
+ DDR_POISONCFG
+ DDR_PCCFG
+ >;
+
+ st,ctl-timing = <
+ DDR_RFSHTMG
+ DDR_RFSHTMG1
+ DDR_DRAMTMG0
+ DDR_DRAMTMG1
+ DDR_DRAMTMG2
+ DDR_DRAMTMG3
+ DDR_DRAMTMG4
+ DDR_DRAMTMG5
+ DDR_DRAMTMG6
+ DDR_DRAMTMG7
+ DDR_DRAMTMG8
+ DDR_DRAMTMG9
+ DDR_DRAMTMG10
+ DDR_DRAMTMG11
+ DDR_DRAMTMG12
+ DDR_DRAMTMG13
+ DDR_DRAMTMG14
+ DDR_DRAMTMG15
+ DDR_ODTCFG
+ DDR_ODTMAP
+ >;
+
+ st,ctl-map = <
+ DDR_ADDRMAP0
+ DDR_ADDRMAP1
+ DDR_ADDRMAP2
+ DDR_ADDRMAP3
+ DDR_ADDRMAP4
+ DDR_ADDRMAP5
+ DDR_ADDRMAP6
+ DDR_ADDRMAP7
+ DDR_ADDRMAP8
+ DDR_ADDRMAP9
+ DDR_ADDRMAP10
+ DDR_ADDRMAP11
+ >;
+
+ st,ctl-perf = <
+ DDR_SCHED
+ DDR_SCHED1
+ DDR_PERFHPR1
+ DDR_PERFLPR1
+ DDR_PERFWR1
+ DDR_SCHED3
+ DDR_SCHED4
+ DDR_PCFGR_0
+ DDR_PCFGW_0
+ DDR_PCTRL_0
+ DDR_PCFGQOS0_0
+ DDR_PCFGQOS1_0
+ DDR_PCFGWQOS0_0
+ DDR_PCFGWQOS1_0
+ DDR_PCFGR_1
+ DDR_PCFGW_1
+ DDR_PCTRL_1
+ DDR_PCFGQOS0_1
+ DDR_PCFGQOS1_1
+ DDR_PCFGWQOS0_1
+ DDR_PCFGWQOS1_1
+ >;
+
+ st,phy-basic = <
+ DDR_UIB_DRAMTYPE
+ DDR_UIB_DIMMTYPE
+ DDR_UIB_LP4XMODE
+ DDR_UIB_NUMDBYTE
+ DDR_UIB_NUMACTIVEDBYTEDFI0
+ DDR_UIB_NUMACTIVEDBYTEDFI1
+ DDR_UIB_NUMANIB
+ DDR_UIB_NUMRANK_DFI0
+ DDR_UIB_NUMRANK_DFI1
+ DDR_UIB_DRAMDATAWIDTH
+ DDR_UIB_NUMPSTATES
+ DDR_UIB_FREQUENCY_0
+ DDR_UIB_PLLBYPASS_0
+ DDR_UIB_DFIFREQRATIO_0
+ DDR_UIB_DFI1EXISTS
+ DDR_UIB_TRAIN2D
+ DDR_UIB_HARDMACROVER
+ DDR_UIB_READDBIENABLE_0
+ DDR_UIB_DFIMODE
+ >;
+
+ st,phy-advanced = <
+ DDR_UIA_LP4RXPREAMBLEMODE_0
+ DDR_UIA_LP4POSTAMBLEEXT_0
+ DDR_UIA_D4RXPREAMBLELENGTH_0
+ DDR_UIA_D4TXPREAMBLELENGTH_0
+ DDR_UIA_EXTCALRESVAL
+ DDR_UIA_IS2TTIMING_0
+ DDR_UIA_ODTIMPEDANCE_0
+ DDR_UIA_TXIMPEDANCE_0
+ DDR_UIA_ATXIMPEDANCE
+ DDR_UIA_MEMALERTEN
+ DDR_UIA_MEMALERTPUIMP
+ DDR_UIA_MEMALERTVREFLEVEL
+ DDR_UIA_MEMALERTSYNCBYPASS
+ DDR_UIA_DISDYNADRTRI_0
+ DDR_UIA_PHYMSTRTRAININTERVAL_0
+ DDR_UIA_PHYMSTRMAXREQTOACK_0
+ DDR_UIA_WDQSEXT
+ DDR_UIA_CALINTERVAL
+ DDR_UIA_CALONCE
+ DDR_UIA_LP4RL_0
+ DDR_UIA_LP4WL_0
+ DDR_UIA_LP4WLS_0
+ DDR_UIA_LP4DBIRD_0
+ DDR_UIA_LP4DBIWR_0
+ DDR_UIA_LP4NWR_0
+ DDR_UIA_LP4LOWPOWERDRV
+ DDR_UIA_DRAMBYTESWAP
+ DDR_UIA_RXENBACKOFF
+ DDR_UIA_TRAINSEQUENCECTRL
+ DDR_UIA_SNPSUMCTLOPT
+ DDR_UIA_SNPSUMCTLF0RC5X_0
+ DDR_UIA_TXSLEWRISEDQ_0
+ DDR_UIA_TXSLEWFALLDQ_0
+ DDR_UIA_TXSLEWRISEAC
+ DDR_UIA_TXSLEWFALLAC
+ DDR_UIA_DISABLERETRAINING
+ DDR_UIA_DISABLEPHYUPDATE
+ DDR_UIA_ENABLEHIGHCLKSKEWFIX
+ DDR_UIA_DISABLEUNUSEDADDRLNS
+ DDR_UIA_PHYINITSEQUENCENUM
+ DDR_UIA_ENABLEDFICSPOLARITYFIX
+ DDR_UIA_PHYVREF
+ DDR_UIA_SEQUENCECTRL_0
+ >;
+
+ st,phy-mr = <
+ DDR_UIM_MR0_0
+ DDR_UIM_MR1_0
+ DDR_UIM_MR2_0
+ DDR_UIM_MR3_0
+ DDR_UIM_MR4_0
+ DDR_UIM_MR5_0
+ DDR_UIM_MR6_0
+ DDR_UIM_MR11_0
+ DDR_UIM_MR12_0
+ DDR_UIM_MR13_0
+ DDR_UIM_MR14_0
+ DDR_UIM_MR22_0
+ >;
+
+ st,phy-swizzle = <
+ DDR_UIS_SWIZZLE_0
+ DDR_UIS_SWIZZLE_1
+ DDR_UIS_SWIZZLE_2
+ DDR_UIS_SWIZZLE_3
+ DDR_UIS_SWIZZLE_4
+ DDR_UIS_SWIZZLE_5
+ DDR_UIS_SWIZZLE_6
+ DDR_UIS_SWIZZLE_7
+ DDR_UIS_SWIZZLE_8
+ DDR_UIS_SWIZZLE_9
+ DDR_UIS_SWIZZLE_10
+ DDR_UIS_SWIZZLE_11
+ DDR_UIS_SWIZZLE_12
+ DDR_UIS_SWIZZLE_13
+ DDR_UIS_SWIZZLE_14
+ DDR_UIS_SWIZZLE_15
+ DDR_UIS_SWIZZLE_16
+ DDR_UIS_SWIZZLE_17
+ DDR_UIS_SWIZZLE_18
+ DDR_UIS_SWIZZLE_19
+ DDR_UIS_SWIZZLE_20
+ DDR_UIS_SWIZZLE_21
+ DDR_UIS_SWIZZLE_22
+ DDR_UIS_SWIZZLE_23
+ DDR_UIS_SWIZZLE_24
+ DDR_UIS_SWIZZLE_25
+ DDR_UIS_SWIZZLE_26
+ DDR_UIS_SWIZZLE_27
+ DDR_UIS_SWIZZLE_28
+ DDR_UIS_SWIZZLE_29
+ DDR_UIS_SWIZZLE_30
+ DDR_UIS_SWIZZLE_31
+ DDR_UIS_SWIZZLE_32
+ DDR_UIS_SWIZZLE_33
+ DDR_UIS_SWIZZLE_34
+ DDR_UIS_SWIZZLE_35
+ DDR_UIS_SWIZZLE_36
+ DDR_UIS_SWIZZLE_37
+ DDR_UIS_SWIZZLE_38
+ DDR_UIS_SWIZZLE_39
+ DDR_UIS_SWIZZLE_40
+ DDR_UIS_SWIZZLE_41
+ DDR_UIS_SWIZZLE_42
+ DDR_UIS_SWIZZLE_43
+ >;
+};
diff --git a/fdts/stm32mp25-ddr4-2x16Gbits-2x16bits-1200MHz.dtsi b/fdts/stm32mp25-ddr4-2x16Gbits-2x16bits-1200MHz.dtsi
new file mode 100644
index 0000000..3d69448
--- /dev/null
+++ b/fdts/stm32mp25-ddr4-2x16Gbits-2x16bits-1200MHz.dtsi
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ */
+
+/*
+ * STM32MP25 DDR4 board configuration
+ * DDR4 2x16Gbits 2x16bits 1200MHz
+ *
+ * version 2
+ * package 1 Package selection (14x14 and 18x18)
+ * memclk 1200MHz (2x DFI clock) + range check
+ * Speed_Bin Worse from JEDEC
+ * device_width 16 x16 by default
+ * width 32 32: full width / 16: half width
+ * density 16Gbits (per 16bit device)
+ * Addressing RBC row/bank interleaving
+ * RDBI No Read DBI
+ */
+
+#define DDR_MEM_NAME "DDR4 2x16Gbits 2x16bits 1200MHz"
+#define DDR_MEM_SPEED 1200000
+#define DDR_MEM_SIZE 0x100000000
+
+#define DDR_MSTR 0x01040010
+#define DDR_MRCTRL0 0x00000030
+#define DDR_MRCTRL1 0x00000000
+#define DDR_MRCTRL2 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00000000
+#define DDR_DERATECTL 0x00000000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00130001
+#define DDR_HWLPCTL 0x00000002
+#define DDR_RFSHCTL0 0x00210010
+#define DDR_RFSHCTL1 0x00000000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0092014A
+#define DDR_RFSHTMG1 0x008C0000
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_CRCPARCTL1 0x00001000
+#define DDR_INIT0 0xC0020002
+#define DDR_INIT1 0x00010002
+#define DDR_INIT2 0x00000D00
+#define DDR_INIT3 0x09400103
+#define DDR_INIT4 0x00180000
+#define DDR_INIT5 0x00100004
+#define DDR_INIT6 0x00080460
+#define DDR_INIT7 0x00000C16
+#define DDR_DIMMCTL 0x00000000
+#define DDR_RANKCTL 0x0000066F
+#define DDR_RANKCTL1 0x0000000D
+#define DDR_DRAMTMG0 0x11152815
+#define DDR_DRAMTMG1 0x0004051E
+#define DDR_DRAMTMG2 0x0609060D
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x0904050A
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020005
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x0606100B
+#define DDR_DRAMTMG9 0x0002040A
+#define DDR_DRAMTMG10 0x001C180A
+#define DDR_DRAMTMG11 0x4408021C
+#define DDR_DRAMTMG12 0x0C020010
+#define DDR_DRAMTMG13 0x1C200004
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_DRAMTMG15 0x00000000
+#define DDR_ZQCTL0 0x01000040
+#define DDR_ZQCTL1 0x2000493E
+#define DDR_ZQCTL2 0x00000000
+#define DDR_DFITMG0 0x038F8209
+#define DDR_DFITMG1 0x00080303
+#define DDR_DFILPCFG0 0x07004111
+#define DDR_DFILPCFG1 0x00000000
+#define DDR_DFIUPD0 0xC0300018
+#define DDR_DFIUPD1 0x005700B4
+#define DDR_DFIUPD2 0x80000000
+#define DDR_DFIMISC 0x00000041
+#define DDR_DFITMG2 0x00000F09
+#define DDR_DFITMG3 0x00000000
+#define DDR_DBICTL 0x00000001
+#define DDR_DFIPHYMSTR 0x80000000
+#define DDR_ADDRMAP0 0x0000001F
+#define DDR_ADDRMAP1 0x003F0909
+#define DDR_ADDRMAP2 0x00000700
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x070F0707
+#define DDR_ADDRMAP6 0x07070707
+#define DDR_ADDRMAP7 0x00000F07
+#define DDR_ADDRMAP8 0x00003F01
+#define DDR_ADDRMAP9 0x07070707
+#define DDR_ADDRMAP10 0x07070707
+#define DDR_ADDRMAP11 0x00000007
+#define DDR_ODTCFG 0x06000618
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x80001B00
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x04000200
+#define DDR_PERFLPR1 0x08000080
+#define DDR_PERFWR1 0x08000400
+#define DDR_SCHED3 0x04040208
+#define DDR_SCHED4 0x08400810
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_SWCTL 0x00000000
+#define DDR_SWCTLSTATIC 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000000
+#define DDR_PCFGR_0 0x00704100
+#define DDR_PCFGW_0 0x00004100
+#define DDR_PCTRL_0 0x00000000
+#define DDR_PCFGQOS0_0 0x0021000C
+#define DDR_PCFGQOS1_0 0x01000080
+#define DDR_PCFGWQOS0_0 0x01100C07
+#define DDR_PCFGWQOS1_0 0x04000200
+#define DDR_PCFGR_1 0x00704100
+#define DDR_PCFGW_1 0x00004100
+#define DDR_PCTRL_1 0x00000000
+#define DDR_PCFGQOS0_1 0x00100007
+#define DDR_PCFGQOS1_1 0x01000080
+#define DDR_PCFGWQOS0_1 0x01100C07
+#define DDR_PCFGWQOS1_1 0x04000200
+
+#define DDR_UIB_DRAMTYPE 0x00000000
+#define DDR_UIB_DIMMTYPE 0x00000004
+#define DDR_UIB_LP4XMODE 0x00000000
+#define DDR_UIB_NUMDBYTE 0x00000004
+#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000004
+#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000000
+#define DDR_UIB_NUMANIB 0x00000008
+#define DDR_UIB_NUMRANK_DFI0 0x00000001
+#define DDR_UIB_NUMRANK_DFI1 0x00000001
+#define DDR_UIB_DRAMDATAWIDTH 0x00000010
+#define DDR_UIB_NUMPSTATES 0x00000001
+#define DDR_UIB_FREQUENCY_0 0x000004B0
+#define DDR_UIB_PLLBYPASS_0 0x00000000
+#define DDR_UIB_DFIFREQRATIO_0 0x00000001
+#define DDR_UIB_DFI1EXISTS 0x00000001
+#define DDR_UIB_TRAIN2D 0x00000000
+#define DDR_UIB_HARDMACROVER 0x00000003
+#define DDR_UIB_READDBIENABLE_0 0x00000000
+#define DDR_UIB_DFIMODE 0x00000000
+
+#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000
+#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000000
+#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000000
+#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000
+#define DDR_UIA_EXTCALRESVAL 0x00000000
+#define DDR_UIA_IS2TTIMING_0 0x00000000
+#define DDR_UIA_ODTIMPEDANCE_0 0x00000035
+#define DDR_UIA_TXIMPEDANCE_0 0x00000028
+#define DDR_UIA_ATXIMPEDANCE 0x00000028
+#define DDR_UIA_MEMALERTEN 0x00000000
+#define DDR_UIA_MEMALERTPUIMP 0x00000000
+#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
+#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000
+#define DDR_UIA_DISDYNADRTRI_0 0x00000001
+#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x00000000
+#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000000
+#define DDR_UIA_WDQSEXT 0x00000000
+#define DDR_UIA_CALINTERVAL 0x00000009
+#define DDR_UIA_CALONCE 0x00000000
+#define DDR_UIA_LP4RL_0 0x00000000
+#define DDR_UIA_LP4WL_0 0x00000000
+#define DDR_UIA_LP4WLS_0 0x00000000
+#define DDR_UIA_LP4DBIRD_0 0x00000000
+#define DDR_UIA_LP4DBIWR_0 0x00000000
+#define DDR_UIA_LP4NWR_0 0x00000000
+#define DDR_UIA_LP4LOWPOWERDRV 0x00000000
+#define DDR_UIA_DRAMBYTESWAP 0x00000000
+#define DDR_UIA_RXENBACKOFF 0x00000000
+#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000
+#define DDR_UIA_SNPSUMCTLOPT 0x00000000
+#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000
+#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000F
+#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000F
+#define DDR_UIA_TXSLEWRISEAC 0x0000000F
+#define DDR_UIA_TXSLEWFALLAC 0x0000000F
+#define DDR_UIA_DISABLERETRAINING 0x00000001
+#define DDR_UIA_DISABLEPHYUPDATE 0x00000000
+#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000
+#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001
+#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000
+#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000
+#define DDR_UIA_PHYVREF 0x0000005E
+#define DDR_UIA_SEQUENCECTRL_0 0x0000031F
+
+#define DDR_UIM_MR0_0 0x00000940
+#define DDR_UIM_MR1_0 0x00000103
+#define DDR_UIM_MR2_0 0x00000018
+#define DDR_UIM_MR3_0 0x00000000
+#define DDR_UIM_MR4_0 0x00000008
+#define DDR_UIM_MR5_0 0x00000460
+#define DDR_UIM_MR6_0 0x00000C16
+#define DDR_UIM_MR11_0 0x00000000
+#define DDR_UIM_MR12_0 0x00000000
+#define DDR_UIM_MR13_0 0x00000000
+#define DDR_UIM_MR14_0 0x00000000
+#define DDR_UIM_MR22_0 0x00000000
+
+#define DDR_UIS_SWIZZLE_0 0x0000000C
+#define DDR_UIS_SWIZZLE_1 0x00000005
+#define DDR_UIS_SWIZZLE_2 0x00000013
+#define DDR_UIS_SWIZZLE_3 0x0000001A
+#define DDR_UIS_SWIZZLE_4 0x00000009
+#define DDR_UIS_SWIZZLE_5 0x00000003
+#define DDR_UIS_SWIZZLE_6 0x00000001
+#define DDR_UIS_SWIZZLE_7 0x00000019
+#define DDR_UIS_SWIZZLE_8 0x00000007
+#define DDR_UIS_SWIZZLE_9 0x00000004
+#define DDR_UIS_SWIZZLE_10 0x0000000A
+#define DDR_UIS_SWIZZLE_11 0x0000000D
+#define DDR_UIS_SWIZZLE_12 0x00000014
+#define DDR_UIS_SWIZZLE_13 0x00000000
+#define DDR_UIS_SWIZZLE_14 0x00000000
+#define DDR_UIS_SWIZZLE_15 0x00000000
+#define DDR_UIS_SWIZZLE_16 0x00000000
+#define DDR_UIS_SWIZZLE_17 0x00000000
+#define DDR_UIS_SWIZZLE_18 0x00000006
+#define DDR_UIS_SWIZZLE_19 0x0000000B
+#define DDR_UIS_SWIZZLE_20 0x00000000
+#define DDR_UIS_SWIZZLE_21 0x00000000
+#define DDR_UIS_SWIZZLE_22 0x00000000
+#define DDR_UIS_SWIZZLE_23 0x00000008
+#define DDR_UIS_SWIZZLE_24 0x00000002
+#define DDR_UIS_SWIZZLE_25 0x00000018
+#define DDR_UIS_SWIZZLE_26 0x1A13050C
+#define DDR_UIS_SWIZZLE_27 0x19010309
+#define DDR_UIS_SWIZZLE_28 0x0D0A0407
+#define DDR_UIS_SWIZZLE_29 0x00000014
+#define DDR_UIS_SWIZZLE_30 0x000B0600
+#define DDR_UIS_SWIZZLE_31 0x02080000
+#define DDR_UIS_SWIZZLE_32 0x00000018
+#define DDR_UIS_SWIZZLE_33 0x00000000
+#define DDR_UIS_SWIZZLE_34 0x00000000
+#define DDR_UIS_SWIZZLE_35 0x00000000
+#define DDR_UIS_SWIZZLE_36 0x00000000
+#define DDR_UIS_SWIZZLE_37 0x00000000
+#define DDR_UIS_SWIZZLE_38 0x00000000
+#define DDR_UIS_SWIZZLE_39 0x00000000
+#define DDR_UIS_SWIZZLE_40 0x00000000
+#define DDR_UIS_SWIZZLE_41 0x00000000
+#define DDR_UIS_SWIZZLE_42 0x00000000
+#define DDR_UIS_SWIZZLE_43 0x00000000
+
+#include "stm32mp25-ddr.dtsi"
diff --git a/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi b/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
new file mode 100644
index 0000000..674cb3d
--- /dev/null
+++ b/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ */
+
+/*
+ * STM32MP25 DDR4 board configuration
+ * DDR4 2x8Gbits 2x16bits 1200MHz
+ *
+ * version 1
+ * package 1 Package selection (14x14 and 18x18)
+ * memclk 1200MHz (2x DFI clock) + range check
+ * Speed_Bin Worse from JEDEC
+ * width 32 32: full width / 16: half width
+ * ranks 1 Single or Dual rank
+ * density 8Gbits (per 16bit device)
+ * Addressing RBC row/bank interleaving
+ * RDBI No Read DBI
+ */
+
+#define DDR_MEM_NAME "DDR4 2x8Gbits 2x16bits 1200MHz"
+#define DDR_MEM_SPEED 1200000
+#define DDR_MEM_SIZE 0x80000000
+
+#define DDR_MSTR 0x01040010
+#define DDR_MRCTRL0 0x00000030
+#define DDR_MRCTRL1 0x00000000
+#define DDR_MRCTRL2 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00000000
+#define DDR_DERATECTL 0x00000000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00130001
+#define DDR_HWLPCTL 0x00000002
+#define DDR_RFSHCTL0 0x00210010
+#define DDR_RFSHCTL1 0x00000000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x009200D2
+#define DDR_RFSHTMG1 0x008C0000
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_CRCPARCTL1 0x00001000
+#define DDR_INIT0 0xC0020002
+#define DDR_INIT1 0x00010002
+#define DDR_INIT2 0x00000D00
+#define DDR_INIT3 0x09400103
+#define DDR_INIT4 0x00180000
+#define DDR_INIT5 0x00100004
+#define DDR_INIT6 0x00080460
+#define DDR_INIT7 0x00000C16
+#define DDR_DIMMCTL 0x00000000
+#define DDR_RANKCTL 0x0000066F
+#define DDR_DRAMTMG0 0x11152815
+#define DDR_DRAMTMG1 0x0004051E
+#define DDR_DRAMTMG2 0x0609060D
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x0904050A
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020005
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x04041007
+#define DDR_DRAMTMG9 0x0002040A
+#define DDR_DRAMTMG10 0x001C180A
+#define DDR_DRAMTMG11 0x4408021C
+#define DDR_DRAMTMG12 0x0C020010
+#define DDR_DRAMTMG13 0x1C200004
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_DRAMTMG15 0x00000000
+#define DDR_ZQCTL0 0x01000040
+#define DDR_ZQCTL1 0x2000493E
+#define DDR_ZQCTL2 0x00000000
+#define DDR_DFITMG0 0x038F8209
+#define DDR_DFITMG1 0x00080303
+#define DDR_DFILPCFG0 0x07004111
+#define DDR_DFILPCFG1 0x00000000
+#define DDR_DFIUPD0 0xC0300018
+#define DDR_DFIUPD1 0x005700B4
+#define DDR_DFIUPD2 0x80000000
+#define DDR_DFIMISC 0x00000041
+#define DDR_DFITMG2 0x00000F09
+#define DDR_DFITMG3 0x00000000
+#define DDR_DBICTL 0x00000001
+#define DDR_DFIPHYMSTR 0x80000000
+#define DDR_ADDRMAP0 0x0000001F
+#define DDR_ADDRMAP1 0x003F0909
+#define DDR_ADDRMAP2 0x00000700
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x070F0707
+#define DDR_ADDRMAP6 0x07070707
+#define DDR_ADDRMAP7 0x00000F0F
+#define DDR_ADDRMAP8 0x00003F01
+#define DDR_ADDRMAP9 0x07070707
+#define DDR_ADDRMAP10 0x07070707
+#define DDR_ADDRMAP11 0x00000007
+#define DDR_ODTCFG 0x06000618
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000F00
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x0F000001
+#define DDR_PERFLPR1 0x0F000080
+#define DDR_PERFWR1 0x01000200
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_SWCTL 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000000
+#define DDR_PCFGR_0 0x00004100
+#define DDR_PCFGW_0 0x00004100
+#define DDR_PCTRL_0 0x00000000
+#define DDR_PCFGQOS0_0 0x00200007
+#define DDR_PCFGQOS1_0 0x01000100
+#define DDR_PCFGWQOS0_0 0x00000C07
+#define DDR_PCFGWQOS1_0 0x02000200
+#define DDR_PCFGR_1 0x00004100
+#define DDR_PCFGW_1 0x00004100
+#define DDR_PCTRL_1 0x00000000
+#define DDR_PCFGQOS0_1 0x00200007
+#define DDR_PCFGQOS1_1 0x01000180
+#define DDR_PCFGWQOS0_1 0x00000C07
+#define DDR_PCFGWQOS1_1 0x04000400
+
+#define DDR_UIB_DRAMTYPE 0x00000000
+#define DDR_UIB_DIMMTYPE 0x00000004
+#define DDR_UIB_LP4XMODE 0x00000000
+#define DDR_UIB_NUMDBYTE 0x00000004
+#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000004
+#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000000
+#define DDR_UIB_NUMANIB 0x00000008
+#define DDR_UIB_NUMRANK_DFI0 0x00000001
+#define DDR_UIB_NUMRANK_DFI1 0x00000001
+#define DDR_UIB_DRAMDATAWIDTH 0x00000010
+#define DDR_UIB_NUMPSTATES 0x00000001
+#define DDR_UIB_FREQUENCY_0 0x000004B0
+#define DDR_UIB_PLLBYPASS_0 0x00000000
+#define DDR_UIB_DFIFREQRATIO_0 0x00000001
+#define DDR_UIB_DFI1EXISTS 0x00000001
+#define DDR_UIB_TRAIN2D 0x00000000
+#define DDR_UIB_HARDMACROVER 0x00000003
+#define DDR_UIB_READDBIENABLE_0 0x00000000
+#define DDR_UIB_DFIMODE 0x00000000
+
+#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000
+#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000000
+#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000000
+#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000
+#define DDR_UIA_EXTCALRESVAL 0x00000000
+#define DDR_UIA_IS2TTIMING_0 0x00000000
+#define DDR_UIA_ODTIMPEDANCE_0 0x00000035
+#define DDR_UIA_TXIMPEDANCE_0 0x00000028
+#define DDR_UIA_ATXIMPEDANCE 0x00000028
+#define DDR_UIA_MEMALERTEN 0x00000000
+#define DDR_UIA_MEMALERTPUIMP 0x00000000
+#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
+#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000
+#define DDR_UIA_DISDYNADRTRI_0 0x00000001
+#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x00000000
+#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000000
+#define DDR_UIA_WDQSEXT 0x00000000
+#define DDR_UIA_CALINTERVAL 0x00000009
+#define DDR_UIA_CALONCE 0x00000000
+#define DDR_UIA_LP4RL_0 0x00000000
+#define DDR_UIA_LP4WL_0 0x00000000
+#define DDR_UIA_LP4WLS_0 0x00000000
+#define DDR_UIA_LP4DBIRD_0 0x00000000
+#define DDR_UIA_LP4DBIWR_0 0x00000000
+#define DDR_UIA_LP4NWR_0 0x00000000
+#define DDR_UIA_LP4LOWPOWERDRV 0x00000000
+#define DDR_UIA_DRAMBYTESWAP 0x00000000
+#define DDR_UIA_RXENBACKOFF 0x00000000
+#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000
+#define DDR_UIA_SNPSUMCTLOPT 0x00000000
+#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000
+#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000F
+#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000F
+#define DDR_UIA_TXSLEWRISEAC 0x0000000F
+#define DDR_UIA_TXSLEWFALLAC 0x0000000F
+#define DDR_UIA_DISABLERETRAINING 0x00000001
+#define DDR_UIA_DISABLEPHYUPDATE 0x00000000
+#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000
+#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001
+#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000
+#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000
+#define DDR_UIA_PHYVREF 0x0000005E
+#define DDR_UIA_SEQUENCECTRL_0 0x0000031F
+
+#define DDR_UIM_MR0_0 0x00000940
+#define DDR_UIM_MR1_0 0x00000103
+#define DDR_UIM_MR2_0 0x00000018
+#define DDR_UIM_MR3_0 0x00000000
+#define DDR_UIM_MR4_0 0x00000008
+#define DDR_UIM_MR5_0 0x00000460
+#define DDR_UIM_MR6_0 0x00000C16
+#define DDR_UIM_MR11_0 0x00000000
+#define DDR_UIM_MR12_0 0x00000000
+#define DDR_UIM_MR13_0 0x00000000
+#define DDR_UIM_MR14_0 0x00000000
+#define DDR_UIM_MR22_0 0x00000000
+
+#define DDR_UIS_SWIZZLE_0 0x0000000C
+#define DDR_UIS_SWIZZLE_1 0x00000005
+#define DDR_UIS_SWIZZLE_2 0x00000013
+#define DDR_UIS_SWIZZLE_3 0x0000001A
+#define DDR_UIS_SWIZZLE_4 0x00000009
+#define DDR_UIS_SWIZZLE_5 0x00000003
+#define DDR_UIS_SWIZZLE_6 0x00000001
+#define DDR_UIS_SWIZZLE_7 0x00000019
+#define DDR_UIS_SWIZZLE_8 0x00000007
+#define DDR_UIS_SWIZZLE_9 0x00000004
+#define DDR_UIS_SWIZZLE_10 0x0000000A
+#define DDR_UIS_SWIZZLE_11 0x0000000D
+#define DDR_UIS_SWIZZLE_12 0x00000014
+#define DDR_UIS_SWIZZLE_13 0x00000000
+#define DDR_UIS_SWIZZLE_14 0x00000000
+#define DDR_UIS_SWIZZLE_15 0x00000000
+#define DDR_UIS_SWIZZLE_16 0x00000000
+#define DDR_UIS_SWIZZLE_17 0x00000000
+#define DDR_UIS_SWIZZLE_18 0x00000006
+#define DDR_UIS_SWIZZLE_19 0x0000000B
+#define DDR_UIS_SWIZZLE_20 0x00000000
+#define DDR_UIS_SWIZZLE_21 0x00000000
+#define DDR_UIS_SWIZZLE_22 0x00000000
+#define DDR_UIS_SWIZZLE_23 0x00000008
+#define DDR_UIS_SWIZZLE_24 0x00000002
+#define DDR_UIS_SWIZZLE_25 0x00000018
+#define DDR_UIS_SWIZZLE_26 0x1A13050C
+#define DDR_UIS_SWIZZLE_27 0x19010309
+#define DDR_UIS_SWIZZLE_28 0x0D0A0407
+#define DDR_UIS_SWIZZLE_29 0x00000014
+#define DDR_UIS_SWIZZLE_30 0x000B0600
+#define DDR_UIS_SWIZZLE_31 0x02080000
+#define DDR_UIS_SWIZZLE_32 0x00000018
+#define DDR_UIS_SWIZZLE_33 0x00000000
+#define DDR_UIS_SWIZZLE_34 0x00000000
+#define DDR_UIS_SWIZZLE_35 0x00000000
+#define DDR_UIS_SWIZZLE_36 0x00000000
+#define DDR_UIS_SWIZZLE_37 0x00000000
+#define DDR_UIS_SWIZZLE_38 0x00000000
+#define DDR_UIS_SWIZZLE_39 0x00000000
+#define DDR_UIS_SWIZZLE_40 0x00000000
+#define DDR_UIS_SWIZZLE_41 0x00000000
+#define DDR_UIS_SWIZZLE_42 0x00000000
+#define DDR_UIS_SWIZZLE_43 0x00000000
+
+#include "stm32mp25-ddr.dtsi"
diff --git a/fdts/stm32mp25-fw-config.dtsi b/fdts/stm32mp25-fw-config.dtsi
index 102980d..2f83f24 100644
--- a/fdts/stm32mp25-fw-config.dtsi
+++ b/fdts/stm32mp25-fw-config.dtsi
@@ -31,6 +31,10 @@
id = <BL31_IMAGE_ID>;
};
+ soc_fw-config {
+ id = <SOC_FW_CONFIG_ID>;
+ };
+
tos_fw {
id = <BL32_IMAGE_ID>;
};
diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi
index fb12808..a22c823 100644
--- a/fdts/stm32mp25-pinctrl.dtsi
+++ b/fdts/stm32mp25-pinctrl.dtsi
@@ -7,6 +7,17 @@
&pinctrl {
/omit-if-no-ref/
+ i2c7_pins_a: i2c7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 15, AF10)>, /* I2C7_SCL */
+ <STM32_PINMUX('D', 14, AF10)>; /* I2C7_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
diff --git a/fdts/stm32mp251.dtsi b/fdts/stm32mp251.dtsi
index 6f39b5a..c2c2764 100644
--- a/fdts/stm32mp251.dtsi
+++ b/fdts/stm32mp251.dtsi
@@ -98,6 +98,134 @@
status = "disabled";
};
+ usart3: serial@400f0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400f0000 0x400>;
+ clocks = <&rcc CK_KER_USART3>;
+ resets = <&rcc USART3_R>;
+ status = "disabled";
+ };
+
+ uart4: serial@40100000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40100000 0x400>;
+ clocks = <&rcc CK_KER_UART4>;
+ resets = <&rcc UART4_R>;
+ status = "disabled";
+ };
+
+ uart5: serial@40110000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40110000 0x400>;
+ clocks = <&rcc CK_KER_UART5>;
+ resets = <&rcc UART5_R>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@40120000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40120000 0x400>;
+ clocks = <&rcc CK_KER_I2C1>;
+ resets = <&rcc I2C1_R>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40130000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40130000 0x400>;
+ clocks = <&rcc CK_KER_I2C2>;
+ resets = <&rcc I2C2_R>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@40140000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40140000 0x400>;
+ clocks = <&rcc CK_KER_I2C3>;
+ resets = <&rcc I2C3_R>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@40150000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40150000 0x400>;
+ clocks = <&rcc CK_KER_I2C4>;
+ resets = <&rcc I2C4_R>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@40160000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40160000 0x400>;
+ clocks = <&rcc CK_KER_I2C5>;
+ resets = <&rcc I2C5_R>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@40170000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40170000 0x400>;
+ clocks = <&rcc CK_KER_I2C6>;
+ resets = <&rcc I2C6_R>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@40180000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40180000 0x400>;
+ clocks = <&rcc CK_KER_I2C7>;
+ resets = <&rcc I2C7_R>;
+ status = "disabled";
+ };
+
+ usart6: serial@40220000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40220000 0x400>;
+ clocks = <&rcc CK_KER_USART6>;
+ resets = <&rcc USART6_R>;
+ status = "disabled";
+ };
+
+ uart9: serial@402c0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x402c0000 0x400>;
+ clocks = <&rcc CK_KER_UART9>;
+ resets = <&rcc UART9_R>;
+ status = "disabled";
+ };
+
+ usart1: serial@40330000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40330000 0x400>;
+ clocks = <&rcc CK_KER_USART1>;
+ resets = <&rcc USART1_R>;
+ status = "disabled";
+ };
+
+ uart7: serial@40370000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40370000 0x400>;
+ clocks = <&rcc CK_KER_UART7>;
+ resets = <&rcc UART7_R>;
+ status = "disabled";
+ };
+
+ uart8: serial@40380000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40380000 0x400>;
+ clocks = <&rcc CK_KER_UART8>;
+ resets = <&rcc UART8_R>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@46040000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x46040000 0x400>;
+ clocks = <&rcc CK_KER_I2C8>;
+ resets = <&rcc I2C8_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@48220000 {
compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
@@ -200,6 +328,13 @@
reg = <0x44230000 0x10000>;
};
+ ddr: ddr@48040000 {
+ compatible = "st,stm32mp2-ddr";
+ reg = <0x48040000 0x10000>,
+ <0x48c00000 0x400000>;
+ status = "okay";
+ };
+
pinctrl: pinctrl@44240000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi b/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
index e41c6b9..5bfcf8d 100644
--- a/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
+++ b/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
@@ -11,6 +11,10 @@
/ {
dtb-registry {
+ soc_fw-config {
+ load-address = <0x0 0x81ff0000>;
+ max-size = <0x10000>;
+ };
tos_fw {
load-address = <0x0 0x82000000>;
max-size = <0x2000000>;
diff --git a/fdts/stm32mp257f-ev1.dts b/fdts/stm32mp257f-ev1.dts
index 6df1b30..5d5e35d 100644
--- a/fdts/stm32mp257f-ev1.dts
+++ b/fdts/stm32mp257f-ev1.dts
@@ -10,6 +10,7 @@
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp257f-ev1-ca35tdcid-rcc.dtsi"
+#include "stm32mp25-ddr4-2x16Gbits-2x16bits-1200MHz.dtsi"
#include "stm32mp25-pinctrl.dtsi"
#include "stm32mp25xxai-pinctrl.dtsi"
@@ -37,6 +38,138 @@
};
};
+&ddr {
+ vdd-supply = <&vdd_ddr>;
+ vtt-supply = <&vtt_ddr>;
+ vpp-supply = <&vpp_ddr>;
+ vref-supply = <&vref_ddr>;
+};
+
+&i2c7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic2: stpmic@33 {
+ compatible = "st,stpmic2";
+ reg = <0x33>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic2-regulators";
+
+ vddcpu: buck1 {
+ regulator-name = "vddcpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <910000>;
+ regulator-always-on;
+ };
+ vddcore: buck2 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <820000>;
+ regulator-max-microvolt = <820000>;
+ regulator-always-on;
+ };
+ vddgpu: buck3 {
+ regulator-name = "vddgpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ };
+ vddio_pmic: buck4 {
+ regulator-name = "vddio_pmic";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ v1v8: buck5 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vdd_ddr: buck6 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ v3v3: buck7 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vdda1v8_aon: ldo1 {
+ regulator-name = "vdda1v8_aon";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vdd_emmc: ldo2 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ st,regulator-sink-source;
+ };
+ vdd3v3_usb: ldo4 {
+ regulator-name = "vdd3v3_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vpp_ddr: ldo5 {
+ regulator-name = "vpp_ddr";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-enable-ramp-delay = <1000>;
+ };
+ vdd_sdcard: ldo7 {
+ regulator-name = "vdd_sdcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vddio_sdcard: ldo8 {
+ regulator-name = "vddio_sdcard";
+ st,regulator-bypass-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vref_ddr: refddr {
+ regulator-name = "vref_ddr";
+ };
+ };
+ };
+};
+
+&pwr {
+ vddio1: vddio1 {
+ vddio1-supply = <&vddio_sdcard>;
+ };
+ vddio2: vddio2 {
+ vddio2-supply = <&v1v8>;
+ };
+ vddio3: vddio3 {
+ vddio3-supply = <&vddio_pmic>;
+ };
+ vddio4: vddio4 {
+ vddio4-supply = <&vddio_pmic>;
+ };
+ vddio: vddio {
+ vdd-supply = <&vddio_pmic>;
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
diff --git a/fdts/tbbr_cot_descriptors.dtsi b/fdts/tbbr_cot_descriptors.dtsi
index b3c0ca7..253297f 100644
--- a/fdts/tbbr_cot_descriptors.dtsi
+++ b/fdts/tbbr_cot_descriptors.dtsi
@@ -195,6 +195,12 @@
hash = <&hw_config_hash>;
};
+ fw_config {
+ image-id = <FW_CONFIG_ID>;
+ parent = <&trusted_boot_fw_cert>;
+ hash = <&fw_config_hash>;
+ };
+
scp_bl2_image {
image-id = <SCP_BL2_IMAGE_ID>;
parent = <&scp_fw_content_cert>;
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index be0a9f6..735d429 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -247,10 +247,6 @@
reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
};
- fwu_mm {
- reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>;
- no-map;
- };
};
memory {
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index d8ad881..6a19822 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -406,6 +406,10 @@
#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8)
#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4)
+#define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf)
+#define SCTLR2_IMPLEMENTED ULL(1)
+
#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
@@ -433,6 +437,10 @@
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define GCS_IMPLEMENTED ULL(1)
+#define ID_AA64PFR1_EL1_THE_SHIFT U(48)
+#define ID_AA64PFR1_EL1_THE_MASK ULL(0xf)
+#define THE_IMPLEMENTED ULL(1)
+
#define RNG_TRAP_IMPLEMENTED ULL(0x1)
/* ID_AA64PFR2_EL1 definitions */
@@ -589,7 +597,9 @@
#define SCR_TWEDEL_SHIFT U(30)
#define SCR_TWEDEL_MASK ULL(0xf)
#define SCR_PIEN_BIT (UL(1) << 45)
+#define SCR_SCTLR2En_BIT (UL(1) << 44)
#define SCR_TCR2EN_BIT (UL(1) << 43)
+#define SCR_RCWMASKEn_BIT (UL(1) << 42)
#define SCR_TRNDR_BIT (UL(1) << 40)
#define SCR_GCSEn_BIT (UL(1) << 39)
#define SCR_HXEn_BIT (UL(1) << 38)
@@ -623,6 +633,8 @@
/* MDCR_EL3 definitions */
#define MDCR_EBWE_BIT (ULL(1) << 43)
+#define MDCR_E3BREC (ULL(1) << 38)
+#define MDCR_E3BREW (ULL(1) << 37)
#define MDCR_EnPMSN_BIT (ULL(1) << 36)
#define MDCR_MPMX_BIT (ULL(1) << 35)
#define MDCR_MCCD_BIT (ULL(1) << 34)
@@ -1473,6 +1485,18 @@
#define TRFCR_EL1 S3_0_C1_C2_1
/*******************************************************************************
+ * FEAT_THE - Translation Hardening Extension Registers
+ ******************************************************************************/
+#define RCWMASK_EL1 S3_0_C13_C0_6
+#define RCWSMASK_EL1 S3_0_C13_C0_3
+
+/*******************************************************************************
+ * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers
+ ******************************************************************************/
+#define SCTLR2_EL2 S3_4_C1_C0_3
+#define SCTLR2_EL1 S3_0_C1_C0_3
+
+/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/
#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index f03c9d5..de21fea 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -134,6 +134,10 @@
* +----------------------------+
* | FEAT_FGT2 |
* +----------------------------+
+ * | FEAT_THE |
+ * +----------------------------+
+ * | FEAT_SCTLR2 |
+ * +----------------------------+
*/
__attribute__((always_inline))
@@ -262,6 +266,15 @@
CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
+/* FEAT_THE: Translation Hardening Extension */
+CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT,
+ ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE)
+
+/* FEAT_SCTLR2 */
+CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT,
+ ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED,
+ ENABLE_FEAT_SCTLR2)
+
__attribute__((always_inline))
static inline bool is_feat_sxpie_supported(void)
{
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index a892654..acaa1b8 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -670,6 +670,14 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
+/* FEAT_THE Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
+
+/* FEAT_SCTLR2 Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
+
/* DynamIQ Control registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcr_el1, CLUSTERPMCR_EL1)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 60c5a0c..1666e3b 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -59,24 +59,18 @@
* zero here but are updated ahead of transitioning to a lower EL in the
* function cm_init_context_common().
*
- * SCR_EL3.SIF: Set to one to disable instruction fetches from
- * Non-secure memory.
- *
- * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
- * to EL3 when executing at any EL.
- *
* SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
*
* NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
* against ERRATA_V2_3099206.
* ---------------------------------------------------------------------
*/
- mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
+ mov_imm x0, SCR_RESET_VAL
#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
- mrs x1, id_aa64pfr0_el1
- and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
- cbz x1, 1f
- orr x0, x0, #SCR_EEL2_BIT
+ mrs x1, id_aa64pfr0_el1
+ and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
+ cbz x1, 1f
+ orr x0, x0, #SCR_EEL2_BIT
#endif
1:
msr scr_el3, x0
@@ -84,22 +78,11 @@
/* ---------------------------------------------------------------------
* Initialise MDCR_EL3, setting all fields rather than relying on hw.
* Some fields are architecturally UNKNOWN on reset.
- *
- * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
- * Debug exceptions, other than Breakpoint Instruction exceptions, are
- * disabled from all ELs in Secure state.
*/
- mov_imm x0, (MDCR_EL3_RESET_VAL | MDCR_SDD_BIT)
+ mov_imm x0, MDCR_EL3_RESET_VAL
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
- * Enable External Aborts and SError Interrupts now that the exception
- * vectors have been setup.
- * ---------------------------------------------------------------------
- */
- msr daifclr, #DAIF_ABT_BIT
-
- /* ---------------------------------------------------------------------
* Initialise CPTR_EL3, setting all fields rather than relying on hw.
* All fields are architecturally UNKNOWN on reset.
* ---------------------------------------------------------------------
@@ -107,28 +90,6 @@
mov_imm x0, CPTR_EL3_RESET_VAL
msr cptr_el3, x0
- /*
- * If Data Independent Timing (DIT) functionality is implemented,
- * always enable DIT in EL3.
- * First assert that the FEAT_DIT build flag matches the feature id
- * register value for DIT.
- */
-#if ENABLE_FEAT_DIT
-#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1
- mrs x0, id_aa64pfr0_el1
- ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
-#if ENABLE_FEAT_DIT > 1
- cbz x0, 1f
-#else
- cmp x0, #DIT_IMPLEMENTED
- ASM_ASSERT(eq)
-#endif
-
-#endif /* ENABLE_ASSERTIONS */
- mov x0, #DIT_BIT
- msr DIT, x0
-1:
-#endif
.endm
/* -----------------------------------------------------------------------------
@@ -270,6 +231,12 @@
el3_arch_init_common
+ /* ---------------------------------------------------------------------
+ * Set the el3 execution context(i.e. root_context).
+ * ---------------------------------------------------------------------
+ */
+ setup_el3_execution_context
+
.if \_secondary_cold_boot
/* -------------------------------------------------------------
* Check if this is a primary or secondary CPU cold boot.
@@ -460,4 +427,68 @@
end:
.endm
+/*-----------------------------------------------------------------------------
+ * Helper macro to configure EL3 registers we care about, while executing
+ * at EL3/Root world. Root world has its own execution environment and
+ * needs to have its settings configured to be independent of other worlds.
+ * -----------------------------------------------------------------------------
+ */
+ .macro setup_el3_execution_context
+
+ /* ---------------------------------------------------------------------
+ * The following registers need to be part of separate root context
+ * as their values are of importance during EL3 execution.
+ * Hence these registers are overwritten to their intital values,
+ * irrespective of whichever world they return from to ensure EL3 has a
+ * consistent execution context throughout the lifetime of TF-A.
+ *
+ * DAIF.A: Enable External Aborts and SError Interrupts at EL3.
+ *
+ * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
+ * Debug exceptions, other than Breakpoint Instruction exceptions, are
+ * disabled from all ELs in Secure state.
+ *
+ * SCR_EL3.EA: Set to one to enable SError interrupts at EL3.
+ *
+ * SCR_EL3.SIF: Set to one to disable instruction fetches from
+ * Non-secure memory.
+ *
+ * PMCR_EL0.DP: Set to one so that the cycle counter,
+ * PMCCNTR_EL0 does not count when event counting is prohibited.
+ * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not
+ * available.
+ *
+ * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT)
+ * functionality, if implemented in EL3.
+ * ---------------------------------------------------------------------
+ */
+ msr daifclr, #DAIF_ABT_BIT
+
+ mrs x15, mdcr_el3
+ orr x15, x15, #MDCR_SDD_BIT
+ msr mdcr_el3, x15
+
+ mrs x15, scr_el3
+ orr x15, x15, #SCR_EA_BIT
+ orr x15, x15, #SCR_SIF_BIT
+ msr scr_el3, x15
+
+ mrs x15, pmcr_el0
+ orr x15, x15, #PMCR_EL0_DP_BIT
+ msr pmcr_el0, x15
+
+#if ENABLE_FEAT_DIT
+#if ENABLE_FEAT_DIT > 1
+ mrs x15, id_aa64pfr0_el1
+ ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
+ cbz x15, 1f
+#endif
+ mov x15, #DIT_BIT
+ msr DIT, x15
+ 1:
+#endif
+
+ isb
+ .endm
+
#endif /* EL3_COMMON_MACROS_S */
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index abbf976..de08f1d 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,8 @@
const char *prop_name, uint32_t dflt_value);
int fdt_read_uint64(const void *dtb, int node, const char *prop_name,
uint64_t *value);
+uint64_t fdt_read_uint64_default(const void *dtb, int node,
+ const char *prop_name, uint64_t dflt_value);
int fdt_read_uint32_array(const void *dtb, int node, const char *prop_name,
unsigned int cells, uint32_t *value);
int fdtw_read_string(const void *dtb, int node, const char *prop,
diff --git a/include/common/sha_common_macros.h b/include/common/sha_common_macros.h
new file mode 100644
index 0000000..a419488
--- /dev/null
+++ b/include/common/sha_common_macros.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SHA_COMMON_MACROS_H
+#define SHA_COMMON_MACROS_H
+
+#define MD5_DIGEST_SIZE 16U
+#define SHA1_DIGEST_SIZE 20U
+#define SHA224_DIGEST_SIZE 28U
+#define SHA256_DIGEST_SIZE 32U
+#define SHA384_DIGEST_SIZE 48U
+#define SHA512_224_DIGEST_SIZE 28U
+#define SHA512_256_DIGEST_SIZE 32U
+#define SHA512_DIGEST_SIZE 64U
+
+#endif /* SHA_COMMON_MACROS_H */
diff --git a/include/drivers/arm/dcc.h b/include/drivers/arm/dcc.h
index 072bed5..7f71932 100644
--- a/include/drivers/arm/dcc.h
+++ b/include/drivers/arm/dcc.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2021, Xilinx Inc.
+ * Copyright (c) 2021-2022, Xilinx Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +15,7 @@
* Initialize a new dcc console instance and register it with the console
* framework.
*/
-int console_dcc_register(void);
-void console_dcc_unregister(void);
+int console_dcc_register(console_t *console);
+void console_dcc_unregister(console_t *console);
-#endif /* DCC */
+#endif /* DCC_H */
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index 8bf3b78..4be7414 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -281,7 +281,6 @@
(SDMMC_CDN_##_reg))
/* MMC Peripheral Definition */
-#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
#define MMC_RESPONSE_NONE 0
diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h
index 20a5543..e9fdfb7 100644
--- a/include/drivers/delay_timer.h
+++ b/include/drivers/delay_timer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -25,27 +25,12 @@
uint32_t (*get_timer_value)(void);
uint32_t clk_mult;
uint32_t clk_div;
+ uint64_t (*timeout_init_us)(uint32_t usec);
+ bool (*timeout_elapsed)(uint64_t cnt);
} timer_ops_t;
-static inline uint64_t timeout_cnt_us2cnt(uint32_t us)
-{
- return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL;
-}
-
-static inline uint64_t timeout_init_us(uint32_t us)
-{
- uint64_t cnt = timeout_cnt_us2cnt(us);
-
- cnt += read_cntpct_el0();
-
- return cnt;
-}
-
-static inline bool timeout_elapsed(uint64_t expire_cnt)
-{
- return read_cntpct_el0() > expire_cnt;
-}
-
+uint64_t timeout_init_us(uint32_t usec);
+bool timeout_elapsed(uint64_t cnt);
void mdelay(uint32_t msec);
void udelay(uint32_t usec);
void timer_init(const timer_ops_t *ops_ptr);
diff --git a/include/drivers/measured_boot/event_log/tcg.h b/include/drivers/measured_boot/event_log/tcg.h
index 4ac2c2f..653f9c2 100644
--- a/include/drivers/measured_boot/event_log/tcg.h
+++ b/include/drivers/measured_boot/event_log/tcg.h
@@ -8,6 +8,7 @@
#define TCG_H
#include <stdint.h>
+#include <common/sha_common_macros.h>
#define TCG_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
#define TCG_STARTUP_LOCALITY_SIGNATURE "StartupLocality"
@@ -66,12 +67,6 @@
#define PLATFORM_CLASS_CLIENT 0
#define PLATFORM_CLASS_SERVER 1
-/* SHA digest sizes in bytes */
-#define SHA1_DIGEST_SIZE 20
-#define SHA256_DIGEST_SIZE 32
-#define SHA384_DIGEST_SIZE 48
-#define SHA512_DIGEST_SIZE 64
-
enum {
/*
* SRTM, BIOS, Host Platform Extensions, Embedded
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
index de633ae..d34dc22 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
@@ -95,4 +95,12 @@
#define S32CC_CLK_LINFLEX_BAUD S32CC_ARCH_CLK(16)
#define S32CC_CLK_LINFLEX S32CC_ARCH_CLK(17)
+/* DDR PLL */
+#define S32CC_CLK_DDR_PLL_MUX S32CC_ARCH_CLK(18)
+#define S32CC_CLK_DDR_PLL_VCO S32CC_ARCH_CLK(19)
+
+/* DDR clock */
+#define S32CC_CLK_MC_CGM5_MUX0 S32CC_ARCH_CLK(20)
+#define S32CC_CLK_DDR S32CC_ARCH_CLK(21)
+
#endif /* S32CC_CLK_IDS_H */
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index a6d58cc..4837f79 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -22,6 +22,9 @@
s32cc_clkmux_t,
s32cc_shared_clkmux_t,
s32cc_fixed_div_t,
+ s32cc_part_t,
+ s32cc_part_block_t,
+ s32cc_part_block_link_t,
};
enum s32cc_clk_source {
@@ -33,6 +36,8 @@
S32CC_PERIPH_PLL,
S32CC_CGM0,
S32CC_CGM1,
+ S32CC_DDR_PLL,
+ S32CC_CGM5,
};
struct s32cc_clk_obj {
@@ -208,6 +213,76 @@
#define S32CC_CHILD_CLK(PARENT, MIN_F, MAX_F) \
S32CC_FREQ_CLK(NULL, &(PARENT), MIN_F, MAX_F)
+struct s32cc_part {
+ struct s32cc_clk_obj desc;
+ uint32_t partition_id;
+};
+
+#define S32CC_PART(PART_NUM) \
+{ \
+ .desc = { \
+ .type = s32cc_part_t, \
+ }, \
+ .partition_id = (PART_NUM), \
+}
+
+enum s32cc_part_block_type {
+ s32cc_part_block0,
+ s32cc_part_block1,
+ s32cc_part_block2,
+ s32cc_part_block3,
+ s32cc_part_block4,
+ s32cc_part_block5,
+ s32cc_part_block6,
+ s32cc_part_block7,
+ s32cc_part_block8,
+ s32cc_part_block9,
+ s32cc_part_block10,
+ s32cc_part_block11,
+ s32cc_part_block12,
+ s32cc_part_block13,
+ s32cc_part_block14,
+ s32cc_part_block15,
+};
+
+struct s32cc_part_block {
+ struct s32cc_clk_obj desc;
+ struct s32cc_part *part;
+ enum s32cc_part_block_type block;
+ bool status;
+};
+
+#define S32CC_PART_BLOCK_STATUS(PART_META, BLOCK_TYPE, STATUS) \
+{ \
+ .desc = { \
+ .type = s32cc_part_block_t, \
+ }, \
+ .part = (PART_META), \
+ .block = (BLOCK_TYPE), \
+ .status = (STATUS), \
+}
+
+#define S32CC_PART_BLOCK(PARENT, BLOCK_TYPE) \
+ S32CC_PART_BLOCK_STATUS(PARENT, BLOCK_TYPE, true)
+
+#define S32CC_PART_BLOCK_NO_STATUS(PARENT, BLOCK_TYPE) \
+ S32CC_PART_BLOCK_STATUS(PARENT, BLOCK_TYPE, false)
+
+struct s32cc_part_block_link {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ struct s32cc_part_block *block;
+};
+
+#define S32CC_PART_BLOCK_LINK(PARENT, BLOCK) \
+{ \
+ .desc = { \
+ .type = s32cc_part_block_link_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .block = (BLOCK), \
+}
+
static inline struct s32cc_osc *s32cc_obj2osc(const struct s32cc_clk_obj *mod)
{
uintptr_t osc_addr;
@@ -294,4 +369,30 @@
return (struct s32cc_dfs_div *)dfs_div_addr;
}
+static inline struct s32cc_part *s32cc_obj2part(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t part_addr;
+
+ part_addr = ((uintptr_t)mod) - offsetof(struct s32cc_part, desc);
+ return (struct s32cc_part *)part_addr;
+}
+
+static inline struct s32cc_part_block *
+s32cc_obj2partblock(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t part_blk_addr;
+
+ part_blk_addr = ((uintptr_t)mod) - offsetof(struct s32cc_part_block, desc);
+ return (struct s32cc_part_block *)part_blk_addr;
+}
+
+static inline struct s32cc_part_block_link *
+s32cc_obj2partblocklink(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t blk_link;
+
+ blk_link = ((uintptr_t)mod) - offsetof(struct s32cc_part_block_link, desc);
+ return (struct s32cc_part_block_link *)blk_link;
+}
+
#endif /* S32CC_CLK_MODULES_H */
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
index 6a90406..e6adecc 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
@@ -11,7 +11,12 @@
size_t size,
unsigned long clk_id);
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+ size_t size, const struct s32cc_clk *clk,
+ unsigned long *clk_index);
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id);
void s32cc_clk_register_drv(void);
diff --git a/include/drivers/nxp/crypto/caam/hash.h b/include/drivers/nxp/crypto/caam/hash.h
index 9136dca..6201d23 100644
--- a/include/drivers/nxp/crypto/caam/hash.h
+++ b/include/drivers/nxp/crypto/caam/hash.h
@@ -9,6 +9,7 @@
#define __HASH_H__
#include <stdbool.h>
+#include <common/sha_common_macros.h>
/* List of hash algorithms */
enum hash_algo {
@@ -16,9 +17,6 @@
SHA256
};
-/* number of bytes in the SHA256-256 digest */
-#define SHA256_DIGEST_SIZE 32
-
/*
* number of words in the digest - Digest is kept internally
* as 8 32-bit words
diff --git a/include/drivers/st/stm32mp2_ddr.h b/include/drivers/st/stm32mp2_ddr.h
new file mode 100644
index 0000000..6b0462c
--- /dev/null
+++ b/include/drivers/st/stm32mp2_ddr.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32MP2_DDR_H
+#define STM32MP2_DDR_H
+
+#include <stdbool.h>
+
+#include <ddrphy_phyinit_struct.h>
+
+#include <drivers/st/stm32mp_ddr.h>
+
+struct stm32mp2_ddrctrl_reg {
+ uint32_t mstr;
+ uint32_t mrctrl0;
+ uint32_t mrctrl1;
+ uint32_t mrctrl2;
+ uint32_t derateen;
+ uint32_t derateint;
+ uint32_t deratectl;
+ uint32_t pwrctl;
+ uint32_t pwrtmg;
+ uint32_t hwlpctl;
+ uint32_t rfshctl0;
+ uint32_t rfshctl1;
+ uint32_t rfshctl3;
+ uint32_t crcparctl0;
+ uint32_t crcparctl1;
+ uint32_t init0;
+ uint32_t init1;
+ uint32_t init2;
+ uint32_t init3;
+ uint32_t init4;
+ uint32_t init5;
+ uint32_t init6;
+ uint32_t init7;
+ uint32_t dimmctl;
+ uint32_t rankctl;
+ uint32_t rankctl1;
+ uint32_t zqctl0;
+ uint32_t zqctl1;
+ uint32_t zqctl2;
+ uint32_t dfitmg0;
+ uint32_t dfitmg1;
+ uint32_t dfilpcfg0;
+ uint32_t dfilpcfg1;
+ uint32_t dfiupd0;
+ uint32_t dfiupd1;
+ uint32_t dfiupd2;
+ uint32_t dfimisc;
+ uint32_t dfitmg2;
+ uint32_t dfitmg3;
+ uint32_t dbictl;
+ uint32_t dfiphymstr;
+ uint32_t dbg0;
+ uint32_t dbg1;
+ uint32_t dbgcmd;
+ uint32_t swctl;
+ uint32_t swctlstatic;
+ uint32_t poisoncfg;
+ uint32_t pccfg;
+};
+
+struct stm32mp2_ddrctrl_timing {
+ uint32_t rfshtmg;
+ uint32_t rfshtmg1;
+ uint32_t dramtmg0;
+ uint32_t dramtmg1;
+ uint32_t dramtmg2;
+ uint32_t dramtmg3;
+ uint32_t dramtmg4;
+ uint32_t dramtmg5;
+ uint32_t dramtmg6;
+ uint32_t dramtmg7;
+ uint32_t dramtmg8;
+ uint32_t dramtmg9;
+ uint32_t dramtmg10;
+ uint32_t dramtmg11;
+ uint32_t dramtmg12;
+ uint32_t dramtmg13;
+ uint32_t dramtmg14;
+ uint32_t dramtmg15;
+ uint32_t odtcfg;
+ uint32_t odtmap;
+};
+
+struct stm32mp2_ddrctrl_map {
+ uint32_t addrmap0;
+ uint32_t addrmap1;
+ uint32_t addrmap2;
+ uint32_t addrmap3;
+ uint32_t addrmap4;
+ uint32_t addrmap5;
+ uint32_t addrmap6;
+ uint32_t addrmap7;
+ uint32_t addrmap8;
+ uint32_t addrmap9;
+ uint32_t addrmap10;
+ uint32_t addrmap11;
+};
+
+struct stm32mp2_ddrctrl_perf {
+ uint32_t sched;
+ uint32_t sched1;
+ uint32_t perfhpr1;
+ uint32_t perflpr1;
+ uint32_t perfwr1;
+ uint32_t sched3;
+ uint32_t sched4;
+ uint32_t pcfgr_0;
+ uint32_t pcfgw_0;
+ uint32_t pctrl_0;
+ uint32_t pcfgqos0_0;
+ uint32_t pcfgqos1_0;
+ uint32_t pcfgwqos0_0;
+ uint32_t pcfgwqos1_0;
+#if STM32MP_DDR_DUAL_AXI_PORT
+ uint32_t pcfgr_1;
+ uint32_t pcfgw_1;
+ uint32_t pctrl_1;
+ uint32_t pcfgqos0_1;
+ uint32_t pcfgqos1_1;
+ uint32_t pcfgwqos0_1;
+ uint32_t pcfgwqos1_1;
+#endif /* STM32MP_DDR_DUAL_AXI_PORT */
+};
+
+struct stm32mp_ddr_config {
+ struct stm32mp_ddr_info info;
+ struct stm32mp2_ddrctrl_reg c_reg;
+ struct stm32mp2_ddrctrl_timing c_timing;
+ struct stm32mp2_ddrctrl_map c_map;
+ struct stm32mp2_ddrctrl_perf c_perf;
+ bool self_refresh;
+ uint32_t zdata;
+ struct user_input_basic uib;
+ struct user_input_advanced uia;
+ struct user_input_mode_register uim;
+ struct user_input_swizzle uis;
+};
+
+void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config);
+
+#endif /* STM32MP2_DDR_H */
diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
index 069fb83..9329fff 100644
--- a/include/drivers/st/stm32mp2_ddr_helpers.h
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h
@@ -7,6 +7,29 @@
#ifndef STM32MP2_DDR_HELPERS_H
#define STM32MP2_DDR_HELPERS_H
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <drivers/st/stm32mp2_ddr_regs.h>
+
+enum stm32mp2_ddr_sr_mode {
+ DDR_SR_MODE_INVALID = 0,
+ DDR_SSR_MODE,
+ DDR_HSR_MODE,
+ DDR_ASR_MODE,
+};
+
+void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
+void ddr_wait_lp3_mode(bool state);
+int ddr_sr_exit_loop(void);
+uint32_t ddr_get_io_calibration_val(void);
+int ddr_sr_entry(bool standby);
+int ddr_sr_exit(void);
+enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);
+void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode);
+void ddr_save_sr_mode(void);
+void ddr_restore_sr_mode(void);
void ddr_sub_system_clk_init(void);
+void ddr_sub_system_clk_off(void);
#endif /* STM32MP2_DDR_HELPERS_H */
diff --git a/include/drivers/st/stm32mp2_ddr_regs.h b/include/drivers/st/stm32mp2_ddr_regs.h
new file mode 100644
index 0000000..9370f1c
--- /dev/null
+++ b/include/drivers/st/stm32mp2_ddr_regs.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32MP2_DDR_REGS_H
+#define STM32MP2_DDR_REGS_H
+
+#include <drivers/st/stm32mp_ddrctrl_regs.h>
+#include <lib/utils_def.h>
+
+/* DDR Physical Interface Control (DDRPHYC) registers*/
+struct stm32mp_ddrphy {
+ uint32_t dummy;
+} __packed;
+
+/* DDRPHY registers offsets */
+#define DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6 U(0x240004)
+#define DDRPHY_INITENG0_P0_PHYINLPX U(0x2400A0)
+#define DDRPHY_DRTUB0_UCCLKHCLKENABLES U(0x300200)
+#define DDRPHY_APBONLY0_MICROCONTMUXSEL U(0x340000)
+
+/* DDRPHY registers fields */
+#define DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3 BIT(0)
+#define DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN BIT(0)
+#define DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN BIT(1)
+#define DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL BIT(0)
+
+/* DDRDBG registers offsets */
+#define DDRDBG_LP_DISABLE U(0x0)
+#define DDRDBG_BYPASS_PCLKEN U(0x4)
+
+/* DDRDBG registers fields */
+#define DDRDBG_LP_DISABLE_LPI_XPI_DISABLE BIT(0)
+#define DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE BIT(8)
+
+#endif /* STM32MP2_DDR_REGS_H */
diff --git a/include/drivers/st/stm32mp2_ram.h b/include/drivers/st/stm32mp2_ram.h
new file mode 100644
index 0000000..b6fa928
--- /dev/null
+++ b/include/drivers/st/stm32mp2_ram.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_RAM_H
+#define STM32MP2_RAM_H
+
+bool stm32mp2_ddr_is_restored(void);
+int stm32mp2_ddr_probe(void);
+
+#endif /* STM32MP2_RAM_H */
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 4535e3c..57b0668 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -26,9 +26,11 @@
};
struct stm32mp_ddr_reg_desc {
- const char *name;
uint16_t offset; /* Offset for base address */
uint8_t par_offset; /* Offset for parameter array */
+#if !STM32MP13 && !STM32MP15
+ bool qd; /* quasi-dynamic register if true */
+#endif
};
struct stm32mp_ddr_reg_info {
@@ -57,13 +59,26 @@
size_t size; /* Memory size in byte = col * row * width */
};
-#define TIMEOUT_US_1S 1000000U
+#define DDR_DELAY_1US 1U
+#define DDR_DELAY_2US 2U
+#define DDR_DELAY_10US 10U
+#define DDR_DELAY_50US 50U
+#define DDR_TIMEOUT_500US 500U
+#define DDR_TIMEOUT_US_1S 1000000U
void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
const void *param, const struct stm32mp_ddr_reg_info *ddr_registers);
void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
+int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl);
+int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_unset_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_wait_refresh_update_done_ack(struct stm32mp_ddrctl *ctl);
int stm32mp_board_ddr_power_init(enum ddr_type ddr_type);
#endif /* STM32MP_DDR_H */
diff --git a/include/drivers/st/stm32mp_ddrctrl_regs.h b/include/drivers/st/stm32mp_ddrctrl_regs.h
index 79de86b..f9f46aa 100644
--- a/include/drivers/st/stm32mp_ddrctrl_regs.h
+++ b/include/drivers/st/stm32mp_ddrctrl_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -51,7 +51,8 @@
uint32_t init7; /* 0xec SDRAM Initialization 7 */
uint32_t dimmctl; /* 0xf0 DIMM Control */
uint32_t rankctl; /* 0xf4 Rank Control */
- uint8_t reserved0f4[0x100 - 0xf8];
+ uint32_t rankctl1; /* 0xf8 Rank Control 1 */
+ uint8_t reserved0fc[0x100 - 0xfc];
uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */
uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */
uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */
@@ -112,7 +113,9 @@
uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */
uint32_t reserved268;
uint32_t perfwr1; /* 0x26c Write CAM 1 */
- uint8_t reserved27c[0x300 - 0x270];
+ uint32_t sched3; /* 0x270 Scheduler Control 3 */
+ uint32_t sched4; /* 0x274 Scheduler Control 4 */
+ uint8_t reserved278[0x300 - 0x278];
uint32_t dbg0; /* 0x300 Debug 0 */
uint32_t dbg1; /* 0x304 Debug 1 */
uint32_t dbgcam; /* 0x308 CAM Debug */
@@ -121,7 +124,8 @@
uint8_t reserved314[0x320 - 0x314];
uint32_t swctl; /* 0x320 Software Programming Control Enable */
uint32_t swstat; /* 0x324 Software Programming Control Status */
- uint8_t reserved328[0x36c - 0x328];
+ uint32_t swctlstatic; /* 0x328 Statics Write Enable */
+ uint8_t reserved32c[0x36c - 0x32c];
uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
uint32_t poisonstat; /* 0x370 AXI Poison Status Register */
uint8_t reserved374[0x3f0 - 0x374];
@@ -153,7 +157,7 @@
uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
-#endif
+#endif /* STM32MP_DDR_DUAL_AXI_PORT */
uint8_t reserved554[0xff0 - 0x554];
uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */
@@ -170,6 +174,7 @@
#define DDRCTRL_RFSHCTL3 0x060
#define DDRCTRL_RFSHTMG 0x064
#define DDRCTRL_INIT0 0x0D0
+#define DDRCTRL_DFILPCFG0 0x198
#define DDRCTRL_DFIMISC 0x1B0
#define DDRCTRL_DBG1 0x304
#define DDRCTRL_DBGCAM 0x308
@@ -181,7 +186,7 @@
#define DDRCTRL_PCTRL_0 0x490
#if STM32MP_DDR_DUAL_AXI_PORT
#define DDRCTRL_PCTRL_1 0x540
-#endif
+#endif /* STM32MP_DDR_DUAL_AXI_PORT */
/* DDR Controller Register fields */
#define DDRCTRL_MSTR_DDR3 BIT(0)
@@ -201,6 +206,8 @@
#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5))
#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5)
+#define DDRCTRL_STAT_SELFREF_STATE_MASK GENMASK(9, 8)
+#define DDRCTRL_STAT_SELFREF_STATE_SRPD BIT(9)
#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0)
/* Only one rank supported */
@@ -217,6 +224,7 @@
#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
+#define DDRCTRL_PWRCTL_STAY_IN_SELFREF BIT(6)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
@@ -225,6 +233,9 @@
#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL BIT(1)
#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
+#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN BIT(1)
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_MASK GENMASK(27, 16)
+#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_SHIFT 16
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
@@ -232,21 +243,31 @@
#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30)
+#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR BIT(8)
+
#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
#define DDRCTRL_DFIMISC_DFI_INIT_START BIT(5)
+#define DDRCTRL_DFIMISC_DFI_FREQUENCY GENMASK(12, 8)
#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE BIT(0)
+#define DDRCTRL_DFISTAT_DFI_LP_ACK BIT(1)
+#define DDRCTRL_DBG1_DIS_DQ BIT(0)
#define DDRCTRL_DBG1_DIS_HIF BIT(1)
#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
+#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY BIT(25)
#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
(DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
+#define DDRCTRL_DBG_Q_AND_DATA_PIPELINE_EMPTY \
+ (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
+ DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY | \
+ DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY)
#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
(DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h
index 303c571..7384571 100644
--- a/include/drivers/st/stm32mp_pmic.h
+++ b/include/drivers/st/stm32mp_pmic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,13 +42,6 @@
#endif
/*
- * pmic_ddr_power_init - Initialize regulators required for DDR
- *
- * Returns 0 on success, and negative values on errors
- */
-int pmic_ddr_power_init(enum ddr_type ddr_type);
-
-/*
* pmic_voltages_init - Update voltages for platform init
*
* Returns 0 on success, and negative values on errors
diff --git a/include/drivers/st/stm32mp_pmic2.h b/include/drivers/st/stm32mp_pmic2.h
new file mode 100644
index 0000000..51eba38
--- /dev/null
+++ b/include/drivers/st/stm32mp_pmic2.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_PMIC2_H
+#define STM32MP_PMIC2_H
+
+#include <stdbool.h>
+#include <drivers/st/regulator.h>
+
+#include <platform_def.h>
+
+/*
+ * dt_pmic_status - Check PMIC status from device tree
+ *
+ * Returns the status of the PMIC (secure, non-secure), or a negative value on
+ * error
+ */
+int dt_pmic_status(void);
+
+/*
+ * initialize_pmic_i2c - Initialize I2C for the PMIC control
+ *
+ * Returns true if PMIC is available, false if not found, panics on errors
+ */
+bool initialize_pmic_i2c(void);
+
+/*
+ * initialize_pmic - Main PMIC initialization function, called at platform init
+ *
+ * Panics on errors
+ */
+void initialize_pmic(void);
+
+/*
+ * stpmic2_set_prop - Set PMIC2 proprietary property
+ *
+ * Returns non zero on errors
+ */
+int stpmic2_set_prop(const struct regul_description *desc, uint16_t prop, uint32_t value);
+
+/*
+ * pmic_switch_off - switch off the platform with PMIC
+ *
+ * Panics on errors
+ */
+void pmic_switch_off(void);
+
+#endif /* STM32MP_PMIC2_H */
diff --git a/include/drivers/st/stpmic2.h b/include/drivers/st/stpmic2.h
new file mode 100644
index 0000000..58ba64a
--- /dev/null
+++ b/include/drivers/st/stpmic2.h
@@ -0,0 +1,307 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STPMIC2_H
+#define STPMIC2_H
+
+#include <drivers/st/stm32_i2c.h>
+#include <lib/utils_def.h>
+
+enum {
+ STPMIC2_BUCK1 = 0,
+ STPMIC2_BUCK2,
+ STPMIC2_BUCK3,
+ STPMIC2_BUCK4,
+ STPMIC2_BUCK5,
+ STPMIC2_BUCK6,
+ STPMIC2_BUCK7,
+ STPMIC2_REFDDR,
+ STPMIC2_LDO1,
+ STPMIC2_LDO2,
+ STPMIC2_LDO3,
+ STPMIC2_LDO4,
+ STPMIC2_LDO5,
+ STPMIC2_LDO6,
+ STPMIC2_LDO7,
+ STPMIC2_LDO8,
+ STPMIC2_NB_REG
+};
+
+/* Status Registers */
+#define PRODUCT_ID 0x00
+#define VERSION_SR 0x01
+#define TURN_ON_SR 0x02
+#define TURN_OFF_SR 0x03
+#define RESTART_SR 0x04
+#define OCP_SR1 0x05
+#define OCP_SR2 0x06
+#define EN_SR1 0x07
+#define EN_SR2 0x08
+#define FS_CNT_SR1 0x09
+#define FS_CNT_SR2 0x0A
+#define FS_CNT_SR3 0x0B
+#define MODE_SR 0x0C
+/* Control Registers */
+#define MAIN_CR 0x10
+#define VINLOW_CR 0x11
+#define PKEY_LKP_CR 0x12
+#define WDG_CR 0x13
+#define WDG_TMR_CR 0x14
+#define WDG_TMR_SR 0x15
+#define FS_OCP_CR1 0x16
+#define FS_OCP_CR2 0x17
+#define PADS_PULL_CR 0x18
+#define BUCKS_PD_CR1 0x19
+#define BUCKS_PD_CR2 0x1A
+#define LDOS_PD_CR1 0x1B
+#define LDOS_PD_CR2 0x1C
+#define BUCKS_MRST_CR 0x1D
+#define LDOS_MRST_CR 0x1E
+/* Buck CR */
+#define BUCK1_MAIN_CR1 0x20
+#define BUCK1_MAIN_CR2 0x21
+#define BUCK1_ALT_CR1 0x22
+#define BUCK1_ALT_CR2 0x23
+#define BUCK1_PWRCTRL_CR 0x24
+#define BUCK2_MAIN_CR1 0x25
+#define BUCK2_MAIN_CR2 0x26
+#define BUCK2_ALT_CR1 0x27
+#define BUCK2_ALT_CR2 0x28
+#define BUCK2_PWRCTRL_CR 0x29
+#define BUCK3_MAIN_CR1 0x2A
+#define BUCK3_MAIN_CR2 0x2B
+#define BUCK3_ALT_CR1 0x2C
+#define BUCK3_ALT_CR2 0x2D
+#define BUCK3_PWRCTRL_CR 0x2E
+#define BUCK4_MAIN_CR1 0x2F
+#define BUCK4_MAIN_CR2 0x30
+#define BUCK4_ALT_CR1 0x31
+#define BUCK4_ALT_CR2 0x32
+#define BUCK4_PWRCTRL_CR 0x33
+#define BUCK5_MAIN_CR1 0x34
+#define BUCK5_MAIN_CR2 0x35
+#define BUCK5_ALT_CR1 0x36
+#define BUCK5_ALT_CR2 0x37
+#define BUCK5_PWRCTRL_CR 0x38
+#define BUCK6_MAIN_CR1 0x39
+#define BUCK6_MAIN_CR2 0x3A
+#define BUCK6_ALT_CR1 0x3B
+#define BUCK6_ALT_CR2 0x3C
+#define BUCK6_PWRCTRL_CR 0x3D
+#define BUCK7_MAIN_CR1 0x3E
+#define BUCK7_MAIN_CR2 0x3F
+#define BUCK7_ALT_CR1 0x40
+#define BUCK7_ALT_CR2 0x41
+#define BUCK7_PWRCTRL_CR 0x42
+/* LDO CR */
+#define LDO1_MAIN_CR 0x4C
+#define LDO1_ALT_CR 0x4D
+#define LDO1_PWRCTRL_CR 0x4E
+#define LDO2_MAIN_CR 0x4F
+#define LDO2_ALT_CR 0x50
+#define LDO2_PWRCTRL_CR 0x51
+#define LDO3_MAIN_CR 0x52
+#define LDO3_ALT_CR 0x53
+#define LDO3_PWRCTRL_CR 0x54
+#define LDO4_MAIN_CR 0x55
+#define LDO4_ALT_CR 0x56
+#define LDO4_PWRCTRL_CR 0x57
+#define LDO5_MAIN_CR 0x58
+#define LDO5_ALT_CR 0x59
+#define LDO5_PWRCTRL_CR 0x5A
+#define LDO6_MAIN_CR 0x5B
+#define LDO6_ALT_CR 0x5C
+#define LDO6_PWRCTRL_CR 0x5D
+#define LDO7_MAIN_CR 0x5E
+#define LDO7_ALT_CR 0x5F
+#define LDO7_PWRCTRL_CR 0x60
+#define LDO8_MAIN_CR 0x61
+#define LDO8_ALT_CR 0x62
+#define LDO8_PWRCTRL_CR 0x63
+#define REFDDR_MAIN_CR 0x64
+#define REFDDR_ALT_CR 0x65
+#define REFDDR_PWRCTRL_CR 0x66
+/* INTERRUPT CR */
+#define INT_PENDING_R1 0x70
+#define INT_PENDING_R2 0x71
+#define INT_PENDING_R3 0x72
+#define INT_PENDING_R4 0x73
+#define INT_CLEAR_R1 0x74
+#define INT_CLEAR_R2 0x75
+#define INT_CLEAR_R3 0x76
+#define INT_CLEAR_R4 0x77
+#define INT_MASK_R1 0x78
+#define INT_MASK_R2 0x79
+#define INT_MASK_R3 0x7A
+#define INT_MASK_R4 0x7B
+#define INT_SRC_R1 0x7C
+#define INT_SRC_R2 0x7D
+#define INT_SRC_R3 0x7E
+#define INT_SRC_R4 0x7F
+#define INT_DBG_LATCH_R1 0x80
+#define INT_DBG_LATCH_R2 0x81
+#define INT_DBG_LATCH_R3 0x82
+#define INT_DBG_LATCH_R4 0x83
+
+/* BUCKS_MRST_CR bits definition */
+#define BUCK1_MRST BIT(0)
+#define BUCK2_MRST BIT(1)
+#define BUCK3_MRST BIT(2)
+#define BUCK4_MRST BIT(3)
+#define BUCK5_MRST BIT(4)
+#define BUCK6_MRST BIT(5)
+#define BUCK7_MRST BIT(6)
+#define REFDDR_MRST BIT(7)
+
+/* LDOS_MRST_CR bits definition */
+#define LDO1_MRST BIT(0)
+#define LDO2_MRST BIT(1)
+#define LDO3_MRST BIT(2)
+#define LDO4_MRST BIT(3)
+#define LDO5_MRST BIT(4)
+#define LDO6_MRST BIT(5)
+#define LDO7_MRST BIT(6)
+#define LDO8_MRST BIT(7)
+
+/* LDOx_MAIN_CR */
+#define LDO_VOLT_SHIFT 1
+#define LDO_BYPASS BIT(6)
+#define LDO1_INPUT_SRC BIT(7)
+#define LDO3_SNK_SRC BIT(7)
+#define LDO4_INPUT_SRC_SHIFT 6
+#define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6)
+
+/* PWRCTRL register bit definition */
+#define PWRCTRL_EN BIT(0)
+#define PWRCTRL_RS BIT(1)
+#define PWRCTRL_SEL_SHIFT 2
+#define PWRCTRL_SEL_MASK GENMASK_32(3, 2)
+
+/* BUCKx_MAIN_CR2 */
+#define PREG_MODE_SHIFT 1
+#define PREG_MODE_MASK GENMASK_32(2, 1)
+
+/* BUCKS_PD_CR1 */
+#define BUCK1_PD_MASK GENMASK_32(1, 0)
+#define BUCK2_PD_MASK GENMASK_32(3, 2)
+#define BUCK3_PD_MASK GENMASK_32(5, 4)
+#define BUCK4_PD_MASK GENMASK_32(7, 6)
+
+#define BUCK1_PD_FAST BIT(1)
+#define BUCK2_PD_FAST BIT(3)
+#define BUCK3_PD_FAST BIT(5)
+#define BUCK4_PD_FAST BIT(7)
+
+/* BUCKS_PD_CR2 */
+#define BUCK5_PD_MASK GENMASK_32(1, 0)
+#define BUCK6_PD_MASK GENMASK_32(3, 2)
+#define BUCK7_PD_MASK GENMASK_32(5, 4)
+
+#define BUCK5_PD_FAST BIT(1)
+#define BUCK6_PD_FAST BIT(3)
+#define BUCK7_PD_FAST BIT(5)
+
+/* LDOS_PD_CR1 */
+#define LDO1_PD BIT(0)
+#define LDO2_PD BIT(1)
+#define LDO3_PD BIT(2)
+#define LDO4_PD BIT(3)
+#define LDO5_PD BIT(4)
+#define LDO6_PD BIT(5)
+#define LDO7_PD BIT(6)
+#define LDO8_PD BIT(7)
+
+/* LDOS_PD_CR2 */
+#define REFDDR_PD BIT(0)
+
+/* FS_OCP_CR1 */
+#define FS_OCP_BUCK1 BIT(0)
+#define FS_OCP_BUCK2 BIT(1)
+#define FS_OCP_BUCK3 BIT(2)
+#define FS_OCP_BUCK4 BIT(3)
+#define FS_OCP_BUCK5 BIT(4)
+#define FS_OCP_BUCK6 BIT(5)
+#define FS_OCP_BUCK7 BIT(6)
+#define FS_OCP_REFDDR BIT(7)
+
+/* FS_OCP_CR2 */
+#define FS_OCP_LDO1 BIT(0)
+#define FS_OCP_LDO2 BIT(1)
+#define FS_OCP_LDO3 BIT(2)
+#define FS_OCP_LDO4 BIT(3)
+#define FS_OCP_LDO5 BIT(4)
+#define FS_OCP_LDO6 BIT(5)
+#define FS_OCP_LDO7 BIT(6)
+#define FS_OCP_LDO8 BIT(7)
+
+/* IRQ definitions */
+#define IT_PONKEY_F 0
+#define IT_PONKEY_R 1
+#define IT_BUCK1_OCP 16
+#define IT_BUCK2_OCP 17
+#define IT_BUCK3_OCP 18
+#define IT_BUCK4_OCP 19
+#define IT_BUCK5_OCP 20
+#define IT_BUCK6_OCP 21
+#define IT_BUCK7_OCP 22
+#define IT_REFDDR_OCP 23
+#define IT_LDO1_OCP 24
+#define IT_LDO2_OCP 25
+#define IT_LDO3_OCP 26
+#define IT_LDO4_OCP 27
+#define IT_LDO5_OCP 28
+#define IT_LDO6_OCP 29
+#define IT_LDO7_OCP 30
+#define IT_LDO8_OCP 31
+
+enum stpmic2_prop_id {
+ STPMIC2_MASK_RESET = 0,
+ STPMIC2_PULL_DOWN,
+ STPMIC2_BYPASS, /* arg: 1=set 0=reset */
+ STPMIC2_SINK_SOURCE,
+ STPMIC2_OCP,
+};
+
+struct pmic_handle_s {
+ struct i2c_handle_s *i2c_handle;
+ uint32_t i2c_addr;
+ unsigned int pmic_status;
+};
+
+int stpmic2_register_read(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t *value);
+int stpmic2_register_write(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value);
+int stpmic2_register_update(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value, uint8_t mask);
+
+int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool enable);
+int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool *enabled);
+
+int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
+ uint8_t id, const uint16_t **levels,
+ size_t *levels_count);
+int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t *val);
+int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t millivolts);
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+void stpmic2_dump_regulators(struct pmic_handle_s *pmic);
+#endif
+
+int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val);
+int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val);
+
+int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop);
+
+int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop, uint32_t arg);
+
+#endif /*STPMIC2_H*/
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index ca79991..7a97ed1 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -50,6 +50,11 @@
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
+
+#if ERRATA_A75_764081
+long check_erratum_cortex_a75_764081(long cpu_rev);
+#endif /* ERRATA_A75_764081 */
+
#endif /* __ASSEMBLER__ */
#endif /* CORTEX_A75_H */
diff --git a/include/lib/cpus/aarch64/cortex_arcadia.h b/include/lib/cpus/aarch64/cortex_arcadia.h
new file mode 100644
index 0000000..8b74de2
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_arcadia.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_ARCADIA_H
+#define CORTEX_ARCADIA_H
+
+#define CORTEX_ARCADIA_MIDR U(0x410FD8F0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_ARCADIA_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_ARCADIA_CPUECTLR_EL1_EXTLLC_BIT U(0)
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_ARCADIA_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_ARCADIA_H */
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
index 4b6af8b..f701216 100644
--- a/include/lib/cpus/aarch64/cortex_x4.h
+++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -26,7 +26,9 @@
/*******************************************************************************
* CPU Auxiliary control register specific definitions
******************************************************************************/
+#define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
+#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3
/*******************************************************************************
* CPU Auxiliary control register 5 specific definitions
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 98294b9..5e92934 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -433,7 +433,7 @@
*
* _get_rev:
* Optional parameter that determines whether to insert a call to the CPU revision fetching
- * procedure. Stores the result of this in the temporary register x10.
+ * procedure. Stores the result of this in the temporary register x10 to allow for chaining
*
* clobbers: x0-x10 (PCS compliant)
*/
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index ef1b02b..2c31515 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -35,6 +35,15 @@
void print_errata_status(void);
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void);
+#else
+static inline bool errata_a75_764081_applies(void)
+{
+ return false;
+}
+#endif
+
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void);
#endif
diff --git a/include/lib/el3_runtime/context_el1.h b/include/lib/el3_runtime/context_el1.h
index 038de25..94af210 100644
--- a/include/lib/el3_runtime/context_el1.h
+++ b/include/lib/el3_runtime/context_el1.h
@@ -107,6 +107,15 @@
uint64_t gcspr_el0;
} el1_gcs_regs_t;
+typedef struct el1_the_regs {
+ uint64_t rcwmask_el1;
+ uint64_t rcwsmask_el1;
+} el1_the_regs_t;
+
+typedef struct el1_sctlr2_regs {
+ uint64_t sctlr2_el1;
+} el1_sctlr2_regs_t;
+
typedef struct el1_sysregs {
el1_common_regs_t common;
@@ -155,6 +164,14 @@
el1_gcs_regs_t gcs;
#endif
+#if ENABLE_FEAT_THE
+ el1_the_regs_t the;
+#endif
+
+#if ENABLE_FEAT_SCTLR2
+ el1_sctlr2_regs_t sctlr2;
+#endif
+
} el1_sysregs_t;
@@ -266,6 +283,25 @@
#define read_el1_ctx_gcs(ctx, reg) ULL(0)
#define write_el1_ctx_gcs(ctx, reg, val)
#endif /* ENABLE_FEAT_GCS */
+
+#if ENABLE_FEAT_THE
+#define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg)
+#define write_el1_ctx_the(ctx, reg, val) ((((ctx)->the).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_the(ctx, reg) ULL(0)
+#define write_el1_ctx_the(ctx, reg, val)
+#endif /* ENABLE_FEAT_THE */
+
+#if ENABLE_FEAT_SCTLR2
+#define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg)
+#define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_sctlr2(ctx, reg) ULL(0)
+#define write_el1_ctx_sctlr2(ctx, reg, val)
+#endif /* ENABLE_FEAT_SCTLR2 */
+
/******************************************************************************/
#endif /* __ASSEMBLER__ */
diff --git a/include/lib/el3_runtime/context_el2.h b/include/lib/el3_runtime/context_el2.h
index 14c1fb6..ad0b68f 100644
--- a/include/lib/el3_runtime/context_el2.h
+++ b/include/lib/el3_runtime/context_el2.h
@@ -135,6 +135,10 @@
uint64_t mpamvpmv_el2;
} el2_mpam_regs_t;
+typedef struct el2_sctlr2_regs {
+ uint64_t sctlr2_el2;
+} el2_sctlr2_regs_t;
+
typedef struct el2_sysregs {
el2_common_regs_t common;
@@ -203,6 +207,10 @@
el2_mpam_regs_t mpam;
#endif
+#if ENABLE_FEAT_SCTLR2
+ el2_sctlr2_regs_t sctlr2;
+#endif
+
} el2_sysregs_t;
/*
@@ -358,6 +366,15 @@
#define write_el2_ctx_mpam(ctx, reg, val)
#endif /* CTX_INCLUDE_MPAM_REGS */
+#if ENABLE_FEAT_SCTLR2
+#define read_el2_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg)
+#define write_el2_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el2_ctx_sctlr2(ctx, reg) ULL(0)
+#define write_el2_ctx_sctlr2(ctx, reg, val)
+#endif /* ENABLE_FEAT_SCTLR2 */
+
/******************************************************************************/
#endif /* __ASSEMBLER__ */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 2c7b619..8b54806 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -59,8 +59,19 @@
#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
#endif
+/* buffer space for EHF data is sizeof(pe_exc_data_t) */
+#define CPU_DATA_EHF_DATA_SIZE 8
+#define CPU_DATA_EHF_DATA_BUF_OFFSET CPU_DATA_CRASH_BUF_END
+
+#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
+#define CPU_DATA_EHF_DATA_BUF_END (CPU_DATA_EHF_DATA_BUF_OFFSET + \
+ CPU_DATA_EHF_DATA_SIZE)
+#else
+#define CPU_DATA_EHF_DATA_BUF_END CPU_DATA_EHF_DATA_BUF_OFFSET
+#endif /* EL3_EXCEPTION_HANDLING */
+
/* cpu_data size is the data size rounded up to the platform cache line size */
-#define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \
+#define CPU_DATA_SIZE (((CPU_DATA_EHF_DATA_BUF_END + \
CACHE_WRITEBACK_GRANULE - 1) / \
CACHE_WRITEBACK_GRANULE) * \
CACHE_WRITEBACK_GRANULE)
@@ -68,7 +79,7 @@
#if ENABLE_RUNTIME_INSTRUMENTATION
/* Temporary space to store PMF timestamps from assembly code */
#define CPU_DATA_PMF_TS_COUNT 1
-#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
+#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_EHF_DATA_BUF_END
#define CPU_DATA_PMF_TS0_IDX 0
#endif
@@ -159,6 +170,12 @@
assert_cpu_data_crash_stack_offset_mismatch);
#endif
+#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
+CASSERT(CPU_DATA_EHF_DATA_BUF_OFFSET == __builtin_offsetof
+ (cpu_data_t, ehf_data),
+ assert_cpu_data_ehf_stack_offset_mismatch);
+#endif
+
CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
assert_cpu_data_size_mismatch);
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 83a5cd2..c3756bf 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -262,6 +262,9 @@
/* BL2 at EL3 functions */
void arm_bl2_el3_early_platform_setup(void);
void arm_bl2_el3_plat_arch_setup(void);
+#if ARM_FW_CONFIG_LOAD_ENABLE
+void arm_bl2_el3_plat_config_load(void);
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
/* BL2U utility functions */
void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index ae5aa23..118b537 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -15,6 +15,7 @@
#endif
#if ENABLE_RME
#include <services/rmm_core_manifest.h>
+#include <services/rmm_el3_token_sign.h>
#endif
#include <drivers/fwu/fwu_metadata.h>
#if TRNG_SUPPORT
@@ -376,6 +377,15 @@
uint64_t *remaining_len);
int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
unsigned int type);
+/* The following 3 functions are to be implement if
+ * RMMD_ENABLE_EL3_TOKEN_SIGN=1.
+ * The following three functions are expected to return E_RMM_* error codes.
+ */
+int plat_rmmd_el3_token_sign_get_rak_pub(uintptr_t buf, size_t *len,
+ unsigned int type);
+int plat_rmmd_el3_token_sign_push_req(
+ const struct el3_token_sign_request *req);
+int plat_rmmd_el3_token_sign_pull_resp(struct el3_token_sign_response *resp);
size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared);
int plat_rmmd_load_manifest(struct rmm_manifest *manifest);
#endif
diff --git a/include/services/rmm_el3_token_sign.h b/include/services/rmm_el3_token_sign.h
new file mode 100644
index 0000000..154940c
--- /dev/null
+++ b/include/services/rmm_el3_token_sign.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RMM_EL3_TOKEN_SIGN_H
+#define RMM_EL3_TOKEN_SIGN_H
+
+#include <stdint.h>
+#include <lib/cassert.h>
+#include <services/rmmd_svc.h>
+
+/*
+ * Defines member of structure and reserves space
+ * for the next member with specified offset.
+ */
+/* cppcheck-suppress [misra-c2012-20.7] */
+#define SET_MEMBER(member, start, end) \
+ union { \
+ member; \
+ unsigned char reserved##end[((end) - (start))]; \
+ }
+
+#define EL3_TOKEN_RESPONSE_MAX_SIG_LEN U(512)
+
+struct el3_token_sign_request {
+ SET_MEMBER(uint32_t sig_alg_id, 0x0, 0x8);
+ SET_MEMBER(uint64_t rec_granule, 0x8, 0x10);
+ SET_MEMBER(uint64_t req_ticket, 0x10, 0x18);
+ SET_MEMBER(uint32_t hash_alg_id, 0x18, 0x20);
+ SET_MEMBER(uint8_t hash_buf[SHA512_DIGEST_SIZE], 0x20, 0x60);
+};
+
+CASSERT(__builtin_offsetof(struct el3_token_sign_request, sig_alg_id) == 0x0U,
+ assert_el3_token_sign_request_sig_alg_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_request, rec_granule) == 0x8U,
+ assert_el3_token_sign_request_rec_granule_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_request, req_ticket) == 0x10U,
+ assert_el3_token_sign_request_req_ticket_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_request, hash_alg_id) == 0x18U,
+ assert_el3_token_sign_request_hash_alg_id_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_request, hash_buf) == 0x20U,
+ assert_el3_token_sign_request_hash_buf_mismatch);
+
+
+struct el3_token_sign_response {
+ SET_MEMBER(uint64_t rec_granule, 0x0, 0x8);
+ SET_MEMBER(uint64_t req_ticket, 0x8, 0x10);
+ SET_MEMBER(uint16_t sig_len, 0x10, 0x12);
+ SET_MEMBER(uint8_t signature_buf[EL3_TOKEN_RESPONSE_MAX_SIG_LEN], 0x12, 0x212);
+};
+
+CASSERT(__builtin_offsetof(struct el3_token_sign_response, rec_granule) == 0x0U,
+ assert_el3_token_sign_resp_rec_granule_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_response, req_ticket) == 0x8U,
+ assert_el3_token_sign_resp_req_ticket_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_response, sig_len) == 0x10U,
+ assert_el3_token_sign_resp_sig_len_mismatch);
+CASSERT(__builtin_offsetof(struct el3_token_sign_response, signature_buf) == 0x12U,
+ assert_el3_token_sign_resp_sig_buf_mismatch);
+
+#endif /* RMM_EL3_TOKEN_SIGN_H */
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index 4615ffb..0cc8628 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -7,6 +7,7 @@
#ifndef RMMD_SVC_H
#define RMMD_SVC_H
+#include <common/sha_common_macros.h>
#include <lib/smccc.h>
#include <lib/utils_def.h>
@@ -96,11 +97,6 @@
#define RMI_SUCCESS 0
#define RMI_ERROR_INPUT 1
-/* Acceptable SHA sizes for Challenge object */
-#define SHA256_DIGEST_SIZE 32U
-#define SHA384_DIGEST_SIZE 48U
-#define SHA512_DIGEST_SIZE 64U
-
/*
* Retrieve Realm attestation key from EL3. Only P-384 ECC curve key is
* supported. The arguments to this SMC are :
@@ -133,8 +129,43 @@
/* 0x1B3 */
#define RMM_ATTEST_GET_PLAT_TOKEN SMC64_RMMD_EL3_FID(U(3))
+/* Starting RMM-EL3 interface version 0.4 */
+#define RMM_EL3_FEATURES SMC64_RMMD_EL3_FID(U(4))
+#define RMM_EL3_FEAT_REG_0_IDX U(0)
+/* Bit 0 of FEAT_REG_0 */
+/* 1 - the feature is present in EL3 , 0 - the feature is absent */
+#define RMM_EL3_FEAT_REG_0_EL3_TOKEN_SIGN_MASK U(0x1)
+
+/*
+ * Function codes to support attestation where EL3 is used to sign
+ * realm attestation tokens. In this model, the private key is not
+ * exposed to the RMM.
+ * The arguments to this SMC are:
+ * arg0 - Function ID.
+ * arg1 - Opcode, one of:
+ * RMM_EL3_TOKEN_SIGN_PUSH_REQ_OP,
+ * RMM_EL3_TOKEN_SIGN_PULL_RESP_OP,
+ * RMM_EL3_TOKEN_SIGN_GET_RAK_PUB_OP
+ * arg2 - Pointer to buffer with request/response structures,
+ * which is in the RMM<->EL3 shared buffer.
+ * arg3 - Buffer size of memory pointed by arg2.
+ * arg4 - ECC Curve, when opcode is RMM_EL3_TOKEN_SIGN_GET_RAK_PUB_OP
+ * The return arguments are:
+ * ret0 - Status/Error
+ * ret1 - Size of public key if opcode is RMM_EL3_TOKEN_SIGN_GET_RAK_PUB_OP
+ */
+#define RMM_EL3_TOKEN_SIGN SMC64_RMMD_EL3_FID(U(5))
+
+/* Opcodes for RMM_EL3_TOKEN_SIGN */
+#define RMM_EL3_TOKEN_SIGN_PUSH_REQ_OP U(1)
+#define RMM_EL3_TOKEN_SIGN_PULL_RESP_OP U(2)
+#define RMM_EL3_TOKEN_SIGN_GET_RAK_PUB_OP U(3)
+
/* ECC Curve types for attest key generation */
-#define ATTEST_KEY_CURVE_ECC_SECP384R1 0
+#define ATTEST_KEY_CURVE_ECC_SECP384R1 U(0)
+
+/* Identifier for the hash algorithm used for attestation signing */
+#define EL3_TOKEN_SIGN_HASH_ALG_SHA384 U(1)
/*
* RMM_BOOT_COMPLETE originates on RMM when the boot finishes (either cold
@@ -157,7 +188,7 @@
* Increase this when a bug is fixed, or a feature is added without
* breaking compatibility.
*/
-#define RMM_EL3_IFC_VERSION_MINOR (U(3))
+#define RMM_EL3_IFC_VERSION_MINOR (U(4))
#define RMM_EL3_INTERFACE_VERSION \
(((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 374cc5d..fecb56f 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -57,7 +57,7 @@
msr osdlr_el1, x0
isb
- apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169
+ apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169, NO_GET_CPU_REV
dsb sy
ret
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 4c33dda..b9f6081 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -216,7 +216,7 @@
* ----------------------------------------------------
*/
func cortex_a710_core_pwr_dwn
- apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+ apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV
apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
/* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 9115303..152c81f 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -10,6 +10,8 @@
#include <cpuamu.h>
#include <cpu_macros.S>
+.global check_erratum_cortex_a75_764081
+
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 97e036e..017086a 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -505,7 +505,7 @@
*/
sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
- apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
+ apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index d1fc41a..f53b646 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -161,7 +161,7 @@
sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
+ apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 5a63e78..1de570a 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -192,7 +192,7 @@
func cortex_a78_core_pwr_dwn
sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
+ apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 97d5743..260cc73 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -132,7 +132,7 @@
*/
sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+ apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_arcadia.S b/lib/cpus/aarch64/cortex_arcadia.S
new file mode 100644
index 0000000..c97d87d
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_arcadia.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_arcadia.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-ARCADIA must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex-ARCADIA supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_arcadia
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_arcadia
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_arcadia_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_ARCADIA_CPUPWRCTLR_EL1, CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc cortex_arcadia_core_pwr_dwn
+
+ /* ---------------------------------------------
+ * This function provides Cortex-Arcadia specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_arcadia_regs, "aS"
+cortex_arcadia_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_arcadia_cpu_reg_dump
+ adr x6, cortex_arcadia_regs
+ mrs x8, CORTEX_ARCADIA_CPUECTLR_EL1
+ ret
+endfunc cortex_arcadia_cpu_reg_dump
+
+declare_cpu_ops cortex_arcadia, CORTEX_ARCADIA_MIDR, \
+ cortex_arcadia_reset_func, \
+ cortex_arcadia_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index ab0b19d..ac60903 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -126,10 +126,10 @@
check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1)
-workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
+workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
/* dsb before isb of power down sequence */
dsb sy
-workaround_reset_end cortex_x2, ERRATUM(2768515)
+workaround_runtime_end cortex_x2, ERRATUM(2768515)
check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
@@ -172,12 +172,7 @@
*/
sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-#if ERRATA_X2_2768515
- mov x15, x30
- bl cpu_get_rev_var
- bl erratum_cortex_x2_2768515_wa
- mov x30, x15
-#endif /* ERRATA_X2_2768515 */
+ apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV
isb
ret
endfunc cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 248f107..a81c4cf 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -114,13 +114,13 @@
* ----------------------------------------------------
*/
func cortex_x3_core_pwr_dwn
- apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
+ apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV
isb
ret
endfunc cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 1220d38..320fd90 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -69,6 +69,20 @@
check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503
+ sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8)
+workaround_reset_end cortex_x4, ERRATUM(2897503)
+
+check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+
+workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789
+ sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14)
+ sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13)
+ sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52)
+workaround_reset_end cortex_x4, ERRATUM(3076789)
+
+check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
+
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
@@ -97,7 +111,7 @@
*/
sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
+ apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 50e1ae3..f727226 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -236,7 +236,7 @@
*/
sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
- apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 7d7cc44..d2237f1 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -265,8 +265,7 @@
cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
-
- apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
+ apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV
apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
/* ---------------------------------------------------
@@ -276,7 +275,7 @@
*/
sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
- apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
+ apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 89299b7..1ec3e94 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -253,7 +253,7 @@
* ---------------------------------------------
*/
sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
+ apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index d8c32a4..ca66f8d 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -100,7 +100,7 @@
* ---------------------------------------------------
*/
sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+ apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c55597a..4c20785 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -839,6 +839,14 @@
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2816013
+# Flag to apply erratum 2897503 workaround on reset. This erratum applies
+# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_2897503
+
+# Flag to apply erratum 3076789 workaround on reset. This erratum applies
+# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_3076789
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 9801245..a4515a9 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <cortex_a520.h>
#include <cortex_x4.h>
+#include <cortex_a75.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -28,3 +29,14 @@
return ERRATA_NOT_APPLIES;
}
#endif
+
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void)
+{
+ long rev_var = cpu_get_rev_var();
+ if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
+ return true;
+ }
+ return false;
+}
+#endif /* ERRATA_A75_764081 */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index ab9d4b6..a353a87 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -400,9 +400,6 @@
/* PMUv3 is presumed to be always present */
mrs x9, pmcr_el0
str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
- /* Disable cycle counter when event counting is prohibited */
- orr x9, x9, #PMCR_EL0_DP_BIT
- msr pmcr_el0, x9
isb
#if CTX_INCLUDE_PAUTH_REGS
/* ----------------------------------------------------------
@@ -444,12 +441,7 @@
*/
func prepare_el3_entry
save_gp_pmcr_pauth_regs
- enable_serror_at_el3
- /*
- * Set the PSTATE bits not described in the Aarch64.TakeException
- * pseudocode to their default values.
- */
- set_unset_pstate_bits
+ setup_el3_execution_context
ret
endfunc prepare_el3_entry
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 218ad11..003cb25 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -89,13 +89,13 @@
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
/* Store the initialised SCTLR_EL1 value in the cpu_context */
write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx);
@@ -260,6 +260,21 @@
*/
scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
#endif
+
+ if (is_feat_the_supported()) {
+ /* Set the RCWMASKEn bit in SCR_EL3 to enable access to
+ * RCWMASK_EL1 and RCWSMASK_EL1 registers.
+ */
+ scr_el3 |= SCR_RCWMASKEn_BIT;
+ }
+
+ if (is_feat_sctlr2_supported()) {
+ /* Set the SCTLR2En bit in SCR_EL3 to enable access to
+ * SCTLR2_ELx registers.
+ */
+ scr_el3 |= SCR_SCTLR2En_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
/* Initialize EL2 context registers */
@@ -760,13 +775,6 @@
*/
trf_enable(ctx);
}
-
- if (is_feat_brbe_supported()) {
- /*
- * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state.
- */
- brbe_enable(ctx);
- }
#endif /* IMAGE_BL31 */
}
@@ -792,6 +800,10 @@
debugv8p9_extended_bp_wp_enable(ctx);
}
+ if (is_feat_brbe_supported()) {
+ brbe_enable(ctx);
+ }
+
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
@@ -1070,14 +1082,16 @@
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Initialize SCTLR_EL2 register with reset value. */
sctlr_el2 = SCTLR_EL2_RES1;
-#if ERRATA_A75_764081
+
/*
* If workaround of errata 764081 for Cortex-A75
* is used then set SCTLR_EL2.IESB to enable
* Implicit Error Synchronization Barrier.
*/
- sctlr_el2 |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_el2 |= SCTLR_IESB_BIT;
+ }
+
write_sctlr_el2(sctlr_el2);
} else {
/*
@@ -1435,6 +1449,10 @@
write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2());
write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2());
}
+
+ if (is_feat_sctlr2_supported()) {
+ write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2());
+ }
}
/*******************************************************************************
@@ -1522,6 +1540,10 @@
write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2));
write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2));
}
+
+ if (is_feat_sctlr2_supported()) {
+ write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2));
+ }
}
#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
@@ -1710,6 +1732,16 @@
write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1());
write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0());
}
+
+ if (is_feat_the_supported()) {
+ write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1());
+ write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1());
+ }
+
+ if (is_feat_sctlr2_supported()) {
+ write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1());
+ }
+
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@@ -1805,6 +1837,16 @@
write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1));
write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0));
}
+
+ if (is_feat_the_supported()) {
+ write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1));
+ write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1));
+ }
+
+ if (is_feat_sctlr2_supported()) {
+ write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1));
+ }
+
}
/*******************************************************************************
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c
index dde0266..fef6647 100644
--- a/lib/extensions/brbe/brbe.c
+++ b/lib/extensions/brbe/brbe.c
@@ -16,11 +16,13 @@
/*
* MDCR_EL3.SBRBE = 0b01
- *
* Allows BRBE usage in non-secure world and prohibited in
* secure world.
+ *
+ * MDCR_EL3.{E3BREW, E3BREC} = 0b00
+ * Branch recording at EL3 is disabled
*/
- mdcr_el3_val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
+ mdcr_el3_val &= ~((MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT) | MDCR_E3BREW | MDCR_E3BREC);
mdcr_el3_val |= (0x1UL << MDCR_SBRBE_SHIFT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index d028fce..79c4ea5 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -495,7 +495,7 @@
*
* Parameters
* l0_mem_base Base address of memory used for L0 tables.
- * l1_mem_size Size of memory available for L0 tables.
+ * l0_mem_size Size of memory available for L0 tables.
*
* Return
* Negative Linux error code in the event of a failure, 0 for success.
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index 3b77ab2..cca08c1 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <assert_macros.S>
+#include <cpu_macros.S>
#include <lib/psci/psci.h>
#include <platform_def.h>
@@ -124,9 +125,8 @@
* -----------------------------------------------------------------------
*/
func psci_power_down_wfi
-#if ERRATA_A510_2684597
- bl apply_cpu_pwr_dwn_errata
-#endif
+ apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597
+
dsb sy // ensure write buffer empty
1:
wfi
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
deleted file mode 100644
index 89e3e12..0000000
--- a/lib/psci/aarch64/runtime_errata.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <cortex_a510.h>
-#include <cpu_macros.S>
-
-/*
- * void apply_cpu_pwr_dwn_errata(void);
- *
- * This function applies various CPU errata during power down.
- */
- .globl apply_cpu_pwr_dwn_errata
-func apply_cpu_pwr_dwn_errata
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A510_2684597
- bl erratum_cortex_a510_2684597_wa
-#endif
-
- ret x19
-endfunc apply_cpu_pwr_dwn_errata
diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index c71580f..527ad3a 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -21,8 +21,7 @@
lib/psci/${ARCH}/psci_helpers.S
ifeq (${ARCH}, aarch64)
-PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
- lib/psci/aarch64/runtime_errata.S
+PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
endif
ifeq (${USE_COHERENT_MEM}, 1)
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 29fbf78..3d2b850 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -4,12 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-ifeq ($(filter-out clean,$(or $(MAKECMDGOALS),all)),)
- toolchains :=
-else
- toolchains := aarch64
-endif
-
include ../../make_helpers/build-rules.mk
include ../../make_helpers/common.mk
include ../../make_helpers/toolchain.mk
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 675779f..9533e98 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -90,7 +90,7 @@
# Enable the features which are mandatory from ARCH version 8.9 and upwards.
ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-armv8-9-a-feats := ENABLE_FEAT_TCR2 ENABLE_FEAT_DEBUGV8P9
+armv8-9-a-feats := ENABLE_FEAT_TCR2 ENABLE_FEAT_DEBUGV8P9 ENABLE_FEAT_SCTLR2
# 8.8 Compliant
armv8-9-a-feats += ${armv8-8-a-feats}
FEAT_LIST := ${armv8-9-a-feats}
@@ -219,6 +219,9 @@
# Flag to enable access to TCR2 (FEAT_TCR2).
ENABLE_FEAT_TCR2 ?= 0
+# Flag to enable access to SCTLR2 (FEAT_SCTLR2).
+ENABLE_FEAT_SCTLR2 ?= 0
+
#
################################################################################
# Optional Features defaulted to 0 or 2, if they are not enabled from
@@ -341,6 +344,13 @@
ENABLE_FEAT_FGT2 ?= 0
#----
+# 8.8
+#----
+
+# Flag to enable FEAT_THE (Translation Hardening Extension)
+ENABLE_FEAT_THE ?= 0
+
+#----
# 8.9
#----
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 8c884b4..584542c 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -409,3 +409,6 @@
# Allow platforms to save/restore DSU PMU registers over a power cycle.
# Disabled by default and must be enabled by individual platforms.
PRESERVE_DSU_PMU_REGS := 0
+
+# Enable RMMD to forward attestation requests from RMM to EL3.
+RMMD_ENABLE_EL3_TOKEN_SIGN := 0
diff --git a/make_helpers/toolchain.mk b/make_helpers/toolchain.mk
index 9a06a9c..2ab577c 100644
--- a/make_helpers/toolchain.mk
+++ b/make_helpers/toolchain.mk
@@ -18,13 +18,74 @@
ifndef toolchain-mk
toolchain-mk := $(lastword $(MAKEFILE_LIST))
- toolchains ?= host $(ARCH)
+ include $(dir $(toolchain-mk))build_env.mk
+ include $(dir $(toolchain-mk))utilities.mk
- include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
- include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
+ #
+ # Make assigns generic default values to `CC`, `CPP`, `AS`, etc. if they
+ # are not explicitly assigned values by the user. These are usually okay
+ # for very simple programs when building for the host system, but we
+ # need greater control over the toolchain flow.
+ #
+ # Therefore, we undefine these built-in variables if they have default
+ # values, so that we can provide our own default values later instead.
+ #
+
+ ifeq ($(origin CC),default)
+ undefine CC
+ endif
+
+ ifeq ($(origin CPP),default)
+ undefine CPP
+ endif
+
+ ifeq ($(origin AS),default)
+ undefine AS
+ endif
+
+ ifeq ($(origin AR),default)
+ undefine AR
+ endif
+
+ ifeq ($(origin LD),default)
+ undefine LD
+ endif
+
+ #
+ # The full list of toolchains supported by TF-A.
+ #
+ # Each of these toolchains defines a file of the same name in the
+ # `toolchains` directory, which must configure the following variables:
+ #
+ # - <toolchain>-name
+ #
+ # A human-readable name for the toolchain,
+ #
+ # Additionally, for every tool class, it must also define:
+ #
+ # - <toolchain>-<tool-class>-parameter
+ #
+ # The command line or environment variable used to set the tool for
+ # for the given tool class.
+ #
+ # - <toolchain>-<tool-class>-default-id
+ #
+ # The default tool identifier used if the tool for the given tool
+ # class cannot be identified.
+ #
+ # - <toolchain>-<tool-class>-default
+ #
+ # The default commands to try, in the order defined, for the given
+ # tool class if the user does not explicitly provide one, and if the
+ # command could not be derived from the C compiler.
+ #
- include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
- $(addsuffix .mk,$(toolchains)))
+ toolchains := host # Used for host targets
+ toolchains += aarch32 # Used for AArch32 targets
+ toolchains += aarch64 # Used for AArch64 targets
+ toolchains += rk3399-m0 # Used for RK3399 Cortex-M0 targets
+
+ include $(toolchains:%=$(dir $(toolchain-mk))toolchains/%.mk)
#
# Configure tool classes that we recognize.
@@ -33,29 +94,32 @@
# specific role or type of tool in the toolchain.
#
- tool-classes := cc
- tool-class-name-cc := C compiler
+ toolchain-tool-classes := cc
+ toolchain-tool-class-name-cc := C compiler
- tool-classes += cpp
- tool-class-name-cpp := C preprocessor
+ toolchain-tool-classes += cpp
+ toolchain-tool-class-name-cpp := C preprocessor
- tool-classes += as
- tool-class-name-as := assembler
+ toolchain-tool-classes += as
+ toolchain-tool-class-name-as := assembler
- tool-classes += ld
- tool-class-name-ld := linker
+ toolchain-tool-classes += ld
+ toolchain-tool-class-name-ld := linker
- tool-classes += oc
- tool-class-name-oc := object copier
+ toolchain-tool-classes += oc
+ toolchain-tool-class-name-oc := object copier
- tool-classes += od
- tool-class-name-od := object dumper
+ toolchain-tool-classes += od
+ toolchain-tool-class-name-od := object dumper
- tool-classes += ar
- tool-class-name-ar := archiver
+ toolchain-tool-classes += ar
+ toolchain-tool-class-name-ar := archiver
- tool-classes += dtc
- tool-class-name-dtc := device tree compiler
+ toolchain-tool-classes += dtc
+ toolchain-tool-class-name-dtc := device tree compiler
+
+ toolchain-tool-classes += poetry
+ toolchain-tool-class-name-poetry := Python Poetry package manager
#
# Configure tools that we recognize.
@@ -66,53 +130,56 @@
#
# Arm® Compiler for Embedded
- tools := arm-clang
- tool-name-arm-clang := Arm® Compiler for Embedded `armclang`
+ toolchain-tools := arm-clang
+ toolchain-tool-name-arm-clang := Arm® Compiler for Embedded `armclang`
- tools += arm-link
- tool-name-arm-link := Arm® Compiler for Embedded `armlink`
+ toolchain-tools += arm-link
+ toolchain-tool-name-arm-link := Arm® Compiler for Embedded `armlink`
- tools += arm-ar
- tool-name-arm-ar := Arm® Compiler for Embedded `armar`
+ toolchain-tools += arm-ar
+ toolchain-tool-name-arm-ar := Arm® Compiler for Embedded `armar`
- tools += arm-fromelf
- tool-name-arm-fromelf := Arm® Compiler for Embedded `fromelf`
+ toolchain-tools += arm-fromelf
+ toolchain-tool-name-arm-fromelf := Arm® Compiler for Embedded `fromelf`
# LLVM Project
- tools += llvm-clang
- tool-name-llvm-clang := LLVM Clang (`clang`)
+ toolchain-tools += llvm-clang
+ toolchain-tool-name-llvm-clang := LLVM Clang (`clang`)
- tools += llvm-lld
- tool-name-llvm-lld := LLVM LLD (`lld`)
+ toolchain-tools += llvm-lld
+ toolchain-tool-name-llvm-lld := LLVM LLD (`lld`)
- tools += llvm-objcopy
- tool-name-llvm-objcopy := LLVM `llvm-objcopy`
+ toolchain-tools += llvm-objcopy
+ toolchain-tool-name-llvm-objcopy := LLVM `llvm-objcopy`
- tools += llvm-objdump
- tool-name-llvm-objdump := LLVM `llvm-objdump`
+ toolchain-tools += llvm-objdump
+ toolchain-tool-name-llvm-objdump := LLVM `llvm-objdump`
- tools += llvm-ar
- tool-name-llvm-ar := LLVM `llvm-ar`
+ toolchain-tools += llvm-ar
+ toolchain-tool-name-llvm-ar := LLVM `llvm-ar`
# GNU Compiler Collection & GNU Binary Utilities
- tools += gnu-gcc
- tool-name-gnu-gcc := GNU GCC (`gcc`)
+ toolchain-tools += gnu-gcc
+ toolchain-tool-name-gnu-gcc := GNU GCC (`gcc`)
- tools += gnu-ld
- tool-name-gnu-ld := GNU LD (`ld.bfd`)
+ toolchain-tools += gnu-ld
+ toolchain-tool-name-gnu-ld := GNU LD (`ld.bfd`)
- tools += gnu-objcopy
- tool-name-gnu-objcopy := GNU `objcopy`
+ toolchain-tools += gnu-objcopy
+ toolchain-tool-name-gnu-objcopy := GNU `objcopy`
- tools += gnu-objdump
- tool-name-gnu-objdump := GNU `objdump`
+ toolchain-tools += gnu-objdump
+ toolchain-tool-name-gnu-objdump := GNU `objdump`
- tools += gnu-ar
- tool-name-gnu-ar := GNU `ar`
+ toolchain-tools += gnu-ar
+ toolchain-tool-name-gnu-ar := GNU `ar`
# Other tools
- tools += generic-dtc
- tool-name-generic-dtc := Device Tree Compiler (`dtc`)
+ toolchain-tools += generic-dtc
+ toolchain-tool-name-generic-dtc := Device Tree Compiler (`dtc`)
+
+ toolchain-tools += generic-poetry
+ toolchain-tool-name-generic-poetry := Poetry (`poetry`)
#
# Assign tools to tool classes.
@@ -120,71 +187,25 @@
# Multifunctional tools, i.e. tools which can perform multiple roles in
# a toolchain, may be specified in multiple tool class lists. For
# example, a C compiler which can also perform the role of a linker may
- # be placed in both `tools-cc` and `tools-ld`.
+ # be placed in both `toolchain-tools-cc` and `toolchain-tools-ld`.
#
# C-related tools
- tools-cc := arm-clang llvm-clang gnu-gcc # C compilers
- tools-cpp := arm-clang llvm-clang gnu-gcc # C preprocessors
+ toolchain-tools-cc := arm-clang llvm-clang gnu-gcc # C compilers
+ toolchain-tools-cpp := arm-clang llvm-clang gnu-gcc # C preprocessors
# Assembly-related tools
- tools-as := arm-clang llvm-clang gnu-gcc # Assemblers
+ toolchain-tools-as := arm-clang llvm-clang gnu-gcc # Assemblers
# Linking and object-handling tools
- tools-ld := arm-clang arm-link llvm-clang llvm-lld gnu-gcc gnu-ld # Linkers
- tools-oc := arm-fromelf llvm-objcopy gnu-objcopy # Object copiers
- tools-od := arm-fromelf llvm-objdump gnu-objdump # Object dumpers
- tools-ar := arm-ar llvm-ar gnu-ar # Archivers
+ toolchain-tools-ld := arm-clang arm-link llvm-clang llvm-lld gnu-gcc gnu-ld # Linkers
+ toolchain-tools-oc := arm-fromelf llvm-objcopy gnu-objcopy # Object copiers
+ toolchain-tools-od := arm-fromelf llvm-objdump gnu-objdump # Object dumpers
+ toolchain-tools-ar := arm-ar llvm-ar gnu-ar # Archivers
# Other tools
- tools-dtc := generic-dtc # Device tree compilers
-
- define check-tool-class-tools
- $(eval tool-class := $(1))
-
- ifndef tools-$(tool-class)
- $$(error no tools registered to handle tool class `$(tool-class)`)
- endif
- endef
-
- $(foreach tool-class,$(tool-classes), \
- $(eval $(call check-tool-class-tools,$(tool-class))))
-
- #
- # Default tools for each toolchain.
- #
- # Toolchains can specify a default path to any given tool with a tool
- # class. These values are used in the absence of user-specified values,
- # and are configured by the makefile for each toolchain using variables
- # of the form:
- #
- # - $(toolchain)-$(tool-class)-default
- #
- # For example, the default C compiler for the AArch32 and AArch64
- # toolchains could be configured with:
- #
- # - aarch32-cc-default
- # - aarch64-cc-default
- #
-
- define check-toolchain-tool-class-default
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
-
- ifndef $(toolchain)-$(tool-class)-default
- $$(error no default value specified for tool class `$(tool-class)` of toolchain `$(toolchain)`)
- endif
- endef
-
- define check-toolchain-tool-class-defaults
- $(eval toolchain := $(1))
-
- $(foreach tool-class,$(tool-classes), \
- $(eval $(call check-toolchain-tool-class-default,$(toolchain),$(tool-class))))
- endef
-
- $(foreach toolchain,$(toolchains), \
- $(eval $(call check-toolchain-tool-class-defaults,$(toolchain))))
+ toolchain-tools-dtc := generic-dtc # Device tree compilers
+ toolchain-tools-poetry := generic-poetry # Python Poetry package manager
#
# Helper functions to identify toolchain tools.
@@ -194,14 +215,15 @@
# to more reliably identify tools than by looking at the path alone
# (e.g. `gcc` on macOS is actually Apple Clang).
#
- # Each tool-guessing function (`guess-tool-$(tool)`) takes a single
- # argument giving the path to the tool to guess, and returns a non-empty
- # value if the tool corresponds to the tool identifier `$(tool)`:
+ # Each tool-guessing function (`toolchain-guess-tool-$(tool)`) takes a
+ # single argument giving the path to the tool to guess, and returns a
+ # non-empty value if the tool corresponds to the tool identifier
+ # `$(tool)`:
#
- # $(call guess-tool-llvm-clang,aarch64-none-elf-gcc) # <empty>
- # $(call guess-tool-gnu-gcc,aarch64-none-elf-gcc) # <non-empty>
+ # $(call toolchain-guess-tool-llvm-clang,aarch64-none-elf-gcc) # <empty>
+ # $(call toolchain-guess-tool-gnu-gcc,aarch64-none-elf-gcc) # <non-empty>
#
- # The `guess-tool` function tries to find the corresponding tool
+ # The `toolchain-guess-tool` function tries to find the corresponding tool
# identifier for a tool given its path. It takes two arguments:
#
# - $(1): a list of candidate tool identifiers to check
@@ -211,41 +233,75 @@
# identifiers return a non-empty value then the tool identifier of the
# first function to do so is returned:
#
- # $(call guess-tool,gnu-gcc llvm-clang,armclang) # <empty>
- # $(call guess-tool,gnu-gcc llvm-clang,clang-14) # llvm-clang
- # $(call guess-tool,gnu-gcc llvm-clang,aarch64-none-elf-gcc-12) # gnu-gcc
+ # $(call toolchain-guess-tool,gnu-gcc llvm-clang,armclang) # <empty>
+ # $(call toolchain-guess-tool,gnu-gcc llvm-clang,clang-14) # llvm-clang
+ # $(call toolchain-guess-tool,gnu-gcc llvm-clang,aarch64-none-elf-gcc-12) # gnu-gcc
#
- # Tools are checked in the order that they appear in
- # `tools-$(tool-class)`, and the first match is returned.
+ # Tools are checked in the order that they are provided, and the first
+ # match is returned.
#
# Arm Compiler for Embedded
- guess-tool-arm-clang = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
- guess-tool-arm-link = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
- guess-tool-arm-fromelf = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
- guess-tool-arm-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armar")
+ toolchain-guess-tool-arm-clang = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
+ toolchain-guess-tool-arm-link = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
+ toolchain-guess-tool-arm-fromelf = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
+ toolchain-guess-tool-arm-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armar")
# LLVM Project
- guess-tool-llvm-clang = $(shell $(1) -v 2>&1 <$(nul) | grep -o "clang version")
- guess-tool-llvm-lld = $(shell $(1) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
- guess-tool-llvm-objcopy = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
- guess-tool-llvm-objdump = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
- guess-tool-llvm-ar = $(shell $(1) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
+ toolchain-guess-tool-llvm-clang = $(shell $(1) -v 2>&1 <$(nul) | grep -o "clang version")
+ toolchain-guess-tool-llvm-lld = $(shell $(1) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
+ toolchain-guess-tool-llvm-objcopy = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
+ toolchain-guess-tool-llvm-objdump = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
+ toolchain-guess-tool-llvm-ar = $(shell $(1) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
# GNU Compiler Collection & GNU Binary Utilities
- guess-tool-gnu-gcc = $(shell $(1) -v 2>&1 <$(nul) | grep -o "gcc version")
- guess-tool-gnu-ld = $(shell $(1) -v 2>&1 <$(nul) | grep -o "GNU ld")
- guess-tool-gnu-objcopy = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
- guess-tool-gnu-objdump = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objdump")
- guess-tool-gnu-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU ar")
+ toolchain-guess-tool-gnu-gcc = $(shell $(1) -v 2>&1 <$(nul) | grep -o "gcc version")
+ toolchain-guess-tool-gnu-ld = $(shell $(1) -v 2>&1 <$(nul) | grep -o "GNU ld")
+ toolchain-guess-tool-gnu-objcopy = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
+ toolchain-guess-tool-gnu-objdump = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objdump")
+ toolchain-guess-tool-gnu-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU ar")
# Other tools
- guess-tool-generic-dtc = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Version: DTC")
+ toolchain-guess-tool-generic-dtc = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Version: DTC")
+ toolchain-guess-tool-generic-poetry = $(shell $(1) --version 2>&1 <$(nul))
- guess-tool = $(firstword $(foreach candidate,$(1), \
- $(if $(call guess-tool-$(candidate),$(2)),$(candidate))))
+ toolchain-guess-tool = $(if $(2),$(firstword $(foreach candidate,$(1),$\
+ $(if $(call toolchain-guess-tool-$(candidate),$(2)),$(candidate)))))
#
+ # Warn the user that a tool could not be identified.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain that the tool belongs to.
+ # - $2: The tool class that the tool belongs to.
+ #
+
+ define toolchain-warn-unrecognized
+ $(warning )
+ $(warning The configured $($(1)-name) $(toolchain-tool-class-name-$(2)) could not be identified:)
+ $(warning )
+ $(warning $(space) $($(1)-$(2))$(if $($(1)-$(2)-parameter), (via `$($(1)-$(2)-parameter)`)))
+ $(warning )
+ $(warning The following tools were tried, but either did not exist or could not be identified:)
+ $(warning )
+
+ $(foreach default,$($(1)-$(2)-default), \
+ $(warning $(space) - $(default)))
+
+ $(warning )
+ $(warning The following tools are supported:)
+ $(warning )
+
+ $(foreach tool,$(toolchain-tools-$(2)), \
+ $(warning $(space) - $(toolchain-tool-name-$(tool))))
+
+ $(warning )
+ $(warning The build system will treat this $(toolchain-tool-class-name-$(2)) as $(toolchain-tool-name-$($(1)-$(2)-default-id)).)
+ $(warning )
+ endef
+
+ #
# Locate and identify tools belonging to each toolchain.
#
# Each tool class in each toolchain receives a variable of the form
@@ -258,89 +314,123 @@
#
# For each of these variables, if no program path is explicitly provided
# by the parent Makefile then the C compiler is queried (if supported)
- # for its location. This is done via the `guess-$(tool)-$(tool-class)`
- # set of functions. For example:
- #
- # - `guess-arm-clang-ld` guesses the linker via Arm Clang,
- # - `guess-llvm-clang-as` guesses the assembler via LLVM Clang, and
- # - `guess-gnu-gcc-od` guesses the object dumper via GNU GCC.
+ # for its location.
#
- # If the C compiler cannot provide the location (or the tool class is
- # the C compiler), then it is assigned the value of the
- # `$(toolchain)-$(tool)-default` variable.
+ # If the C compiler cannot provide the location (or the tool class *is*
+ # the C compiler), then it is assigned a default value specific for that
+ # toolchain.
#
- guess-arm-clang-cpp = $(1)
- guess-arm-clang-as = $(1)
- guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
- guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
- guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
- guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
+ toolchain-derive-arm-clang-cpp = $(1)
+ toolchain-derive-arm-clang-as = $(1)
+ toolchain-derive-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
+ toolchain-derive-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
+ toolchain-derive-arm-clang-od = # Fall back to `$(toolchain)-od-default`
+ toolchain-derive-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
- guess-llvm-clang-cpp = $(1)
- guess-llvm-clang-as = $(1)
- guess-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
- guess-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
- guess-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
- guess-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
+ toolchain-derive-llvm-clang-cpp = $(1)
+ toolchain-derive-llvm-clang-as = $(1)
+ toolchain-derive-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
+ toolchain-derive-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
+ toolchain-derive-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
+ toolchain-derive-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
- guess-gnu-gcc-cpp = $(1)
- guess-gnu-gcc-as = $(1)
- guess-gnu-gcc-ld = $(1)
- guess-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
- guess-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
- guess-gnu-gcc-ar = $(shell $(1) --print-prog-name ar 2>$(nul))
+ toolchain-derive-gnu-gcc-cpp = $(1)
+ toolchain-derive-gnu-gcc-as = $(1)
+ toolchain-derive-gnu-gcc-ld = $(1)
+ toolchain-derive-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
+ toolchain-derive-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
+ toolchain-derive-gnu-gcc-ar = $(shell $(1) --print-prog-name ar 2>$(nul))
- define toolchain-warn-unrecognized
- $$(warning )
- $$(warning The configured $$($(1)-name) $$(tool-class-name-$(2)) could not be identified and may not be supported:)
- $$(warning )
- $$(warning $$(space) $$($(1)-$(2)))
- $$(warning )
- $$(warning The default $$($(1)-name) $$(tool-class-name-$(2)) is:)
- $$(warning )
- $$(warning $$(space) $$($(1)-$(2)-default))
- $$(warning )
- $$(warning The following tools are supported:)
- $$(warning )
+ toolchain-derive = $(if $3,$(call toolchain-derive-$1-$2,$3))
+
+ #
+ # Configure a toolchain.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain to configure.
+ #
+ # This function iterates over all tool classes and configures them for
+ # the provided toolchain. Toolchain tools are initialized lazily and
+ # on-demand based on the first read of the tool path or identifier
+ # variables.
+ #
- $$(foreach tool,$$(tools-$(2)), \
- $$(warning $$(space) - $$(tool-name-$$(tool))))
+ define toolchain-configure
+ $$(foreach tool-class,$$(toolchain-tool-classes), \
+ $$(eval $$(call toolchain-configure-tool,$1,$$(tool-class))))
+ endef
- $$(warning )
- $$(warning The build system will treat this $$(tool-class-name-$(2)) as $$(tool-name-$$($(1)-$(2)-id-default)).)
- $$(warning )
+ #
+ # Configure a specific tool within a toolchain.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain to configure.
+ # - $2: The tool class to configure.
+ #
+
+ define toolchain-configure-tool
+ $1-$2-configure = $\
+ $$(eval $$(call toolchain-determine-tool,$1,$2))
+
+ #
+ # When either of the following variables are read for the first
+ # time, the appropriate tool is determined and *both* variables
+ # are overwritten with their final values.
+ #
+
+ $1-$2 = $$($1-$2-configure)$$($1-$2)
+ $1-$2-id = $$($1-$2-configure)$$($1-$2-id)
endef
- define toolchain-determine-tool
- $(1)-$(2)-guess = $$(if $$(filter-out cc,$(2)),$\
- $$(call guess-$$($(1)-cc-id)-$(2),$$($(1)-cc)))
+ #
+ # Determines and identifies a tool.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain identifier.
+ # - $2: The tool class.
+ #
+ # Tool identification happens by reading the designated tool parameter
+ # to get the user-specified command for the tool (e.g. `CC` or `LD`). If
+ # no tool parameter is defined then try to derive the tool from the C
+ # compiler.
+ #
+ # If all else fails, fall back to the default command defined by the
+ # toolchain makefile.
+ #
- $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-guess))
- $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-default))
+ define toolchain-determine-tool
+ toolchain-$1-$2-derive-from-cc = $$(if $$(filter-out cc,$2),$\
+ $$(call toolchain-derive,$$($1-cc-id),$2,$$($1-cc)))
- ifneq ($$(call which,$$($(1)-$(2))),)
- # If we can resolve this tool to a program on the `PATH`
- # then escape it for use in a shell, which allows us to
- # preserve spaces.
+ toolchain-$1-$2-shell = $\
+ $$(if $$(call defined,$$($1-$2-parameter)),$\
+ $$($$($1-$2-parameter)),$\
+ $$(or $$(toolchain-$1-$2-derive-from-cc),$\
+ $$(toolchain-$1-$2-default)))
- $(1)-$(2) := $$(call escape-shell,$$($(1)-$(2)))
- endif
+ toolchain-$1-$2-default = $$(firstword $\
+ $$(foreach default,$$($1-$2-default),$\
+ $$(if $$(call which,$$(default)),$$(default))) $\
+ $$($1-$2-default))
- $(1)-$(2)-id := $$(call guess-tool,$$(tools-$(2)),$$($(1)-$(2)))
+ $1-$2 := $$(if $$(call which,$$(toolchain-$1-$2-shell)),$\
+ $$(call escape-shell,$$(toolchain-$1-$2-shell)),$\
+ $$(toolchain-$1-$2-shell))
- ifndef $(1)-$(2)-id
- $(1)-$(2)-id := $$($(1)-$(2)-id-default)
+ $1-$2-id := $$(if $$($1-$2),$$(or $\
+ $$(call toolchain-guess-tool,$$\
+ $$(toolchain-tools-$2),$$($1-$2)),$\
+ $$($1-$2-default-id)))
- $$(eval $$(call toolchain-warn-unrecognized,$(1),$(2)))
+ ifeq ($$(or $$($1-$2-id),$$(call bool,$$($1-$2-optional))),)
+ $$(call toolchain-warn-unrecognized,$1,$2)
endif
endef
- define toolchain-determine
- $$(foreach tool-class,$$(tool-classes), \
- $$(eval $$(call toolchain-determine-tool,$(1),$$(tool-class))))
- endef
-
$(foreach toolchain,$(toolchains), \
- $(eval $(call toolchain-determine,$(toolchain))))
+ $(eval $(call toolchain-configure,$(toolchain))))
endif
diff --git a/make_helpers/toolchains/aarch32.mk b/make_helpers/toolchains/aarch32.mk
index ff00a53..4063ed9 100644
--- a/make_helpers/toolchains/aarch32.mk
+++ b/make_helpers/toolchains/aarch32.mk
@@ -6,34 +6,34 @@
aarch32-name := AArch32
-aarch32-cc := $(if $(filter-out default,$(origin CC)),$(CC))
+aarch32-cc-parameter := CC
+aarch32-cc-default-id := gnu-gcc
aarch32-cc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-cc-id-default := gnu-gcc
-aarch32-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
+aarch32-cpp-parameter := CPP
+aarch32-cpp-default-id := gnu-gcc
aarch32-cpp-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-cpp-id-default := gnu-gcc
-aarch32-as := $(if $(filter-out default,$(origin AS)),$(AS))
+aarch32-as-parameter := AS
+aarch32-as-default-id := gnu-gcc
aarch32-as-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-as-id-default := gnu-gcc
-aarch32-ld := $(if $(filter-out default,$(origin LD)),$(LD))
+aarch32-ld-parameter := LD
+aarch32-ld-default-id := gnu-gcc
aarch32-ld-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-ld-id-default := gnu-gcc
-aarch32-oc := $(if $(filter-out default,$(origin OC)),$(OC))
+aarch32-oc-parameter := OC
+aarch32-oc-default-id := gnu-objcopy
aarch32-oc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objcopy
-aarch32-oc-id-default := gnu-objcopy
-aarch32-od := $(if $(filter-out default,$(origin OD)),$(OD))
+aarch32-od-parameter := OD
+aarch32-od-default-id := gnu-objdump
aarch32-od-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objdump
-aarch32-od-id-default := gnu-objdump
-aarch32-ar := $(if $(filter-out default,$(origin AR)),$(AR))
+aarch32-ar-parameter := AR
+aarch32-ar-default-id := gnu-ar
aarch32-ar-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc-ar
-aarch32-ar-id-default := gnu-ar
-aarch32-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
+aarch32-dtc-parameter := DTC
+aarch32-dtc-default-id := generic-dtc
aarch32-dtc-default := dtc
-aarch32-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/aarch64.mk b/make_helpers/toolchains/aarch64.mk
index 407f068..476fbf3 100644
--- a/make_helpers/toolchains/aarch64.mk
+++ b/make_helpers/toolchains/aarch64.mk
@@ -6,34 +6,41 @@
aarch64-name := AArch64
-aarch64-cc := $(if $(filter-out default,$(origin CC)),$(CC))
+aarch64-cc-parameter := CC
+aarch64-cc-default-id := gnu-gcc
aarch64-cc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-cc-id-default := gnu-gcc
+aarch64-cc-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
+aarch64-cpp-parameter := CPP
+aarch64-cpp-default-id := gnu-gcc
aarch64-cpp-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-cpp-id-default := gnu-gcc
+aarch64-cpp-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-as := $(if $(filter-out default,$(origin AS)),$(AS))
+aarch64-as-parameter := AS
+aarch64-as-default-id := gnu-gcc
aarch64-as-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-as-id-default := gnu-gcc
+aarch64-as-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-ld := $(if $(filter-out default,$(origin LD)),$(LD))
+aarch64-ld-parameter := LD
+aarch64-ld-default-id := gnu-gcc
aarch64-ld-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-ld-id-default := gnu-gcc
+aarch64-ld-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-oc := $(if $(filter-out default,$(origin OC)),$(OC))
+aarch64-oc-parameter := OC
+aarch64-oc-default-id := gnu-objcopy
aarch64-oc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objcopy
-aarch64-oc-id-default := gnu-objcopy
+aarch64-oc-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-objcopy)
-aarch64-od := $(if $(filter-out default,$(origin OD)),$(OD))
+aarch64-od-parameter := OD
+aarch64-od-default-id := gnu-objdump
aarch64-od-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objdump
-aarch64-od-id-default := gnu-objdump
+aarch64-od-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-objdump)
-aarch64-ar := $(if $(filter-out default,$(origin AR)),$(AR))
+aarch64-ar-parameter := AR
+aarch64-ar-default-id := gnu-ar
aarch64-ar-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc-ar
-aarch64-ar-id-default := gnu-ar
+aarch64-ar-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc-ar)
-aarch64-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
+aarch64-dtc-parameter := DTC
+aarch64-dtc-default-id := generic-dtc
aarch64-dtc-default := dtc
-aarch64-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/host.mk b/make_helpers/toolchains/host.mk
index 733c289..dc538c6 100644
--- a/make_helpers/toolchains/host.mk
+++ b/make_helpers/toolchains/host.mk
@@ -6,34 +6,39 @@
host-name := host
-host-cc := $(HOSTCC)
+host-cc-parameter := HOSTCC
+host-cc-default-id := gnu-gcc
host-cc-default := gcc
-host-cc-id-default := gnu-gcc
-host-cpp := $(HOSTCPP)
+host-cpp-parameter := HOSTCPP
+host-cpp-default-id := gnu-gcc
host-cpp-default := gcc
-host-cpp-id-default := gnu-gcc
-host-as := $(HOSTAS)
+host-as-parameter := HOSTAS
+host-as-default-id := gnu-gcc
host-as-default := gcc
-host-as-id-default := gnu-gcc
-host-ld := $(HOSTLD)
+host-ld-parameter := HOSTLD
+host-ld-default-id := gnu-gcc
host-ld-default := gcc
-host-ld-id-default := gnu-gcc
-host-oc := $(HOSTOC)
+host-oc-parameter := HOSTOC
+host-oc-default-id := gnu-objcopy
host-oc-default := objcopy
-host-oc-id-default := gnu-objcopy
-host-od := $(HOSTOD)
+host-od-parameter := HOSTOD
+host-od-default-id := gnu-objdump
host-od-default := objdump
-host-od-id-default := gnu-objdump
-host-ar := $(HOSTAR)
+host-ar-parameter := HOSTAR
+host-ar-default-id := gnu-ar
host-ar-default := gcc-ar
-host-ar-id-default := gnu-ar
-host-dtc := $(HOSTDTC)
+host-dtc-parameter := HOSTDTC
+host-dtc-default-id := generic-dtc
host-dtc-default := dtc
-host-dtc-id-default := generic-dtc
+
+host-poetry-parameter := POETRY
+host-poetry-optional := yes
+host-poetry-default-id := generic-poetry
+host-poetry-default := poetry
diff --git a/make_helpers/toolchains/rk3399-m0.mk b/make_helpers/toolchains/rk3399-m0.mk
index 92309f1..3a7f173 100644
--- a/make_helpers/toolchains/rk3399-m0.mk
+++ b/make_helpers/toolchains/rk3399-m0.mk
@@ -6,26 +6,26 @@
rk3399-m0-name := RK3399 M0
+rk3399-m0-cc-default-id := gnu-gcc
rk3399-m0-cc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-cc-id-default := gnu-gcc
+rk3399-m0-cpp-default-id := gnu-gcc
rk3399-m0-cpp-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-cpp-id-default := gnu-gcc
+rk3399-m0-as-default-id := gnu-gcc
rk3399-m0-as-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-as-id-default := gnu-gcc
+rk3399-m0-ld-default-id := gnu-gcc
rk3399-m0-ld-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-ld-id-default := gnu-gcc
+rk3399-m0-oc-default-id := gnu-objcopy
rk3399-m0-oc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objcopy
-rk3399-m0-oc-id-default := gnu-objcopy
+rk3399-m0-od-default-id := gnu-objdump
rk3399-m0-od-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objdump
-rk3399-m0-od-id-default := gnu-objdump
+rk3399-m0-ar-default-id := gnu-ar
rk3399-m0-ar-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc-ar
-rk3399-m0-ar-id-default := gnu-ar
+rk3399-m0-dtc-default-id := generic-dtc
rk3399-m0-dtc-default := dtc
-rk3399-m0-dtc-id-default := generic-dtc
diff --git a/make_helpers/utilities.mk b/make_helpers/utilities.mk
index 45ef12e..efa0ab9 100644
--- a/make_helpers/utilities.mk
+++ b/make_helpers/utilities.mk
@@ -100,3 +100,23 @@
#
bool-01 = $(if $(call bool,$(1)),1,0)
+
+#
+# Determine whether a variable is defined or not.
+#
+# Parameters:
+#
+# - $(1): The variable to check.
+#
+# Example usage:
+#
+# xyz-defined := $(call defined,xyz) # <empty>
+#
+# xyz :=
+# xyz-defined := $(call defined,xyz) # <non-empty>
+#
+# xyz := hello
+# xyz-defined := $(call defined,xyz) # <non-empty>
+#
+
+defined = $(call bool,$(filter-out undefined,$(origin $(1))))
diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 3ab3dca..5fce01e 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c
@@ -31,7 +31,7 @@
MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
-#if defined(TRANSFER_LIST)
+#if TRANSFER_LIST
MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_BASE + FW_HANDOFF_SIZE,
MT_MEMORY | MT_RW | MT_NS),
#endif
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index e878863..64c356a 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -20,12 +20,14 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <plat_arm.h>
+#include <plat_console.h>
#include <scmi.h>
#include <def.h>
#include <plat_fdt.h>
#include <plat_private.h>
#include <plat_startup.h>
+#include <plat_xfer_list.h>
#include <pm_api_sys.h>
#include <pm_client.h>
@@ -74,6 +76,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
uint32_t uart_clock;
int32_t rc;
@@ -121,30 +127,7 @@
uart_clock = get_uart_clk();
- if (CONSOLE_IS(pl011_0) || CONSOLE_IS(pl011_1)) {
- static console_t _runtime_console;
-
- /* Initialize the console to provide early debug support */
- rc = console_pl011_register(UART_BASE, uart_clock,
- UART_BAUDRATE,
- &_runtime_console);
- if (rc == 0) {
- panic();
- }
-
- console_set_scope(&_runtime_console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
- } else if (CONSOLE_IS(dcc)) {
- /* Initialize the dcc console for debug.
- * dcc is over jtag and does not configures uart0 or uart1.
- */
- rc = console_dcc_register();
- if (rc == 0) {
- panic();
- }
- } else {
- /* Making MISRA C 2012 15.7 compliant */
- }
+ setup_console();
NOTICE("TF-A running on %s %d.%d\n", board_name_decode(),
platform_version / 10U, platform_version % 10U);
@@ -164,7 +147,12 @@
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
- bl31_set_default_config();
+
+ rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info);
+ if (rc == TL_OPS_NON || rc == TL_OPS_CUS) {
+ NOTICE("BL31: TL not found, using default config\n");
+ bl31_set_default_config();
+ }
long rev_var = cpu_get_rev_var();
@@ -206,6 +194,7 @@
static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
+ (void)id;
uint32_t intr_id;
uint32_t i;
interrupt_type_handler_t handler = NULL;
@@ -249,6 +238,8 @@
if (rc != 0) {
panic();
}
+
+ console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*
@@ -257,10 +248,6 @@
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
-#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
- MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
- MT_MEMORY | MT_RW | MT_NS),
-#endif
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index 67244a4..f3a7907 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h
@@ -15,12 +15,23 @@
#define MAX_INTR_EL3 2
/* List all consoles */
-#define CONSOLE_ID_pl011 U(1)
-#define CONSOLE_ID_pl011_0 U(1)
-#define CONSOLE_ID_pl011_1 U(2)
-#define CONSOLE_ID_dcc U(3)
+#define VERSAL2_CONSOLE_ID_none 0
+#define VERSAL2_CONSOLE_ID_pl011 1
+#define VERSAL2_CONSOLE_ID_pl011_0 1
+#define VERSAL2_CONSOLE_ID_pl011_1 2
+#define VERSAL2_CONSOLE_ID_dcc 3
+#define VERSAL2_CONSOLE_ID_dtb 4
-#define CONSOLE_IS(con) (CONSOLE_ID_ ## con == CONSOLE)
+#define CONSOLE_IS(con) (VERSAL2_CONSOLE_ID_ ## con == VERSAL2_CONSOLE)
+
+/* Runtime console */
+#define RT_CONSOLE_ID_pl011 1
+#define RT_CONSOLE_ID_pl011_0 1
+#define RT_CONSOLE_ID_pl011_1 2
+#define RT_CONSOLE_ID_dcc 3
+#define RT_CONSOLE_ID_dtb 4
+
+#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
/* List all platforms */
#define SILICON U(0)
@@ -143,11 +154,35 @@
#define UART_BAUDRATE 115200
-#if CONSOLE_IS(pl011_1)
-#define UART_BASE UART1_BASE
+#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
+#define UART_BASE UART0_BASE
+# define UART_TYPE CONSOLE_PL011
+#elif CONSOLE_IS(pl011_1)
+#define UART_BASE UART1_BASE
+# define UART_TYPE CONSOLE_PL011
+#elif CONSOLE_IS(dcc)
+# define UART_BASE 0x0
+# define UART_TYPE CONSOLE_DCC
+#elif CONSOLE_IS(none)
+# define UART_TYPE CONSOLE_NONE
+#else
+# error "invalid VERSAL2_CONSOLE"
+#endif
+
+/* Runtime console */
+#if defined(CONSOLE_RUNTIME)
+#if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb)
+# define RT_UART_BASE UART0_BASE
+# define RT_UART_TYPE CONSOLE_PL011
+#elif RT_CONSOLE_IS(pl011_1)
+# define RT_UART_BASE UART1_BASE
+# define RT_UART_TYPE CONSOLE_PL011
+#elif RT_CONSOLE_IS(dcc)
+# define RT_UART_BASE 0x0
+# define RT_UART_TYPE CONSOLE_DCC
#else
-/* Default console is UART0 */
-#define UART_BASE UART0_BASE
+# error "invalid CONSOLE_RUNTIME"
+#endif
#endif
#endif /* DEF_H */
diff --git a/plat/amd/versal2/include/platform_def.h b/plat/amd/versal2/include/platform_def.h
index 090fe46..42c9b08 100644
--- a/plat/amd/versal2/include/platform_def.h
+++ b/plat/amd/versal2/include/platform_def.h
@@ -91,7 +91,7 @@
#define PLAT_OCM_BASE U(0xBBF00000)
#define PLAT_OCM_LIMIT U(0xBC000000)
-#if defined(TRANSFER_LIST)
+#if TRANSFER_LIST
/*
* FIXME: This address should come from firmware before TF-A
* Having this to make sure the transfer list functionality works
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 1c977a3..3114976 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -6,6 +6,9 @@
PLAT_PATH := plat/amd/versal2
+override NEED_BL1 := no
+override NEED_BL2 := no
+
# A78 Erratum for SoC
ERRATA_A78_AE_1941500 := 1
ERRATA_A78_AE_1951502 := 1
@@ -28,11 +31,15 @@
override CTX_INCLUDE_AARCH32_REGS := 0
+# Platform to support Dynamic XLAT Table by default
+override PLAT_XLAT_TABLES_DYNAMIC := 1
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+
ifdef MEM_BASE
$(eval $(call add_define,MEM_BASE))
ifndef MEM_SIZE
- $(error "ATF_BASE defined without ATF_SIZE")
+ $(error "MEM_BASE defined without MEM_SIZE")
endif
$(eval $(call add_define,MEM_SIZE))
@@ -45,7 +52,7 @@
$(eval $(call add_define,BL32_MEM_BASE))
ifndef BL32_MEM_SIZE
- $(error "BL32_BASE defined without BL32_SIZE")
+ $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE")
endif
$(eval $(call add_define,BL32_MEM_SIZE))
endif
@@ -57,13 +64,28 @@
USE_COHERENT_MEM := 0
HW_ASSISTED_COHERENCY := 1
-CONSOLE ?= pl011
-ifeq (${CONSOLE}, $(filter ${CONSOLE},pl011 pl011_0 pl011_1 dcc))
+VERSAL2_CONSOLE ?= pl011
+ifeq (${VERSAL2_CONSOLE}, $(filter ${VERSAL2_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none))
+ else
+ $(error "Please define VERSAL2_CONSOLE")
+ endif
+
+$(eval $(call add_define_val,VERSAL2_CONSOLE,VERSAL2_CONSOLE_ID_${VERSAL2_CONSOLE}))
+
+# Runtime console in default console in DEBUG build
+ifeq ($(DEBUG), 1)
+CONSOLE_RUNTIME ?= pl011
+endif
+
+# Runtime console
+ifdef CONSOLE_RUNTIME
+ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb))
+$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
else
- $(error Please define CONSOLE)
+ $(error "Please define CONSOLE_RUNTIME")
+endif
endif
-$(eval $(call add_define_val,CONSOLE,CONSOLE_ID_${CONSOLE}))
ifdef XILINX_OF_BOARD_DTB_ADDR
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
@@ -109,6 +131,9 @@
BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
+ common/fdt_wrappers.c \
+ plat/xilinx/common/plat_fdt.c \
+ plat/xilinx/common/plat_console.c \
plat/xilinx/common/plat_startup.c \
plat/xilinx/common/ipi.c \
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
@@ -126,3 +151,9 @@
CORTEX_A78_AE_H_INC := 1
$(eval $(call add_define, CORTEX_A78_AE_H_INC))
endif
+
+# Enable Handoff protocol using transfer lists
+TRANSFER_LIST := 1
+
+include lib/transfer_list/transfer_list.mk
+BL31_SOURCES += plat/xilinx/common/plat_xfer_list.c
diff --git a/plat/amd/versal2/scmi.c b/plat/amd/versal2/scmi.c
index 7f4b6df..59aff08 100644
--- a/plat/amd/versal2/scmi.c
+++ b/plat/amd/versal2/scmi.c
@@ -51,8 +51,8 @@
CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000),
CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000),
CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000),
- CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000),
- CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000),
+ CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 26000000),
+ CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 26000000),
CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000),
CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000),
CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000),
@@ -649,6 +649,11 @@
/* Keep i2c on 100MHz to calculate rates properly */
if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
continue;
+
+ /* Keep UFS clocks to default values to get the expected rates */
+ if (i >= CLK_UFS0_0 && i <= CLK_UFS0_2)
+ continue;
+
/*
* SPP supports multiple versions.
* The cpu_clock value is set to corresponding SPP
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts b/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts
new file mode 100644
index 0000000..53cd3b0
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ hw-config {
+ load-address = <0x0 0x83000000>;
+ max-size = <0x8000>;
+ id = <HW_CONFIG_ID>;
+ };
+ };
+};
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S
new file mode 100644
index 0000000..8efe8ac
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <arm_macros.S>
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ *
+ * There are currently no platform specific regs
+ * to print.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
new file mode 100644
index 0000000..44c8ee3
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+/* These are referenced by arm_def.h #included next, so #define first. */
+#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0)
+
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_CORE_COUNT U(16)
+#define PLAT_ARM_CLUSTER_COUNT U(16)
+#define PLAT_MAX_CPUS_PER_CLUSTER U(1)
+#define PLAT_MAX_PE_PER_CPU U(1)
+
+#define PLATFORM_STACK_SIZE UL(0x1000)
+
+/* BL1 is not supported */
+#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0)
+#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0)
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000)
+
+/* USE_ROMLIB is not supported */
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
+
+/* Defined based on actual binary sizes */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0x0
+#define PLAT_ARM_MAX_BL2_SIZE 0x20000
+#define PLAT_ARM_MAX_BL31_SIZE 0x70000
+
+#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+
+#define PLAT_CSS_MHU_BASE UL(0x2A920000)
+#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
+
+#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
+#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
+#define SOC_CSS_UART_SIZE UL(0x10000)
+#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
+#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+
+/* Physical and virtual address space limits for MMU */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE UL(0x30000000)
+#define PLAT_ARM_GICR_BASE UL(0x301C0000)
+#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+/* Virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
+
+/* Secure Watchdog Constants */
+#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+#define V2M_SYSREGS_BASE UL(0x0C010000)
+#define V2M_SYS_LED U(0x8)
+
+#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+#ifdef IMAGE_BL2
+#define PLAT_ARM_MMAP_ENTRIES U(5)
+#else
+#define PLAT_ARM_MMAP_ENTRIES U(6)
+#endif
+#define MAX_XLAT_TABLES U(6)
+
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE)
+#define PLAT_FW_CONFIG_BASE ARM_FW_CONFIG_BASE
+
+/* RD1AE-specific memory mappings */
+#define RD1AE_EXTERNAL_FLASH MAP_REGION_FLAT(V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | \
+ MT_SECURE)
+
+#define RD1AE_MAP_NS_DRAM1 MAP_REGION_FLAT(ARM_DRAM1_BASE, \
+ ARM_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | \
+ MT_NS)
+
+#define RD1AE_DEVICE_BASE (0x20000000)
+#define RD1AE_DEVICE_SIZE (0x20000000)
+#define RD1AE_MAP_DEVICE MAP_REGION_FLAT(RD1AE_DEVICE_BASE, \
+ RD1AE_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | \
+ MT_SECURE)
+
+#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT(SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/* Non-volatile counters */
+#define TRUSTED_NVCTR_BASE_OFFSET UL(0x00E70000)
+#define TFW_NVCTR_BASE_OFFSET 0x0000
+#define NTFW_CTR_BASE_OFFSET 0x0004
+#define SOC_TRUSTED_NVCTR_BASE (SOC_PLATFORM_PERIPH_BASE + TRUSTED_NVCTR_BASE_OFFSET)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + TFW_NVCTR_BASE_OFFSET)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + NTFW_CTR_BASE_OFFSET)
+#define NTFW_CTR_SIZE U(4)
+
+/*******************************************************************************
+ * Memprotect definitions
+ ******************************************************************************/
+/* PSCI memory protect definitions:
+ * This variable is stored in a non-secure flash because some ARM reference
+ * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
+ * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
+ */
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - \
+ V2M_FLASH_BLOCK_SIZE)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S
new file mode 100644
index 0000000..32260ef
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_arm_calc_core_pos
+
+ /* ---------------------------------------------------------------------
+ * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
+ *
+ * Function to calculate the core position on rd1ae.
+ *
+ * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
+ * (CPUId * PLAT_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func plat_arm_calc_core_pos
+ mov x4, x0
+
+ /* Extract individual affinity fields from MPIDR */
+ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* Compute linear position */
+ mov x4, #PLAT_ARM_CLUSTER_COUNT
+ madd x2, x3, x4, x2
+ mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x4, x1
+ mov x4, #PLAT_MAX_PE_PER_CPU
+ madd x0, x1, x4, x0
+ ret
+endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
new file mode 100644
index 0000000..35cd8a1
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
@@ -0,0 +1,88 @@
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# RD1AE (Kronos) platform.
+$(info Platform ${PLAT} is (kronos) specific.)
+
+RD1AE_BASE = plat/arm/board/automotive_rd/platform/rd1ae
+
+PLAT_INCLUDES += -I${RD1AE_BASE}/include/
+
+override ARM_FW_CONFIG_LOAD_ENABLE := 1
+override ARM_PLAT_MT := 1
+override ARM_RECOM_STATE_ID_ENC := 1
+override CSS_LOAD_SCP_IMAGES := 0
+override CTX_INCLUDE_AARCH32_REGS := 0
+override ENABLE_SVE_FOR_NS := 1
+override ENABLE_SVE_FOR_SWD := 1
+override NEED_BL1 := 0
+override NEED_BL2U := 0
+override PSCI_EXTENDED_STATE_ID := 1
+
+ARM_ARCH_MAJOR := 9
+ARM_ARCH_MINOR := 2
+CSS_USE_SCMI_SDS_DRIVER := 1
+ENABLE_FEAT_AMU := 1
+ENABLE_FEAT_ECV := 1
+ENABLE_FEAT_FGT := 1
+ENABLE_FEAT_MTE2 := 1
+ENABLE_MPAM_FOR_LOWER_ELS := 1
+GIC_ENABLE_V4_EXTN := 1
+GICV3_SUPPORT_GIC600 := 1
+HW_ASSISTED_COHERENCY := 1
+PLAT_MHU_VERSION := 1
+RESET_TO_BL2 := 1
+SVE_VECTOR_LEN := 128
+USE_COHERENT_MEM := 0
+
+RD1AE_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
+
+include drivers/arm/gic/v3/gicv3.mk
+RD1AE_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c \
+ plat/arm/common/arm_gicv3.c
+
+PLAT_BL_COMMON_SOURCES += ${RD1AE_BASE}/rd1ae_plat.c \
+ ${RD1AE_BASE}/include/rd1ae_helpers.S
+
+BL2_SOURCES += ${RD1AE_CPU_SOURCES} \
+ ${RD1AE_BASE}/rd1ae_err.c \
+ ${RD1AE_BASE}/rd1ae_bl2_mem_params_desc.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
+ drivers/arm/sbsa/sbsa.c
+
+BL31_SOURCES += ${RD1AE_CPU_SOURCES} \
+ ${RD1AE_GIC_SOURCES} \
+ ${RD1AE_BASE}/rd1ae_bl31_setup.c \
+ ${RD1AE_BASE}/rd1ae_topology.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+BL2_SOURCES += ${RD1AE_BASE}/rd1ae_tbb.c
+endif
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${RD1AE_BASE}/fdts/${PLAT}_fw_config.dts \
+ fdts/${PLAT}.dts
+
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+FIP_BL2_ARGS := tb-fw
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+
+include plat/arm/common/arm_common.mk
+include plat/arm/css/common/css_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c
new file mode 100644
index 0000000..30cc90f
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+#if DEBUG
+ .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
+#endif
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+ /* Fill HW_CONFIG related information */
+ {
+ .image_id = HW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ NON_SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+ .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+ - PLAT_ARM_NS_IMAGE_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
new file mode 100644
index 0000000..ce7bad7
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/css/css_mhu_doorbell.h>
+#include <drivers/arm/css/scmi.h>
+
+static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+};
+
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
+{
+ return &plat_rd_scmi_info[channel_id];
+}
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+ return css_scmi_override_pm_ops(ops);
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
new file mode 100644
index 0000000..6254473
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/sbsa.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rd1ae error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ console_flush();
+
+ sbsa_wdog_refresh(SBSA_SECURE_WDOG_BASE);
+
+ while (1) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c
new file mode 100644
index 0000000..e917330
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/sbsa.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ RD1AE_MAP_DEVICE,
+ RD1AE_EXTERNAL_FLASH,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE,
+#if IMAGE_BL2
+ RD1AE_MAP_NS_DRAM1,
+#endif
+ {0}
+};
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+}
+
+/*
+ * For rd1ae we should not do anything in these interface functions.
+ * They are used to override the weak functions in cci drivers
+ */
+void plat_arm_interconnect_init(void)
+{
+}
+
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
+
+/*
+ * TZC programming is currently not done.
+ */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c
new file mode 100644
index 0000000..01fbcce
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier ::= SEQUENCE {
+ * algorithm OBJECT IDENTIFIER,
+ * parameters ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ * digestAlgorithm AlgorithmIdentifier,
+ * digest OCTET STRING
+ * }
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c
new file mode 100644
index 0000000..2533184
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ *
+ * This descriptor defines the layout of the power domain tree for the RD1AE
+ * platform, which consists of 16 clusters.
+ ******************************************************************************/
+const unsigned char rd1_ae_pd_tree_desc[] = {
+ (PLAT_ARM_CLUSTER_COUNT),
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rd1_ae_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+};
+
+unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
+{
+ return PLAT_MAX_CPUS_PER_CLUSTER;
+}
diff --git a/plat/arm/board/fvp/fvp_el3_token_sign.c b/plat/arm/board/fvp/fvp_el3_token_sign.c
new file mode 100644
index 0000000..282f94a
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_el3_token_sign.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2024, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+#include <services/rmm_el3_token_sign.h>
+
+static struct el3_token_sign_request el3_req = { 0 };
+static bool el3_req_valid;
+
+/*
+ * According to https://www.secg.org/sec1-v2.pdf 2.3.3
+ * the size of the ECDSA P384 public key is 97 bytes,
+ * with the first byte being 0x04.
+ */
+static uint8_t sample_attest_pub_key[] = {
+ 0x04, 0x76, 0xf9, 0x88, 0x09, 0x1b, 0xe5, 0x85, 0xed, 0x41,
+ 0x80, 0x1a, 0xec, 0xfa, 0xb8, 0x58, 0x54, 0x8c, 0x63, 0x05,
+ 0x7e, 0x16, 0xb0, 0xe6, 0x76, 0x12, 0x0b, 0xbd, 0x0d, 0x2f,
+ 0x9c, 0x29, 0xe0, 0x56, 0xc5, 0xd4, 0x1a, 0x01, 0x30, 0xeb,
+ 0x9c, 0x21, 0x51, 0x78, 0x99, 0xdc, 0x23, 0x14, 0x6b, 0x28,
+ 0xe1, 0xb0, 0x62, 0xbd, 0x3e, 0xa4, 0xb3, 0x15, 0xfd, 0x21,
+ 0x9f, 0x1c, 0xbb, 0x52, 0x8c, 0xb6, 0xe7, 0x4c, 0xa4, 0x9b,
+ 0xe1, 0x67, 0x73, 0x73, 0x4f, 0x61, 0xa1, 0xca, 0x61, 0x03,
+ 0x1b, 0x2b, 0xbf, 0x3d, 0x91, 0x8f, 0x2f, 0x94, 0xff, 0xc4,
+ 0x22, 0x8e, 0x50, 0x91, 0x95, 0x44, 0xae
+};
+
+/*
+ * FVP does not support HES, so provide 0's as keys.
+ */
+int plat_rmmd_el3_token_sign_get_rak_pub(uintptr_t buf, size_t *len,
+ unsigned int type)
+{
+ (void)type;
+ if (*len < sizeof(sample_attest_pub_key)) {
+ return E_RMM_INVAL;
+ }
+
+ if (type != ATTEST_KEY_CURVE_ECC_SECP384R1) {
+ ERROR("Invalid ECC curve specified\n");
+ return E_RMM_INVAL;
+ }
+
+ *len = sizeof(sample_attest_pub_key);
+
+ (void)memcpy((void *)buf, sample_attest_pub_key,
+ sizeof(sample_attest_pub_key));
+
+ return 0;
+}
+
+int plat_rmmd_el3_token_sign_push_req(const struct el3_token_sign_request *req)
+{
+ /*
+ * TODO: Today this function is called with a lock held on the
+ * RMM<->EL3 shared buffer. In the future, we may move to a
+ * different design that may require handling multi-threaded
+ * calls to this function, for example, if we have a per CPU
+ * buffer between RMM and EL3.
+ */
+ if (el3_req_valid) {
+ return E_RMM_AGAIN;
+ }
+
+ el3_req = *req;
+
+ if ((el3_req.hash_alg_id != EL3_TOKEN_SIGN_HASH_ALG_SHA384) ||
+ (el3_req.sig_alg_id != ATTEST_KEY_CURVE_ECC_SECP384R1)) {
+ return E_RMM_INVAL;
+ }
+
+ el3_req_valid = true;
+
+ return 0;
+}
+
+int plat_rmmd_el3_token_sign_pull_resp(struct el3_token_sign_response *resp)
+{
+ if (!el3_req_valid) {
+ return E_RMM_AGAIN;
+ }
+
+ resp->rec_granule = el3_req.rec_granule;
+ resp->req_ticket = el3_req.req_ticket;
+ resp->sig_len = (uint16_t)sizeof(resp->signature_buf);
+ /* TODO: Provide real signature */
+ memset(resp->signature_buf, 0, sizeof(resp->signature_buf));
+
+ el3_req_valid = false;
+
+ return 0;
+}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index a900a9b..e0c9725 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -149,6 +149,10 @@
#define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE
#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+#if RESET_TO_BL31
+#define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET
+#endif
+
#else
#define PLAT_ARM_FW_HANDOFF_SIZE U(0)
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index bbd9141..1ec1943 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -71,11 +71,13 @@
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
ENABLE_FEAT_FGT2 := 2
+ENABLE_FEAT_THE := 2
ENABLE_FEAT_TCR2 := 2
ENABLE_FEAT_S2PIE := 2
ENABLE_FEAT_S1PIE := 2
ENABLE_FEAT_S2POE := 2
ENABLE_FEAT_S1POE := 2
+ENABLE_FEAT_SCTLR2 := 2
ENABLE_FEAT_MTE2 := 2
# The FVP platform depends on this macro to build with correct GIC driver.
@@ -209,10 +211,11 @@
#Build AArch64-only CPUs with no FVP model yet.
ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
- FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
+ FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
- lib/cpus/aarch64/travis.S
+ lib/cpus/aarch64/travis.S \
+ lib/cpus/aarch64/cortex_arcadia.S
endif
else
@@ -264,7 +267,8 @@
plat/arm/board/fvp/fvp_cpu_pwr.c
BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \
- plat/arm/board/fvp/fvp_realm_attest_key.c
+ plat/arm/board/fvp/fvp_realm_attest_key.c \
+ plat/arm/board/fvp/fvp_el3_token_sign.c
endif
ifeq (${ENABLE_FEAT_RNG_TRAP},1)
@@ -392,9 +396,10 @@
ifeq ($(RESET_TO_BL31), 1)
HW_CONFIG := ${FVP_HW_CONFIG}
-FW_HANDOFF_SIZE := 20000
+FW_HANDOFF_SIZE := 20000
-$(eval $(call add_define,ARM_PRELOADED_DTB_OFFSET))
+TRANSFER_LIST_DTB_OFFSET := 0x20
+$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET))
endif
endif
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
index 1b92ec2..3fbc125 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -111,4 +111,18 @@
ARM_REALM_SIZE, \
MT_MEMORY | MT_RW | MT_REALM)
+#if RESET_TO_BL31
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+
+/* Define the DTB image base and size */
+#define NRD_CSS_BL31_PRELOAD_DTB_BASE UL(0xF3000000)
+#define NRD_CSS_BL31_PRELOAD_DTB_SIZE UL(0x1000)
+#define NRD_CSS_MAP_BL31_DTB MAP_REGION_FLAT( \
+ NRD_CSS_BL31_PRELOAD_DTB_BASE, \
+ NRD_CSS_BL31_PRELOAD_DTB_SIZE, \
+ MT_RW_DATA | MT_NS)
+#endif /* RESET_TO_BL31 */
+
#endif /* NRD_CSS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
index 0dce512..8d6d1cb 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -56,8 +56,8 @@
* chips are accessed - secure ram, css device and soc device regions.
*/
#if defined(IMAGE_BL31)
-# define PLAT_ARM_MMAP_ENTRIES (9 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (10 + ((NRD_CHIP_COUNT - 1) * 3))
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES U(8)
# define MAX_XLAT_TABLES U(5)
@@ -442,7 +442,7 @@
* SRAM layout
******************************************************************************/
-/*
+/* if !RESET_TO_BL31
* Trusted SRAM
* 0x00100000 +--------------+
* | L0 GPT |
@@ -460,6 +460,26 @@
* 0x00019000 +--------------+
* | BL1 (ro) |
* 0x00000000 +--------------+
+ *
+ * else
+ *
+ * Trusted SRAM
+ * 0x00100000 +--------------+
+ * | L0 GPT |
+ * 0x000E0000 +--------------
+ * | | side-loaded +----------------+
+ * | | <<<<<<<<<<<<< | |
+ * | | <<<<<<<<<<<<< | BL31 NOBITS |
+ * | | <<<<<<<<<<<<< | |
+ * | | <<<<<<<<<<<<< |----------------|
+ * | | <<<<<<<<<<<<< | BL31 PROGBITS |
+ * 0x00063000 | | +----------------+
+ * 0x0001A000 +--------------+
+ * | Shared |
+ * 0x00019000 +--------------+
+ * | BL1 (ro) |
+ * 0x00000000 +--------------+
+ * endif
*/
/*******************************************************************************
@@ -531,7 +551,11 @@
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
+#if RESET_TO_BL31
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE)
+#else
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+#endif
/*******************************************************************************
* BL1 RW specifics
@@ -556,9 +580,13 @@
******************************************************************************/
/* Keep BL31 below BL2 in the Trusted SRAM.*/
+#if RESET_TO_BL31
+#define BL31_BASE (0x63000)
+#else
#define BL31_BASE ((ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE) - \
PLAT_ARM_MAX_BL31_SIZE)
+#endif
#define BL31_PROGBITS_LIMIT BL2_BASE
#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
diff --git a/plat/arm/board/neoverse_rd/common/nrd-common.mk b/plat/arm/board/neoverse_rd/common/nrd-common.mk
index 95a221f..a09f369 100644
--- a/plat/arm/board/neoverse_rd/common/nrd-common.mk
+++ b/plat/arm/board/neoverse_rd/common/nrd-common.mk
@@ -54,11 +54,6 @@
${NRD_COMMON_BASE}/nrd_topology.c \
drivers/delay_timer/generic_delay_timer.c
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
$(eval $(call add_define,NRD_CHIP_COUNT))
$(eval $(call add_define,NRD_PLATFORM_VARIANT))
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 18aa2fb..bce8834 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -155,6 +155,65 @@
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
}
+/*******************************************************************************
+ * This function inserts platform information via device tree nodes as,
+ * system-id {
+ * platform-id = <0>;
+ * config-id = <0>;
+ * }
+ ******************************************************************************/
+#if RESET_TO_BL31
+static int append_config_node(uintptr_t fdt_base_addr, uintptr_t fdt_base_size)
+{
+ void *fdt;
+ int nodeoffset, err;
+ unsigned int platid = 0, platcfg = 0;
+
+ if (fdt_base_addr == 0) {
+ ERROR("NT_FW CONFIG base address is NULL\n");
+ return -1;
+ }
+
+ fdt = (void *)fdt_base_addr;
+
+ /* Check the validity of the fdt */
+ if (fdt_check_header(fdt) != 0) {
+ ERROR("Invalid NT_FW_CONFIG DTB passed\n");
+ return -1;
+ }
+
+ nodeoffset = fdt_subnode_offset(fdt, 0, "system-id");
+ if (nodeoffset < 0) {
+ ERROR("Failed to get system-id node offset\n");
+ return -1;
+ }
+
+ platid = plat_arm_nrd_get_platform_id();
+ err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid);
+ if (err < 0) {
+ ERROR("Failed to set platform-id\n");
+ return -1;
+ }
+
+ platcfg = plat_arm_nrd_get_config_id();
+ err = fdt_setprop_u32(fdt, nodeoffset, "config-id", platcfg);
+ if (err < 0) {
+ ERROR("Failed to set config-id\n");
+ return -1;
+ }
+
+ platcfg = plat_arm_nrd_get_multi_chip_mode();
+ err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg);
+ if (err < 0) {
+ ERROR("Failed to set multi-chip-mode\n");
+ return -1;
+ }
+
+ flush_dcache_range((uintptr_t)fdt, fdt_base_size);
+ return 0;
+}
+#endif
+
void nrd_bl31_common_platform_setup(void)
{
generic_delay_timer_init();
@@ -169,6 +228,15 @@
ehf_register_priority_handler(PLAT_REBOOT_PRI,
css_reboot_interrupt_handler);
#endif
+
+#if RESET_TO_BL31
+ int ret = append_config_node(NRD_CSS_BL31_PRELOAD_DTB_BASE,
+ NRD_CSS_BL31_PRELOAD_DTB_SIZE);
+
+ if (ret != 0) {
+ panic();
+ }
+#endif
}
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
index 7b98052..00f346e 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat3.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -60,6 +60,9 @@
NRD_CSS_GPT_L1_DRAM_MMAP,
NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
+#if RESET_TO_BL31
+ NRD_CSS_MAP_BL31_DTB,
+#endif
{0}
};
#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
index 15fc9bb..4892804 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
@@ -71,6 +71,11 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index c8f0899..c2dfba6 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
@@ -103,6 +103,11 @@
$(eval $(call TOOL_ADD_PAYLOAD,${TOS_FW_CONFIG},--tos-fw-config,${TOS_FW_CONFIG}))
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_FEAT_AMU := 2
override ENABLE_FEAT_MTE2 := 2
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
index fe87779..db8efbb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
@@ -66,5 +66,10 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
# Enable the flag since RD-V1 has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
index a0a1204..6d518d5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
@@ -77,5 +77,10 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
# Enable the flag since RD-V1-MC has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index 98029bb..f37d903 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
@@ -24,6 +24,24 @@
# Misc options
override CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${PLAT_RESET_TO_BL31}, 1)
+# Support for BL31 boot flow
+override RESET_TO_BL31 := 1
+
+# arm_common.mk sets ENABLE_PIE=1, but Makefile blocks PIE for RME
+override ENABLE_PIE := 0
+
+# Non Trusted Firmware parameters
+override ARM_PRELOADED_DTB_BASE := 0xF3000000
+override ARM_LINUX_KERNEL_AS_BL33 := 1
+override PRELOADED_BL33_BASE := 0xE0000000
+
+# These are internal build flags but as of now RESET_TO_BL31 won't work without defining them
+override NEED_BL1 := no
+override NEED_BL2 := no
+override NEED_BL32 := no
+endif
+
# RD-V3 platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
@@ -86,6 +104,10 @@
${RDV3_BASE}/rdv3_bl2_measured_boot.c
endif
+ifeq (${PLAT_RESET_TO_BL31}, 1)
+BL31_SOURCES += ${RDV3_BASE}/rdv3_security.c
+endif
+
BL31_SOURCES += ${NRD_CPU_SOURCES} \
${MBEDTLS_SOURCES} \
${RSE_COMMS_SOURCES} \
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
index 21675f6..a5d687e 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
@@ -130,3 +130,92 @@
WARN("Failed initializing AP-RSE comms.\n");
}
}
+
+#if RESET_TO_BL31
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ NRD_PAS_SHARED_SRAM,
+ NRD_PAS_SYSTEM_NCI,
+ NRD_PAS_DEBUG_NIC,
+ NRD_PAS_NS_UART,
+ NRD_PAS_REALM_UART,
+ NRD_PAS_AP_NS_WDOG,
+ NRD_PAS_AP_ROOT_WDOG,
+ NRD_PAS_AP_SECURE_WDOG,
+ NRD_PAS_SECURE_SRAM_ERB_AP,
+ NRD_PAS_NS_SRAM_ERB_AP,
+ NRD_PAS_ROOT_SRAM_ERB_AP,
+ NRD_PAS_REALM_SRAM_ERB_AP,
+ NRD_PAS_SECURE_SRAM_ERB_SCP,
+ NRD_PAS_NS_SRAM_ERB_SCP,
+ NRD_PAS_ROOT_SRAM_ERB_SCP,
+ NRD_PAS_REALM_SRAM_ERB_SCP,
+ NRD_PAS_SECURE_SRAM_ERB_MCP,
+ NRD_PAS_NS_SRAM_ERB_MCP,
+ NRD_PAS_ROOT_SRAM_ERB_MCP,
+ NRD_PAS_REALM_SRAM_ERB_MCP,
+ NRD_PAS_SECURE_SRAM_ERB_RSE,
+ NRD_PAS_NS_SRAM_ERB_RSE,
+ NRD_PAS_ROOT_SRAM_ERB_RSE,
+ NRD_PAS_REALM_SRAM_ERB_RSE,
+ NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_RSE_NS_SRAM_ERB_RSM,
+ NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_SCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_MCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_AP_SCP_ROOT_MHU,
+ NRD_PAS_AP_MCP_NS_MHU,
+ NRD_PAS_AP_MCP_SECURE_MHU,
+ NRD_PAS_AP_MCP_ROOT_MHU,
+ NRD_PAS_AP_RSE_NS_MHU,
+ NRD_PAS_AP_RSE_SECURE_MHU,
+ NRD_PAS_AP_RSE_ROOT_MHU,
+ NRD_PAS_AP_RSE_REALM_MHU,
+ NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
+ NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
+ NRD_PAS_STM_SYSTEM_ITS,
+ NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
+ NRD_PAS_GIC,
+ NRD_PAS_NS_DRAM,
+ NRD_PAS_RMM,
+ NRD_PAS_L1GPT,
+ NRD_PAS_CMN,
+ NRD_PAS_LCP_PERIPHERAL,
+ NRD_PAS_DDR_IO,
+ NRD_PAS_SMMU_NCI_IO,
+ NRD_PAS_DRAM2_CHIP0,
+#if NRD_CHIP_COUNT > 1
+ NRD_PAS_DRAM1_CHIP1,
+ NRD_PAS_DRAM2_CHIP1,
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_PAS_DRAM1_CHIP2,
+ NRD_PAS_DRAM2_CHIP2,
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_PAS_DRAM1_CHIP3,
+ NRD_PAS_DRAM2_CHIP3
+#endif
+};
+
+static const arm_gpt_info_t arm_gpt_info = {
+ .pas_region_base = pas_regions,
+ .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
+ .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
+ .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
+ .l0_size = (size_t)ARM_L0_GPT_SIZE,
+ .l1_size = (size_t)ARM_L1_GPT_SIZE,
+ .pps = GPCCR_PPS_256TB,
+ .pgs = GPCCR_PGS_4K
+};
+
+const arm_gpt_info_t *plat_arm_get_gpt_info(void)
+{
+ return &arm_gpt_info;
+}
+
+#endif /* RESET_TO_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
index 37306be..1f40107 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
@@ -65,4 +65,9 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
index a6b63a1..737997d 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
@@ -99,11 +99,7 @@
memory@1 {
device_type = "ns-memory";
- reg =
-#ifdef TS_SP_FW_CONFIG
- <0x0 0x08000000 0x0 0x4000000>,
-#endif /* TS_SP_FW_CONFIG */
- <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
+ reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
@@ -117,4 +113,11 @@
device_type = "device-memory";
reg = <0x0 PLAT_ARM_BOOT_UART_BASE 0x0 0x01000>;
};
+
+#ifdef TS_SP_FW_CONFIG
+ ns_flash {
+ device_type = "ns-device-memory";
+ reg = <0x0 V2M_FLASH0_BASE 0x0 V2M_FLASH0_SIZE>;
+ };
+#endif
};
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 0652148..613f508 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -51,9 +51,6 @@
* | (4KB) |
* 0x8000_9000 ------------------
* | ... |
- * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE
- * | FWU shmem |
- * | (4MB) |
* 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE
* | OP-TEE shmem |
* | (2MB) |
@@ -85,8 +82,6 @@
#define TC_NS_OPTEE_SIZE (2 * SZ_1M)
#define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE)
-#define TC_NS_FWU_SIZE (4 * SZ_1M)
-#define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE)
/*
* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
@@ -192,7 +187,7 @@
# if SPM_MM
# define PLATFORM_STACK_SIZE 0x500
# else
-# define PLATFORM_STACK_SIZE 0xa00
+# define PLATFORM_STACK_SIZE 0xb00
# endif
#elif defined(IMAGE_BL32)
# define PLATFORM_STACK_SIZE 0x440
@@ -228,7 +223,7 @@
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
-#define PLAT_ARM_NSTIMER_FRAME_ID 0
+#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk
index 8d39325..2ce6648 100644
--- a/plat/arm/board/tc/platform_test.mk
+++ b/plat/arm/board/tc/platform_test.mk
@@ -33,6 +33,7 @@
$(eval $(call add_define,PLATFORM_TEST_ROTPK))
else ifeq (${PLATFORM_TEST},tfm-testsuite)
include drivers/arm/rse/rse_comms.mk
+ include drivers/measured_boot/rse/qcbor.mk
# The variables need to be set to compile the platform test:
ifeq (${TF_M_TESTS_PATH},)
@@ -80,7 +81,8 @@
$(DELEGATED_ATTEST_TESTS_PATH)/delegated_attest_test.c \
drivers/auth/mbedtls/mbedtls_common.c \
lib/psa/measured_boot.c \
- lib/psa/delegated_attestation.c
+ lib/psa/delegated_attestation.c \
+ ${QCBOR_SOURCES}
PLAT_INCLUDES += -I$(TF_M_EXTRAS_PATH)/partitions/measured_boot/interface/include \
-I$(TF_M_EXTRAS_PATH)/partitions/delegated_attestation/interface/include \
@@ -93,7 +95,8 @@
-Iplat/arm/board/tc \
-Iinclude/drivers/auth/mbedtls \
-Iinclude/drivers/arm \
- -Iinclude/lib/psa
+ -Iinclude/lib/psa \
+ -I${QCBOR_INCLUDES}
# Some of the PSA functions are declared in multiple header files, that
# triggers this warning.
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 01e0db0..869830d 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,8 @@
#include <drivers/generic_delay_timer.h>
#include <drivers/partition/partition.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -64,6 +66,43 @@
generic_delay_timer_init();
}
+#if ARM_FW_CONFIG_LOAD_ENABLE
+/*************************************************************************************
+ * FW CONFIG load function for BL2 when RESET_TO_BL2=1 && ARM_FW_CONFIG_LOAD_ENABLE=1
+ *************************************************************************************/
+void arm_bl2_el3_plat_config_load(void)
+{
+ int ret;
+ const struct dyn_cfg_dtb_info_t *fw_config_info;
+
+ /* Set global DTB info for fixed fw_config information */
+ set_config_info(PLAT_FW_CONFIG_BASE, ~0UL, PLAT_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
+
+ /* Fill the device tree information struct with the info from the config dtb */
+ ret = fconf_load_config(FW_CONFIG_ID);
+ if (ret < 0) {
+ ERROR("Loading of FW_CONFIG failed %d\n", ret);
+ plat_error_handler(ret);
+ }
+
+ /*
+ * FW_CONFIG loaded successfully. Check the FW_CONFIG device tree parsing
+ * is successful.
+ */
+ fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+ if (fw_config_info == NULL) {
+ ret = -1;
+ ERROR("Invalid FW_CONFIG address\n");
+ plat_error_handler(ret);
+ }
+ ret = fconf_populate_dtb_registry(fw_config_info->config_addr);
+ if (ret < 0) {
+ ERROR("Parsing of FW_CONFIG failed %d\n", ret);
+ plat_error_handler(ret);
+ }
+}
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
+
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only initializes the mmu in a quick and dirty way.
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index b5a7db1..90ee70c 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -42,7 +42,7 @@
#if TRANSFER_LIST
CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE,
assert_bl2_base_overflows);
-#else
+#elif !RESET_TO_BL2
CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
#endif /* TRANSFER_LIST */
@@ -140,6 +140,9 @@
arm_transfer_list_dyn_cfg_init(secure_tl);
#else
+#if ARM_FW_CONFIG_LOAD_ENABLE
+ arm_bl2_el3_plat_config_load();
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
arm_bl2_dyn_cfg_init();
#endif
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index e91746b..3650854 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -147,8 +148,7 @@
bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
- bl33_image_ep_info.args.arg0 =
- FW_NS_HANDOFF_BASE + ARM_PRELOADED_DTB_OFFSET;
+ bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET;
bl33_image_ep_info.args.arg1 =
TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE;
@@ -545,6 +545,13 @@
enable_mmu_el3(0);
#if ENABLE_RME
+#if RESET_TO_BL31
+ /* initialize GPT only when RME is enabled. */
+ assert(is_feat_rme_present());
+
+ /* Initialise and enable granule protection after MMU. */
+ arm_gpt_setup();
+#endif /* RESET_TO_BL31 */
/*
* Initialise Granule Protection library and enable GPC for the primary
* processor. The tables have already been initialized by a previous BL
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 859791d..2fd993c 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -164,6 +164,25 @@
ENABLE_PIE := 1
endif
+# On Arm platform, disable ARM_FW_CONFIG_LOAD_ENABLE by default.
+ARM_FW_CONFIG_LOAD_ENABLE := 0
+$(eval $(call assert_boolean,ARM_FW_CONFIG_LOAD_ENABLE))
+$(eval $(call add_define,ARM_FW_CONFIG_LOAD_ENABLE))
+
+# In order to enable ARM_FW_CONFIG_LOAD_ENABLE for the Arm platform, the
+# platform should be reset to BL2 (RESET_TO_BL2=1), and FW_CONFIG must be
+# specified.
+ifeq (${ARM_FW_CONFIG_LOAD_ENABLE},1)
+ ifneq (${RESET_TO_BL2},1)
+ $(error RESET_TO_BL2 must be enabled when ARM_FW_CONFIG_LOAD_ENABLE \
+ is enabled)
+ endif
+ ifeq (${FW_CONFIG},)
+ $(error FW_CONFIG must be specified when ARM_FW_CONFIG_LOAD_ENABLE \
+ is enabled)
+ endif
+endif
+
# Disable GPT parser support, use FIP image by default
ARM_GPT_SUPPORT := 0
$(eval $(call assert_boolean,ARM_GPT_SUPPORT))
@@ -275,7 +294,7 @@
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
else
-ifneq (${PLAT}, corstone1000)
+ifeq ($(filter $(PLAT), corstone1000 rd1ae),)
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
endif
endif
@@ -469,20 +488,6 @@
endif
endif
-TRANSFER_LIST_BIN := ${BUILD_PLAT}/tl.bin
-
-.PHONY: tl
-tl: ${HW_CONFIG}
- @echo " TLC ${TRANSFER_LIST_BIN}"
- $(Q)${PYTHON} -m tools.tlc.tlc create --fdt ${HW_CONFIG} -s ${FW_HANDOFF_SIZE} ${TRANSFER_LIST_BIN}
- $(Q)$(eval ARM_PRELOADED_DTB_OFFSET := `tlc info --fdt-offset ${TRANSFER_LIST_BIN}`)
-
-ifeq (${TRANSFER_LIST}, 1)
- ifeq (${RESET_TO_BL31}, 1)
- bl31: tl
- endif
-endif
-
ifneq ($(COTDTPATH),)
cot-dt-defines = IMAGE_BL2 $(BL2_DEFINES) $(PLAT_BL_COMMON_DEFINES)
cot-dt-include-dirs = $(BL2_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)
@@ -498,8 +503,8 @@
$(q)$($(ARCH)-cpp) $(cot-dt-cpp-flags)
$(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c): $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.dts) | $$(@D)/
- $(q)poetry -q install
- $(q)poetry run cot-dt2c convert-to-c $< $@
+ $(if $(host-poetry),$(q)poetry -q install)
+ $(q)$(if $(host-poetry),poetry run )cot-dt2c convert-to-c $< $@
BL2_SOURCES += $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c)
endif
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 36820b2..084539e 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -129,11 +129,13 @@
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
+ NOTICE("SDMMC boot\n");
dw_mmc_init(¶ms, &mmc_info);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break;
case BOOT_SOURCE_QSPI:
+ NOTICE("QSPI boot\n");
cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 6e45158..4c10e7b 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,12 +14,16 @@
#include <drivers/ti/uart/uart_16550.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
+#include <plat/common/platform.h>
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
#include "socfpga_sip_svc.h"
+/* Get non-secure SPSR for BL33. Zephyr and Linux */
+uint32_t arm_get_spsr_for_bl33_entry(void);
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -59,9 +64,7 @@
u_register_t arg2, u_register_t arg3)
{
static console_t console;
-
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
-
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
/*
@@ -69,6 +72,33 @@
*/
void *from_bl2 = (void *) arg0;
+#if RESET_TO_BL31
+ /* There are no parameters from BL2 if BL31 is a reset vector */
+ assert(from_bl2 == NULL);
+ void *plat_params_from_bl2 = (void *) arg3;
+
+ assert(plat_params_from_bl2 == NULL);
+
+ /* Populate entry point information for BL33 */
+ SET_PARAM_HEAD(&bl33_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+
+# if ARM_LINUX_KERNEL_AS_BL33
+ /*
+ * According to the file ``Documentation/arm64/booting.txt`` of the
+ * Linux kernel tree, Linux expects the physical address of the device
+ * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+ * must be 0.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+# endif
+
+#else /* RESET_TO_BL31 */
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
assert(params_from_bl2 != NULL);
@@ -76,28 +106,38 @@
* Copy BL32 (if populated by BL31) and BL33 entry point information.
* They are stored in Secure RAM, in BL31's address space.
*/
-
if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
params_from_bl2->h.version >= VERSION_2) {
-
bl_params_node_t *bl_params = params_from_bl2->head;
-
while (bl_params) {
if (bl_params->image_id == BL33_IMAGE_ID)
bl33_image_ep_info = *bl_params->ep_info;
-
bl_params = bl_params->next_params_info;
}
} else {
struct socfpga_bl31_params *arg_from_bl2 =
(struct socfpga_bl31_params *) from_bl2;
-
assert(arg_from_bl2->h.type == PARAM_BL31);
assert(arg_from_bl2->h.version >= VERSION_1);
-
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
}
+
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+#endif
+
+ /*
+ * Tell BL31 where the non-trusted software image
+ * is located and the entry state information
+ */
+# if ARM_LINUX_KERNEL_AS_BL33
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+#endif
+
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
@@ -172,8 +212,34 @@
#endif
{0}
};
-
setup_page_tables(bl_regions, plat_agilex_mmap);
enable_mmu_el3(0);
}
+/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+#ifdef PRELOADED_BL33_BASE
+ return PRELOADED_BL33_BASE;
+#else
+ return PLAT_NS_IMAGE_OFFSET;
+#endif
+}
+
+/* Get non-secure SPSR for BL33. Zephyr and Linux */
+uint32_t arm_get_spsr_for_bl33_entry(void)
+{
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h
index 9db4292..f0bbeea 100644
--- a/plat/intel/soc/agilex/include/agilex_memory_controller.h
+++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +28,7 @@
#define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
#define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
-#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff
+#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x0000000f
#define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 9ef7598..72ffbe2 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,9 +16,15 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+/* 1 = Flush cache, 0 = No cache flush.
+ * Default for Agilex is No cache flush.
+ * For Agilex FP8, set to Flush cache.
+ */
+#define CACHE_FLUSH 0
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@@ -27,6 +34,13 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 265ee57..b75c78c 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -20,9 +20,11 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include "agilex5_clock_manager.h"
+#include "agilex5_ddr.h"
#include "agilex5_memory_controller.h"
#include "agilex5_mmc.h"
#include "agilex5_pinmux.h"
+#include "agilex5_power_manager.h"
#include "agilex5_system_manager.h"
#include "ccu/ncore_ccu.h"
#include "combophy/combophy.h"
@@ -70,29 +72,50 @@
u_register_t x2, u_register_t x4)
{
static console_t console;
+ handoff reverse_handoff_ptr;
- handoff reverse_handoff_ptr = { 0 };
+ /* Enable nonsecure access for peripherals and other misc components */
+ enable_nonsecure_access();
+
+ /* Bring all the required peripherals out of reset */
+ deassert_peripheral_reset();
+
+ /*
+ * Initialize the UART console early in BL2 EL3 boot flow to get
+ * the error/notice messages wherever required.
+ */
+ console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
+ PLAT_BAUDRATE, &console);
+ /* Generic delay timer init */
generic_delay_timer_init();
+
+ socfpga_delay_timer_init();
+
+ /* Get the handoff data */
+ if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) {
+ ERROR("BL2: Failed to get the correct handoff data\n");
+ panic();
+ }
+
config_clkmgr_handoff(&reverse_handoff_ptr);
+ /* Configure power manager PSS SRAM power gate */
+ config_pwrmgr_handoff(&reverse_handoff_ptr);
+
+ /* Initialize the mailbox to enable communication between HPS and SDM */
mailbox_init();
- enable_nonsecure_access();
- deassert_peripheral_reset();
+ /* DDR and IOSSM driver init */
+ agilex5_ddr_init(&reverse_handoff_ptr);
+
if (combo_phy_init(&reverse_handoff_ptr) != 0) {
ERROR("Combo Phy initialization failed\n");
}
- console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
- PLAT_BAUDRATE, &console);
-
- /* Store magic number */
- // TODO: Temp workaround to ungate testing
- // mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
-
+ /* Enable FPGA bridges as required */
if (!intel_mailbox_is_fpga_not_ready()) {
socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
- FPGA2SOC_MASK | F2SDRAM0_MASK);
+ FPGA2SOC_MASK | F2SDRAM0_MASK);
}
}
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 8d3928f..b6fc93e 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +18,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
+#include "agilex5_cache.h"
#include "agilex5_power_manager.h"
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
@@ -56,9 +58,8 @@
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
- PLAT_BAUDRATE, &console);
+ PLAT_BAUDRATE, &console);
- init_ncore_ccu();
setup_smmu_stream_id();
/*
@@ -189,11 +190,12 @@
uint32_t boot_core = 0x00;
uint32_t cpuid = 0x00;
- cpuid = read_mpidr();
- boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
+ cpuid = MPIDR_AFFLVL1_VAL(read_mpidr());
+ boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10);
NOTICE("BL31: Boot Core = %x\n", boot_core);
NOTICE("BL31: CPU ID = %x\n", cpuid);
-
+ INFO("BL31: Invalidate Data cache\n");
+ invalidate_dcache_all();
}
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
diff --git a/plat/intel/soc/agilex5/include/agilex5_cache.h b/plat/intel/soc/agilex5/include/agilex5_cache.h
new file mode 100644
index 0000000..f7801b9
--- /dev/null
+++ b/plat/intel/soc/agilex5/include/agilex5_cache.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX5_CACHE_H
+#define AGX5_CACHE_H
+
+void invalidate_dcache_all(void);
+void invalidate_cache_low_el(void);
+
+#endif /* AGX5_CACHE_H */
diff --git a/plat/intel/soc/agilex5/include/agilex5_ddr.h b/plat/intel/soc/agilex5/include/agilex5_ddr.h
new file mode 100644
index 0000000..631e006
--- /dev/null
+++ b/plat/intel/soc/agilex5/include/agilex5_ddr.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGILEX5_DDR_H
+#define AGILEX5_DDR_H
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <lib/utils_def.h>
+
+#include "socfpga_handoff.h"
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+typedef phys_addr_t fdt_addr_t;
+
+/* DDR/RAM configuration */
+struct ddr_info {
+ phys_addr_t start;
+ phys_size_t size;
+};
+
+int agilex5_ddr_init(handoff *hoff_ptr);
+
+#endif /* AGILEX5_DDR_H */
diff --git a/plat/intel/soc/agilex5/include/agilex5_iossm_mailbox.h b/plat/intel/soc/agilex5/include/agilex5_iossm_mailbox.h
new file mode 100644
index 0000000..1fd8ef6
--- /dev/null
+++ b/plat/intel/soc/agilex5/include/agilex5_iossm_mailbox.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGILEX5_IOSSM_MAILBOX_H
+#define AGILEX5_IOSSM_MAILBOX_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "lib/mmio.h"
+#include "agilex5_ddr.h"
+
+#define TIMEOUT_5000MS 5000
+#define TIMEOUT TIMEOUT_5000MS
+#define IOSSM_STATUS_CAL_SUCCESS BIT(0)
+#define IOSSM_STATUS_CAL_FAIL BIT(1)
+#define IOSSM_STATUS_CAL_BUSY BIT(2)
+#define IOSSM_STATUS_COMMAND_RESPONSE_READY 1
+#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C
+#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458
+#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454
+#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450
+#define IOSSM_CMD_REQ_OFFSET 0x43C
+#define IOSSM_CMD_PARAM_0_OFFSET 0x438
+#define IOSSM_CMD_PARAM_1_OFFSET 0x434
+#define IOSSM_CMD_PARAM_2_OFFSET 0x430
+#define IOSSM_CMD_PARAM_3_OFFSET 0x42C
+#define IOSSM_CMD_PARAM_4_OFFSET 0x428
+#define IOSSM_CMD_PARAM_5_OFFSET 0x424
+#define IOSSM_CMD_PARAM_6_OFFSET 0x420
+#define IOSSM_STATUS_OFFSET 0x400
+#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
+#define IOSSM_CMD_RESPONSE_DATA_SHORT(data) (((data) & \
+ IOSSM_CMD_RESPONSE_DATA_SHORT_MASK) >> 16)
+#define MAX_IO96B_SUPPORTED 2
+#define MAX_MEM_INTERFACES_SUPPORTED 2
+
+/* supported mailbox command type */
+enum iossm_mailbox_cmd_type {
+ CMD_NOP,
+ CMD_GET_SYS_INFO,
+ CMD_GET_MEM_INFO,
+ CMD_GET_MEM_CAL_INFO,
+ CMD_TRIG_CONTROLLER_OP,
+ CMD_TRIG_MEM_CAL_OP
+};
+
+/* supported mailbox command opcode */
+enum iossm_mailbox_cmd_opcode {
+ GET_MEM_INTF_INFO = 0x0001,
+ GET_MEM_TECHNOLOGY,
+ GET_MEMCLK_FREQ_KHZ,
+ GET_MEM_WIDTH_INFO,
+ ECC_ENABLE_SET = 0x0101,
+ ECC_ENABLE_STATUS,
+ ECC_INTERRUPT_STATUS,
+ ECC_INTERRUPT_ACK,
+ ECC_INTERRUPT_MASK,
+ ECC_WRITEBACK_ENABLE,
+ ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201,
+ ECC_SCRUB_MODE_0_START,
+ ECC_SCRUB_MODE_1_START,
+ BIST_STANDARD_MODE_START = 0x0301,
+ BIST_RESULTS_STATUS,
+ BIST_MEM_INIT_START,
+ BIST_MEM_INIT_STATUS,
+ BIST_SET_DATA_PATTERN_UPPER,
+ BIST_SET_DATA_PATTERN_LOWER,
+ TRIG_MEM_CAL = 0x000a,
+ GET_MEM_CAL_STATUS
+};
+
+/*
+ * IOSSM mailbox required information
+ *
+ * @num_mem_interface: Number of memory interfaces instantiated
+ * @ip_type: IP type implemented on the IO96B
+ * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B
+ */
+struct io96b_mb_ctrl {
+ uint32_t num_mem_interface;
+ uint32_t ip_type[2];
+ uint32_t ip_instance_id[2];
+};
+
+/*
+ * IOSSM mailbox response outputs
+ *
+ * @cmd_resp_status: Command Interface status
+ * @cmd_resp_data_*: More spaces for command response
+ */
+struct io96b_mb_resp {
+ uint32_t cmd_resp_status;
+ uint32_t cmd_resp_data_0;
+ uint32_t cmd_resp_data_1;
+ uint32_t cmd_resp_data_2;
+};
+
+/*
+ * IO96B instance specific information
+ *
+ * @size: Memory size
+ * @io96b_csr_addr: IO96B instance CSR address
+ * @cal_status: IO96B instance calibration status
+ * @mb_ctrl: IOSSM mailbox required information
+ */
+struct io96b_instance {
+ uint16_t size;
+ phys_addr_t io96b_csr_addr;
+ bool cal_status;
+ struct io96b_mb_ctrl mb_ctrl;
+};
+
+/*
+ * Overall IO96B instance(s) information
+ *
+ * @num_instance: Number of instance(s) assigned to HPS
+ * @overall_cal_status: Overall calibration status for all IO96B instance(s)
+ * @ddr_type: DDR memory type
+ * @ecc_status: ECC enable status (false = disabled, true = enabled)
+ * @overall_size: Total DDR memory size
+ * @io96b_0: IO96B 0 instance specific information
+ * @io96b_1: IO96B 1 instance specific information
+ */
+struct io96b_info {
+ uint8_t num_instance;
+ bool overall_cal_status;
+ const char *ddr_type;
+ bool ecc_status;
+ uint16_t overall_size;
+ struct io96b_instance io96b_0;
+ struct io96b_instance io96b_1;
+};
+
+int io96b_mb_req(phys_addr_t io96b_csr_addr, uint32_t ip_type, uint32_t instance_id,
+ uint32_t usr_cmd_type, uint32_t usr_cmd_opcode, uint32_t cmd_param_0,
+ uint32_t cmd_param_1, uint32_t cmd_param_2, uint32_t cmd_param_3,
+ uint32_t cmd_param_4, uint32_t cmd_param_5, uint32_t cmd_param_6,
+ uint32_t resp_data_len, struct io96b_mb_resp *resp);
+
+/* Supported IOSSM mailbox function */
+void io96b_mb_init(struct io96b_info *io96b_ctrl);
+int io96b_cal_status(phys_addr_t addr);
+void init_mem_cal(struct io96b_info *io96b_ctrl);
+int trig_mem_cal(struct io96b_info *io96b_ctrl);
+int get_mem_technology(struct io96b_info *io96b_ctrl);
+int get_mem_width_info(struct io96b_info *io96b_ctrl);
+int ecc_enable_status(struct io96b_info *io96b_ctrl);
+int bist_mem_init_start(struct io96b_info *io96b_ctrl);
+
+#endif /* AGILEX5_IOSSM_MAILBOX_H */
diff --git a/plat/intel/soc/agilex5/include/agilex5_power_manager.h b/plat/intel/soc/agilex5/include/agilex5_power_manager.h
index 1bba74b..178fd5b 100644
--- a/plat/intel/soc/agilex5/include/agilex5_power_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_power_manager.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -77,7 +78,5 @@
#define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0
#define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0)
-int pss_sram_power_off(handoff *hoff_ptr);
-int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff);
-
+void config_pwrmgr_handoff(handoff *hoff_ptr);
#endif
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 53dcd13..75ae78a 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -25,6 +25,7 @@
#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50
#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54
#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58
+#define SOCFPGA_SYSMGR_FPGA_BRIDGE_CTRL 0x5C
#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68
#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C
#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
@@ -189,6 +190,8 @@
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
#define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0)
+#define SYSMGR_SOC_BRIDGE_CTRL_EN BIT(0)
+#define SYSMGR_LWSOC_BRIDGE_CTRL_EN BIT(1)
#define IDLE_DATA_LWSOC2FPGA BIT(4)
#define IDLE_DATA_SOC2FPGA BIT(0)
#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 9bfc304..ab6e2bc 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -11,11 +11,16 @@
#include "agilex5_memory_controller.h"
#include "agilex5_system_manager.h"
+
#include <platform_def.h>
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+/* 1 = Flush cache, 0 = No cache flush.
+ * Default for Agilex5 is Cache flush.
+ */
+#define CACHE_FLUSH 1
#define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */
#define XLAT_TABLES_V2 U(1)
#define PLAT_PRIMARY_CPU_A55 0x000
@@ -23,22 +28,30 @@
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_L2_RESET_REQ 0xB007C0DE
+#define PLAT_TIMER_BASE_ADDR 0x10D01000
/* System Counter */
/* TODO: Update back to 400MHz.
* This shall be updated to read from L4 clock instead of hardcoded.
*/
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000
-#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
+#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000
/* QSPI Setting */
#define CAD_QSPIDATA_OFST 0x10900000
#define CAD_QSPI_OFFSET 0x108d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000
@@ -88,11 +101,10 @@
#define GIC_SIZE (0x00100000)
#define BL2_BASE (0x00000000)
-#define BL2_LIMIT (0x0002b000)
+#define BL2_LIMIT (0x0007E000)
#define BL31_BASE (0x80000000)
#define BL31_LIMIT (0x82000000)
-
/*******************************************************************************
* UART related constants
******************************************************************************/
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 409c7b1..4bb90d5 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -58,14 +58,16 @@
lib/cpus/aarch64/cortex_a76.S \
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
plat/intel/soc/agilex5/soc/agilex5_memory_controller.c \
- plat/intel/soc/agilex5/soc/agilex5_mmc.c \
+ plat/intel/soc/agilex5/soc/agilex5_mmc.c \
plat/intel/soc/agilex5/soc/agilex5_pinmux.c \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
+ plat/intel/soc/agilex5/soc/agilex5_ddr.c \
+ plat/intel/soc/agilex5/soc/agilex5_iossm_mailbox.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_ros.c \
plat/intel/soc/common/socfpga_storage.c \
- plat/intel/soc/common/socfpga_vab.c \
+ plat/intel/soc/common/socfpga_vab.c \
plat/intel/soc/common/soc/socfpga_emac.c \
plat/intel/soc/common/soc/socfpga_firewall.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
@@ -87,6 +89,7 @@
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_psci_common.c \
plat/intel/soc/agilex5/bl31_plat_setup.c \
+ plat/intel/soc/agilex5/soc/agilex5_cache.S \
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
plat/intel/soc/common/socfpga_psci.c \
diff --git a/plat/intel/soc/agilex5/soc/agilex5_cache.S b/plat/intel/soc/agilex5/soc/agilex5_cache.S
new file mode 100644
index 0000000..52ed5d3
--- /dev/null
+++ b/plat/intel/soc/agilex5/soc/agilex5_cache.S
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+ .globl invalidate_dcache_all
+ .globl invalidate_cache_low_el
+ /* --------------------------------------------------------
+ * Invalidate for NS EL2 and EL1
+ * --------------------------------------------------------
+ */
+func invalidate_cache_low_el
+ mrs x0,SCR_EL3
+ orr x1,x0,#SCR_NS_BIT
+ msr SCR_EL3, x1
+ isb
+ tlbi ALLE2
+ dsb sy
+ tlbi ALLE1
+ dsb sy
+endfunc invalidate_cache_low_el
+
+.pushsection .text.asm_dcache_level, "ax"
+func asm_dcache_level
+ lsl x12, x0, #1
+ msr csselr_el1, x12 /* select cache level */
+ isb /* sync change of cssidr_el1 */
+ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
+ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
+ ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
+ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
+ add x2, x2, #4 /* x2 <- log2(cache line size) */
+ clz w5, w3 /* bit position of #ways */
+ /* x12 <- cache level << 1 */
+ /* x2 <- line length offset */
+ /* x3 <- number of cache ways - 1 */
+ /* x4 <- number of cache sets - 1 */
+ /* x5 <- bit position of #ways */
+
+loop_set:
+ mov x6, x3 /* x6 <- working copy of #ways */
+loop_way:
+ lsl x7, x6, x5
+ orr x9, x12, x7 /* map way and level to cisw value */
+ lsl x7, x4, x2
+ orr x9, x9, x7 /* map set number to cisw value */
+ tbz w1, #0, 1f
+ dc isw, x9
+ b 2f
+1: dc cisw, x9 /* clean & invalidate by set/way */
+2: subs x6, x6, #1 /* decrement the way */
+ b.ge loop_way
+ subs x4, x4, #1 /* decrement the set */
+ b.ge loop_set
+
+ ret
+endfunc asm_dcache_level
+.popsection
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.pushsection .text.asm_dcache_all, "ax"
+func asm_dcache_all
+ mov x1, x0
+ dsb sy
+ mrs x10, clidr_el1 /* read clidr_el1 */
+ ubfx x11, x10, #24, #3 /* x11 <- loc */
+ cbz x11, finished /* if loc is 0, exit */
+ mov x15, x30
+ mov x0, #0 /* start flush at cache level 0 */
+ /* x0 <- cache level */
+ /* x10 <- clidr_el1 */
+ /* x11 <- loc */
+ /* x15 <- return address */
+
+loop_level:
+ add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
+ lsr x12, x10, x12
+ and x12, x12, #7 /* x12 <- cache type */
+ cmp x12, #2
+ b.lt skip /* skip if no cache or icache */
+ bl asm_dcache_level /* x1 = 0 flush, 1 invalidate */
+skip:
+ add x0, x0, #1 /* increment cache level */
+ cmp x11, x0
+ b.gt loop_level
+
+ mov x0, #0
+ msr csselr_el1, x0 /* restore csselr_el1 */
+ dsb sy
+ isb
+ mov x30, x15
+
+finished:
+ ret
+endfunc asm_dcache_all
+.popsection
+
+.pushsection .text.invalidate_dcache_all, "ax"
+func invalidate_dcache_all
+ mov x0, #0x1
+ b asm_dcache_all
+endfunc invalidate_dcache_all
+.popsection
diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
new file mode 100644
index 0000000..ef2ae57
--- /dev/null
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include "lib/mmio.h"
+
+#include "agilex5_ddr.h"
+#include "agilex5_iossm_mailbox.h"
+
+/*
+ * TODO: We need to leverage the legacy products DDR drivers and consider
+ * the upcoming products like KM and then come up with common source code/driver
+ * architecture to address all the products in one view.
+ */
+
+#define SYSMGR_BS_COLD3_DDR_RESET_TYPE_MASK GENMASK(31, 29)
+#define SYSMGR_BS_COLD3_DDR_RESET_TYPE_SHIFT 29
+#define SYSMGR_BS_COLD3_DDR_DBE_MASK (1 << 1)
+#define SYSMGR_BS_COLD3_OCRAM_DBE_MASK (1)
+#define SYSMGR_BS_POR0_DDR_PROGRESS_MASK (1)
+
+/* MPFE NOC registers */
+#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50
+#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54
+#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58
+
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000
+#define SOCFPGA_MPFE_SCR_IO96B0 0x18000D00
+#define SOCFPGA_MPFE_SCR_IO96B1 0x18000D04
+#define SOCFPGA_MPFE_NOC_SCHED_CSR 0x18000D08
+
+#define SIDEBANDMGR_FLAGOUTSET0_REG (SOCFPGA_F2SDRAM_MGR_ADDRESS \
+ + F2SDRAM_SIDEBAND_FLAGOUTSET0)
+#define SIDEBANDMGR_FLAGOUTSTATUS0_REG (SOCFPGA_F2SDRAM_MGR_ADDRESS \
+ +F2SDRAM_SIDEBAND_FLAGOUTSTATUS0)
+#define SIDEBANDMGR_FLAGOUTCLR0_REG (SOCFPGA_F2SDRAM_MGR_ADDRESS \
+ + F2SDRAM_SIDEBAND_FLAGOUTCLR0)
+#define SZ_8 0x00000008
+
+
+/* Firewall MPU DDR SCR registers */
+#define FW_MPU_DDR_SCR_EN 0x00
+#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800
+#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00
+#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff
+
+/* Firewall F2SDRAM DDR SCR registers */
+#define FW_F2SDRAM_DDR_SCR_EN 0x00
+#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
+ do { \
+ mmio_write_32(SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg), data); \
+ mmio_write_32(SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg), data); \
+ } while (0)
+
+#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \
+ mmio_write_32(SOCFPGA_FW_TBU2NOC_ADDRESS + (reg), data)
+
+/* DDR banks info set */
+static struct ddr_info ddr_info_set[CONFIG_NR_DRAM_BANKS];
+
+/* Reset type */
+enum reset_type {
+ POR_RESET,
+ WARM_RESET,
+ COLD_RESET,
+ NCONFIG,
+ JTAG_CONFIG,
+ RSU_RECONFIG
+};
+
+/* Get reset type by reading boot scratch register cold3 */
+static inline enum reset_type get_reset_type(uint32_t sys_reg)
+{
+ return ((sys_reg & SYSMGR_BS_COLD3_DDR_RESET_TYPE_MASK) >>
+ SYSMGR_BS_COLD3_DDR_RESET_TYPE_SHIFT);
+}
+
+/* DDR hang check before the reset */
+static inline bool is_ddr_init_hang(void)
+{
+ uint32_t sys_reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0));
+
+ if ((sys_reg & SYSMGR_BS_POR0_DDR_PROGRESS_MASK) != 0) {
+ INFO("DDR: Hang before this reset\n");
+ return true;
+ }
+
+ return false;
+}
+
+/* Set the DDR init progress bit */
+static inline void ddr_init_inprogress(bool start)
+{
+ if (start) {
+ mmio_setbits_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0),
+ SYSMGR_BS_POR0_DDR_PROGRESS_MASK);
+ } else {
+ mmio_clrbits_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0),
+ SYSMGR_BS_POR0_DDR_PROGRESS_MASK);
+ }
+}
+
+/* Configure the IO96B CSRs address based on the handoff data */
+static void config_io96b_csr_addr(bool is_dualemif, struct io96b_info *io96b_ctrl)
+{
+ if (is_dualemif)
+ io96b_ctrl->num_instance = 2;
+ else
+ io96b_ctrl->num_instance = 1;
+
+ /* Assign IO96B CSR base address if it is valid */
+ for (int i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ io96b_ctrl->io96b_0.io96b_csr_addr = 0x18400000;
+ INFO("DDR: IO96B0 0x%llx CSR enabled\n",
+ io96b_ctrl->io96b_0.io96b_csr_addr);
+ break;
+
+ case 1:
+ io96b_ctrl->io96b_1.io96b_csr_addr = 0x18800000;
+ INFO("DDR: IO96B1 0x%llx CSR enabled\n",
+ io96b_ctrl->io96b_1.io96b_csr_addr);
+ break;
+
+ default:
+ ERROR("%s: Invalid IO96B CSR\n", __func__);
+ } /* switch */
+ } /* for */
+}
+
+static inline bool hps_ocram_dbe_status(void)
+{
+ uint32_t sys_reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_3));
+
+ if ((sys_reg & SYSMGR_BS_COLD3_OCRAM_DBE_MASK) != 0)
+ return true;
+
+ return false;
+}
+
+static inline bool ddr_ecc_dbe_status(void)
+{
+ uint32_t sys_reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_3));
+
+ if ((sys_reg & SYSMGR_BS_COLD3_DDR_DBE_MASK) != 0)
+ return true;
+
+ return false;
+}
+
+static void sdram_set_firewall_non_f2sdram(void)
+{
+ uint32_t i;
+ phys_size_t value;
+ uint32_t lower, upper;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (ddr_info_set[i].size == 0) {
+ continue;
+ }
+
+ value = ddr_info_set[i].start;
+
+ /*
+ * Keep first 1MB of SDRAM memory region as secure region when
+ * using ATF flow, where the ATF code is located.
+ */
+ value += SZ_1M;
+
+ /* Setting non-secure MPU region base and base extended */
+ lower = LO(value);
+ upper = HI(value);
+
+ FW_MPU_DDR_SCR_WRITEL(lower,
+ FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE +
+ (i * 4 * sizeof(uint32_t)));
+ FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
+ FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT +
+ (i * 4 * sizeof(uint32_t)));
+
+ /* Setting non-secure Non-MPU region base and base extended */
+ FW_MPU_DDR_SCR_WRITEL(lower,
+ FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE +
+ (i * 4 * sizeof(uint32_t)));
+ FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
+ FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
+ (i * 4 * sizeof(uint32_t)));
+
+ /* Setting non-secure MPU limit and limit extended */
+ value = ddr_info_set[i].start + ddr_info_set[i].size - 1;
+
+ lower = LO(value);
+ upper = HI(value);
+
+ FW_MPU_DDR_SCR_WRITEL(lower,
+ FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT +
+ (i * 4 * sizeof(uint32_t)));
+ FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
+ FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
+ (i * 4 * sizeof(uint32_t)));
+
+ /* Setting non-secure Non-MPU limit and limit extended */
+ FW_MPU_DDR_SCR_WRITEL(lower,
+ FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
+ (i * 4 * sizeof(uint32_t)));
+ FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
+ FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT +
+ (i * 4 * sizeof(uint32_t)));
+
+ FW_MPU_DDR_SCR_WRITEL(BIT(i) | BIT(i + 8),
+ FW_MPU_DDR_SCR_EN_SET);
+ }
+}
+
+static void sdram_set_firewall_f2sdram(void)
+{
+ uint32_t i;
+ phys_size_t value;
+ uint32_t lower, upper;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (ddr_info_set[i].size == 0) {
+ continue;
+ }
+
+ value = ddr_info_set[i].start;
+
+ /* Keep first 1MB of SDRAM memory region as secure region when
+ * using ATF flow, where the ATF code is located.
+ */
+ value += SZ_1M;
+
+ /* Setting base and base extended */
+ lower = LO(value);
+ upper = HI(value);
+ FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE +
+ (i * 4 * sizeof(uint32_t)));
+ FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT +
+ (i * 4 * sizeof(uint32_t)));
+
+ /* Setting limit and limit extended */
+ value = ddr_info_set[i].start + ddr_info_set[i].size - 1;
+
+ lower = LO(value);
+ upper = HI(value);
+
+ FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT +
+ (i * 4 * sizeof(uint32_t)));
+ FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT +
+ (i * 4 * sizeof(uint32_t)));
+
+ FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET);
+ }
+}
+
+static void sdram_set_firewall(void)
+{
+ sdram_set_firewall_non_f2sdram();
+ sdram_set_firewall_f2sdram();
+}
+
+/*
+ * Agilex5 DDR/IOSSM controller initialization routine
+ */
+int agilex5_ddr_init(handoff *hoff_ptr)
+{
+ int ret;
+ bool full_mem_init = false;
+ phys_size_t hw_ddr_size;
+ phys_size_t config_ddr_size;
+ struct io96b_info io96b_ctrl;
+ enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR(
+ BOOT_SCRATCH_COLD_3)));
+ bool is_dualport = hoff_ptr->ddr_config & BIT(0);
+ bool is_dualemif = hoff_ptr->ddr_config & BIT(1);
+
+ NOTICE("DDR: Reset type is '%s'\n",
+ (reset_t == POR_RESET ? "Power-On" : (reset_t == COLD_RESET ? "Cold" : "Warm")));
+
+ /* DDR initialization progress status tracking */
+ bool is_ddr_hang_bfr_rst = is_ddr_init_hang();
+
+ /* Set the DDR initialization progress */
+ ddr_init_inprogress(true);
+
+ /* Configure the IO96B CSR address based on the handoff data */
+ config_io96b_csr_addr(is_dualemif, &io96b_ctrl);
+
+ /* Configuring MPFE sideband manager registers */
+ /* Dual port setting */
+ if (is_dualport)
+ mmio_setbits_32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4));
+
+ /* Dual EMIF setting */
+ if (is_dualemif) {
+ /* Set mpfe_lite_active in the system manager */
+ /* TODO: recheck on the bit value?? */
+ mmio_setbits_32(SOCFPGA_SYSMGR(MPFE_CONFIG), BIT(8));
+
+ mmio_setbits_32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5));
+ }
+
+ if (is_dualport || is_dualemif)
+ INFO("DDR: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n",
+ mmio_read_32(SIDEBANDMGR_FLAGOUTSTATUS0_REG));
+
+ /* Ensure calibration status passing */
+ init_mem_cal(&io96b_ctrl);
+
+ /* Initiate IOSSM mailbox */
+ io96b_mb_init(&io96b_ctrl);
+
+ /* Need to trigger re-calibration for DDR DBE */
+ if (ddr_ecc_dbe_status()) {
+ io96b_ctrl.io96b_0.cal_status = false;
+ io96b_ctrl.io96b_1.cal_status = false;
+ io96b_ctrl.overall_cal_status = io96b_ctrl.io96b_0.cal_status ||
+ io96b_ctrl.io96b_1.cal_status;
+ }
+
+ /* Trigger re-calibration if calibration failed */
+ if (!(io96b_ctrl.overall_cal_status)) {
+ NOTICE("DDR: Re-calibration in progress...\n");
+ trig_mem_cal(&io96b_ctrl);
+ }
+ NOTICE("DDR: Calibration success\n");
+
+ /* DDR type, DDR size and ECC status) */
+ ret = get_mem_technology(&io96b_ctrl);
+ if (ret != 0) {
+ ERROR("DDR: Failed to get DDR type\n");
+ return ret;
+ }
+
+ ret = get_mem_width_info(&io96b_ctrl);
+ if (ret != 0) {
+ ERROR("DDR: Failed to get DDR size\n");
+ return ret;
+ }
+
+ /* DDR size queried from the IOSSM controller */
+ hw_ddr_size = (phys_size_t)io96b_ctrl.overall_size * SZ_1G / SZ_8;
+
+ /* TODO: Hard code 1GB as of now, and DDR start and end address */
+ config_ddr_size = 0x40000000;
+ ddr_info_set[0].start = 0x80000000;
+ ddr_info_set[0].size = 0x40000000;
+
+ if (config_ddr_size != hw_ddr_size) {
+ WARN("DDR: DDR size configured is (%lld MiB)\n", config_ddr_size >> 20);
+ WARN("DDR: Mismatch with hardware size (%lld MiB).\n", hw_ddr_size >> 20);
+ }
+
+ if (config_ddr_size > hw_ddr_size) {
+ ERROR("DDR: Confgured DDR size is greater than the hardware size - HANG!!!\n");
+ while (1)
+ ;
+ }
+
+ ret = ecc_enable_status(&io96b_ctrl);
+ if (ret != 0) {
+ ERROR("DDR: Failed to get DDR ECC status\n");
+ return ret;
+ }
+
+ /*
+ * HPS cold or warm reset? If yes, skip full memory initialization if
+ * ECC is enabled to preserve memory content.
+ */
+ if (io96b_ctrl.ecc_status != 0) {
+ full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() |
+ is_ddr_hang_bfr_rst;
+ if ((full_mem_init == true) || (reset_t == WARM_RESET ||
+ reset_t == COLD_RESET) == 0) {
+ ret = bist_mem_init_start(&io96b_ctrl);
+ if (ret != 0) {
+ ERROR("DDR: Failed to fully initialize DDR memory\n");
+ return ret;
+ }
+ }
+ INFO("DDR: ECC initialized successfully\n");
+ }
+
+ sdram_set_firewall();
+
+ /*
+ * Firewall setting for MPFE CSRs, allow both secure and non-secure
+ * transactions.
+ */
+ /* IO96B0_reg */
+ mmio_setbits_32(SOCFPGA_MPFE_SCR_IO96B0, BIT(0));
+ /* IO96B1_reg */
+ mmio_setbits_32(SOCFPGA_MPFE_SCR_IO96B1, BIT(0));
+ /* noc_scheduler_csr */
+ mmio_setbits_32(SOCFPGA_MPFE_NOC_SCHED_CSR, BIT(0));
+
+ INFO("DDR: firewall init done\n");
+
+ /* Ending DDR driver initialization success tracking */
+ ddr_init_inprogress(false);
+
+ NOTICE("###DDR:init success###\n");
+
+ return 0;
+}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_iossm_mailbox.c b/plat/intel/soc/agilex5/soc/agilex5_iossm_mailbox.c
new file mode 100644
index 0000000..c2ab047
--- /dev/null
+++ b/plat/intel/soc/agilex5/soc/agilex5_iossm_mailbox.c
@@ -0,0 +1,811 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+
+#include "agilex5_iossm_mailbox.h"
+
+/* supported DDR type list */
+static const char *ddr_type_list[7] = {
+ "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN"
+};
+
+static inline int wait_for_bit(const void *reg,
+ const uint32_t mask,
+ const bool set,
+ const unsigned int timeout_ms)
+{
+ uint32_t val;
+ uint32_t timeout_sec = (timeout_ms / 1000);
+
+ while (timeout_sec > 0) {
+ val = mmio_read_32((uintptr_t)reg);
+
+ INFO("IOSSM: timeout_sec %d, val %x\n", timeout_sec, val);
+
+ if (!set) {
+ val = ~val;
+ }
+
+ if ((val & mask) == mask) {
+ INFO("IOSSM: %s, success\n", __func__);
+ return 0;
+ }
+
+ /* one second delay */
+ mdelay(1000);
+
+ timeout_sec--;
+ }
+
+ ERROR("IOSSM: %s, failed, time out\n", __func__);
+ return -ETIMEDOUT;
+}
+
+int io96b_mb_req(phys_addr_t io96b_csr_addr, uint32_t ip_type, uint32_t instance_id,
+ uint32_t usr_cmd_type, uint32_t usr_cmd_opcode, uint32_t cmd_param_0,
+ uint32_t cmd_param_1, uint32_t cmd_param_2, uint32_t cmd_param_3,
+ uint32_t cmd_param_4, uint32_t cmd_param_5, uint32_t cmd_param_6,
+ uint32_t resp_data_len, struct io96b_mb_resp *resp)
+{
+ int i;
+ int ret;
+ uint32_t cmd_req, cmd_resp;
+
+ /* Initialized zeros for responses*/
+ resp->cmd_resp_status = 0;
+ resp->cmd_resp_data_0 = 0;
+ resp->cmd_resp_data_1 = 0;
+ resp->cmd_resp_data_2 = 0;
+
+ /* Ensure CMD_REQ is cleared before write any command request */
+ ret = wait_for_bit((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET),
+ GENMASK(31, 0), 0, 10000);
+
+ if (ret != 0) {
+ ERROR("%s: CMD_REQ not ready\n", __func__);
+ return -1;
+ }
+
+ /* Write CMD_PARAM_* */
+ for (i = 0; i < 6 ; i++) {
+ switch (i) {
+ case 0:
+ if (cmd_param_0 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET,
+ cmd_param_0);
+ }
+ break;
+ case 1:
+ if (cmd_param_1 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET,
+ cmd_param_1);
+ }
+ break;
+ case 2:
+ if (cmd_param_2 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET,
+ cmd_param_2);
+ }
+ break;
+ case 3:
+ if (cmd_param_3 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET,
+ cmd_param_3);
+ }
+ break;
+ case 4:
+ if (cmd_param_4 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET,
+ cmd_param_4);
+ }
+ break;
+ case 5:
+ if (cmd_param_5 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET,
+ cmd_param_5);
+ }
+ break;
+ case 6:
+ if (cmd_param_6 != 0) {
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET,
+ cmd_param_6);
+ }
+ break;
+ default:
+ ERROR("IOSSM: %s: Invalid command parameter\n", __func__);
+ }
+ }
+
+ /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */
+ cmd_req = (usr_cmd_opcode << 0) | (usr_cmd_type << 16) | (instance_id << 24) |
+ (ip_type << 29);
+ mmio_write_32(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET, cmd_req);
+ INFO("IOSSM: %s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n",
+ __func__, cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+ /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS*/
+ ret = wait_for_bit((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+ IOSSM_STATUS_COMMAND_RESPONSE_READY, 1, 10000);
+
+ if (ret != 0) {
+ ERROR("%s: CMD_RESPONSE ERROR:\n", __func__);
+ cmd_resp = (io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+ ERROR("%s: STATUS_GENERAL_ERROR: 0x%x\n", __func__, (cmd_resp >> 1) & 0xF);
+ ERROR("%s: STATUS_CMD_RESPONSE_ERROR: 0x%x\n", __func__, (cmd_resp >> 5) & 0x7);
+ }
+
+ /* read CMD_RESPONSE_STATUS*/
+ resp->cmd_resp_status = mmio_read_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+ INFO("IOSSM: %s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n",
+ __func__, io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status);
+
+ /* read CMD_RESPONSE_DATA_* */
+ for (i = 0; i < resp_data_len; i++) {
+ switch (i) {
+ case 0:
+ resp->cmd_resp_data_0 =
+ mmio_read_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET);
+
+ break;
+ case 1:
+ resp->cmd_resp_data_1 =
+ mmio_read_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET);
+
+ break;
+ case 2:
+ resp->cmd_resp_data_2 =
+ mmio_read_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET);
+ break;
+ default:
+ ERROR("%s: Invalid response data\n", __func__);
+ }
+ }
+
+ resp->cmd_resp_status = mmio_read_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+ INFO("IOSSM: %s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n",
+ __func__, io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status);
+
+ /* write CMD_RESPONSE_READY = 0 */
+ mmio_clrbits_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET,
+ IOSSM_STATUS_COMMAND_RESPONSE_READY);
+
+ resp->cmd_resp_status = mmio_read_32(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+ INFO("IOSSM: %s: CMD_RESPONSE_READY 0x%llx: 0x%x\n",
+ __func__, io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status);
+
+ return 0;
+}
+
+/*
+ * Initial function to be called to set memory interface IP type and instance ID
+ * IP type and instance ID need to be determined before sending mailbox command
+ */
+void io96b_mb_init(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_resp usr_resp;
+ uint8_t ip_type_ret, instance_id_ret;
+ int i, j, k;
+
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ /* Get memory interface IP type & instance ID (IP identifier) */
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0,
+ CMD_GET_SYS_INFO, GET_MEM_INTF_INFO, 0, 0,
+ 0, 0, 0, 0, 0, 2, &usr_resp);
+ /* Retrieve number of memory interface(s) */
+ io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface =
+ IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3;
+
+ /* Retrieve memory interface IP type and instance ID (IP identifier) */
+ j = 0;
+ for (k = 0; k < MAX_MEM_INTERFACES_SUPPORTED; k++) {
+ switch (k) {
+ case 0:
+ ip_type_ret = (usr_resp.cmd_resp_data_0 >> 29) & 0x7;
+ instance_id_ret = (usr_resp.cmd_resp_data_0 >> 24) & 0x1F;
+ break;
+ case 1:
+ ip_type_ret = (usr_resp.cmd_resp_data_1 >> 29) & 0x7;
+ instance_id_ret = (usr_resp.cmd_resp_data_1 >> 24) & 0x1F;
+ break;
+ }
+
+ if (ip_type_ret != 0) {
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] = ip_type_ret;
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] =
+ instance_id_ret;
+ j++;
+ }
+ }
+ break;
+ case 1:
+ /* Get memory interface IP type and instance ID (IP identifier) */
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0, CMD_GET_SYS_INFO,
+ GET_MEM_INTF_INFO, 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+
+ /* Retrieve number of memory interface(s) */
+ io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface =
+ IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3;
+
+ /* Retrieve memory interface IP type and instance ID (IP identifier) */
+ j = 0;
+ for (k = 0; k < MAX_MEM_INTERFACES_SUPPORTED; k++) {
+ switch (k) {
+ case 0:
+ ip_type_ret = (usr_resp.cmd_resp_data_0 >> 29) & 0x7;
+ instance_id_ret = (usr_resp.cmd_resp_data_0 >> 24) & 0x1F;
+ break;
+ case 1:
+ ip_type_ret = (usr_resp.cmd_resp_data_1 >> 29) & 0x7;
+ instance_id_ret = (usr_resp.cmd_resp_data_1 >> 24) & 0x1F;
+ break;
+ }
+
+ if (ip_type_ret != 0) {
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] = ip_type_ret;
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] =
+ instance_id_ret;
+ j++;
+ }
+ }
+ break;
+ }
+
+ }
+}
+
+static inline void hang(void)
+{
+ ERROR("IOSSM: %s: system is going to die :(\n", __func__);
+ while (1)
+ ;
+}
+
+int io96b_cal_status(phys_addr_t addr)
+{
+ int cal_busy_status, cal_success_status;
+ phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET;
+
+ /* Ensure calibration busy status */
+ cal_busy_status = wait_for_bit((const void *)status_addr, IOSSM_STATUS_CAL_BUSY,
+ false, 15000);
+ if (cal_busy_status != 0) {
+ ERROR("IOSSM: One or more EMIF instances are busy with calibration\n");
+ return -EBUSY;
+ }
+
+ /* Calibration success status check */
+ NOTICE("IOSSM: Calibration success status check...\n");
+ cal_success_status = wait_for_bit((const void *)status_addr, IOSSM_STATUS_CAL_SUCCESS,
+ true, 15000);
+ if (cal_success_status != 0) {
+ ERROR("IOSSM: One/more EMIF instances either failed to calibrate/not completed\n");
+ return -EBUSY;
+ }
+
+ NOTICE("IOSSM: All EMIF instances within the IO96 have calibrated successfully!\n");
+ return 0;
+}
+
+void init_mem_cal(struct io96b_info *io96b_ctrl)
+{
+ int count, i, ret;
+
+ /* Initialize overall calibration status */
+ io96b_ctrl->overall_cal_status = false;
+
+ /* Check initial calibration status for the assigned IO96B */
+ count = 0;
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ ret = io96b_cal_status(io96b_ctrl->io96b_0.io96b_csr_addr);
+ if (ret != 0) {
+ io96b_ctrl->io96b_0.cal_status = false;
+ ERROR("%s: Initial DDR calibration IO96B_0 failed %d\n",
+ __func__, ret);
+ break;
+ }
+ io96b_ctrl->io96b_0.cal_status = true;
+ INFO("IOSSM: %s: Initial DDR calibration IO96B_0 succeed\n", __func__);
+ count++;
+ break;
+ case 1:
+ ret = io96b_cal_status(io96b_ctrl->io96b_1.io96b_csr_addr);
+ if (ret != 0) {
+ io96b_ctrl->io96b_1.cal_status = false;
+ ERROR("%s: Initial DDR calibration IO96B_1 failed %d\n",
+ __func__, ret);
+ break;
+ }
+ io96b_ctrl->io96b_1.cal_status = true;
+ INFO("IOSSM: %s: Initial DDR calibration IO96B_1 succeed\n", __func__);
+ count++;
+ break;
+ }
+ }
+
+ if (count == io96b_ctrl->num_instance)
+ io96b_ctrl->overall_cal_status = true;
+}
+
+/*
+ * Trying 3 times re-calibration if initial calibration failed
+ */
+int trig_mem_cal(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_resp usr_resp;
+ bool recal_success;
+ int i;
+ uint8_t cal_stat;
+
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ if (!(io96b_ctrl->io96b_0.cal_status)) {
+ /* Get the memory calibration status for first memory interface */
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0,
+ 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+
+ recal_success = false;
+
+ /* Re-calibration first memory interface with failed calibration */
+ for (i = 0; i < 3; i++) {
+ cal_stat = usr_resp.cmd_resp_data_0 & GENMASK(2, 0);
+ if (cal_stat < 0x2) {
+ recal_success = true;
+ break;
+ }
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[0],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[0],
+ CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0,
+ 0, 0, 0, 2, &usr_resp);
+ mdelay(1000);
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS,
+ 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+ }
+
+ if (!recal_success) {
+ ERROR("%s: Error as SDRAM calibration failed\n", __func__);
+ hang();
+ }
+
+ /* Get the memory calibration status for second memory interface */
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0, 0, 0,
+ 0, 0, 0, 0, 2, &usr_resp);
+
+ recal_success = false;
+
+ /* Re-calibration second memory interface with failed calibration*/
+ for (i = 0; i < 3; i++) {
+ cal_stat = usr_resp.cmd_resp_data_1 & GENMASK(2, 0);
+ if (cal_stat < 0x2) {
+ recal_success = true;
+ break;
+ }
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[1],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[1],
+ CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0,
+ 0, 0, 0, 2, &usr_resp);
+ mdelay(1000);
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS,
+ 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+ }
+
+ if (!recal_success) {
+ ERROR("IOSSMM: Error as SDRAM calibration failed\n");
+ hang();
+ }
+
+ io96b_ctrl->io96b_0.cal_status = true;
+ }
+ break;
+ case 1:
+ if (!(io96b_ctrl->io96b_1.cal_status)) {
+ /* Get the memory calibration status for first memory interface */
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0,
+ 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+
+ recal_success = false;
+
+ /* Re-calibration first memory interface with failed calibration */
+ for (i = 0; i < 3; i++) {
+ cal_stat = usr_resp.cmd_resp_data_0 & GENMASK(2, 0);
+ if (cal_stat < 0x2) {
+ recal_success = true;
+ break;
+ }
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[0],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[0],
+ CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0,
+ 0, 0, 0, 2, &usr_resp);
+ mdelay(1000);
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS,
+ 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+ }
+
+ if (!recal_success) {
+ ERROR("IOSSM: Error as SDRAM calibration failed\n");
+ hang();
+ }
+
+ /* Get the memory calibration status for second memory interface */
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0, 0, 0,
+ 0, 0, 0, 0, 2, &usr_resp);
+
+ recal_success = false;
+
+ /* Re-calibration second memory interface with failed calibration*/
+ for (i = 0; i < 3; i++) {
+ cal_stat = usr_resp.cmd_resp_data_0 & GENMASK(2, 0);
+ if (cal_stat < 0x2) {
+ recal_success = true;
+ break;
+ }
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[1],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[1],
+ CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0,
+ 0, 0, 0, 2, &usr_resp);
+ mdelay(1000);
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0,
+ CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS,
+ 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp);
+ }
+
+ if (!recal_success) {
+ ERROR("IOSSM: Error as SDRAM calibration failed\n");
+ hang();
+ }
+
+ io96b_ctrl->io96b_1.cal_status = true;
+ }
+ break;
+ }
+ }
+
+ if (io96b_ctrl->io96b_0.cal_status && io96b_ctrl->io96b_1.cal_status) {
+ INFO("IOSSM: %s: Overall SDRAM calibration success\n", __func__);
+ io96b_ctrl->overall_cal_status = true;
+ }
+
+ return 0;
+}
+
+int get_mem_technology(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_resp usr_resp;
+ int i, j;
+ uint8_t ddr_type_ret;
+
+ /* Initialize ddr type */
+ io96b_ctrl->ddr_type = ddr_type_list[6];
+
+ /* Get and ensure all memory interface(s) same DDR type */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) {
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j],
+ CMD_GET_MEM_INFO, GET_MEM_TECHNOLOGY, 0, 0, 0, 0,
+ 0, 0, 0, 0, &usr_resp);
+
+ ddr_type_ret =
+ IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & GENMASK(2, 0);
+
+ if (strcmp(io96b_ctrl->ddr_type, "UNKNOWN") == 0)
+ io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret];
+
+ if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) {
+ ERROR("IOSSM: Mismatch DDR type on IO96B_0\n");
+ return -ENOEXEC;
+ }
+ }
+ break;
+ case 1:
+ for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) {
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j],
+ CMD_GET_MEM_INFO, GET_MEM_TECHNOLOGY, 0, 0, 0,
+ 0, 0, 0, 0, 0, &usr_resp);
+
+ ddr_type_ret =
+ IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & GENMASK(2, 0);
+
+ if (strcmp(io96b_ctrl->ddr_type, "UNKNOWN") == 0)
+ io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret];
+
+ if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) {
+ ERROR("IOSSM: Mismatch DDR type on IO96B_1\n");
+ return -ENOEXEC;
+ }
+ }
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int get_mem_width_info(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_resp usr_resp;
+ int i, j;
+ uint16_t memory_size = 0U;
+ uint16_t total_memory_size = 0U;
+
+ /* Get all memory interface(s) total memory size on all instance(s) */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ memory_size = 0;
+ for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) {
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j],
+ CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, 0, 0, 0,
+ 0, 0, 0, 0, 2, &usr_resp);
+
+ memory_size = memory_size +
+ (usr_resp.cmd_resp_data_1 & GENMASK(7, 0));
+ }
+
+ if (memory_size == 0U) {
+ ERROR("IOSSM: %s: Failed to get valid memory size\n", __func__);
+ return -ENOEXEC;
+ }
+
+ io96b_ctrl->io96b_0.size = memory_size;
+
+ break;
+ case 1:
+ memory_size = 0;
+ for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) {
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j],
+ CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, 0, 0, 0,
+ 0, 0, 0, 0, 2, &usr_resp);
+
+ memory_size = memory_size +
+ (usr_resp.cmd_resp_data_1 & GENMASK(7, 0));
+ }
+
+ if (memory_size == 0U) {
+ ERROR("IOSSM: %s: Failed to get valid memory size\n", __func__);
+ return -ENOEXEC;
+ }
+
+ io96b_ctrl->io96b_1.size = memory_size;
+
+ break;
+ }
+
+ total_memory_size = total_memory_size + memory_size;
+ }
+
+ if (total_memory_size == 0U) {
+ ERROR("IOSSM: %s: Failed to get valid memory size\n", __func__);
+ return -ENOEXEC;
+ }
+
+ io96b_ctrl->overall_size = total_memory_size;
+
+ return 0;
+}
+
+int ecc_enable_status(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_resp usr_resp;
+ int i, j;
+ bool ecc_stat_set = false;
+ bool ecc_stat;
+
+ /* Initialize ECC status */
+ io96b_ctrl->ecc_status = false;
+
+ /* Get and ensure all memory interface(s) same ECC status */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) {
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j],
+ CMD_TRIG_CONTROLLER_OP, ECC_ENABLE_STATUS, 0, 0,
+ 0, 0, 0, 0, 0, 0, &usr_resp);
+
+ ecc_stat = ((IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & GENMASK(1, 0)) == 0 ? false : true);
+
+ if (!ecc_stat_set) {
+ io96b_ctrl->ecc_status = ecc_stat;
+ ecc_stat_set = true;
+ }
+
+ if (ecc_stat != io96b_ctrl->ecc_status) {
+ ERROR("IOSSM: %s: Mismatch DDR ECC status on IO96B_0\n",
+ __func__);
+ return -ENOEXEC;
+ }
+ }
+ break;
+ case 1:
+ for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) {
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j],
+ CMD_TRIG_CONTROLLER_OP, ECC_ENABLE_STATUS, 0, 0,
+ 0, 0, 0, 0, 0, 0, &usr_resp);
+
+ ecc_stat = ((IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & GENMASK(1, 0)) == 0 ? false : true);
+
+ if (!ecc_stat_set) {
+ io96b_ctrl->ecc_status = ecc_stat;
+ ecc_stat_set = true;
+ }
+
+ if (ecc_stat != io96b_ctrl->ecc_status) {
+ ERROR("%s: Mismatch DDR ECC status on IO96B_1\n"
+ , __func__);
+ return -ENOEXEC;
+ }
+ }
+ break;
+ }
+ }
+ return 0;
+}
+
+int bist_mem_init_start(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_resp usr_resp;
+ int i, j;
+ bool bist_start, bist_success;
+ uint32_t read_count;
+ uint32_t read_interval_ms;
+
+ /* Full memory initialization BIST performed on all memory interface(s) */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ switch (i) {
+ case 0:
+ for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) {
+ bist_start = false;
+ bist_success = false;
+ read_interval_ms = 500U;
+
+ /* Start memory initialization BIST on full memory address */
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j],
+ CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0x40,
+ 0, 0, 0, 0, 0, 0, 0, &usr_resp);
+
+ bist_start =
+ (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & 1);
+
+ if (!bist_start) {
+ ERROR("IOSSM: %s: Failed to initialized memory on IO96B_0\n"
+ , __func__);
+ ERROR("IOSSM: %s: BIST_MEM_INIT_START Error code 0x%x\n",
+ __func__,
+ (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & GENMASK(2, 1)) > 0x1);
+ return -ENOEXEC;
+ }
+
+ /* Polling for the initiated memory initialization BIST status */
+ read_count = read_interval_ms / TIMEOUT;
+ while (!bist_success) {
+ io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr,
+ io96b_ctrl->io96b_0.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j],
+ CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_STATUS,
+ 0, 0, 0, 0, 0, 0, 0, 0, &usr_resp);
+
+ bist_success = (IOSSM_CMD_RESPONSE_DATA_SHORT
+ (usr_resp.cmd_resp_status) & 1);
+
+ if ((!bist_success) && (read_count == 0U)) {
+ ERROR("IOSSM: %s: Timeout init memory on IO96B_0\n"
+ , __func__);
+ ERROR("IOSSM: %s: BIST_MEM_INIT_STATUS Err code%x\n"
+ , __func__, (IOSSM_CMD_RESPONSE_DATA_SHORT
+ (usr_resp.cmd_resp_status)
+ & GENMASK(2, 1)) > 0x1);
+ return -ETIMEDOUT;
+ }
+ read_count--;
+ mdelay(read_interval_ms);
+ }
+ }
+
+ NOTICE("IOSSM: %s: Memory initialized successfully on IO96B_0\n", __func__);
+ break;
+
+ case 1:
+ for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) {
+ bist_start = false;
+ bist_success = false;
+ read_interval_ms = 500U;
+
+ /* Start memory initialization BIST on full memory address */
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j],
+ CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0x40,
+ 0, 0, 0, 0, 0, 0, 0, &usr_resp);
+
+ bist_start =
+ (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & 1);
+
+ if (!bist_start) {
+ ERROR("IOSSM: %s: Failed to initialized memory on IO96B_1\n"
+ , __func__);
+ ERROR("IOSSM: %s: BIST_MEM_INIT_START Error code 0x%x\n",
+ __func__,
+ (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & GENMASK(2, 1)) > 0x1);
+ return -ENOEXEC;
+ }
+
+ /* Polling for the initiated memory initialization BIST status */
+ read_count = read_interval_ms / TIMEOUT;
+ while (!bist_success) {
+ io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr,
+ io96b_ctrl->io96b_1.mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j],
+ CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_STATUS,
+ 0, 0, 0, 0, 0, 0, 0, 0, &usr_resp);
+
+ bist_success = (IOSSM_CMD_RESPONSE_DATA_SHORT
+ (usr_resp.cmd_resp_status) & 1);
+
+ if ((!bist_success) && (read_count == 0U)) {
+ ERROR("IOSSM: %s: Timeout init memory on IO96B_1\n"
+ , __func__);
+ ERROR("IOSSM: %s: BIST_MEM_INIT_STATUS ErrCode %x\n"
+ , __func__, (IOSSM_CMD_RESPONSE_DATA_SHORT
+ (usr_resp.cmd_resp_status)
+ & GENMASK(2, 1)) > 0x1);
+ return -ETIMEDOUT;
+ }
+ read_count--;
+ mdelay(read_interval_ms);
+ }
+ }
+
+ NOTICE("IOSSM: %s: Memory initialized successfully on IO96B_1\n", __func__);
+ break;
+ }
+ }
+ return 0;
+}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_pinmux.c b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
index 50d9e36..7c4eb57 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -195,11 +196,15 @@
{
unsigned int i;
- mmio_write_32(PINMUX_HANDOFF_CONFIG_ADDR, PINMUX_HANDOFF_CONFIG_VAL);
- for (i = 0; i < PINMUX_HANDOFF_ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) {
- mmio_write_32(AGX5_PINMUX_PIN0SEL +
- hoff_ptr->pinmux_sel_array[i],
- hoff_ptr->pinmux_sel_array[i + 1]);
+ /*
+ * Configure the FPGA use.
+ * The actual generic handoff contains extra 4 elements, and these 4 elements
+ * are not applicable to the Agilex5 platform. Writing these extra 4 elements
+ * will cause the system to crash, so let's avoid writing them here.
+ */
+ for (i = 0; i < (ARRAY_SIZE(hoff_ptr->pinmux_fpga_array) - 4); i += 2) {
+ mmio_write_32(AGX5_PINMUX_EMAC0_USEFPGA + hoff_ptr->pinmux_fpga_array[i],
+ hoff_ptr->pinmux_fpga_array[i+1]);
}
config_fpgaintf_mod();
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index cbd0121..9a17587 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
index 2094c65..931ffcf 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -1,22 +1,522 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
+#include <drivers/delay_timer.h>
#include <errno.h>
#include <lib/mmio.h>
#include <platform_def.h>
#include "ncore_ccu.h"
+#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
#include "socfpga_system_manager.h"
uint32_t poll_active_bit(uint32_t dir);
-#define SMMU_DMI 1
+#define SMMU_DMI 1
+#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_NOC_REG_BASE + 0x7340
+#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_NOC_REG_BASE + 0x7344
+#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0)
+#define MAX_DISTRIBUTED_MEM_INTERFACE 2
+#define FLUSH_ALL_ENTRIES 0x4
+#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16)
+#define ARRAY_ID_TAG 0x0
+#define ARRAY_ID_DATA 0x1
+#define CACHE_OPERATION_DONE BIT(0)
+#define TIMEOUT_200MS 200
+#define __bf_shf(x) (__builtin_ffsll(x) - 1)
+
+#define FIELD_PREP(_mask, _val) \
+ ({ \
+ ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
+ })
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ncore_ccu_reg_t ncore_ccu_modules[] = {
+ {"caiu0@1c000000", 0x1C000000, 0x00001000},
+ {"ncaiu0@1c001000", 0x1C001000, 0x00001000},
+ {"ncaiu1@1c002000", 0x1C002000, 0x00001000},
+ {"ncaiu2@1c003000", 0x1C003000, 0x00001000},
+ {"ncaiu3@1c004000", 0x1C004000, 0x00001000},
+ {"dce0@1c005000", 0x1C005000, 0x00001000},
+ {"dce1@1c006000", 0x1C006000, 0x00001000},
+ {"dmi0@1c007000", 0x1C007000, 0x00001000},
+ {"dmi1@1c008000", 0x1C008000, 0x00001000},
+ {"noc_fw_l4_per@10d21000", 0x10D21000, 0x0000008C},
+ {"noc_fw_l4_sys@10d21100", 0x10D21100, 0x00000098},
+ {"noc_fw_lwsoc2fpga@10d21300", 0x10D21300, 0x00000004},
+ {"noc_fw_soc2fpga@10d21200", 0x10D21200, 0x00000004},
+ {"noc_fw_tcu@10d21400", 0x10D21400, 0x00000004}
+ };
+
+ncore_ccu_t ccu_caiu0[] = {
+ /* CAIUAMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* CAIUMIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DII1_MPFEREGS */
+ {0x00000414, 0x00018000, 0xFFFFFFFF},
+ {0x00000418, 0x00000000, 0x000000FF},
+ {0x00000410, 0xC0E00200, 0xC1F03E1F},
+ /* DII2_GICREGS */
+ {0x00000424, 0x0001D000, 0xFFFFFFFF},
+ {0x00000428, 0x00000000, 0x000000FF},
+ {0x00000420, 0xC0800400, 0xC1F03E1F},
+ /* NCAIU0_LWSOC2FPGA */
+ {0x00000444, 0x00020000, 0xFFFFFFFF},
+ {0x00000448, 0x00000000, 0x000000FF},
+ {0x00000440, 0xC1100006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_1G */
+ {0x00000454, 0x00040000, 0xFFFFFFFF},
+ {0x00000458, 0x00000000, 0x000000FF},
+ {0x00000450, 0xC1200006, 0xC1F03E1F},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_16G */
+ {0x00000474, 0x00400000, 0xFFFFFFFF},
+ {0x00000478, 0x00000000, 0x000000FF},
+ {0x00000470, 0xC1600006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_256G */
+ {0x00000494, 0x04000000, 0xFFFFFFFF},
+ {0x00000498, 0x00000000, 0x000000FF},
+ {0x00000490, 0xC1A00006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu0[] = {
+ /* NCAIU0AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU0MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* PSS */
+ {0x00000404, 0x00010000, 0xFFFFFFFF},
+ {0x00000408, 0x00000000, 0x000000FF},
+ {0x00000400, 0xC0F00000, 0xC1F03E1F},
+ /* DII1_MPFEREGS */
+ {0x00000414, 0x00018000, 0xFFFFFFFF},
+ {0x00000418, 0x00000000, 0x000000FF},
+ {0x00000410, 0xC0E00200, 0xC1F03E1F},
+ /* NCAIU0_LWSOC2FPGA */
+ {0x00000444, 0x00020000, 0xFFFFFFFF},
+ {0x00000448, 0x00000000, 0x000000FF},
+ {0x00000440, 0xC1100006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_1G */
+ {0x00000454, 0x00040000, 0xFFFFFFFF},
+ {0x00000458, 0x00000000, 0x000000FF},
+ {0x00000450, 0xC1200006, 0xC1F03E1F},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_16G */
+ {0x00000474, 0x00400000, 0xFFFFFFFF},
+ {0x00000478, 0x00000000, 0x000000FF},
+ {0x00000470, 0xC1600006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* NCAIU0_SOC2FPGA_256G */
+ {0x00000494, 0x04000000, 0xFFFFFFFF},
+ {0x00000498, 0x00000000, 0x000000FF},
+ {0x00000490, 0xC1A00006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu1[] = {
+ /* NCAIU1AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU1MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu2[] = {
+ /* NCAIU2AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU2MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_ncaiu3[] = {
+ /* NCAIU3AMIGR */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* NCAIU3MIFSR */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DII1_MPFEREGS */
+ {0x00000414, 0x00018000, 0xFFFFFFFF},
+ {0x00000418, 0x00000000, 0x000000FF},
+ {0x00000410, 0xC0E00200, 0xC1F03E1F},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_dce0[] = {
+ /* DCEUAMIGR0 */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* DCEUMIFSR0 */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_dce1[] = {
+ /* DCEUAMIGR1 */
+ {0x000003C0, 0x00000003, 0x0000001F},
+ /* DCEUMIFSR1 */
+ {0x000003C4, 0x00000000, 0x07070777},
+ /* DMI_SDRAM_2G */
+ {0x00000464, 0x00080000, 0xFFFFFFFF},
+ {0x00000468, 0x00000000, 0x000000FF},
+ {0x00000460, 0x81300006, 0xC1F03E1F},
+ /* DMI_SDRAM_30G */
+ {0x00000484, 0x00800000, 0xFFFFFFFF},
+ {0x00000488, 0x00000000, 0x000000FF},
+ {0x00000480, 0x81700006, 0xC1F03E1F},
+ /* DMI_SDRAM_480G */
+ {0x000004A4, 0x08000000, 0xFFFFFFFF},
+ {0x000004A8, 0x00000000, 0x000000FF},
+ {0x000004A0, 0x81B00006, 0xC1F03E1F}
+ };
+
+ncore_ccu_t ccu_dmi0[] = {
+ /* DMIUSMCTCR */
+ {0x00000300, 0x00000001, 0x00000003},
+ {0x00000300, 0x00000003, 0x00000003}
+ };
+
+ncore_ccu_t ccu_dmi1[] = {
+ /* DMIUSMCTCR */
+ {0x00000300, 0x00000001, 0x00000003},
+ {0x00000300, 0x00000003, 0x00000003}
+ };
+
+ncore_ccu_t ccu_noc_fw_l4_per[] = {
+ /* NAND */
+ {0x00000000, 0x01010001, 0x01010001},
+ /* USB0 */
+ {0x0000000C, 0x01010001, 0x01010001},
+ /* USB1 */
+ {0x00000010, 0x01010001, 0x01010001},
+ /* SPI_MAIN0 */
+ {0x0000001C, 0x01010301, 0x01010301},
+ /* SPI_MAIN1 */
+ {0x00000020, 0x01010301, 0x01010301},
+ /* SPI_SECONDARY0 */
+ {0x00000024, 0x01010301, 0x01010301},
+ /* SPI_SECONDARY1 */
+ {0x00000028, 0x01010301, 0x01010301},
+ /* EMAC0 */
+ {0x0000002C, 0x01010001, 0x01010001},
+ /* EMAC1 */
+ {0x00000030, 0x01010001, 0x01010001},
+ /* EMAC2 */
+ {0x00000034, 0x01010001, 0x01010001},
+ /* SDMMC */
+ {0x00000040, 0x01010001, 0x01010001},
+ /* GPIO0 */
+ {0x00000044, 0x01010301, 0x01010301},
+ /* GPIO1 */
+ {0x00000048, 0x01010301, 0x01010301},
+ /* I2C0 */
+ {0x00000050, 0x01010301, 0x01010301},
+ /* I2C1 */
+ {0x00000054, 0x01010301, 0x01010301},
+ /* I2C2 */
+ {0x00000058, 0x01010301, 0x01010301},
+ /* I2C3 */
+ {0x0000005C, 0x01010301, 0x01010301},
+ /* I2C4 */
+ {0x00000060, 0x01010301, 0x01010301},
+ /* SP_TIMER0 */
+ {0x00000064, 0x01010301, 0x01010301},
+ /* SP_TIMER1 */
+ {0x00000068, 0x01010301, 0x01010301},
+ /* UART0 */
+ {0x0000006C, 0x01010301, 0x01010301},
+ /* UART1 */
+ {0x00000070, 0x01010301, 0x01010301},
+ /* I3C0 */
+ {0x00000074, 0x01010301, 0x01010301},
+ /* I3C1 */
+ {0x00000078, 0x01010301, 0x01010301},
+ /* DMA0 */
+ {0x0000007C, 0x01010001, 0x01010001},
+ /* DMA1 */
+ {0x00000080, 0x01010001, 0x01010001},
+ /* COMBO_PHY */
+ {0x00000084, 0x01010001, 0x01010001},
+ /* NAND_SDMA */
+ {0x00000088, 0x01010301, 0x01010301}
+ };
+
+ncore_ccu_t ccu_noc_fw_l4_sys[] = {
+ /* DMA_ECC */
+ {0x00000008, 0x01010001, 0x01010001},
+ /* EMAC0RX_ECC */
+ {0x0000000C, 0x01010001, 0x01010001},
+ /* EMAC0TX_ECC */
+ {0x00000010, 0x01010001, 0x01010001},
+ /* EMAC1RX_ECC */
+ {0x00000014, 0x01010001, 0x01010001},
+ /* EMAC1TX_ECC */
+ {0x00000018, 0x01010001, 0x01010001},
+ /* EMAC2RX_ECC */
+ {0x0000001C, 0x01010001, 0x01010001},
+ /* EMAC2TX_ECC */
+ {0x00000020, 0x01010001, 0x01010001},
+ /* NAND_ECC */
+ {0x0000002C, 0x01010001, 0x01010001},
+ /* NAND_READ_ECC */
+ {0x00000030, 0x01010001, 0x01010001},
+ /* NAND_WRITE_ECC */
+ {0x00000034, 0x01010001, 0x01010001},
+ /* OCRAM_ECC */
+ {0x00000038, 0x01010001, 0x01010001},
+ /* SDMMC_ECC */
+ {0x00000040, 0x01010001, 0x01010001},
+ /* USB0_ECC */
+ {0x00000044, 0x01010001, 0x01010001},
+ /* USB1_CACHEECC */
+ {0x00000048, 0x01010001, 0x01010001},
+ /* CLOCK_MANAGER */
+ {0x0000004C, 0x01010001, 0x01010001},
+ /* IO_MANAGER */
+ {0x00000054, 0x01010001, 0x01010001},
+ /* RESET_MANAGER */
+ {0x00000058, 0x01010001, 0x01010001},
+ /* SYSTEM_MANAGER */
+ {0x0000005C, 0x01010001, 0x01010001},
+ /* OSC0_TIMER */
+ {0x00000060, 0x01010301, 0x01010301},
+ /* OSC1_TIMER0*/
+ {0x00000064, 0x01010301, 0x01010301},
+ /* WATCHDOG0 */
+ {0x00000068, 0x01010301, 0x01010301},
+ /* WATCHDOG1 */
+ {0x0000006C, 0x01010301, 0x01010301},
+ /* WATCHDOG2 */
+ {0x00000070, 0x01010301, 0x01010301},
+ /* WATCHDOG3 */
+ {0x00000074, 0x01010301, 0x01010301},
+ /* DAP */
+ {0x00000078, 0x03010001, 0x03010001},
+ /* WATCHDOG4 */
+ {0x0000007C, 0x01010301, 0x01010301},
+ /* POWER_MANAGER */
+ {0x00000080, 0x01010001, 0x01010001},
+ /* USB1_RXECC */
+ {0x00000084, 0x01010001, 0x01010001},
+ /* USB1_TXECC */
+ {0x00000088, 0x01010001, 0x01010001},
+ /* L4_NOC_PROBES */
+ {0x00000090, 0x01010001, 0x01010001},
+ /* L4_NOC_QOS */
+ {0x00000094, 0x01010001, 0x01010001}
+ };
+
+ncore_ccu_t ccu_noc_fw_lwsoc2fpga[] = {
+ /* LWSOC2FPGA_CSR */
+ {0x00000000, 0x0FFE0301, 0x0FFE0301}
+ };
+
+ncore_ccu_t ccu_noc_fw_soc2fpga[] = {
+ /* SOC2FPGA_CSR */
+ {0x00000000, 0x0FFE0301, 0x0FFE0301}
+ };
+
+ncore_ccu_t ccu_noc_fw_tcu[] = {
+ /* TCU_CSR */
+ {0x00000000, 0x01010001, 0x01010001}
+ };
+
+uint32_t init_ncore_ccu(void)
+{
+ ncore_ccu_t *ccu_module_table = NULL;
+ uint32_t base;
+ uint32_t size;
+ uint32_t val;
+ uint32_t offset;
+ uint32_t mask;
+ uint32_t set_mask = 0U;
+ uint32_t reg = 0U;
+
+ for (int index = 0; index < ARRAY_SIZE(ncore_ccu_modules); index++) {
+ base = ncore_ccu_modules[index].base;
+ size = ncore_ccu_modules[index].size;
+
+ switch (index) {
+ case 0:
+ ccu_module_table = ccu_caiu0;
+ size = (sizeof(ccu_caiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 1:
+ ccu_module_table = ccu_ncaiu0;
+ size = (sizeof(ccu_ncaiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 2:
+ ccu_module_table = ccu_ncaiu1;
+ size = (sizeof(ccu_ncaiu1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 3:
+ ccu_module_table = ccu_ncaiu2;
+ size = (sizeof(ccu_ncaiu2) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 4:
+ ccu_module_table = ccu_ncaiu3;
+ size = (sizeof(ccu_ncaiu3) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 5:
+ ccu_module_table = ccu_dce0;
+ size = (sizeof(ccu_dce0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 6:
+ ccu_module_table = ccu_dce1;
+ size = (sizeof(ccu_dce1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 7:
+ ccu_module_table = ccu_dmi0;
+ size = (sizeof(ccu_dmi0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 8:
+ ccu_module_table = ccu_dmi1;
+ size = (sizeof(ccu_dmi1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 9:
+ ccu_module_table = ccu_noc_fw_l4_per;
+ size = (sizeof(ccu_noc_fw_l4_per) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 10:
+ ccu_module_table = ccu_noc_fw_l4_sys;
+ size = (sizeof(ccu_noc_fw_l4_sys) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 11:
+ ccu_module_table = ccu_noc_fw_lwsoc2fpga;
+ size = (sizeof(ccu_noc_fw_lwsoc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 12:
+ ccu_module_table = ccu_noc_fw_soc2fpga;
+ size = (sizeof(ccu_noc_fw_soc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ case 13:
+ ccu_module_table = ccu_noc_fw_tcu;
+ size = (sizeof(ccu_noc_fw_tcu) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
+ break;
+
+ default:
+ break;
+ }
+
+ VERBOSE("CCU node base addr 0x%x, name %s, size 0x%x and module table %p\n",
+ base, ncore_ccu_modules[index].name, size, (uint32_t *)ccu_module_table);
+
+ /*
+ * First element: offset
+ * Second element: val
+ * Third element: mask
+ */
+ for (int i = 0; i < size; i++) {
+ offset = ccu_module_table[i].offset;
+ val = ccu_module_table[i].val;
+
+ /* Reads the masking bit value from the list */
+ mask = ccu_module_table[i].mask;
+
+ if (mask != 0) {
+ if (mask == 0xFFFFFFFF) {
+ reg = base + offset;
+ mmio_write_32((uintptr_t)reg, val);
+ } else {
+ /* Mask the value with the masking bits */
+ set_mask = val & mask;
+ reg = base + offset;
+
+ /* Clears and sets specific bits in the register */
+ mmio_clrsetbits_32((uintptr_t)reg, mask, set_mask);
+ }
+ }
+
+ }
+
+ }
+
+ return 0;
+}
+#endif
static coh_ss_id_t subsystem_id;
void get_subsystem_id(void)
@@ -29,6 +529,7 @@
subsystem_id.num_directory = directory;
subsystem_id.num_coh_agent = coh_agent;
}
+
uint32_t directory_init(void)
{
uint32_t dir_sf_mtn, dir_sf_en;
@@ -42,7 +543,7 @@
/* Poll Active Bit */
ret = poll_active_bit(dir);
if (ret != 0) {
- ERROR("Timeout during active bit polling");
+ ERROR("Timeout during active bit polling\n");
return -ETIMEDOUT;
}
/* Disable snoop filter, a bit per snoop filter */
@@ -51,6 +552,7 @@
}
return 0;
}
+
uint32_t coherent_agent_intfc_init(void)
{
uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
@@ -65,11 +567,12 @@
ca_type = CACHING_AGENT_TYPE(ca_id);
if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
mmio_setbits_32(NCORE_CCU_CSR(NCORE_CSADSER0),
- BIT(ca));
+ BIT(ca));
}
}
return 0;
}
+
uint32_t poll_active_bit(uint32_t dir)
{
uint32_t timeout = 80000;
@@ -81,6 +584,7 @@
}
return -1;
}
+
void bypass_ocram_firewall(void)
{
mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
@@ -92,6 +596,7 @@
mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
+
void ncore_enable_ocram_firewall(void)
{
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
@@ -103,6 +608,8 @@
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
+
+#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
uint32_t init_ncore_ccu(void)
{
uint32_t status;
@@ -112,6 +619,7 @@
bypass_ocram_firewall();
return status;
}
+#endif
void setup_smmu_stream_id(void)
{
@@ -130,7 +638,6 @@
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN0), TSN0);
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN1), TSN1);
mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN2), TSN2);
-
/* Enabled Stream ctrl register for Agilex5 */
mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA0), ENABLE_STREAMID);
mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA1), ENABLE_STREAMID);
@@ -144,3 +651,61 @@
mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1), ENABLE_STREAMID);
mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2), ENABLE_STREAMID);
}
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+/* TODO: Temp added this here*/
+static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
+{
+ int time_out = delay_ms;
+
+ while (time_out-- > 0) {
+
+ if ((mmio_read_32(addr) & mask) == match) {
+ return 0;
+ }
+ udelay(1000);
+ }
+
+ return -ETIMEDOUT;
+}
+
+int flush_l3_dcache(void)
+{
+ int i;
+ int ret = 0;
+
+ /* Flushing all entries in CCU system memory cache */
+ for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
+ mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+ FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
+ (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+ /* Wait for cache maintenance operation done */
+ ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
+ (i * 0x1000)), CACHE_OPERATION_DONE,
+ CACHE_OPERATION_DONE, TIMEOUT_200MS);
+
+ if (ret != 0) {
+ VERBOSE("%s: Timeout while waiting for flushing tag in DMI%d done\n",
+ __func__, i);
+ return ret;
+ }
+
+ mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+ FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
+ (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+ /* Wait for cache maintenance operation done */
+ ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
+ (i * 0x1000)), CACHE_OPERATION_DONE,
+ CACHE_OPERATION_DONE, TIMEOUT_200MS);
+
+ if (ret != 0) {
+ VERBOSE("%s: Timeout while waiting for flushing data in DMI%d done\n",
+ __func__, i);
+ }
+ }
+
+ return ret;
+}
+#endif
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
index 6cdbeb8..a89c098 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,192 +10,206 @@
#include <stdbool.h>
#include <stdint.h>
+#include "socfpga_plat_def.h"
+
#ifndef CCU_ACTIVATE_COH_FPGA
-#define CCU_ACTIVATE_COH_FPGA 0
+#define CCU_ACTIVATE_COH_FPGA 0
#endif
-// Address map for ccu init
-#define addr_CAIUIDR1 (0x1C000000)
-#define addr_GRBUNRRUCR (0x1c0ffff8)
-#define base_addr_NRS_CAIU0 (0x1c000000)
-#define base_addr_NRS_NCAIU0 (0x1c001000)
-#define base_addr_NRS_NCAIU1 (0x1c002000)
-#define base_addr_NRS_NCAIU2 (0x1c003000)
-#define base_addr_NRS_NCAIU3 (0x1c004000)
-#define base_addr_NRS_DCE0 (0x1c005000)
-#define base_addr_NRS_DCE1 (0x1c006000)
-//#define base_addr_NRS_DMI0 (0x1c007000)
-//#define base_addr_NRS_DMI1 (0x1c008000)
-//DMI
-#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR 0x1C007300
-#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR 0x1C008300
-//DSU
-#define ALT_CCU_DSU_CAIUAMIGR_ADDR 0x1C0003C0
-#define ALT_CCU_DSU_CAIUMIFSR_ADDR 0x1C0003C4
-#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR 0x1C000414
-#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR 0x1C000418
-#define ALT_CCU_DSU_CAIUGPRAR1_ADDR 0x1C000410
-#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR 0x1C000424
-#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR 0x1C000428
-#define ALT_CCU_DSU_CAIUGPRAR2_ADDR 0x1C000420
-#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR 0x1C000444
-#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR 0x1C000448
-#define ALT_CCU_DSU_CAIUGPRAR4_ADDR 0x1C000440
-#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR 0x1C000454
-#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR 0x1C000458
-#define ALT_CCU_DSU_CAIUGPRAR5_ADDR 0x1C000450
-#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR 0x1C000464
-#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR 0x1C000468
-#define ALT_CCU_DSU_CAIUGPRAR6_ADDR 0x1C000460
-#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR 0x1C000474
-#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR 0x1C000478
-#define ALT_CCU_DSU_CAIUGPRAR7_ADDR 0x1C000470
-#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR 0x1C000484
-#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR 0x1C000488
-#define ALT_CCU_DSU_CAIUGPRAR8_ADDR 0x1C000480
-#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR 0x1C000494
-#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR 0x1C000498
-#define ALT_CCU_DSU_CAIUGPRAR9_ADDR 0x1C000490
-#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR 0x1C0004A4
-#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR 0x1C0004A8
-#define ALT_CCU_DSU_CAIUGPRAR10_ADDR 0x1C0004A0
-//GIC
-#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR 0x1C0023C0
-#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR 0x1C0023C4
-#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR 0x1C002414
-#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR 0x1C002418
-#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR 0x1C002410
-#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR 0x1C002464
-#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR 0x1C002468
-#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR 0x1C002460
-#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR 0x1C002484
-#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR 0x1C002488
-#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR 0x1C002480
-#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR 0x1C0024A4
-#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR 0x1C0024A8
-#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR 0x1C0024A0
-//FPGA2SOC
-#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR 0x1C0013C0
-#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR 0x1C0013C4
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR 0x1C001414
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR 0x1C001418
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR 0x1C001410
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR 0x1C001464
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR 0x1C001468
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR 0x1C001460
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR 0x1C001484
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR 0x1C001488
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR 0x1C001480
-#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR 0x1C0014A4
-#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR 0x1C0014A8
-#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR 0x1C0014A0
-//TCU
-#define ALT_CCU_TCU_BASE 0x1C003000
-#define ALT_CCU_TCU_XAIUAMIGR_ADDR ALT_CCU_TCU_BASE + 0x03C0
-#define ALT_CCU_TCU_XAIUMIFSR_ADDR ALT_CCU_TCU_BASE + 0x03C4
-#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR ALT_CCU_TCU_BASE + 0x0404
-#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR ALT_CCU_TCU_BASE + 0x0408
-#define ALT_CCU_TCU_XAIUGPRAR0_ADDR ALT_CCU_TCU_BASE + 0x0400
-#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR ALT_CCU_TCU_BASE + 0x0414
-#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR ALT_CCU_TCU_BASE + 0x0418
-#define ALT_CCU_TCU_XAIUGPRAR1_ADDR ALT_CCU_TCU_BASE + 0x0410
-#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR ALT_CCU_TCU_BASE + 0x0424
-#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR ALT_CCU_TCU_BASE + 0x0428
-#define ALT_CCU_TCU_XAIUGPRAR2_ADDR ALT_CCU_TCU_BASE + 0x0420
-#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR 0x1C003464
-#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR 0x1C003468
-#define ALT_CCU_TCU_XAIUGPRAR6_ADDR 0x1C003460
-#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR 0x1C003484
-#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR 0x1C003488
-#define ALT_CCU_TCU_XAIUGPRAR8_ADDR 0x1C003480
-#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR 0x1C0034A4
-#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR 0x1C0034A8
-#define ALT_CCU_TCU_XAIUGPRAR10_ADDR 0x1C0034A0
-//IOM
-#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR 0x1C0043C0
-#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR 0x1C0013C4
-#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR 0x1C001414
-#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR 0x1C001418
-#define ALT_CCU_IOM_XAIUGPRAR1_ADDR 0x1C001410
-#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR 0x1C001464
-#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR 0x1C001468
-#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR 0x1C001460
-#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR 0x1C001484
-#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR 0x1C001488
-#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR 0x1C001480
-#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR 0x1C0014A4
-#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR 0x1C0014A8
-#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR 0x1C0014A0
-//DCE
-#define ALT_CCU_DCE0_DCEUAMIGR_ADDR 0x1C0053C0
-#define ALT_CCU_DCE0_DCEUMIFSR_ADDR 0x1C0053C4
-#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR 0x1C005464
-#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR 0x1C005468
-#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR 0x1C005460
-#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR 0x1C005484
-#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR 0x1C005488
-#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR 0x1C005480
-#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR 0x1C0054A4
-#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR 0x1C0054A8
-#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR 0x1C0054A0
-#define ALT_CCU_DCE1_DCEUAMIGR_ADDR 0x1C0063C0
-#define ALT_CCU_DCE1_DCEUMIFSR_ADDR 0x1C0063C4
-#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR 0x1C006464
-#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR 0x1C006468
-#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR 0x1C006460
-#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR 0x1C006484
-#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR 0x1C006488
-#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR 0x1C006480
-#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR 0x1C0064A4
-#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR 0x1C0064A8
-#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR 0x1C0064A0
-#define offset_NRS_GPRAR0 (0x400)
-#define offset_NRS_GPRBLR0 (0x404)
-#define offset_NRS_GPRBHR0 (0x408)
-#define offset_NRS_GPRAR1 (0x410)
-#define offset_NRS_GPRBLR1 (0x414)
-#define offset_NRS_GPRBHR1 (0x418)
-#define offset_NRS_GPRAR2 (0x420)
-#define offset_NRS_GPRBLR2 (0x424)
-#define offset_NRS_GPRBHR2 (0x428)
-#define offset_NRS_GPRAR3 (0x430)
-#define offset_NRS_GPRBLR3 (0x434)
-#define offset_NRS_GPRBHR3 (0x438)
-#define offset_NRS_GPRAR4 (0x440)
-#define offset_NRS_GPRBLR4 (0x444)
-#define offset_NRS_GPRBHR4 (0x448)
-#define offset_NRS_GPRAR5 (0x450)
-#define offset_NRS_GPRBLR5 (0x454)
-#define offset_NRS_GPRBHR5 (0x458)
-#define offset_NRS_GPRAR6 (0x460)
-#define offset_NRS_GPRBLR6 (0x464)
-#define offset_NRS_GPRBHR6 (0x468)
-#define offset_NRS_GPRAR7 (0x470)
-#define offset_NRS_GPRBLR7 (0x474)
-#define offset_NRS_GPRBHR7 (0x478)
-#define offset_NRS_GPRAR8 (0x480)
-#define offset_NRS_GPRBLR8 (0x484)
-#define offset_NRS_GPRBHR8 (0x488)
-#define offset_NRS_GPRAR9 (0x490)
-#define offset_NRS_GPRBLR9 (0x494)
-#define offset_NRS_GPRBHR9 (0x498)
-#define offset_NRS_GPRAR10 (0x4a0)
-#define offset_NRS_GPRBLR10 (0x4a4)
-#define offset_NRS_GPRBHR10 (0x4a8)
-#define offset_NRS_AMIGR (0x3c0)
-#define offset_NRS_MIFSR (0x3c4)
-#define offset_NRS_DMIUSMCTCR (0x300)
-#define base_addr_DII0_PSSPERIPHS (0x10000)
-#define base_addr_DII0_LWHPS2FPGA (0x20000)
-#define base_addr_DII0_HPS2FPGA_1G (0x40000)
-#define base_addr_DII0_HPS2FPGA_15G (0x400000)
-#define base_addr_DII0_HPS2FPGA_240G (0x4000000)
-#define base_addr_DII1_MPFEREGS (0x18000)
-#define base_addr_DII2_GICREGS (0x1D000)
-#define base_addr_DII3_OCRAM (0x0)
-#define base_addr_BHR (0x0)
-#define base_addr_DMI_SDRAM_2G (0x80000)
-#define base_addr_DMI_SDRAM_30G (0x800000)
-#define base_addr_DMI_SDRAM_480G (0x8000000)
+
+/* Macros */
+#define CCU_OFFSET_VAL_MASK 3U
+#define CCU_WORD_BYTE 4U
+
+// Address Map for CCU Init
+#define addr_CAIUIDR1 SOCFPGA_CCU_NOC_REG_BASE + 0x00000
+#define addr_GRBUNRRUCR SOCFPGA_CCU_NOC_REG_BASE + 0xFFFF8
+#define base_addr_NRS_CAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x00000
+#define base_addr_NRS_NCAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x01000
+#define base_addr_NRS_NCAIU1 SOCFPGA_CCU_NOC_REG_BASE + 0x02000
+#define base_addr_NRS_NCAIU2 SOCFPGA_CCU_NOC_REG_BASE + 0x03000
+#define base_addr_NRS_NCAIU3 SOCFPGA_CCU_NOC_REG_BASE + 0x04000
+#define base_addr_NRS_DCE0 SOCFPGA_CCU_NOC_REG_BASE + 0x05000
+#define base_addr_NRS_DCE1 SOCFPGA_CCU_NOC_REG_BASE + 0x06000
+//#define base_addr_NRS_DMI0 SOCFPGA_CCU_NOC_REG_BASE + 0x07000
+//#define base_addr_NRS_DMI1 SOCFPGA_CCU_NOC_REG_BASE + 0x08000
+
+/* DMI */
+#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x7300
+#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x8300
+
+/* DSU */
+#define ALT_CCU_DSU_CAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C0
+#define ALT_CCU_DSU_CAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C4
+#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x414
+#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x418
+#define ALT_CCU_DSU_CAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x410
+#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x424
+#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x428
+#define ALT_CCU_DSU_CAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x420
+#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x444
+#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x448
+#define ALT_CCU_DSU_CAIUGPRAR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x440
+#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x454
+#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x458
+#define ALT_CCU_DSU_CAIUGPRAR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x450
+#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x464
+#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x468
+#define ALT_CCU_DSU_CAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x460
+#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x474
+#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x478
+#define ALT_CCU_DSU_CAIUGPRAR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x470
+#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x484
+#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x488
+#define ALT_CCU_DSU_CAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x480
+#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x494
+#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x498
+#define ALT_CCU_DSU_CAIUGPRAR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x490
+#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A4
+#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A8
+#define ALT_CCU_DSU_CAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A0
+
+/* GIC */
+#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C0
+#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C4
+#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2414
+#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2418
+#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2410
+#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2464
+#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2468
+#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2460
+#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2484
+#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2488
+#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2480
+#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A4
+#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A8
+#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A0
+
+/* FPGA2SOC */
+#define ALT_CCU_FPGA2SOC_BASE SOCFPGA_CCU_NOC_REG_BASE + 0x1000
+#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C0
+#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480
+#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4
+#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8
+#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0
+
+/* TCU */
+#define ALT_CCU_TCU_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C0
+#define ALT_CCU_TCU_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C4
+#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3404
+#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3408
+#define ALT_CCU_TCU_XAIUGPRAR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3400
+#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3414
+#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3418
+#define ALT_CCU_TCU_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3410
+#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3424
+#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3428
+#define ALT_CCU_TCU_XAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3420
+#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3464
+#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3468
+#define ALT_CCU_TCU_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3460
+#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3484
+#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3488
+#define ALT_CCU_TCU_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3480
+#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A4
+#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A8
+#define ALT_CCU_TCU_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A0
+
+/* IOM */
+#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x43C0
+#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4
+#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414
+#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418
+#define ALT_CCU_IOM_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410
+#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464
+#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468
+#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460
+#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484
+#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488
+#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480
+#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4
+#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8
+#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0
+
+/* DCE */
+#define ALT_CCU_DCE0_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C0
+#define ALT_CCU_DCE0_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C4
+#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5464
+#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5468
+#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5460
+#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5484
+#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5488
+#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5480
+#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A4
+#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A8
+#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A0
+#define ALT_CCU_DCE1_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C0
+#define ALT_CCU_DCE1_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C4
+#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6464
+#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6468
+#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6460
+#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6484
+#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6488
+#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6480
+#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A4
+#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A8
+#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A0
+#define offset_NRS_GPRAR0 0x400
+#define offset_NRS_GPRBLR0 0x404
+#define offset_NRS_GPRBHR0 0x408
+#define offset_NRS_GPRAR1 0x410
+#define offset_NRS_GPRBLR1 0x414
+#define offset_NRS_GPRBHR1 0x418
+#define offset_NRS_GPRAR2 0x420
+#define offset_NRS_GPRBLR2 0x424
+#define offset_NRS_GPRBHR2 0x428
+#define offset_NRS_GPRAR3 0x430
+#define offset_NRS_GPRBLR3 0x434
+#define offset_NRS_GPRBHR3 0x438
+#define offset_NRS_GPRAR4 0x440
+#define offset_NRS_GPRBLR4 0x444
+#define offset_NRS_GPRBHR4 0x448
+#define offset_NRS_GPRAR5 0x450
+#define offset_NRS_GPRBLR5 0x454
+#define offset_NRS_GPRBHR5 0x458
+#define offset_NRS_GPRAR6 0x460
+#define offset_NRS_GPRBLR6 0x464
+#define offset_NRS_GPRBHR6 0x468
+#define offset_NRS_GPRAR7 0x470
+#define offset_NRS_GPRBLR7 0x474
+#define offset_NRS_GPRBHR7 0x478
+#define offset_NRS_GPRAR8 0x480
+#define offset_NRS_GPRBLR8 0x484
+#define offset_NRS_GPRBHR8 0x488
+#define offset_NRS_GPRAR9 0x490
+#define offset_NRS_GPRBLR9 0x494
+#define offset_NRS_GPRBHR9 0x498
+#define offset_NRS_GPRAR10 0x4A0
+#define offset_NRS_GPRBLR10 0x4A4
+#define offset_NRS_GPRBHR10 0x4A8
+#define offset_NRS_AMIGR 0x3C0
+#define offset_NRS_MIFSR 0x3C4
+#define offset_NRS_DMIUSMCTCR 0x300
+#define base_addr_DII0_PSSPERIPHS 0x10000
+#define base_addr_DII0_LWHPS2FPGA 0x20000
+#define base_addr_DII0_HPS2FPGA_1G 0x40000
+#define base_addr_DII0_HPS2FPGA_15G 0x400000
+#define base_addr_DII0_HPS2FPGA_240G 0x4000000
+#define base_addr_DII1_MPFEREGS 0x18000
+#define base_addr_DII2_GICREGS 0x1D000
+#define base_addr_DII3_OCRAM 0x0
+#define base_addr_BHR 0x0
+#define base_addr_DMI_SDRAM_2G 0x80000
+#define base_addr_DMI_SDRAM_30G 0x800000
+#define base_addr_DMI_SDRAM_480G 0x8000000
// ((0x0<<9) | (0xf<<20) | (0x1<<30) | (0x1<<31))
#define wr_DII0_PSSPERIPHS 0xC0F00000
// ((0x0<<9) | (0x11<<20) | (0x1<<30) | (0x1<<31))
@@ -228,54 +243,46 @@
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31))
#define wr_DMI_SDRAM_30G 0x81700006
// ((0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_240G_ORDERED 0x81a00000
+#define wr_DMI_SDRAM_240G_ORDERED 0x81A00000
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_240G 0x81a00006
+#define wr_DMI_SDRAM_240G 0x81A00006
// ((0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_480G_ORDERED 0x81b00000
+#define wr_DMI_SDRAM_480G_ORDERED 0x81B00000
// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31))
-#define wr_DMI_SDRAM_480G 0x81b00006
+#define wr_DMI_SDRAM_480G 0x81B00006
typedef enum CCU_REGION_SECURITY_e {
- //
- // Allow secure accesses only.
- //
+ /* Allow secure accesses only. */
CCU_REGION_SECURITY_SECURE_ONLY,
- //
- // Allow non-secure accesses only.
- //
+
+ /* Allow non-secure accesses only. */
CCU_REGION_SECURITY_NON_SECURE_ONLY,
- //
- // Allow accesses of any security state.
- //
+
+ /* Allow accesses of any security state. */
CCU_REGION_SECURITY_DONT_CARE
} CCU_REGION_SECURITY_t;
+
typedef enum CCU_REGION_PRIVILEGE_e {
- //
- // Allow privileged accesses only.
- //
+ /* Allow privileged accesses only. */
CCU_REGION_PRIVILEGE_PRIVILEGED_ONLY,
- //
- // Allow unprivileged accesses only.
- //
+ /* Allow unprivileged accesses only. */
CCU_REGION_PRIVILEGE_NON_PRIVILEGED_ONLY,
- //
- // Allow accesses of any privilege.
- //
+ /* Allow accesses of any privilege. */
CCU_REGION_PRIVILEGE_DONT_CARE
} CCU_REGION_PRIVILEGE_t;
-//
-// Initializes the CCU by enabling all regions except RAM 1 - 5.
-// This is needed because of an RTL change around 2016.02.24.
-//
-// Runtime measurement:
-// - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32)
-// - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf)
-//
-// Runtime history:
-// - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32)
-// - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf)
-//
+
+/*
+ * Initializes the CCU by enabling all regions except RAM 1 - 5.
+ * This is needed because of an RTL change around 2016.02.24.
+ *
+ * Runtime measurement:
+ * - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32)
+ * - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf)
+ *
+ * Runtime history:
+ * - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32)
+ * - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf)
+ */
int ccu_hps_init(void);
typedef enum ccu_hps_ram_region_e {
@@ -287,19 +294,21 @@
ccu_hps_ram_region_ramspace5 = 5,
} ccu_hps_ram_region_t;
-// Disables a RAM (OCRAM) region with the given ID.
+/* Disables a RAM (OCRAM) region with the given ID. */
int ccu_hps_ram_region_disable(int id);
-// Enables a RAM (OCRAM) region with the given ID.
+/* Enables a RAM (OCRAM) region with the given ID. */
int ccu_hps_ram_region_enable(int id);
-// Attempts to remap a RAM (OCRAM) region with the given ID to span the given
-// start and end address. It also assigns the security and privilege policy.
-// Regions must be a power-of-two size with a minimum size of 64B.
+/*
+ * Attempts to remap a RAM (OCRAM) region with the given ID to span the given
+ * start and end address. It also assigns the security and privilege policy.
+ * Regions must be a power-of-two size with a minimum size of 64B.
+ */
int ccu_hps_ram_region_remap(int id, uintptr_t start, uintptr_t end,
-CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
+ CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
-// Verifies that all enabled RAM (OCRAM) regions does not overlap.
+/* Verifies that all enabled RAM (OCRAM) regions does not overlap. */
int ccu_hps_ram_validate(void);
typedef enum ccu_hps_mem_region_e {
@@ -312,19 +321,21 @@
ccu_hps_mem_region_memspace1e = 6,
} ccu_hps_mem_region_t;
-// Disables mem0 (DDR) region with the given ID.
+/* Disables mem0 (DDR) region with the given ID. */
int ccu_hps_mem0_region_disable(int id);
-// Enables mem0 (DDR) region with the given ID.
+/* Enables mem0 (DDR) region with the given ID. */
int ccu_hps_mem0_region_enable(int id);
-// Attempts to remap mem0 (DDR) region with the given ID to span the given
-// start and end address. It also assigns the security nad privlege policy.
-// Regions must be a power-of-two in size with a minimum size of 64B.
+/*
+ * Attempts to remap mem0 (DDR) region with the given ID to span the given
+ * start and end address. It also assigns the security nad privlege policy.
+ * Regions must be a power-of-two in size with a minimum size of 64B.
+ */
int ccu_hps_mem0_region_remap(int id, uintptr_t start, uintptr_t end,
-CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
+ CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege);
-// Verifies that all enabled mem0 (DDR) regions does not overlap.
+/* Verifies that all enabled mem0 (DDR) regions does not overlap. */
int ccu_hps_mem0_validate(void);
typedef enum ccu_hps_ios_region_e {
@@ -342,14 +353,23 @@
ccu_hps_ios_region_iospace2c = 11,
} ccu_hps_ios_region_t;
-// Disables the IOS (IO Slave) region with the given ID.
+/* Disables the IOS (IO Slave) region with the given ID. */
int ccu_hps_ios_region_disable(int id);
-// Enables the IOS (IO Slave) region with the given ID.
+/* Enables the IOS (IO Slave) region with the given ID. */
int ccu_hps_ios_region_enable(int id);
+typedef struct ncore_ccu_reg {
+ char name[50];
+ uint32_t base;
+ uint32_t size;
+ } ncore_ccu_reg_t;
-#define NCORE_CCU_OFFSET 0xf7000000
+typedef struct ncore_ccu {
+ uint32_t offset;
+ uint32_t val;
+ uint32_t mask;
+ } ncore_ccu_t;
/* Coherent Sub-System Address Map */
#define NCORE_CAIU_OFFSET 0x00000
@@ -358,43 +378,49 @@
#define NCORE_NCBU_SIZE 0x01000
#define NCORE_DIRU_OFFSET 0x80000
#define NCORE_DIRU_SIZE 0x01000
-#define NCORE_CMIU_OFFSET 0xc0000
+#define NCORE_CMIU_OFFSET 0xC0000
#define NCORE_CMIU_SIZE 0x01000
-#define NCORE_CSR_OFFSET 0xff000
+#define NCORE_CSR_OFFSET 0xFF000
#define NCORE_CSADSERO 0x00040
-#define NCORE_CSUIDR 0x00ff8
-#define NCORE_CSIDR 0x00ffc
+#define NCORE_CSUIDR 0x00FF8
+#define NCORE_CSIDR 0x00FFC
+
/* Directory Unit Register Map */
#define NCORE_DIRUSFER 0x00010
#define NCORE_DIRUMRHER 0x00070
#define NCORE_DIRUSFMCR 0x00080
#define NCORE_DIRUSFMAR 0x00084
+
/* Coherent Agent Interface Unit Register Map */
-#define NCORE_CAIUIDR 0x00ffc
+#define NCORE_CAIUIDR 0x00FFC
+
/* Snoop Enable Register */
#define NCORE_DIRUCASER0 0x00040
#define NCORE_DIRUCASER1 0x00044
#define NCORE_DIRUCASER2 0x00048
-#define NCORE_DIRUCASER3 0x0004c
+#define NCORE_DIRUCASER3 0x0004C
#define NCORE_CSADSER0 0x00040
#define NCORE_CSADSER1 0x00044
#define NCORE_CSADSER2 0x00048
-#define NCORE_CSADSER3 0x0004c
+#define NCORE_CSADSER3 0x0004C
+
/* Protocols Definition */
#define ACE_W_DVM 0
#define ACE_L_W_DVM 1
#define ACE_WO_DVM 2
#define ACE_L_WO_DVM 3
-/* Bypass OC Ram Firewall */
+
+/* Bypass OCRAM Firewall */
#define NCORE_FW_OCRAM_BLK_BASE 0x100200
#define NCORE_FW_OCRAM_BLK_CGF1 0x04
#define NCORE_FW_OCRAM_BLK_CGF2 0x08
-#define NCORE_FW_OCRAM_BLK_CGF3 0x0c
+#define NCORE_FW_OCRAM_BLK_CGF3 0x0C
#define NCORE_FW_OCRAM_BLK_CGF4 0x10
#define OCRAM_PRIVILEGED_MASK BIT(29)
#define OCRAM_SECURE_MASK BIT(30)
+
/* Macros */
-#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base))
+#define NCORE_CCU_REG(base) (SOCFPGA_CCU_NOC_REG_BASE + (base))
#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\
+ (reg))
#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
@@ -407,14 +433,14 @@
+ NCORE_CAIU_SIZE * (x))
#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
+ (reg))
-#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24)
-#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16)
-#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8)
-#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0)
-#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18)
+#define CSUIDR_NUM_CMI(x) (((x) & 0x3F000000) >> 24)
+#define CSUIDR_NUM_DIR(x) (((x) & 0x003F0000) >> 16)
+#define CSUIDR_NUM_NCB(x) (((x) & 0x00003F00) >> 8)
+#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007F) >> 0)
+#define CSIDR_NUM_SF(x) (((x) & 0x007C0000) >> 18)
#define SNOOP_FILTER_ID(x) (((x) << 16))
#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15)
-#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16)
+#define CACHING_AGENT_TYPE(x) (((x) & 0xF0000) >> 16)
typedef struct coh_ss_id {
uint8_t num_coh_mem;
@@ -427,5 +453,6 @@
uint32_t init_ncore_ccu(void);
void ncore_enable_ocram_firewall(void);
void setup_smmu_stream_id(void);
+int flush_l3_dcache(void);
#endif
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 1946898..0788ab8 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,7 +32,6 @@
/* Define next boot image name and offset */
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
-
#ifndef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET 0x80200000
#else
@@ -40,7 +40,12 @@
#define PLAT_HANDOFF_OFFSET 0x0003F000
#else
+/* Legacy Products. Please refactor with Agilex5 */
+#ifndef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET 0x10000000
+#else
+#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
+#endif
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#endif
@@ -48,6 +53,7 @@
#define PLAT_NAND_DATA_BASE (0x0200000)
#define PLAT_SDMMC_DATA_BASE (0x0)
+
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h
index b2913c7..7e1d0c0 100644
--- a/plat/intel/soc/common/include/socfpga_handoff.h
+++ b/plat/intel/soc/common/include/socfpga_handoff.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,12 +11,12 @@
#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
-#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
+#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
-#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
-#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
+#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
+#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
#define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */
-#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
+#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
#include <socfpga_plat_def.h>
@@ -126,6 +127,8 @@
uint32_t clock_magic;
uint32_t clock_length;
uint32_t _pad_0x588_0x590[2];
+
+ /* main group PLL */
uint32_t main_pll_nocclk;
uint32_t main_pll_nocdiv;
uint32_t main_pll_pllglob;
@@ -135,6 +138,8 @@
uint32_t main_pll_pllc2;
uint32_t main_pll_pllc3;
uint32_t main_pll_pllm;
+
+ /* peripheral group PLL */
uint32_t per_pll_emacctl;
uint32_t per_pll_gpiodiv;
uint32_t per_pll_pllglob;
@@ -144,29 +149,25 @@
uint32_t per_pll_pllc2;
uint32_t per_pll_pllc3;
uint32_t per_pll_pllm;
+
+ /* control group */
uint32_t alt_emacactr;
uint32_t alt_emacbctr;
uint32_t alt_emacptpctr;
uint32_t alt_gpiodbctr;
- uint32_t alt_sdmmcctr;
uint32_t alt_s2fuser0ctr;
uint32_t alt_s2fuser1ctr;
uint32_t alt_psirefctr;
- /* TODO: Temp added for clk manager. */
- uint32_t qspi_clk_khz;
+ uint32_t alt_usb31ctr;
+ uint32_t alt_dsuctr;
+ uint32_t alt_core01ctr;
+ uint32_t alt_core23ctr;
+ uint32_t alt_core2ctr;
+ uint32_t alt_core3ctr;
uint32_t hps_osc_clk_hz;
uint32_t fpga_clk_hz;
- /* TODO: Temp added for clk manager. */
- uint32_t ddr_reset_type;
- /* TODO: Temp added for clk manager. */
- uint32_t hps_status_coldreset;
- /* TODO: Temp remove due to add in extra handoff data */
- //uint32_t _pad_0x604_0x610[3];
+ uint32_t _pad_0x604_0x610[3];
#endif
- /* misc configuration */
- uint32_t misc_magic;
- uint32_t misc_length;
- uint32_t _pad_0x618_0x620[2];
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/* peripheral configuration - select */
@@ -179,7 +180,7 @@
uint32_t ddr_magic;
uint32_t ddr_length;
uint32_t _pad_0x1C_0x20[2];
- uint32_t ddr_array[4]; /* offset, value */
+ uint32_t ddr_config; /* BIT[0]-Dual Port. BIT[1]-Dual EMIF */
#endif
} handoff;
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index 041c282..a0d4180 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 74ecc95..5d31e99 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -168,7 +168,7 @@
}
if (MBOX_RESP_ERR(resp_data) > 0U) {
- INFO("Error in response: %x\n", resp_data);
+ INFO("SDM response: Return Code: 0x%x\n", MBOX_RESP_ERR(resp_data));
return -MBOX_RESP_ERR(resp_data);
}
@@ -337,7 +337,7 @@
}
if (MBOX_RESP_ERR(resp_data) > 0U) {
- INFO("Error in response: %x\n", resp_data);
+ INFO("SDM response: Return Code: 0x%x\n", MBOX_RESP_ERR(resp_data));
return -MBOX_RESP_ERR(resp_data);
}
@@ -652,7 +652,7 @@
res = response[RECONFIG_STATUS_SOFTFUNC_STATUS];
if ((res & SOFTFUNC_STATUS_SEU_ERROR) != 0U) {
- ERROR("SoftFunction Status SEU ERROR\n");
+ return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
}
if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) {
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 535e68f..c7d7076 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -76,7 +76,7 @@
RSTMGR_FIELD(PER0, DMAIF6) |
RSTMGR_FIELD(PER0, DMAIF7));
-#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+#if (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5)
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_FIELD(BRG, MPFE));
#endif
@@ -484,6 +484,11 @@
(~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
| RSTMGR_BRGMODRST_LWHPS2FPGA))
| RSTMGR_BRGMODRST_SOC2FPGA);
+
+ /* Set System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
+ VERBOSE("Set SOC soc2fpga_ready_latency_enable ...\n");
+ mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
+ SYSMGR_SOC_BRIDGE_CTRL_EN);
}
/**************** LWSOCFPGA ****************/
@@ -567,6 +572,11 @@
((~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
| RSTMGR_BRGMODRST_LWHPS2FPGA)))
| RSTMGR_BRGMODRST_LWHPS2FPGA);
+
+ /* Set System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
+ VERBOSE("Set LWSOC lwsoc2fpga_ready_latency_enable ...\n");
+ mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
+ SYSMGR_LWSOC_BRIDGE_CTRL_EN);
}
#else
if (brg_mask != 0U) {
@@ -579,10 +589,7 @@
/* Wait until idle ack becomes 0 */
ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
- noc_mask, 0, 300);
- if (ret_hps < 0) {
- ERROR("S2F bridge enable: Timeout idle ack\n");
- }
+ noc_mask, 0, 1000);
}
#endif
@@ -958,6 +965,11 @@
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA);
+ /* Clear System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
+ VERBOSE("Clear SOC soc2fpga_ready_latency_enable ...\n");
+ mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
+ SYSMGR_SOC_BRIDGE_CTRL_EN);
+
udelay(1000);
}
@@ -991,6 +1003,11 @@
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA);
+ /* Clear System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
+ VERBOSE("Clear LWSOC lwsoc2fpga_ready_latency_enable ...\n");
+ mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
+ SYSMGR_LWSOC_BRIDGE_CTRL_EN);
+
udelay(1000);
}
#else
@@ -1266,4 +1283,4 @@
} while (timeout-- > 0);
return RSTMGR_RET_ERROR;
-}
+}
\ No newline at end of file
diff --git a/plat/intel/soc/common/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c
index db173a4..3759009 100644
--- a/plat/intel/soc/common/socfpga_delay_timer.c
+++ b/plat/intel/soc/common/socfpga_delay_timer.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +11,6 @@
#include <lib/mmio.h>
#include "socfpga_plat_def.h"
-
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
#include "agilex_clock_manager.h"
#elif PLATFORM_MODEL == PLAT_SOCFPGA_N5X
@@ -19,7 +19,7 @@
#include "s10_clock_manager.h"
#endif
-#define SOCFPGA_GLOBAL_TIMER 0xffd01000
+#define SOCFPGA_GLOBAL_TIMER PLAT_TIMER_BASE_ADDR
#define SOCFPGA_GLOBAL_TIMER_EN 0x3
static timer_ops_t plat_timer_ops;
@@ -44,7 +44,6 @@
plat_timer_ops.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ;
timer_init(&plat_timer_ops);
-
}
void socfpga_delay_timer_init(void)
@@ -54,5 +53,4 @@
asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
-
}
diff --git a/plat/intel/soc/common/socfpga_image_load.c b/plat/intel/soc/common/socfpga_image_load.c
index a5c3279..ee79158 100644
--- a/plat/intel/soc/common/socfpga_image_load.c
+++ b/plat/intel/soc/common/socfpga_image_load.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +13,13 @@
******************************************************************************/
void plat_flush_next_bl_params(void)
{
+ /*
+ * We cannot flush these descriptors on the Agilex5 platform,
+ * since the BL2 runs on the OCRAM and this OCRAM is not cache coherent.
+ */
+#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
flush_bl_params_desc();
+#endif
}
/*******************************************************************************
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 623843e..8dc39e2 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -17,8 +17,13 @@
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+#include "agilex5_cache.h"
+#endif
+#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
+#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
#include "socfpga_system_manager.h"
@@ -190,6 +195,14 @@
if (intel_rsu_update_address) {
mailbox_rsu_update(addr_buf);
} else {
+#if CACHE_FLUSH
+ /* ATF Flush and Invalidate Cache */
+ dcsw_op_all(DCCISW);
+ invalidate_cache_low_el();
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ flush_l3_dcache();
+#endif
+#endif
mailbox_reset_cold();
}
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index d250d9e..7679f59 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,16 +22,21 @@
#include <drivers/partition/partition.h>
#include <lib/mmio.h>
#include <tools_share/firmware_image_package.h>
-
#include "drivers/sdmmc/sdmmc.h"
#include "socfpga_private.h"
#include "socfpga_ros.h"
#define PLAT_FIP_BASE (0)
+# if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_FIP_MAX_SIZE (0x8000000)
+#define PLAT_MMC_DATA_BASE (0x10000000)
+#define PLAT_MMC_DATA_SIZE (0x100000)
+# else
#define PLAT_FIP_MAX_SIZE (0x1000000)
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000)
+# endif
static const io_dev_connector_t *fip_dev_con;
static const io_dev_connector_t *boot_dev_con;
diff --git a/plat/intel/soc/n5x/include/n5x_clock_manager.h b/plat/intel/soc/n5x/include/n5x_clock_manager.h
index 54477da..95a3d5c 100644
--- a/plat/intel/soc/n5x/include/n5x_clock_manager.h
+++ b/plat/intel/soc/n5x/include/n5x_clock_manager.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +10,6 @@
/* MACRO DEFINITION */
-#define SOCFPGA_GLOBAL_TIMER 0xffd01000
#define SOCFPGA_GLOBAL_TIMER_EN 0x3
#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 1eafeef..c5e66c7 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,6 +19,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@@ -27,6 +29,13 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000)
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h
index 155b279..056f6cf 100644
--- a/plat/intel/soc/stratix10/include/s10_memory_controller.h
+++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,7 +27,7 @@
#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
-#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x0000000f
#define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 7f452bd..cd4c163 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +18,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@@ -26,6 +28,13 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index afcf514..0a33c3d 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -1,6 +1,7 @@
#
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
-# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -26,6 +27,7 @@
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
+ plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/soc/socfpga_firewall.c
diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
index 26bed29..7b867d8 100644
--- a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
+++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
@@ -97,7 +97,7 @@
/* PCI-e protect address(64MB) */
region_info.start = 0xC0000000ULL;
- region_info.end = 0xC3FF0000ULL;
+ region_info.end = 0xC3FFFFFFULL;
region_info.region = 1;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -108,7 +108,7 @@
/* SCP protect address */
region_info.start = 0x50000000ULL;
- region_info.end = 0x513F0000ULL;
+ region_info.end = 0x513FFFFFULL;
region_info.region = 2;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -117,21 +117,10 @@
NO_PROT, FORBIDDEN, FORBIDDEN, NO_PROT);
emi_mpu_set_protection(®ion_info);
- /* DSP protect address */
- region_info.start = 0x40000000ULL; /* dram base addr */
- region_info.end = 0x1FFFF0000ULL;
- region_info.region = 3;
- SET_ACCESS_PERMISSION(region_info.apc, 1,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT);
- emi_mpu_set_protection(®ion_info);
-
/* Forbidden All */
region_info.start = 0x40000000ULL; /* dram base addr */
- region_info.end = 0x1FFFF0000ULL;
- region_info.region = 4;
+ region_info.end = 0x1FFFFFFFFULL;
+ region_info.region = 3;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
diff --git a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
index b6e5a2d..8e4a675 100644
--- a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
+++ b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
@@ -118,7 +118,7 @@
/* SCP DRAM */
region_info.start = 0x50000000ULL;
- region_info.end = 0x51400000ULL;
+ region_info.end = 0x513FFFFFULL;
region_info.region = 2;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
diff --git a/plat/nxp/s32/s32g274ardb2/include/s32cc-ncore.h b/plat/nxp/s32/s32g274ardb2/include/s32cc-ncore.h
new file mode 100644
index 0000000..0c0870f
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/include/s32cc-ncore.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2019-2021, 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef S32G2_NCORE_H
+#define S32G2_NCORE_H
+
+#include <stdbool.h>
+
+#define NCORE_BASE_ADDR UL(0x50400000)
+
+#define A53_CLUSTER0_CAIU U(0)
+#define A53_CLUSTER1_CAIU U(1)
+
+/**
+ * Directory Unit Registers
+ *
+ * The directory provides a point of serialization for establishing transaction
+ * ordering and sequences coherence operations and memory accesses.
+ */
+#define NCORE_DIRU(N) (NCORE_BASE_ADDR + UL(0x80000) + ((N) * UL(0x1000)))
+
+/* DIRU Snoop Filtering Enable */
+#define NCORE_DIRUSFE(N) (NCORE_DIRU(N) + UL(0x10))
+#define NCORE_DIRUSFE_SFEN(SF) BIT_32(SF)
+
+/* DIRU Caching Agent Snoop Enable */
+#define NCORE_DIRUCASE(N) (NCORE_DIRU(N) + UL(0x40))
+#define NCORE_DIRUCASE_CASNPEN(CAIU) BIT_32(CAIU)
+
+/* DIRU Snoop Filter Maintenance Control */
+#define NCORE_DIRUSFMC(N) (NCORE_DIRU(N) + UL(0x80))
+#define NCORE_DIRUSFMC_SFID(SF) ((SF) << 16U)
+#define NCORE_DIRUSFMC_SFMNTOP_ALL U(0x0)
+
+/* DIRU Snoop Filter Maintenance Activity */
+#define NCORE_DIRUSFMA(N) (NCORE_DIRU(N) + UL(0x84))
+#define NCORE_DIRUSFMA_MNTOPACTV BIT_32(0)
+
+/**
+ * Coherent Agent Interface Unit Registers
+ *
+ * CAI provides a means for a fully-coherent agent to be connected to the Ncore.
+ * The CAI behaves as a fully-coherent slave.
+ */
+#define NCORE_CAIU(N) (NCORE_BASE_ADDR + ((N) * UL(0x1000)))
+#define NCORE_CAIU0_BASE_ADDR NCORE_BASE_ADDR
+
+/* CAIU Transaction Control */
+#define NCORE_CAIUTC_OFF UL(0x0)
+#define NCORE_CAIUTC_ISOLEN_SHIFT U(1)
+#define NCORE_CAIUTC_ISOLEN_MASK BIT_32(NCORE_CAIUTC_ISOLEN_SHIFT)
+
+#define NCORE_CAIUTC(N) (NCORE_CAIU(N) + NCORE_CAIUTC_OFF)
+
+/* CAIU Identification */
+#define NCORE_CAIUID(n) (NCORE_CAIU(n) + UL(0xFFC))
+#define NCORE_CAIUID_TYPE GENMASK_32(U(19), U(16))
+#define NCORE_CAIUID_TYPE_ACE_DVM U(0x0)
+
+/**
+ * Coherent Subsystem Registers
+ */
+#define NCORE_CSR (NCORE_BASE_ADDR + UL(0xFF000))
+
+/* Coherent Subsystem ACE DVM Snoop Enable */
+#define NCORE_CSADSE (NCORE_CSR + UL(0x40))
+#define NCORE_CSADSE_DVMSNPEN(CAIU) BIT_32(CAIU)
+
+/* Coherent Subsystem Identification */
+#define NCORE_CSID (NCORE_CSR + UL(0xFFC))
+#define NCORE_CSID_NUMSFS_SHIFT U(18)
+#define NCORE_CSID_NUMSFS_MASK GENMASK_32(U(22), NCORE_CSID_NUMSFS_SHIFT)
+#define NCORE_CSID_NUMSFS(CSIDR) (((CSIDR) & NCORE_CSID_NUMSFS_MASK) \
+ >> NCORE_CSID_NUMSFS_SHIFT)
+
+/* Coherent Subsystem Unit Identification */
+#define NCORE_CSUID (NCORE_CSR + UL(0xFF8))
+#define NCORE_CSUID_NUMCMIUS_SHIFT U(24)
+#define NCORE_CSUID_NUMCMIUS_MASK GENMASK_32(U(29), NCORE_CSUID_NUMCMIUS_SHIFT)
+#define NCORE_CSUID_NUMCMIUS(CSUIDR) (((CSUIDR) & NCORE_CSUID_NUMCMIUS_MASK) \
+ >> NCORE_CSUID_NUMCMIUS_SHIFT)
+#define NCORE_CSUID_NUMDIRUS_SHIFT U(16)
+#define NCORE_CSUID_NUMDIRUS_MASK GENMASK_32(U(21), NCORE_CSUID_NUMDIRUS_SHIFT)
+#define NCORE_CSUID_NUMDIRUS(CSUIDR) (((CSUIDR) & NCORE_CSUID_NUMDIRUS_MASK) \
+ >> NCORE_CSUID_NUMDIRUS_SHIFT)
+#define NCORE_CSUID_NUMNCBUS_SHIFT U(8)
+#define NCORE_CSUID_NUMNCBUS_MASK GENMASK_32(U(13), NCORE_CSUID_NUMNCBUS_SHIFT)
+#define NCORE_CSUID_NUMNCBUS(CSUIDR) (((CSUIDR) & NCORE_CSUID_NUMNCBUS_MASK) \
+ >> NCORE_CSUID_NUMNCBUS_SHIFT)
+
+#ifndef __ASSEMBLER__
+void ncore_caiu_online(uint32_t caiu);
+void ncore_caiu_offline(uint32_t caiu);
+void ncore_init(void);
+bool ncore_is_caiu_online(uint32_t caiu);
+void ncore_disable_caiu_isolation(uint32_t caiu);
+#endif /* __ASSEMBLER__ */
+
+#endif /* S32G2_NCORE_H */
diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
index 705832c..4645f01 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
@@ -11,6 +11,7 @@
#include <plat_console.h>
#include <s32cc-clk-drv.h>
#include <plat_io_storage.h>
+#include <s32cc-ncore.h>
#define SIUL2_PC09_MSCR UL(0x4009C2E4)
#define SIUL2_PC10_MSCR UL(0x4009C2E8)
@@ -62,6 +63,14 @@
linflex_config_pinctrl();
console_s32g2_register();
+ /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which
+ * we have manually set during early BL2 boot.
+ */
+ ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU);
+
+ ncore_init();
+ ncore_caiu_online(A53_CLUSTER0_CAIU);
+
plat_s32g2_io_setup();
}
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index 10c0035..7121900 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -6,10 +6,7 @@
#include <asm_macros.S>
#include <platform_def.h>
-
-#define S32G_NCORE_CAIU0_BASE_ADDR UL(0x50400000)
-#define S32G_NCORE_CAIUTC_OFF U(0x0)
-#define S32G_NCORE_CAIUTC_ISOLEN_SHIFT U(1)
+#include <s32cc-ncore.h>
.globl plat_crash_console_flush
.globl plat_crash_console_init
@@ -104,12 +101,12 @@
* Clobber list: x0, x1, x2
*/
func plat_reset_handler
- mov x0, #S32G_NCORE_CAIU0_BASE_ADDR
- ldr w1, [x0, #S32G_NCORE_CAIUTC_OFF]
+ mov x0, #NCORE_CAIU0_BASE_ADDR
+ ldr w1, [x0, #NCORE_CAIUTC_OFF]
movz w2, #1
- lsl w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT
+ lsl w2, w2, #NCORE_CAIUTC_ISOLEN_SHIFT
orr w1, w1, w2
- str w1, [x0, #S32G_NCORE_CAIUTC_OFF]
+ str w1, [x0, #NCORE_CAIUTC_OFF]
ret
endfunc plat_reset_handler
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index 316ed2c..7d6e960 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -15,6 +15,10 @@
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+# Flag to apply S32 erratum ERR051700. This erratum applies to all S32
+# revisions.
+S32_ERRATA_LIST += ERRATA_S32_051700
+
PLAT_INCLUDES = \
-I${PLAT_S32G274ARDB2}/include
@@ -32,6 +36,7 @@
ERRATA_A53_836870 := 1
ERRATA_A53_1530924 := 1
ERRATA_SPECULATIVE_AT := 1
+ERRATA_S32_051700 := 1
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
@@ -39,7 +44,6 @@
include ${PLAT_DRIVERS_PATH}/drivers.mk
-
BL_COMMON_SOURCES += \
${PLAT_S32G274ARDB2}/plat_console.c \
${PLAT_S32G274ARDB2}/plat_helpers.S \
@@ -49,6 +53,7 @@
${PLAT_S32G274ARDB2}/plat_bl2_el3_setup.c \
${PLAT_S32G274ARDB2}/plat_bl2_image_desc.c \
${PLAT_S32G274ARDB2}/plat_io_storage.c \
+ ${PLAT_S32G274ARDB2}/s32cc_ncore.c \
common/desc_image_load.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
@@ -64,3 +69,8 @@
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
+
+# process all errata flags
+$(eval $(call default_zeros, $(S32_ERRATA_LIST)))
+$(eval $(call add_defines, $(S32_ERRATA_LIST)))
+$(eval $(call assert_booleans, $(S32_ERRATA_LIST)))
diff --git a/plat/nxp/s32/s32g274ardb2/s32cc_ncore.c b/plat/nxp/s32/s32g274ardb2/s32cc_ncore.c
new file mode 100644
index 0000000..aa60ac4
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/s32cc_ncore.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2019-2021, 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#include <s32cc-ncore.h>
+
+static void ncore_diru_online(uint32_t diru)
+{
+ uint32_t numsfs, sf;
+
+ numsfs = NCORE_CSID_NUMSFS(mmio_read_32(NCORE_CSID)) + 1U;
+
+ /* Initialize all entries maintenance operation for each snoop filter */
+ for (sf = 0U; sf < numsfs; sf++) {
+ mmio_write_32(NCORE_DIRUSFMC(diru), NCORE_DIRUSFMC_SFID(sf) |
+ NCORE_DIRUSFMC_SFMNTOP_ALL);
+
+ while ((mmio_read_32(NCORE_DIRUSFMA(diru)) & NCORE_DIRUSFMA_MNTOPACTV) != 0U) {
+ }
+
+ mmio_setbits_32(NCORE_DIRUSFE(diru), NCORE_DIRUSFE_SFEN(sf));
+ }
+}
+
+void ncore_disable_caiu_isolation(uint32_t caiu)
+{
+ /* Exit from low-power state */
+ mmio_clrbits_32(NCORE_CAIUTC(caiu), NCORE_CAIUTC_ISOLEN_MASK);
+}
+
+static void set_caiu(uint32_t caiu, bool on)
+{
+ uint32_t dirucase, csadser, caiuidr;
+ uint32_t numdirus, diru;
+
+ /* Enable or disable snoop messages to the CAI for each DIRU */
+ numdirus = NCORE_CSUID_NUMDIRUS(mmio_read_32(NCORE_CSUID));
+ for (diru = 0; diru < numdirus; diru++) {
+ dirucase = mmio_read_32(NCORE_DIRUCASE(diru));
+
+ if (on) {
+ dirucase |= NCORE_DIRUCASE_CASNPEN(caiu);
+ } else {
+ dirucase &= ~NCORE_DIRUCASE_CASNPEN(caiu);
+ }
+
+ mmio_write_32(NCORE_DIRUCASE(diru), dirucase);
+ }
+
+ /* Enable or disable DVM messages to the CAI */
+ caiuidr = mmio_read_32(NCORE_CAIUID(caiu));
+ if ((caiuidr & NCORE_CAIUID_TYPE) == NCORE_CAIUID_TYPE_ACE_DVM) {
+ csadser = mmio_read_32(NCORE_CSADSE);
+
+ if (on) {
+ csadser |= NCORE_CSADSE_DVMSNPEN(caiu);
+ } else {
+ csadser &= ~NCORE_CSADSE_DVMSNPEN(caiu);
+ }
+
+ mmio_write_32(NCORE_CSADSE, csadser);
+ }
+}
+
+void ncore_caiu_online(uint32_t caiu)
+{
+ set_caiu(caiu, true);
+}
+
+void ncore_caiu_offline(uint32_t caiu)
+{
+ set_caiu(caiu, false);
+}
+
+bool ncore_is_caiu_online(uint32_t caiu)
+{
+ uint32_t stat = mmio_read_32(NCORE_CSADSE);
+
+ return ((stat & NCORE_CSADSE_DVMSNPEN(caiu)) != 0U);
+}
+
+void ncore_init(void)
+{
+ uint32_t csuidr = mmio_read_32(NCORE_CSUID);
+ uint32_t numdirus, diru;
+
+ numdirus = NCORE_CSUID_NUMDIRUS(csuidr);
+ for (diru = 0U; diru < numdirus; diru++) {
+ /**
+ * Transition the directory to an online state by ensuring that
+ * all DIRUs within the interface are operational.
+ */
+ ncore_diru_online(diru);
+ }
+}
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index dde66aa..9b8c971 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,6 +32,17 @@
*
*/
func plat_reset_handler
+#ifdef PLAT_RK_CPU_RESET_EARLY
+ mov x18, x30
+ msr spsel, #0
+ bl plat_set_my_stack
+ mov x0, x20
+ mov x1, x21
+ mov x2, x22
+ mov x3, x23
+ bl rockchip_cpu_reset_early
+ mov x30, x18
+#endif
mrs x0, midr_el1
ubfx x0, x0, MIDR_PN_SHIFT, #12
cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
diff --git a/plat/rockchip/rk3399/drivers/m0/Makefile b/plat/rockchip/rk3399/drivers/m0/Makefile
index e742591..32446ef 100644
--- a/plat/rockchip/rk3399/drivers/m0/Makefile
+++ b/plat/rockchip/rk3399/drivers/m0/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := rk3399-m0
-
include ../../../../../make_helpers/common.mk
include ../../../../../make_helpers/toolchain.mk
diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
index 83d6cad..f693dbd 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -136,6 +136,22 @@
static __pmusramfunc void ddr_resume(void)
{
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
+ dsb();
+ isb();
+
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ }
+
dsu_restore_early();
}
@@ -1437,3 +1453,60 @@
pm_reg_rgns_init();
}
+
+static uint64_t boot_cpu_save[4];
+/* define in .data section */
+static uint32_t need_en_crypto = 1;
+
+void rockchip_cpu_reset_early(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ if (need_en_crypto == 0)
+ return;
+
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* save x0~x3 */
+ boot_cpu_save[0] = arg0;
+ boot_cpu_save[1] = arg1;
+ boot_cpu_save[2] = arg2;
+ boot_cpu_save[3] = arg3;
+
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4),
+ BITS_WITH_WMASK(0, 0x1, 4));
+
+ /* remap pmusram to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
+ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
+ cpuson_flags[0] = PMU_CPU_HOTPLUG;
+ cpuson_entry_point[0] = (uintptr_t)BL31_BASE;
+ dsb();
+
+ /* Must reset core0 to enable the crypto function.
+ * Core0 will boot from pmu_sram and jump to BL31_BASE.
+ */
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ } else {
+ need_en_crypto = 0;
+
+ /* remap bootrom to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
+
+ /*
+ * the crypto function has been enabled,
+ * restore the x0~x3.
+ */
+ __asm__ volatile ("ldr x20, [%0]\n"
+ "ldr x21, [%0, 0x8]\n"
+ "ldr x22, [%0, 0x10]\n"
+ "ldr x23, [%0, 0x18]\n"
+ : : "r" (&boot_cpu_save[0]));
+ }
+}
diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk
index 07eda40..2fadb5a 100644
--- a/plat/rockchip/rk3588/platform.mk
+++ b/plat/rockchip/rk3588/platform.mk
@@ -95,4 +95,4 @@
ENABLE_SPE_FOR_LOWER_ELS := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
-$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
+$(eval $(call add_define,PLAT_RK_CPU_RESET_EARLY))
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index eaaff7d..e139b49 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -23,6 +23,7 @@
BL1_SOURCES += drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
+ drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
plat/common/aarch64/platform_mp_stack.S \
plat/rpi/rpi3/rpi3_bl1_setup.c \
diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c
index 3ac30e0..6c8fb2d 100644
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,8 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <drivers/generic_delay_timer.h>
+#include <plat/common/platform.h>
#include <rpi_shared.h>
@@ -37,6 +39,15 @@
/* Initialize the console to provide early debug support */
rpi3_console_init();
+ /*
+ * Write the System Timer Frequency to CNTFRQ manually, this
+ * is required to use the delay_timer functionality.
+ */
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+
+ /* Enable arch timer */
+ generic_delay_timer_init();
+
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
bl1_tzram_layout.total_size = BL_RAM_SIZE;
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 9af221c..f65301f 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -77,6 +77,8 @@
/* Setup the UART console */
int stm32mp_uart_console_setup(void);
+bool stm32mp_is_wakeup_from_standby(void);
+
/*
* Platform util functions for the GPIO driver
* @bank: Target GPIO bank ID as per DT bindings
@@ -120,6 +122,10 @@
int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void);
+/* Functions to map RETRAM, and unmap it */
+int stm32mp_map_retram(void);
+int stm32mp_unmap_retram(void);
+
/* Function to save boot info */
void stm32_save_boot_info(boot_api_context_t *boot_context);
/* Function to get boot peripheral info */
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 1cbf51b..282f53f 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -243,7 +243,11 @@
return 0U;
}
+#ifdef __aarch64__
+ size = (size_t)fdt_read_uint64_default(fdt, node, "st,mem-size", 0ULL);
+#else /* __aarch64__ */
size = (size_t)fdt_read_uint32_default(fdt, node, "st,mem-size", 0U);
+#endif /* __aarch64__ */
flush_dcache_range((uintptr_t)&size, sizeof(size_t));
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 1aecece..644275e 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -77,7 +77,7 @@
#define DEFAULT_UUID_NUMBER U(7)
#ifdef __aarch64__
-#define BL31_UUID_NUMBER U(1)
+#define BL31_UUID_NUMBER U(2)
#else
#define BL31_UUID_NUMBER U(0)
#endif
@@ -115,6 +115,7 @@
{FW_CONFIG_ID, "fw_cfg_uuid"},
#ifdef __aarch64__
{BL31_IMAGE_ID, "bl31_uuid"},
+ {SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
#endif
{BL32_IMAGE_ID, "bl32_uuid"},
{BL32_EXTRA1_IMAGE_ID, "bl32_extra1_uuid"},
diff --git a/plat/st/stm32mp1/plat_ddr.c b/plat/st/stm32mp1/plat_ddr.c
new file mode 100644
index 0000000..a6a0cdb
--- /dev/null
+++ b/plat/st/stm32mp1/plat_ddr.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <drivers/st/regulator.h>
+#include <drivers/st/stm32mp_ddr.h>
+#include <drivers/st/stm32mp_pmic.h>
+
+/* configure the STPMIC1 regulators on STMicroelectronics boards */
+static int pmic_ddr_power_init(enum ddr_type ddr_type)
+{
+ int status;
+ uint16_t buck3_min_mv __maybe_unused;
+ struct rdev *buck2, *buck3 __maybe_unused, *vref;
+ struct rdev *ldo3 __maybe_unused;
+
+ buck2 = regulator_get_by_name("buck2");
+ if (buck2 == NULL) {
+ return -ENOENT;
+ }
+
+#if STM32MP15
+ ldo3 = regulator_get_by_name("ldo3");
+ if (ldo3 == NULL) {
+ return -ENOENT;
+ }
+#endif
+
+ vref = regulator_get_by_name("vref_ddr");
+ if (vref == NULL) {
+ return -ENOENT;
+ }
+
+ switch (ddr_type) {
+ case STM32MP_DDR3:
+#if STM32MP15
+ status = regulator_set_flag(ldo3, REGUL_SINK_SOURCE);
+ if (status != 0) {
+ return status;
+ }
+#endif
+
+ status = regulator_set_min_voltage(buck2);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(buck2);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(vref);
+ if (status != 0) {
+ return status;
+ }
+
+#if STM32MP15
+ status = regulator_enable(ldo3);
+ if (status != 0) {
+ return status;
+ }
+#endif
+ break;
+
+ case STM32MP_LPDDR2:
+ case STM32MP_LPDDR3:
+#if STM32MP15
+ /*
+ * Set LDO3 to 1.8V according BUCK3 voltage
+ * => bypass mode if BUCK3 = 1.8V
+ * => normal mode if BUCK3 != 1.8V
+ */
+ buck3 = regulator_get_by_name("buck3");
+ if (buck3 == NULL) {
+ return -ENOENT;
+ }
+
+ regulator_get_range(buck3, &buck3_min_mv, NULL);
+
+ if (buck3_min_mv != 1800) {
+ status = regulator_set_min_voltage(ldo3);
+ if (status != 0) {
+ return status;
+ }
+ } else {
+ status = regulator_set_flag(ldo3, REGUL_ENABLE_BYPASS);
+ if (status != 0) {
+ return status;
+ }
+ }
+#endif
+
+ status = regulator_set_min_voltage(buck2);
+ if (status != 0) {
+ return status;
+ }
+
+#if STM32MP15
+ status = regulator_enable(ldo3);
+ if (status != 0) {
+ return status;
+ }
+#endif
+
+ status = regulator_enable(buck2);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(vref);
+ if (status != 0) {
+ return status;
+ }
+ break;
+
+ default:
+ break;
+ };
+
+ return 0;
+}
+
+int stm32mp_board_ddr_power_init(enum ddr_type ddr_type)
+{
+ if (dt_pmic_status() > 0) {
+ return pmic_ddr_power_init(ddr_type);
+ }
+
+ return 0;
+}
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 138f16c..3d37738 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -253,6 +253,8 @@
BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \
drivers/st/ddr/stm32mp1_ram.c
+BL2_SOURCES += plat/st/stm32mp1/plat_ddr.c
+
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | $$(@D)/
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 32de391..45446dc 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -664,6 +664,12 @@
}
#endif
+bool stm32mp_is_wakeup_from_standby(void)
+{
+ /* TODO add source code to determine if platform is waking up from standby mode */
+ return false;
+}
+
uintptr_t stm32_get_bkpr_boot_mode_addr(void)
{
return tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 50d19ab..2fabc41 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -15,10 +15,13 @@
#include <drivers/mmc.h>
#include <drivers/st/regulator_fixed.h>
#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp2_ram.h>
+#include <drivers/st/stm32mp_pmic2.h>
#include <drivers/st/stm32mp_risab_regs.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/mmio.h>
+#include <lib/optee_utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
@@ -134,6 +137,21 @@
void bl2_platform_setup(void)
{
+ int ret;
+
+ ret = stm32mp2_ddr_probe();
+ if (ret != 0) {
+ ERROR("DDR probe: error %d\n", ret);
+ panic();
+ }
+
+ /* Map DDR for binary load, now with cacheable attribute */
+ ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
+ STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
+ if (ret < 0) {
+ ERROR("DDR mapping: error %d\n", ret);
+ panic();
+ }
}
static void reset_backup_domain(void)
@@ -230,8 +248,22 @@
panic();
}
+ if (dt_pmic_status() > 0) {
+ initialize_pmic();
+ }
+
fconf_populate("TB_FW", STM32MP_DTB_BASE);
+ /*
+ * RISAB5 setup (dedicated for RETRAM)
+ *
+ * Allow secure read/writes data accesses to non-secure
+ * blocks or pages, all RISAB registers are writable.
+ * DDR retention registers are saved there and restored
+ * when exiting standby low power state.
+ */
+ mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD);
+
stm32mp_io_setup();
}
@@ -243,10 +275,15 @@
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+ bl_mem_params_node_t *pager_mem_params;
const struct dyn_cfg_dtb_info_t *config_info;
unsigned int i;
const unsigned int image_ids[] = {
BL31_IMAGE_ID,
+ SOC_FW_CONFIG_ID,
+ BL32_IMAGE_ID,
+ BL33_IMAGE_ID,
+ HW_CONFIG_ID,
};
assert(bl_mem_params != NULL);
@@ -290,6 +327,28 @@
case BL31_IMAGE_ID:
bl_mem_params->ep_info.pc = config_info->config_addr;
break;
+
+ case BL32_IMAGE_ID:
+ bl_mem_params->ep_info.pc = config_info->config_addr;
+
+ /* In case of OPTEE, initialize address space with tos_fw addr */
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ if (pager_mem_params != NULL) {
+ pager_mem_params->image_info.image_base =
+ config_info->config_addr;
+ pager_mem_params->image_info.image_max_size =
+ config_info->config_max_size;
+ }
+ break;
+
+ case BL33_IMAGE_ID:
+ bl_mem_params->ep_info.pc = config_info->config_addr;
+ break;
+
+ case HW_CONFIG_ID:
+ case SOC_FW_CONFIG_ID:
+ break;
+
default:
return -EINVAL;
}
@@ -300,8 +359,32 @@
* with BL31 binary, no other data should be read from BL2 DT.
*/
+ break;
+
+ case BL32_IMAGE_ID:
+ if ((bl_mem_params->image_info.image_base != 0UL) &&
+ (optee_header_is_valid(bl_mem_params->image_info.image_base))) {
+ /* BL32 is OP-TEE header */
+ bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ assert(pager_mem_params != NULL);
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ NULL);
+ if (err != 0) {
+ ERROR("OPTEE header parse error.\n");
+ panic();
+ }
+
+ /* Set optee boot info from parsed header data */
+ bl_mem_params->ep_info.args.arg0 = 0U; /* Unused */
+ bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */
+ bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */
+ }
break;
+ case BL33_IMAGE_ID:
default:
/* Do nothing in default case */
break;
diff --git a/plat/st/stm32mp2/bl31_plat_setup.c b/plat/st/stm32mp2/bl31_plat_setup.c
index dbf1371..586bfe8 100644
--- a/plat/st/stm32mp2/bl31_plat_setup.c
+++ b/plat/st/stm32mp2/bl31_plat_setup.c
@@ -8,12 +8,16 @@
#include <stdint.h>
#include <common/bl_common.h>
+#include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32_console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <platform_def.h>
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
@@ -31,6 +35,12 @@
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
+ /*
+ * Map soc_fw_config device tree with secure property, i.e. default region.
+ * DDR region definitions will be finalized at BL32 level.
+ */
+ mmap_add_region(arg1, arg1, STM32MP_SOC_FW_CONFIG_MAX_SIZE, MT_RO_DATA | MT_SECURE);
+
#if USE_COHERENT_MEM
/* Map coherent memory */
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
@@ -40,6 +50,20 @@
configure_mmu();
+ ret = dt_open_and_check(arg1);
+ if (ret < 0) {
+ EARLY_ERROR("%s: failed to open DT (%d)\n", __func__, ret);
+ panic();
+ }
+
+ ret = stm32mp2_clk_init();
+ if (ret < 0) {
+ EARLY_ERROR("%s: failed init clocks (%d)\n", __func__, ret);
+ panic();
+ }
+
+ (void)stm32mp_uart_console_setup();
+
/*
* Map upper SYSRAM where bl_params_t are stored in BL2
*/
@@ -60,6 +84,31 @@
bl_params_node_t *bl_params = params_from_bl2->head;
while (bl_params != NULL) {
+ /*
+ * Copy BL33 entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
+ if (bl_params->image_id == BL33_IMAGE_ID) {
+ bl33_image_ep_info = *bl_params->ep_info;
+ /*
+ * Check if hw_configuration is given to BL32 and
+ * share it to BL33
+ */
+ if (arg2 != 0U) {
+ bl33_image_ep_info.args.arg0 = 0U;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = arg2;
+ }
+ }
+
+ if (bl_params->image_id == BL32_IMAGE_ID) {
+ bl32_image_ep_info = *bl_params->ep_info;
+
+ if (arg2 != 0U) {
+ bl32_image_ep_info.args.arg3 = arg2;
+ }
+ }
+
bl_params = bl_params->next_params_info;
}
@@ -73,6 +122,9 @@
void bl31_plat_arch_setup(void)
{
+ generic_delay_timer_init();
+
+ stm32mp_gic_init();
}
void bl31_platform_setup(void)
@@ -81,5 +133,27 @@
entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
{
- return NULL;
+ entry_point_info_t *next_image_info = NULL;
+
+ assert(sec_state_is_valid(type));
+
+ switch (type) {
+ case NON_SECURE:
+ next_image_info = &bl33_image_ep_info;
+ break;
+
+ case SECURE:
+ next_image_info = &bl32_image_ep_info;
+ break;
+
+ default:
+ break;
+ }
+
+ /* None of the next images on ST platforms can have 0x0 as the entrypoint */
+ if ((next_image_info == NULL) || (next_image_info->pc == 0UL)) {
+ return NULL;
+ }
+
+ return next_image_info;
}
diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h
index 89ca032..b98b56d 100644
--- a/plat/st/stm32mp2/include/platform_def.h
+++ b/plat/st/stm32mp2/include/platform_def.h
@@ -74,7 +74,7 @@
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE 0
-#define BL31_LIMIT STM32MP_BL31_SIZE
+#define BL31_LIMIT (STM32MP_SEC_SYSRAM_SIZE / 2)
/*******************************************************************************
* BL33 specific defines.
diff --git a/plat/st/stm32mp2/include/stm32mp2_private.h b/plat/st/stm32mp2/include/stm32mp2_private.h
index 2ab5001..4bb8c52 100644
--- a/plat/st/stm32mp2/include/stm32mp2_private.h
+++ b/plat/st/stm32mp2/include/stm32mp2_private.h
@@ -11,6 +11,9 @@
uint32_t stm32mp_syscfg_get_chip_dev_id(void);
+/* Get DDRDBG peripheral IO memory base address */
+uintptr_t stm32_ddrdbg_get_base(void);
+
/* Wrappers for OTP / BSEC functions */
static inline uint32_t stm32_otp_probe(void)
{
diff --git a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
index f845560..2513180 100644
--- a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
@@ -67,8 +67,85 @@
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
+ .next_handoff_image_id = BL32_IMAGE_ID,
+ },
+
+ /* Fill SoC FW config related information */
+ {
+ .image_id = SOC_FW_CONFIG_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+ /* Fill BL32 related information */
+ {
+ .image_id = BL32_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+
+ /* Fill BL32 external 1 image related information */
+ {
+ .image_id = BL32_EXTRA1_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
.next_handoff_image_id = INVALID_IMAGE_ID,
},
+
+ /* Fill HW_CONFIG related information if it exists */
+ {
+ .image_id = HW_CONFIG_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ NON_SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ NON_SECURE | EXECUTABLE),
+
+ .ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ }
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/st/stm32mp2/plat_ddr.c b/plat/st/stm32mp2/plat_ddr.c
new file mode 100644
index 0000000..5302e45
--- /dev/null
+++ b/plat/st/stm32mp2/plat_ddr.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdint.h>
+
+#include <common/fdt_wrappers.h>
+
+#include <drivers/delay_timer.h>
+#include <drivers/st/regulator.h>
+#include <drivers/st/stm32mp_ddr.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#if STM32MP_DDR3_TYPE
+struct ddr3_supply {
+ struct rdev *vdd;
+ struct rdev *vref;
+ struct rdev *vtt;
+};
+
+static void ddr3_supply_read(void *fdt, int node, struct ddr3_supply *supply)
+{
+ supply->vdd = regulator_get_by_supply_name(fdt, node, "vdd");
+ supply->vref = regulator_get_by_supply_name(fdt, node, "vref");
+ supply->vtt = regulator_get_by_supply_name(fdt, node, "vtt");
+}
+
+static int ddr_power_init(void *fdt, int node)
+{
+ int status;
+ struct ddr3_supply supply;
+
+ ddr3_supply_read(fdt, node, &supply);
+ if ((supply.vdd == NULL) || (supply.vref == NULL) || (supply.vtt == NULL)) {
+ return -ENOENT;
+ }
+
+ /*
+ * DDR3 power on sequence is:
+ * enable VREF_DDR, VTT_DDR, VPP_DDR
+ */
+ status = regulator_set_min_voltage(supply.vdd);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vdd);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vref);
+ if (status != 0) {
+ return status;
+ }
+
+ return regulator_enable(supply.vtt);
+}
+#endif /* STM32MP_DDR3_TYPE */
+
+#if STM32MP_DDR4_TYPE
+struct ddr4_supply {
+ struct rdev *vdd;
+ struct rdev *vref;
+ struct rdev *vtt;
+ struct rdev *vpp;
+};
+
+static void ddr4_supply_read(void *fdt, int node, struct ddr4_supply *supply)
+{
+ supply->vpp = regulator_get_by_supply_name(fdt, node, "vpp");
+ supply->vdd = regulator_get_by_supply_name(fdt, node, "vdd");
+ supply->vref = regulator_get_by_supply_name(fdt, node, "vref");
+ supply->vtt = regulator_get_by_supply_name(fdt, node, "vtt");
+}
+
+static int ddr_power_init(void *fdt, int node)
+{
+ int status;
+ struct ddr4_supply supply;
+
+ ddr4_supply_read(fdt, node, &supply);
+ if ((supply.vpp == NULL) || (supply.vdd == NULL) || (supply.vref == NULL) ||
+ (supply.vtt == NULL)) {
+ return -ENOENT;
+ }
+
+ /*
+ * DDR4 power on sequence is:
+ * enable VPP_DDR
+ * enable VREF_DDR, VTT_DDR, VPP_DDR
+ */
+ status = regulator_set_min_voltage(supply.vpp);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_set_min_voltage(supply.vdd);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vpp);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vdd);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vref);
+ if (status != 0) {
+ return status;
+ }
+
+ return regulator_enable(supply.vtt);
+}
+#endif /* STM32MP_DDR4_TYPE */
+
+#if STM32MP_LPDDR4_TYPE
+struct lpddr4_supply {
+ struct rdev *vdd1;
+ struct rdev *vdd2;
+ struct rdev *vddq;
+};
+
+static void lpddr4_supply_read(void *fdt, int node, struct lpddr4_supply *supply)
+{
+ supply->vdd1 = regulator_get_by_supply_name(fdt, node, "vdd1");
+ supply->vdd2 = regulator_get_by_supply_name(fdt, node, "vdd2");
+ supply->vddq = regulator_get_by_supply_name(fdt, node, "vddq");
+}
+
+static int ddr_power_init(void *fdt, int node)
+{
+ int status;
+ struct lpddr4_supply supply;
+
+ lpddr4_supply_read(fdt, node, &supply);
+ if ((supply.vdd1 == NULL) || (supply.vdd2 == NULL) || (supply.vddq == NULL)) {
+ return -ENOENT;
+ }
+
+ /*
+ * LPDDR4 power on sequence is:
+ * enable VDD1_DDR
+ * enable VDD2_DDR
+ * enable VDDQ_DDR
+ */
+ status = regulator_set_min_voltage(supply.vdd1);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_set_min_voltage(supply.vdd2);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_set_min_voltage(supply.vddq);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vdd1);
+ if (status != 0) {
+ return status;
+ }
+
+ status = regulator_enable(supply.vdd2);
+ if (status != 0) {
+ return status;
+ }
+
+ return regulator_enable(supply.vddq);
+}
+#endif /* STM32MP_LPDDR4_TYPE */
+
+int stm32mp_board_ddr_power_init(enum ddr_type ddr_type)
+{
+ void *fdt = NULL;
+ int node;
+
+ VERBOSE("DDR power init, ddr_type = %u\n", ddr_type);
+
+#if STM32MP_DDR3_TYPE
+ assert(ddr_type == STM32MP_DDR3);
+#elif STM32MP_DDR4_TYPE
+ assert(ddr_type == STM32MP_DDR4);
+#elif STM32MP_LPDDR4_TYPE
+ assert(ddr_type == STM32MP_LPDDR4);
+#else
+ ERROR("DDR type (%u) not supported\n", ddr_type);
+ panic();
+#endif
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
+ if (node < 0) {
+ ERROR("%s: Cannot read DDR node in DT\n", __func__);
+ return -EINVAL;
+ }
+
+ return ddr_power_init(fdt, node);
+}
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 32d6235..df1cacd 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -42,11 +42,14 @@
endif
# DDR features
+STM32MP_DDR_DUAL_AXI_PORT := 1
STM32MP_DDR_FIP_IO_STORAGE := 1
# Device tree
BL2_DTSI := stm32mp25-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
+BL31_DTSI := stm32mp25-bl31.dtsi
+FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME)))
# Macros and rules to build TF binary
STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
@@ -55,6 +58,7 @@
STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
+STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME)))
ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
@@ -63,6 +67,8 @@
FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
+# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_IMG,STM32MP_SOC_FW_CONFIG,--soc-fw-config))
ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
# Add the FW_DDR to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
@@ -71,6 +77,7 @@
# Enable flags for C files
$(eval $(call assert_booleans,\
$(sort \
+ STM32MP_DDR_DUAL_AXI_PORT \
STM32MP_DDR_FIP_IO_STORAGE \
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
@@ -92,6 +99,7 @@
PLAT_PARTITION_MAX_ENTRIES \
PLAT_TBBR_IMG_DEF \
STM32_TF_A_COPIES \
+ STM32MP_DDR_DUAL_AXI_PORT \
STM32MP_DDR_FIP_IO_STORAGE \
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
@@ -105,11 +113,18 @@
# Include paths and source files
PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
+PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/
+PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/
PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
+PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
+ drivers/st/pmic/stpmic2.c \
+
+PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c
+
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
@@ -121,7 +136,8 @@
BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
-BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
+BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \
+ plat/st/stm32mp2/plat_ddr.c
ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
@@ -131,7 +147,30 @@
BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
endif
+BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \
+ drivers/st/ddr/stm32mp2_ddr_helpers.c \
+ drivers/st/ddr/stm32mp2_ram.c
+
-BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c
+BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \
+ drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \
+ drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
+
+BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \
+ drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \
+ drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
# BL31 sources
BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
@@ -164,4 +203,11 @@
false; \
fi
+# Create DTB file for BL31
+${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/
+ @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
+ @echo '#include "${BL31_DTSI}"' >> $@
+
+${BUILD_PLAT}/fdts/%-bl31.dtb: ${BUILD_PLAT}/fdts/%-bl31.dts
+
include plat/st/common/common_rules.mk
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index d3290c3..b441502 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -73,6 +73,9 @@
#define STM32MP_SYSRAM_SIZE U(0x00040000)
#define SRAM1_BASE U(0x0E040000)
#define SRAM1_SIZE_FOR_TFA U(0x00010000)
+#define RETRAM_BASE U(0x0E080000)
+#define RETRAM_SIZE U(0x00020000)
+
#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
/* DDR configuration */
@@ -109,10 +112,12 @@
#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
-/* Allocate remaining sysram to BL31 */
+/* Allocate remaining sysram to BL31 Binary only */
#define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
+#define BL31_PROGBITS_LIMIT STM32MP_BL31_SIZE
+
#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
@@ -133,7 +138,11 @@
* MAX_MMAP_REGIONS is usually:
* BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
*/
+#if defined(IMAGE_BL31)
+#define MAX_MMAP_REGIONS 7
+#else
#define MAX_MMAP_REGIONS 6
+#endif
/* DTB initialization value */
#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
@@ -148,6 +157,8 @@
#if STM32MP_DDR_FIP_IO_STORAGE
#define STM32MP_DDR_FW_BASE SRAM1_BASE
+#define STM32MP_DDR_FW_DMEM_OFFSET U(0x400)
+#define STM32MP_DDR_FW_IMEM_OFFSET U(0x800)
#define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
#endif
@@ -159,6 +170,7 @@
#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
STM32MP_BL33_MAX_SIZE)
#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
+#define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */
/*******************************************************************************
* STM32MP2 device/io map related constants (used for MMU)
@@ -374,6 +386,7 @@
* STM32MP RIF
******************************************************************************/
#define RISAB3_BASE U(0x42110000)
+#define RISAB5_BASE U(0x42130000)
/*******************************************************************************
* STM32MP CA35SSC
diff --git a/plat/st/stm32mp2/stm32mp2_private.c b/plat/st/stm32mp2/stm32mp2_private.c
index 99f6be2..5be4c5a 100644
--- a/plat/st/stm32mp2/stm32mp2_private.c
+++ b/plat/st/stm32mp2/stm32mp2_private.c
@@ -71,6 +71,19 @@
enable_mmu_el3(0);
}
+int stm32mp_map_retram(void)
+{
+ return mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE,
+ RETRAM_SIZE,
+ MT_RW | MT_SECURE);
+}
+
+int stm32mp_unmap_retram(void)
+{
+ return mmap_remove_dynamic_region(RETRAM_BASE,
+ RETRAM_SIZE);
+}
+
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
@@ -103,6 +116,33 @@
return CK_BUS_GPIOA + (bank - GPIO_BANK_A);
}
+
+#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
+/*
+ * UART Management
+ */
+static const uintptr_t stm32mp2_uart_addresses[STM32MP_NB_OF_UART] = {
+ USART1_BASE,
+ USART2_BASE,
+ USART3_BASE,
+ UART4_BASE,
+ UART5_BASE,
+ USART6_BASE,
+ UART7_BASE,
+ UART8_BASE,
+ UART9_BASE,
+};
+
+uintptr_t get_uart_address(uint32_t instance_nb)
+{
+ if ((instance_nb == 0U) ||
+ (instance_nb > STM32MP_NB_OF_UART)) {
+ return 0U;
+ }
+
+ return stm32mp2_uart_addresses[instance_nb - 1U];
+}
+#endif
uint32_t stm32mp_get_chip_version(void)
{
@@ -277,7 +317,18 @@
}
}
+bool stm32mp_is_wakeup_from_standby(void)
+{
+ /* TODO add source code to determine if platform is waking up from standby mode */
+ return false;
+}
+
uintptr_t stm32_get_bkpr_boot_mode_addr(void)
{
return tamp_bkpr(BKPR_BOOT_MODE);
}
+
+uintptr_t stm32_ddrdbg_get_base(void)
+{
+ return DDRDBG_BASE;
+}
diff --git a/plat/xilinx/common/include/plat_console.h b/plat/xilinx/common/include/plat_console.h
index 0f8320e..fa6021d 100644
--- a/plat/xilinx/common/include/plat_console.h
+++ b/plat/xilinx/common/include/plat_console.h
@@ -8,18 +8,30 @@
#define PLAT_DT_UART_H
#define DT_UART_DCC_COMPAT "arm,dcc"
+#define DT_UART_CAD_COMPAT "xlnx,zynqmp-uart"
+#define DT_UART_PL011_COMPAT "arm,pl011"
-#if defined(PLAT_zynqmp)
-#define DT_UART_COMPAT "xlnx,zynqmp-uart"
-#else
-#define DT_UART_COMPAT "arm,pl011"
-#endif
+/* Default console type is either CADENCE0 or CADENCE1 or PL011_0 or PL011_1
+ * Debug console type is DCC
+ */
+#define CONSOLE_NONE 0
+#define CONSOLE_CDNS 1
+#define CONSOLE_PL011 2
+#define CONSOLE_DCC 3
+
+typedef struct console_hd {
+ uint32_t clk;
+ uint32_t baud_rate;
+ uintptr_t base;
+ uint32_t console_scope;
+ uint8_t console_type;
+} console_holder;
typedef struct dt_uart_info_s {
char compatible[30];
uintptr_t base;
uint32_t baud_rate;
- int32_t status;
+ uint8_t console_type;
} dt_uart_info_t;
void setup_console(void);
diff --git a/plat/xilinx/common/include/plat_xfer_list.h b/plat/xilinx/common/include/plat_xfer_list.h
new file mode 100644
index 0000000..cc79a2c
--- /dev/null
+++ b/plat/xilinx/common/include/plat_xfer_list.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_XFER_LIST_H
+#define PLAT_XFER_LIST_H
+
+#include <lib/transfer_list.h>
+
+int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
+ entry_point_info_t *bl33);
+
+#endif /* PLAT_XFER_LIST_H */
diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index 434cd88..0ea51f0 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -70,6 +70,9 @@
uint64_t x3, uint64_t x4, const void *cookie,
void *handle, uint64_t flags)
{
+ (void) x4;
+ (void) flags;
+ (void) cookie;
int32_t ret;
uint32_t ipi_local_id;
uint32_t ipi_remote_id;
@@ -103,11 +106,11 @@
SMC_RET1(handle, 0);
case IPI_MAILBOX_STATUS_ENQUIRY:
{
- int32_t disable_irq;
+ int32_t disable_interrupt;
- disable_irq = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0;
+ disable_interrupt = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0;
ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
- if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_irq)
+ if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_interrupt)
ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
SMC_RET1(handle, ret);
}
@@ -121,11 +124,11 @@
}
case IPI_MAILBOX_ACK:
{
- int32_t enable_irq;
+ int32_t enable_interrupt;
- enable_irq = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0;
+ enable_interrupt = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0;
ipi_mb_ack(ipi_local_id, ipi_remote_id);
- if (enable_irq)
+ if (enable_interrupt)
ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);
SMC_RET1(handle, 0);
}
diff --git a/plat/xilinx/common/plat_console.c b/plat/xilinx/common/plat_console.c
index b84912a..681226f 100644
--- a/plat/xilinx/common/plat_console.c
+++ b/plat/xilinx/common/plat_console.c
@@ -23,9 +23,64 @@
#include <platform_def.h>
#include <plat_private.h>
-static console_t console;
+#if !(CONSOLE_IS(none))
+static console_t boot_console;
+static console_holder boot_hd_console;
+#if defined(CONSOLE_RUNTIME)
+static console_t runtime_console;
+static console_holder rt_hd_console;
+#endif
+
+#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
+ (!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
+ !IS_TFA_IN_OCM(BL31_BASE)))
+static dt_uart_info_t dt_uart_info;
+#endif
+
+/**
+ * register_console() - Registers the uart with console list.
+ * @consoleh: Console holder structure with UART base address,
+ * UART clock, UART buad rate, flags & console type
+ * @console: Pointer to the console information structure.
+ */
+static void register_console(const console_holder *consoleh, console_t *console)
+{
+ int32_t rc = 0;
+
+ switch (consoleh->console_type) {
+#if defined(PLAT_zynqmp)
+ case CONSOLE_CDNS:
+ rc = console_cdns_register(consoleh->base,
+ consoleh->clk,
+ consoleh->baud_rate,
+ console);
+ break;
+#else
+ case CONSOLE_PL011:
+ rc = console_pl011_register(consoleh->base,
+ consoleh->clk,
+ consoleh->baud_rate,
+ console);
+ break;
+#endif
+ case CONSOLE_DCC:
+ rc = console_dcc_register(console);
+ break;
+ default:
+ INFO("Invalid console type\n");
+ break;
+ }
-#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
+ if (rc == 0) {
+ panic();
+ }
+
+ console_set_scope(console, consoleh->console_scope);
+}
+
+#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
+ (!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
+ !IS_TFA_IN_OCM(BL31_BASE)))
/**
* get_baudrate() - Get the baudrate form DTB.
* @dtb: Address of the Device Tree Blob (DTB).
@@ -103,34 +158,56 @@
* @node: Node address in the device tree.
* @dtb: Address of the Device Tree Blob(DTB).
*
- * Return: On success, it returns 1; on failure, it returns an 0.
+ * Return: On success, it returns 0; on failure, it returns -1 or -FDT_ERR_NOTFOUND.
*/
-static uint32_t fdt_add_uart_info(dt_uart_info_t *info, int node, void *dtb)
+static int32_t fdt_add_uart_info(dt_uart_info_t *info, int node, void *dtb)
{
uintptr_t base_addr;
const char *com;
int32_t ret = 0;
+ uint32_t status;
com = fdt_getprop(dtb, node, "compatible", NULL);
if (com != NULL) {
strlcpy(info->compatible, com, sizeof(info->compatible));
} else {
ERROR("Compatible property not found in DTB node\n");
- ret = -FDT_ERR_NOTFOUND;
+ ret = -FDT_ERR_NOTFOUND;
goto error;
}
- ret = fdt_get_reg_props_by_index(dtb, node, 0, &base_addr, NULL);
- if (ret >= 0) {
- info->base = base_addr;
- } else {
- ERROR("Failed to retrieve base address. Error code: %d\n", ret);
- ret = -FDT_ERR_NOTFOUND;
+ status = get_node_status(dtb, node);
+ if (status == 0) {
+ ERROR("Uart node is disabled in DTB\n");
+ ret = -FDT_ERR_NOTFOUND;
goto error;
}
+ if (strncmp(info->compatible, DT_UART_DCC_COMPAT, strlen(DT_UART_DCC_COMPAT)) != 0) {
+ ret = fdt_get_reg_props_by_index(dtb, node, 0, &base_addr, NULL);
+ if (ret >= 0) {
+ info->base = base_addr;
+ } else {
+ ERROR("Failed to retrieve base address. Error code: %d\n", ret);
+ ret = -FDT_ERR_NOTFOUND;
+ goto error;
+ }
+
- info->status = get_node_status(dtb, node);
- info->baud_rate = get_baudrate(dtb);
+ info->baud_rate = get_baudrate(dtb);
+
+ if (strncmp(info->compatible, DT_UART_CAD_COMPAT,
+ strlen(DT_UART_CAD_COMPAT)) == 0) {
+ info->console_type = CONSOLE_CDNS;
+ } else if (strncmp(info->compatible, DT_UART_PL011_COMPAT,
+ strlen(DT_UART_PL011_COMPAT)) == 0) {
+ info->console_type = CONSOLE_PL011;
+ } else {
+ ERROR("Incompatible uart node in DTB\n");
+ ret = -FDT_ERR_NOTFOUND;
+ }
+ } else {
+ info->console_type = CONSOLE_DCC;
+ }
error:
return ret;
@@ -150,194 +227,87 @@
ret = is_valid_dtb(dtb);
if (ret < 0) {
ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
- ret = -FDT_ERR_NOTFOUND;
goto error;
}
node = fdt_get_stdout_node_offset(dtb);
if (node < 0) {
ERROR("DT get stdout node failed : %d\n", node);
- ret = -FDT_ERR_NOTFOUND;
goto error;
}
ret = fdt_add_uart_info(info, node, dtb);
if (ret < 0) {
ERROR("Failed to add DT UART info: %d\n", ret);
- ret = -FDT_ERR_NOTFOUND;
- goto error;
- }
-
-error:
- return ret;
-}
-
-/**
- * check_fdt_uart_info() - Check early uart info with DTB uart info.
- * @info: Pointer to the UART information structure.
- *
- * Return: On success, it returns 0; on failure, it returns an error+reason.
- */
-static int32_t check_fdt_uart_info(dt_uart_info_t *info)
-{
- int32_t ret = 0;
-
- if (info->status == 0) {
- ret = -ENODEV;
- goto error;
- }
-
- if ((info->base == console.base) &&
- (info->baud_rate == UART_BAUDRATE) && !CONSOLE_IS(dcc)) {
- ret = -ENODEV;
goto error;
}
error:
return ret;
}
-
-/**
- * console_boot_end() - Unregister the console_t instance form the console list.
- * @boot_console: Pointer to the console information structure.
- */
-static void console_boot_end(console_t *boot_console)
-{
- if (CONSOLE_IS(dcc)) {
- console_dcc_unregister();
- } else {
- console_flush();
- (void)console_unregister(boot_console);
- }
-}
-
-/**
- * setup_runtime_console() - Registers the runtime uart with console list.
- * @clock: UART clock.
- * @info: Pointer to the UART information structure.
- */
-static void setup_runtime_console(uint32_t clock, dt_uart_info_t *info)
-{
- static console_t bl31_runtime_console;
- int32_t rc;
-
-#if defined(PLAT_zynqmp)
- rc = console_cdns_register(info->base,
- clock,
- info->baud_rate,
- &bl31_runtime_console);
-#else
- rc = console_pl011_register(info->base,
- clock,
- info->baud_rate,
- &bl31_runtime_console);
#endif
- if (rc == 0) {
- panic();
- }
-
- console_set_scope(&bl31_runtime_console,
- CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME |
- CONSOLE_FLAG_CRASH);
-}
-
-/**
- * runtime_console_init() - Initializes the run time console information.
- * @uart_info: Pointer to the UART information structure.
- * @bl31_boot_console: Pointer to the console information structure.
- * @clock: UART clock.
- *
- * Return: On success, it returns 0; on failure, it returns an error+reason;
- */
-static int32_t runtime_console_init(dt_uart_info_t *uart_info,
- console_t *bl31_boot_console,
- uint32_t clock)
+void setup_console(void)
{
- int32_t rc = 0;
+ /* This is hardcoded console setup just in case that DTB console fails */
+ boot_hd_console.base = (uintptr_t)UART_BASE;
+ boot_hd_console.baud_rate = (uint32_t)UART_BAUDRATE;
+ boot_hd_console.clk = get_uart_clk();
+ boot_hd_console.console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH;
+ boot_hd_console.console_type = UART_TYPE;
- /* Parse UART information from Device Tree Blob (DTB) */
- rc = fdt_get_uart_info(uart_info);
- if (rc < 0) {
- rc = -FDT_ERR_NOTFOUND;
- goto error;
- }
+ /* For DT code decoding uncomment console registration below */
+ /* register_console(&boot_hd_console, &boot_console); */
- if (strncmp(uart_info->compatible, DT_UART_COMPAT,
- strlen(DT_UART_COMPAT)) == 0) {
-
- if (check_fdt_uart_info(uart_info) == 0) {
- setup_runtime_console(clock, uart_info);
- console_boot_end(bl31_boot_console);
- INFO("Runtime console setup\n");
- } else {
- INFO("Early console and DTB console are same\n");
+#if ((CONSOLE_IS(dtb) || RT_CONSOLE_IS(dtb)) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
+ (!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
+ !IS_TFA_IN_OCM(BL31_BASE)))
+ /* Parse DTB console for UART information */
+ if (fdt_get_uart_info(&dt_uart_info) == 0) {
+ if (CONSOLE_IS(dtb)) {
+ boot_hd_console.base = dt_uart_info.base;
+ boot_hd_console.baud_rate = dt_uart_info.baud_rate;
+ boot_hd_console.console_type = dt_uart_info.console_type;
}
- } else if (strncmp(uart_info->compatible, DT_UART_DCC_COMPAT,
- strlen(DT_UART_DCC_COMPAT)) == 0) {
- rc = console_dcc_register();
- if (rc == 0) {
- panic();
- }
- console_boot_end(bl31_boot_console);
} else {
- WARN("BL31: No console device found in DT.\n");
+ ERROR("Failed to initialize DT console or console node is disabled\n");
}
-
-error:
- return rc;
-}
#endif
-void setup_console(void)
-{
- int32_t rc;
- uint32_t uart_clk = get_uart_clk();
+ /* Initialize the boot console */
+ register_console(&boot_hd_console, &boot_console);
-#if defined(PLAT_zynqmp)
- if (CONSOLE_IS(cadence) || (CONSOLE_IS(cadence1))) {
- rc = console_cdns_register(UART_BASE,
- uart_clk,
- UART_BAUDRATE,
- &console);
- if (rc == 0) {
- panic();
- }
+ INFO("BL31: Early console setup\n");
- console_set_scope(&console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
- }
+#ifdef CONSOLE_RUNTIME
+#if (RT_CONSOLE_IS(dtb) && defined(XILINX_OF_BOARD_DTB_ADDR)) && \
+ (!defined(PLAT_zynqmp) || (defined(PLAT_zynqmp) && \
+ !IS_TFA_IN_OCM(BL31_BASE)))
+ rt_hd_console.base = dt_uart_info.base;
+ rt_hd_console.baud_rate = dt_uart_info.baud_rate;
+ rt_hd_console.console_type = dt_uart_info.console_type;
#else
- if (CONSOLE_IS(pl011) || (CONSOLE_IS(pl011_1))) {
- /* Initialize the console to provide early debug support */
- rc = console_pl011_register((uint32_t)UART_BASE,
- uart_clk,
- (uint32_t)UART_BAUDRATE,
- &console);
- if (rc == 0) {
- panic();
- }
-
- console_set_scope(&console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
- }
+ rt_hd_console.base = (uintptr_t)RT_UART_BASE;
+ rt_hd_console.baud_rate = (uint32_t)UART_BAUDRATE;
+ rt_hd_console.console_type = RT_UART_TYPE;
#endif
- if (CONSOLE_IS(dcc)) {
- /* Initialize the dcc console for debug */
- rc = console_dcc_register();
- if (rc == 0) {
- panic();
- }
- }
- INFO("BL31: Early console setup\n");
-#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
- static dt_uart_info_t uart_info = {0};
+ if ((rt_hd_console.console_type == boot_hd_console.console_type) &&
+ (rt_hd_console.base == boot_hd_console.base)) {
+ console_set_scope(&boot_console,
+ CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | CONSOLE_FLAG_RUNTIME);
+ INFO("Successfully initialized runtime console\n");
+ } else {
+ rt_hd_console.clk = get_uart_clk();
+ rt_hd_console.console_scope = CONSOLE_FLAG_RUNTIME;
- /* Initialize the runtime console using UART information from the DTB */
- rc = runtime_console_init(&uart_info, &console, uart_clk);
- if (rc < 0) {
- ERROR("Failed to initialize runtime console: %d\n", rc);
+ register_console(&rt_hd_console, &runtime_console);
+ INFO("Successfully initialized new runtime console\n");
}
#endif
}
+#else
+void setup_console(void)
+{
+}
+#endif
diff --git a/plat/xilinx/common/plat_xfer_list.c b/plat/xilinx/common/plat_xfer_list.c
new file mode 100644
index 0000000..eae7ce4
--- /dev/null
+++ b/plat/xilinx/common/plat_xfer_list.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stddef.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/transfer_list.h>
+
+/*
+ * FIXME: This address should come from firmware before TF-A runs
+ * Having this to make sure the transfer list functionality works
+ */
+#define FW_HANDOFF_BASE U(0x1200000)
+#define FW_HANDOFF_SIZE U(0x600000)
+
+static struct transfer_list_header *tl_hdr;
+
+int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
+ entry_point_info_t *bl33)
+{
+ struct transfer_list_entry *te = NULL;
+ struct entry_point_info *ep;
+ int32_t ret;
+
+ tl_hdr = (struct transfer_list_header *)FW_HANDOFF_BASE;
+ ret = transfer_list_check_header(tl_hdr);
+ if ((ret == TL_OPS_ALL) || (ret == TL_OPS_RO)) {
+ transfer_list_dump(tl_hdr);
+ while ((te = transfer_list_next(tl_hdr, te)) != NULL) {
+ ep = transfer_list_entry_data(te);
+ if (te->tag_id == TL_TAG_EXEC_EP_INFO64) {
+ switch (GET_SECURITY_STATE(ep->h.attr)) {
+ case NON_SECURE:
+ *bl33 = *ep;
+ continue;
+ case SECURE:
+ *bl32 = *ep;
+ continue;
+ default:
+ ERROR("Unrecognized Image Security State %lu\n",
+ GET_SECURITY_STATE(ep->h.attr));
+ ret = TL_OPS_NON;
+ }
+ }
+ }
+ }
+ return ret;
+}
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index 193c5dc..861c5b3 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -79,6 +79,10 @@
static uint64_t cpu_pwrdwn_req_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
+ (void)id;
+ (void)flags;
+ (void)handle;
+ (void)cookie;
uint32_t cpu_id = plat_my_core_pos();
VERBOSE("Powering down CPU %d\n", cpu_id);
@@ -123,6 +127,9 @@
static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
void *cookie)
{
+ (void)flags;
+ (void)handle;
+ (void)cookie;
uint32_t payload[4] = {0};
enum pm_ret_status ret;
int ipi_status, i;
@@ -546,6 +553,7 @@
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle, uint64_t flags)
{
+ (void)cookie;
uintptr_t ret;
uint32_t pm_arg[PAYLOAD_ARG_CNT] = {0};
uint32_t security_flag = NON_SECURE_FLAG;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 57377a9..58589ad 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -69,6 +69,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
uint64_t tfa_handoff_addr;
uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
enum pm_ret_status ret_status;
@@ -171,6 +175,7 @@
static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
{
+ (void)id;
uint32_t intr_id;
uint32_t i;
interrupt_type_handler_t handler = NULL;
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index c50df7e..3a1c127 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -18,13 +18,24 @@
/* number of interrupt handlers. increase as required */
#define MAX_INTR_EL3 2
/* List all consoles */
+#define VERSAL_CONSOLE_ID_none 0
#define VERSAL_CONSOLE_ID_pl011 1
#define VERSAL_CONSOLE_ID_pl011_0 1
#define VERSAL_CONSOLE_ID_pl011_1 2
#define VERSAL_CONSOLE_ID_dcc 3
+#define VERSAL_CONSOLE_ID_dtb 4
#define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
+/* Runtime console */
+#define RT_CONSOLE_ID_pl011 1
+#define RT_CONSOLE_ID_pl011_0 1
+#define RT_CONSOLE_ID_pl011_1 2
+#define RT_CONSOLE_ID_dcc 3
+#define RT_CONSOLE_ID_dtb 4
+
+#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
+
/* List of platforms */
#define VERSAL_SILICON U(0)
#define VERSAL_SPP U(1)
@@ -63,14 +74,37 @@
#define VERSAL_UART0_BASE 0xFF000000
#define VERSAL_UART1_BASE 0xFF010000
-#if CONSOLE_IS(pl011) || CONSOLE_IS(dcc)
+#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
# define UART_BASE VERSAL_UART0_BASE
+# define UART_TYPE CONSOLE_PL011
#elif CONSOLE_IS(pl011_1)
# define UART_BASE VERSAL_UART1_BASE
+# define UART_TYPE CONSOLE_PL011
+#elif CONSOLE_IS(dcc)
+# define UART_BASE 0x0
+# define UART_TYPE CONSOLE_DCC
+#elif CONSOLE_IS(none)
+# define UART_TYPE CONSOLE_NONE
#else
# error "invalid VERSAL_CONSOLE"
#endif
+/* Runtime console */
+#if defined(CONSOLE_RUNTIME)
+#if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb)
+# define RT_UART_BASE VERSAL_UART0_BASE
+# define RT_UART_TYPE CONSOLE_PL011
+#elif RT_CONSOLE_IS(pl011_1)
+# define RT_UART_BASE VERSAL_UART1_BASE
+# define RT_UART_TYPE CONSOLE_PL011
+#elif RT_CONSOLE_IS(dcc)
+# define RT_UART_BASE 0x0
+# define RT_UART_TYPE CONSOLE_DCC
+#else
+# error "invalid CONSOLE_RUNTIME"
+#endif
+#endif
+
/*******************************************************************************
* Platform related constants
******************************************************************************/
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 74c5bf3..a299d14 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -250,7 +250,7 @@
uint32_t pstate = psci_get_pstate_type(power_state);
- assert(req_state);
+ assert(req_state != NULL);
/* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY) {
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 6cc28e1..7c15be0 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -22,7 +22,7 @@
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
ifndef VERSAL_ATF_MEM_SIZE
- $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
+ $(error "VERSAL_ATF_MEM_BASE defined without VERSAL_ATF_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
@@ -35,7 +35,7 @@
$(eval $(call add_define,VERSAL_BL32_MEM_BASE))
ifndef VERSAL_BL32_MEM_SIZE
- $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
+ $(error "VERSAL_BL32_MEM_BASE defined without VERSAL_BL32_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
endif
@@ -85,13 +85,27 @@
${XLAT_TABLES_LIB_SRCS}
VERSAL_CONSOLE ?= pl011
-ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
+ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none))
else
$(error "Please define VERSAL_CONSOLE")
endif
$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
+# Runtime console in default console in DEBUG build
+ifeq ($(DEBUG), 1)
+CONSOLE_RUNTIME ?= pl011
+endif
+
+# Runtime console
+ifdef CONSOLE_RUNTIME
+ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb))
+$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
+else
+$(error "Please define CONSOLE_RUNTIME")
+endif
+endif
+
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a72.S \
common/fdt_wrappers.c \
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index ccbfe77..3e44153 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -155,6 +155,9 @@
case 74:
dev_idx = XPM_NODEIDX_DEV_USB_0;
break;
+ case 122:
+ dev_idx = XPM_NODEIDX_DEV_GPIO_PMC;
+ break;
case 126:
case 127:
dev_idx = XPM_NODEIDX_DEV_SDIO_0;
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 5af2b1d..ebde49f 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -82,6 +82,11 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
+
#if !(TFA_NO_PM)
uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0};
uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index e7d234b..5caf376 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -15,13 +15,24 @@
#define MAX_INTR_EL3 2
/* List all consoles */
+#define VERSAL_NET_CONSOLE_ID_none U(0)
#define VERSAL_NET_CONSOLE_ID_pl011 U(1)
#define VERSAL_NET_CONSOLE_ID_pl011_0 U(1)
#define VERSAL_NET_CONSOLE_ID_pl011_1 U(2)
#define VERSAL_NET_CONSOLE_ID_dcc U(3)
+#define VERSAL_NET_CONSOLE_ID_dtb U(4)
#define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE)
+/* Runtime console */
+#define RT_CONSOLE_ID_pl011 1
+#define RT_CONSOLE_ID_pl011_0 1
+#define RT_CONSOLE_ID_pl011_1 2
+#define RT_CONSOLE_ID_dcc 3
+#define RT_CONSOLE_ID_dtb 4
+
+#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
+
/* List all platforms */
#define VERSAL_NET_SILICON U(0)
#define VERSAL_NET_SPP U(1)
@@ -138,11 +149,35 @@
#define UART_BAUDRATE 115200
-#if CONSOLE_IS(pl011_1)
-#define UART_BASE VERSAL_NET_UART1_BASE
+#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
+#define UART_BASE VERSAL_NET_UART0_BASE
+# define UART_TYPE CONSOLE_PL011
+#elif CONSOLE_IS(pl011_1)
+#define UART_BASE VERSAL_NET_UART1_BASE
+# define UART_TYPE CONSOLE_PL011
+#elif CONSOLE_IS(dcc)
+# define UART_BASE 0x0
+# define UART_TYPE CONSOLE_DCC
+#elif CONSOLE_IS(none)
+# define UART_TYPE CONSOLE_NONE
+#else
+# error "invalid VERSAL_NET_CONSOLE"
+#endif
+
+/* Runtime console */
+#if defined(CONSOLE_RUNTIME)
+#if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb)
+# define RT_UART_BASE VERSAL_NET_UART0_BASE
+# define RT_UART_TYPE CONSOLE_PL011
+#elif RT_CONSOLE_IS(pl011_1)
+# define RT_UART_BASE VERSAL_NET_UART1_BASE
+# define RT_UART_TYPE CONSOLE_PL011
+#elif RT_CONSOLE_IS(dcc)
+# define RT_UART_BASE 0x0
+# define RT_UART_TYPE CONSOLE_DCC
#else
-/* Default console is UART0 */
-#define UART_BASE VERSAL_NET_UART0_BASE
+# error "invalid CONSOLE_RUNTIME"
+#endif
#endif
/* Processor core device IDs */
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index fb2005d..7a653d4 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -247,7 +247,7 @@
int32_t pstate = psci_get_pstate_type(power_state);
- assert(req_state);
+ assert(req_state != NULL);
/* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY) {
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index da91abc..9534118 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -34,7 +34,7 @@
$(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
ifndef VERSAL_NET_ATF_MEM_SIZE
- $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
+ $(error "VERSAL_NET_ATF_MEM_BASE defined without VERSAL_NET_ATF_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
@@ -47,7 +47,7 @@
$(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
ifndef VERSAL_NET_BL32_MEM_SIZE
- $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
+ $(error "VERSAL_NET_BL32_MEM_BASE defined without VERSAL_NET_BL32_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
endif
@@ -60,7 +60,7 @@
HW_ASSISTED_COHERENCY := 1
VERSAL_NET_CONSOLE ?= pl011
-ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
+ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none))
else
$(error Please define VERSAL_NET_CONSOLE)
endif
@@ -71,6 +71,20 @@
$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
endif
+# Runtime console in default console in DEBUG build
+ifeq ($(DEBUG), 1)
+CONSOLE_RUNTIME ?= pl011
+endif
+
+# Runtime console
+ifdef CONSOLE_RUNTIME
+ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb))
+$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
+else
+$(error "Please define CONSOLE_RUNTIME")
+endif
+endif
+
# enable assert() for release/debug builds
ENABLE_ASSERTIONS := 1
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 50d4240..ede3a21 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -72,6 +72,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ (void)arg0;
+ (void)arg1;
+ (void)arg2;
+ (void)arg3;
uint64_t tfa_handoff_addr;
setup_console();
diff --git a/plat/xilinx/zynqmp/custom_sip_svc.c b/plat/xilinx/zynqmp/custom_sip_svc.c
index b9664af..c61c92c 100644
--- a/plat/xilinx/zynqmp/custom_sip_svc.c
+++ b/plat/xilinx/zynqmp/custom_sip_svc.c
@@ -12,6 +12,12 @@
uint64_t x3, uint64_t x4, void *cookie,
void *handle, uint64_t flags)
{
+ (void)x1;
+ (void)x2;
+ (void)x3;
+ (void)x4;
+ (void)cookie;
+ (void)flags;
WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index d715ce2..68485cf 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -10,13 +10,24 @@
#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
+#define ZYNQMP_CONSOLE_ID_none 0
#define ZYNQMP_CONSOLE_ID_cadence 1
#define ZYNQMP_CONSOLE_ID_cadence0 1
#define ZYNQMP_CONSOLE_ID_cadence1 2
#define ZYNQMP_CONSOLE_ID_dcc 3
+#define ZYNQMP_CONSOLE_ID_dtb 4
#define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
+/* Runtime console */
+#define RT_CONSOLE_ID_cadence 1
+#define RT_CONSOLE_ID_cadence0 1
+#define RT_CONSOLE_ID_cadence1 2
+#define RT_CONSOLE_ID_dcc 3
+#define RT_CONSOLE_ID_dtb 4
+
+#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
+
/* Default counter frequency */
#define ZYNQMP_DEFAULT_COUNTER_FREQ 0U
@@ -144,14 +155,38 @@
#define ZYNQMP_UART0_BASE U(0xFF000000)
#define ZYNQMP_UART1_BASE U(0xFF010000)
-#if CONSOLE_IS(cadence) || CONSOLE_IS(dcc)
+/* Boot console */
+#if CONSOLE_IS(cadence) || CONSOLE_IS(dtb)
# define UART_BASE ZYNQMP_UART0_BASE
+# define UART_TYPE CONSOLE_CDNS
#elif CONSOLE_IS(cadence1)
# define UART_BASE ZYNQMP_UART1_BASE
+# define UART_TYPE CONSOLE_CDNS
+#elif CONSOLE_IS(dcc)
+# define UART_BASE 0x0
+# define UART_TYPE CONSOLE_DCC
+#elif CONSOLE_IS(none)
+# define UART_TYPE CONSOLE_NONE
#else
# error "invalid ZYNQMP_CONSOLE"
#endif
+/* Runtime console */
+#if defined(CONSOLE_RUNTIME)
+#if RT_CONSOLE_IS(cadence) || RT_CONSOLE_IS(dtb)
+# define RT_UART_BASE ZYNQMP_UART0_BASE
+# define RT_UART_TYPE CONSOLE_CDNS
+#elif RT_CONSOLE_IS(cadence1)
+# define RT_UART_BASE ZYNQMP_UART1_BASE
+# define RT_UART_TYPE CONSOLE_CDNS
+#elif RT_CONSOLE_IS(dcc)
+# define RT_UART_BASE 0x0
+# define RT_UART_TYPE CONSOLE_DCC
+#else
+# error "invalid CONSOLE_RUNTIME"
+#endif
+#endif
+
/* Must be non zero */
#define UART_BAUDRATE 115200
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 22eceb6..5a86658 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -39,7 +39,7 @@
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
ifndef ZYNQMP_ATF_MEM_SIZE
- $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
+ $(error "ZYNQMP_ATF_MEM_BASE defined without ZYNQMP_ATF_MEM_SIZE")
endif
$(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
@@ -56,7 +56,7 @@
$(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
ifndef ZYNQMP_BL32_MEM_SIZE
- $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
+ $(error "ZYNQMP_BL32_MEM_BASE defined without ZYNQMP_BL32_MEM_SIZE")
endif
$(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
endif
@@ -111,12 +111,26 @@
${XLAT_TABLES_LIB_SRCS}
ZYNQMP_CONSOLE ?= cadence
-ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc))
+ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc dtb none))
else
$(error "Please define ZYNQMP_CONSOLE")
endif
$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
+# Runtime console in default console in DEBUG build
+ifeq ($(DEBUG), 1)
+CONSOLE_RUNTIME ?= cadence
+endif
+
+# Runtime console
+ifdef CONSOLE_RUNTIME
+ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},cadence cadence0 cadence1 dcc dtb))
+$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
+else
+$(error "Please define CONSOLE_RUNTIME")
+endif
+endif
+
# Build PM code as a Library
include plat/xilinx/zynqmp/libpm.mk
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 9682e59..5a1e218 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2791,7 +2791,7 @@
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
- if (pll) {
+ if (pll != NULL) {
*node_id = pll->nid;
return PM_RET_SUCCESS;
}
@@ -2883,7 +2883,7 @@
enum pm_ret_status status;
enum pm_pll_mode mode;
- if ((pll == NULL) || !state) {
+ if ((pll == NULL) || (state == NULL)) {
return PM_RET_ERROR_ARGS;
}
@@ -3013,7 +3013,7 @@
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
- if ((pll == NULL) || !mode) {
+ if ((pll == NULL) || (mode == NULL)) {
return PM_RET_ERROR_ARGS;
}
*mode = pll->mode;
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 66f011a..d7c9f24 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -268,6 +268,7 @@
uint32_t state,
uintptr_t address)
{
+ (void)nid;
uint32_t payload[PAYLOAD_ARG_CNT];
uint32_t cpuid = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpuid);
@@ -1149,7 +1150,7 @@
/* First try to handle it as a PLL */
pll = pm_clock_get_pll(clock_id);
- if (pll) {
+ if (pll != NULL) {
return pm_clock_pll_enable(pll);
}
@@ -1174,7 +1175,7 @@
/* First try to handle it as a PLL */
pll = pm_clock_get_pll(clock_id);
- if (pll) {
+ if (pll != NULL) {
return pm_clock_pll_disable(pll);
}
@@ -1202,9 +1203,9 @@
/* First try to handle it as a PLL */
pll = pm_clock_get_pll(clock_id);
- if (pll)
+ if (pll != NULL) {
return pm_clock_pll_get_state(pll, state);
-
+ }
/* Check if clock ID is a valid on-chip clock */
status = pm_clock_id_is_valid(clock_id);
if (status != PM_RET_SUCCESS) {
@@ -1340,7 +1341,7 @@
/* First try to handle it as a PLL */
pll = pm_clock_get_pll_by_related_clk(clock_id);
- if (pll) {
+ if (pll != NULL) {
return pm_clock_pll_set_parent(pll, clock_id, parent_index);
}
@@ -1375,7 +1376,7 @@
/* First try to handle it as a PLL */
pll = pm_clock_get_pll_by_related_clk(clock_id);
- if (pll) {
+ if (pll != NULL) {
return pm_clock_pll_get_parent(pll, clock_id, parent_index);
}
@@ -1514,6 +1515,7 @@
void pm_query_data(enum pm_query_ids qid, uint32_t arg1, uint32_t arg2,
uint32_t arg3, uint32_t *data)
{
+ (void)arg3;
switch (qid) {
case PM_QID_CLOCK_GET_NAME:
pm_clock_get_name(arg1, (char *)data);
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index bf17ea4..65b2426 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -281,6 +281,9 @@
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle, uint64_t flags)
{
+ (void)x4;
+ (void)cookie;
+ (void)flags;
enum pm_ret_status ret;
uint32_t payload[PAYLOAD_ARG_CNT];
diff --git a/poetry.lock b/poetry.lock
index 9b98b18..9a90704 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -27,13 +27,13 @@
[[package]]
name = "babel"
-version = "2.15.0"
+version = "2.16.0"
description = "Internationalization utilities"
optional = false
python-versions = ">=3.8"
files = [
- {file = "Babel-2.15.0-py3-none-any.whl", hash = "sha256:08706bdad8d0a3413266ab61bd6c34d0c28d6e1e7badf40a2cebe67644e2e1fb"},
- {file = "babel-2.15.0.tar.gz", hash = "sha256:8daf0e265d05768bc6c7a314cf1321e9a123afc328cc635c18622a2f30a04413"},
+ {file = "babel-2.16.0-py3-none-any.whl", hash = "sha256:368b5b98b37c06b7daf6696391c3240c938b37767d4584413e8438c5c435fa8b"},
+ {file = "babel-2.16.0.tar.gz", hash = "sha256:d1f3554ca26605fe173f3de0c65f750f5a42f924499bf134de6423582298e316"},
]
[package.dependencies]
@@ -44,13 +44,13 @@
[[package]]
name = "build"
-version = "1.2.1"
+version = "1.2.2"
description = "A simple, correct Python build frontend"
optional = false
python-versions = ">=3.8"
files = [
- {file = "build-1.2.1-py3-none-any.whl", hash = "sha256:75e10f767a433d9a86e50d83f418e83efc18ede923ee5ff7df93b6cb0306c5d4"},
- {file = "build-1.2.1.tar.gz", hash = "sha256:526263f4870c26f26c433545579475377b2b7588b6f1eac76a001e873ae3e19d"},
+ {file = "build-1.2.2-py3-none-any.whl", hash = "sha256:277ccc71619d98afdd841a0e96ac9fe1593b823af481d3b0cea748e8894e0613"},
+ {file = "build-1.2.2.tar.gz", hash = "sha256:119b2fb462adef986483438377a13b2f42064a2a3a4161f24a0cca698a07ac8c"},
]
[package.dependencies]
@@ -68,14 +68,36 @@
virtualenv = ["virtualenv (>=20.0.35)"]
[[package]]
+name = "cachetools"
+version = "5.5.0"
+description = "Extensible memoizing collections and decorators"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "cachetools-5.5.0-py3-none-any.whl", hash = "sha256:02134e8439cdc2ffb62023ce1debca2944c3f289d66bb17ead3ab3dede74b292"},
+ {file = "cachetools-5.5.0.tar.gz", hash = "sha256:2cc24fb4cbe39633fb7badd9db9ca6295d766d9c2995f245725a46715d050f2a"},
+]
+
+[[package]]
name = "certifi"
-version = "2024.7.4"
+version = "2024.8.30"
description = "Python package for providing Mozilla's CA Bundle."
optional = false
python-versions = ">=3.6"
files = [
+ {file = "certifi-2024.8.30-py3-none-any.whl", hash = "sha256:922820b53db7a7257ffbda3f597266d435245903d80737e34f8a45ff3e3230d8"},
+ {file = "certifi-2024.8.30.tar.gz", hash = "sha256:bec941d2aa8195e248a60b31ff9f0558284cf01a52591ceda73ea9afffd69fd9"},
+]
+
+[[package]]
+name = "chardet"
+version = "5.2.0"
+description = "Universal encoding detector for Python 3"
+optional = false
+python-versions = ">=3.7"
+files = [
- {file = "certifi-2024.7.4-py3-none-any.whl", hash = "sha256:c198e21b1289c2ab85ee4e67bb4b4ef3ead0892059901a8d5b622f24a1101e90"},
- {file = "certifi-2024.7.4.tar.gz", hash = "sha256:5a1e7645bc0ec61a09e26c36f6106dd4cf40c6db3a1fb6352b0244e7fb057c7b"},
+ {file = "chardet-5.2.0-py3-none-any.whl", hash = "sha256:e1cf59446890a00105fe7b7912492ea04b6e6f06d4b742b2c788469e34c82970"},
+ {file = "chardet-5.2.0.tar.gz", hash = "sha256:1b3b6ff479a8c414bc3fa2c0852995695c4a026dcd6d0633b2dd092ca39c1cf7"},
]
[[package]]
@@ -237,6 +259,17 @@
url = "tools/cot_dt2c"
[[package]]
+name = "distlib"
+version = "0.3.8"
+description = "Distribution utilities"
+optional = false
+python-versions = "*"
+files = [
+ {file = "distlib-0.3.8-py2.py3-none-any.whl", hash = "sha256:034db59a0b96f8ca18035f36290806a9a6e6bd9d1ff91e45a7f172eb17e51784"},
+ {file = "distlib-0.3.8.tar.gz", hash = "sha256:1530ea13e350031b6312d8580ddb6b27a104275a31106523b8f123787f494f64"},
+]
+
+[[package]]
name = "docutils"
version = "0.18.1"
description = "Docutils -- Python Documentation Utilities"
@@ -247,15 +280,31 @@
{file = "docutils-0.18.1.tar.gz", hash = "sha256:679987caf361a7539d76e584cbeddc311e3aee937877c87346f31debc63e9d06"},
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- {file = "zipp-3.19.2.tar.gz", hash = "sha256:bf1dcf6450f873a13e952a29504887c89e6de7506209e5b1bcc3460135d4de19"},
+ {file = "zipp-3.20.1-py3-none-any.whl", hash = "sha256:9960cd8967c8f85a56f920d5d507274e74f9ff813a0ab8889a5b5be2daf44064"},
+ {file = "zipp-3.20.1.tar.gz", hash = "sha256:c22b14cc4763c5a5b04134207736c107db42e9d3ef2d9779d465f5f1bcba572b"},
]
[package.extras]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)"]
+cover = ["pytest-cov"]
doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-lint"]
-test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-ignore-flaky", "pytest-mypy", "pytest-ruff (>=0.2.1)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-ignore-flaky"]
+type = ["pytest-mypy"]
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "d893034cad02533bc86fb98c7d93a0eac6a755fea5efd553924e4762ed3f1fdb"
+content-hash = "6a6d2fe9390a4d7d1ecf808d5f303f2dc1eeb44736827b706a858046f3eea1db"
diff --git a/pyproject.toml b/pyproject.toml
index f0b3925..f34c3d1 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -15,7 +15,7 @@
[tool.poetry.dependencies]
python = "^3.8"
cot-dt2c = {path = "tools/cot_dt2c", develop = true}
-tlc = {path = "tools/tlc"}
+tlc = {path = "tools/tlc", develop = true}
[tool.poetry.group.docs]
optional = true
diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c
index 53afb17..8d27e96 100644
--- a/services/std_svc/drtm/drtm_main.c
+++ b/services/std_svc/drtm/drtm_main.c
@@ -463,7 +463,7 @@
* is required to avoid / defend against racing with cache evictions
*/
va_mapping_size = ALIGNED_UP((dlme_end - dlme_start), DRTM_PAGE_SIZE);
- rc = mmap_add_dynamic_region_alloc_va(dlme_img_start, &va_mapping, va_mapping_size,
+ rc = mmap_add_dynamic_region_alloc_va(dlme_start, &va_mapping, va_mapping_size,
MT_MEMORY | MT_NS | MT_RO |
MT_SHAREABILITY_ISH);
if (rc != 0) {
@@ -512,10 +512,10 @@
sctlr &= ~(/* Disable DLME's EL MMU, since the existing page-tables are untrusted. */
SCTLR_M_BIT
| SCTLR_EE_BIT /* Little-endian data accesses. */
+ | SCTLR_C_BIT /* disable data caching */
+ | SCTLR_I_BIT /* disable instruction caching */
);
- sctlr |= SCTLR_C_BIT | SCTLR_I_BIT; /* Allow instruction and data caching. */
-
switch (dlme_el) {
case DLME_AT_EL1:
write_sctlr_el1(sctlr);
@@ -655,6 +655,10 @@
drtm_dl_reset_dlme_el_state(dlme_el);
drtm_dl_reset_dlme_context(dlme_el);
+ /*
+ * Setting the Generic Timer frequency is required before launching
+ * DLME and is already done for running CPU during PSCI setup.
+ */
drtm_dl_prepare_eret_to_dlme(&args, dlme_el);
/*
diff --git a/services/std_svc/rmmd/rmmd_attest.c b/services/std_svc/rmmd/rmmd_attest.c
index f73236c..7d4ea70 100644
--- a/services/std_svc/rmmd/rmmd_attest.c
+++ b/services/std_svc/rmmd/rmmd_attest.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +13,8 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include "rmmd_private.h"
-#include <services/rmmd_svc.h>
+#include <services/rmm_el3_token_sign.h>
+#include <smccc_helpers.h>
static spinlock_t lock;
@@ -156,10 +158,110 @@
(unsigned int)ecc_curve);
if (err != 0) {
ERROR("Failed to get attestation key: %d.\n", err);
- err = E_RMM_UNK;
+ err = E_RMM_UNK;
}
spin_unlock(&lock);
return err;
}
+
+static int rmmd_el3_token_sign_push_req(uint64_t buf_pa, uint64_t buf_size)
+{
+ int err;
+
+ err = validate_buffer_params(buf_pa, buf_size);
+ if (err != 0) {
+ return err;
+ }
+
+ if (buf_size < sizeof(struct el3_token_sign_request)) {
+ return E_RMM_INVAL;
+ }
+
+ spin_lock(&lock);
+
+ /* Call platform port to handle attestation toekn signing request. */
+ err = plat_rmmd_el3_token_sign_push_req((struct el3_token_sign_request *)buf_pa);
+
+ spin_unlock(&lock);
+
+ return err;
+}
+
+static int rmmd_el3_token_sign_pull_resp(uint64_t buf_pa, uint64_t buf_size)
+{
+ int err;
+
+ err = validate_buffer_params(buf_pa, buf_size);
+ if (err != 0) {
+ return err;
+ }
+
+
+ if (buf_size < sizeof(struct el3_token_sign_response)) {
+ return E_RMM_INVAL;
+ }
+
+ spin_lock(&lock);
+
+ /* Pull attestation signing response from HES. */
+ err = plat_rmmd_el3_token_sign_pull_resp(
+ (struct el3_token_sign_response *)buf_pa);
+
+ spin_unlock(&lock);
+
+ return err;
+}
+
+static int rmmd_attest_get_attest_pub_key(uint64_t buf_pa, uint64_t *buf_size,
+ uint64_t ecc_curve)
+{
+ int err;
+
+ err = validate_buffer_params(buf_pa, *buf_size);
+ if (err != 0) {
+ return err;
+ }
+
+ if (ecc_curve != ATTEST_KEY_CURVE_ECC_SECP384R1) {
+ ERROR("Invalid ECC curve specified\n");
+ return E_RMM_INVAL;
+ }
+
+ spin_lock(&lock);
+
+ /* Get the Realm attestation public key from platform port. */
+ err = plat_rmmd_el3_token_sign_get_rak_pub(
+ (uintptr_t)buf_pa, buf_size, (unsigned int)ecc_curve);
+
+ spin_unlock(&lock);
+ if (err != 0) {
+ ERROR("Failed to get attestation public key from HES: %d.\n",
+ err);
+ err = E_RMM_UNK;
+ }
+
+
+ return err;
+}
+
+uint64_t rmmd_el3_token_sign(void *handle, uint64_t opcode, uint64_t x2,
+ uint64_t x3, uint64_t x4)
+{
+ int ret;
+
+ switch (opcode) {
+ case RMM_EL3_TOKEN_SIGN_PUSH_REQ_OP:
+ ret = rmmd_el3_token_sign_push_req(x2, x3);
+ SMC_RET1(handle, ret);
+ case RMM_EL3_TOKEN_SIGN_PULL_RESP_OP:
+ ret = rmmd_el3_token_sign_pull_resp(x2, x3);
+ SMC_RET1(handle, ret);
+ case RMM_EL3_TOKEN_SIGN_GET_RAK_PUB_OP:
+ ret = rmmd_attest_get_attest_pub_key(x2, &x3, x4);
+ SMC_RET2(handle, ret, x3);
+ default:
+ SMC_RET1(handle, SMC_UNK);
+ }
+}
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 153bb01..d063ea3 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -441,6 +441,21 @@
return ret;
}
+static int rmm_el3_ifc_get_feat_register(uint64_t feat_reg_idx,
+ uint64_t *feat_reg)
+{
+ if (feat_reg_idx != RMM_EL3_FEAT_REG_0_IDX) {
+ ERROR("RMMD: Failed to get feature register %ld\n", feat_reg_idx);
+ return E_RMM_INVAL;
+ }
+
+ *feat_reg = 0UL;
+#if RMMD_ENABLE_EL3_TOKEN_SIGN
+ *feat_reg |= RMM_EL3_FEAT_REG_0_EL3_TOKEN_SIGN_MASK;
+#endif
+ return E_RMM_OK;
+}
+
/*******************************************************************************
* This function handles RMM-EL3 interface SMCs
******************************************************************************/
@@ -448,7 +463,7 @@
uint64_t x3, uint64_t x4, void *cookie,
void *handle, uint64_t flags)
{
- uint64_t remaining_len = 0;
+ uint64_t remaining_len = 0UL;
uint32_t src_sec_state;
int ret;
@@ -479,7 +494,13 @@
case RMM_ATTEST_GET_REALM_KEY:
ret = rmmd_attest_get_signing_key(x1, &x2, x3);
SMC_RET2(handle, ret, x2);
-
+ case RMM_EL3_FEATURES:
+ ret = rmm_el3_ifc_get_feat_register(x1, &x2);
+ SMC_RET2(handle, ret, x2);
+#if RMMD_ENABLE_EL3_TOKEN_SIGN
+ case RMM_EL3_TOKEN_SIGN:
+ return rmmd_el3_token_sign(handle, x1, x2, x3, x4);
+#endif
case RMM_BOOT_COMPLETE:
VERBOSE("RMMD: running rmmd_rmm_sync_exit\n");
rmmd_rmm_sync_exit(x1);
diff --git a/services/std_svc/rmmd/rmmd_private.h b/services/std_svc/rmmd/rmmd_private.h
index 6d3b5ec..0ce104d 100644
--- a/services/std_svc/rmmd/rmmd_private.h
+++ b/services/std_svc/rmmd/rmmd_private.h
@@ -51,6 +51,8 @@
uint64_t *remaining_len);
int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size,
uint64_t ecc_curve);
+uint64_t rmmd_el3_token_sign(void *handle, uint64_t x1, uint64_t x2,
+ uint64_t x3, uint64_t x4);
/* Assembly helpers */
uint64_t rmmd_rmm_enter(uint64_t *c_rt_ctx);
diff --git a/services/std_svc/spm/el3_spmc/spmc_setup.c b/services/std_svc/spm/el3_spmc/spmc_setup.c
index 4360832..f7357f1 100644
--- a/services/std_svc/spm/el3_spmc/spmc_setup.c
+++ b/services/std_svc/spm/el3_spmc/spmc_setup.c
@@ -386,7 +386,7 @@
write_el1_ctx_common(get_el1_sysregs_ctx(ctx), vbar_el1,
SPM_SHIM_EXCEPTIONS_PTR);
#if NS_TIMER_SWITCH
- write_el1_ctx_common(get_el1_sysregs_ctx(ctx), cntkctl_el1,
+ write_el1_ctx_arch_timer(get_el1_sysregs_ctx(ctx), cntkctl_el1,
EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
#endif
diff --git a/tools/amlogic/Makefile b/tools/amlogic/Makefile
index 7a53437..7bfee7d 100644
--- a/tools/amlogic/Makefile
+++ b/tools/amlogic/Makefile
@@ -5,8 +5,6 @@
# https://spdx.org/licenses
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 16f4aa3..ce12a66 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -10,8 +10,6 @@
BINARY := $(notdir ${CRTTOOL})
COT := tbbr
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 0210c36..50b0fa2 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -11,8 +11,6 @@
BINARY := $(notdir ${ENCTOOL})
OPENSSL_DIR := /usr
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index 23c8e64..54dee87 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/marvell/doimage/Makefile b/tools/marvell/doimage/Makefile
index 488b768..a4f7a1d 100644
--- a/tools/marvell/doimage/Makefile
+++ b/tools/marvell/doimage/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
-toolchains := host
-
include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
diff --git a/tools/nxp/create_pbl/Makefile b/tools/nxp/create_pbl/Makefile
index 7648b7f..22aa921 100644
--- a/tools/nxp/create_pbl/Makefile
+++ b/tools/nxp/create_pbl/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/sptool/Makefile b/tools/sptool/Makefile
index e336a0c..0da5c09 100644
--- a/tools/sptool/Makefile
+++ b/tools/sptool/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/stm32image/Makefile b/tools/stm32image/Makefile
index 2b34ef8..453daae 100644
--- a/tools/stm32image/Makefile
+++ b/tools/stm32image/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/tlc/.gitignore b/tools/tlc/.gitignore
new file mode 100644
index 0000000..ad4a1f1
--- /dev/null
+++ b/tools/tlc/.gitignore
@@ -0,0 +1,176 @@
+# Created by https://www.toptal.com/developers/gitignore/api/python
+# Edit at https://www.toptal.com/developers/gitignore?templates=python
+
+### Python ###
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+share/python-wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+MANIFEST
+
+# PyInstaller
+# Usually these files are written by a python script from a template
+# before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.nox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*.cover
+*.py,cover
+.hypothesis/
+.pytest_cache/
+cover/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+db.sqlite3
+db.sqlite3-journal
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+.pybuilder/
+target/
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# IPython
+profile_default/
+ipython_config.py
+
+# pyenv
+# For a library or package, you might want to ignore these files since the code is
+# intended to run in multiple environments; otherwise, check them in:
+# .python-version
+
+# pipenv
+# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
+# However, in case of collaboration, if having platform-specific dependencies or dependencies
+# having no cross-platform support, pipenv may install dependencies that don't work, or not
+# install all needed dependencies.
+#Pipfile.lock
+
+# poetry
+# Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control.
+# This is especially recommended for binary packages to ensure reproducibility, and is more
+# commonly ignored for libraries.
+# https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control
+#poetry.lock
+
+# pdm
+# Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control.
+#pdm.lock
+# pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it
+# in version control.
+# https://pdm.fming.dev/#use-with-ide
+.pdm.toml
+
+# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm
+__pypackages__/
+
+# Celery stuff
+celerybeat-schedule
+celerybeat.pid
+
+# SageMath parsed files
+*.sage.py
+
+# Environments
+.env
+.venv
+env/
+venv/
+ENV/
+env.bak/
+venv.bak/
+
+# Spyder project settings
+.spyderproject
+.spyproject
+
+# Rope project settings
+.ropeproject
+
+# mkdocs documentation
+/site
+
+# mypy
+.mypy_cache/
+.dmypy.json
+dmypy.json
+
+# Pyre type checker
+.pyre/
+
+# pytype static type analyzer
+.pytype/
+
+# Cython debug symbols
+cython_debug/
+
+# PyCharm
+# JetBrains specific template is maintained in a separate JetBrains.gitignore that can
+# be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore
+# and can be added to the global gitignore or merged into this file. For a more nuclear
+# option (not recommended) you can uncomment the following to ignore the entire idea folder.
+#.idea/
+
+### Python Patch ###
+# Poetry local configuration file - https://python-poetry.org/docs/configuration/#local-configuration
+poetry.toml
+
+# ruff
+.ruff_cache/
+
+# LSP config files
+pyrightconfig.json
+
+# End of https://www.toptal.com/developers/gitignore/api/python
diff --git a/tools/tlc/Makefile b/tools/tlc/Makefile
deleted file mode 100644
index e50b9dd..0000000
--- a/tools/tlc/Makefile
+++ /dev/null
@@ -1,109 +0,0 @@
-#
-# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-
-##* Variables
-SHELL := /usr/bin/env bash
-PYTHON := python
-PYTHONPATH := `pwd`
-
-#* Docker variables
-IMAGE := tlc
-VERSION := latest
-
-#* Installation
-.PHONY: dist
-dist: clean
- poetry build
-
-.PHONY: dev-install
-dev-install:
- poetry lock -n --no-update && poetry export --without-hashes > requirements.txt
- poetry install -n
- -poetry run mypy --install-types --non-interactive ./
-
-.PHONY: install
-install: dist
- pip install dist/*.whl
-
-.PHONY: pre-commit-install
-pre-commit-install:
- poetry run pre-commit install
-
-#* Formatters
-.PHONY: codestyle
-codestyle:
- poetry run pyupgrade --exit-zero-even-if-changed --py38-plus **/*.py
- poetry run isort --settings-path pyproject.toml ./
- poetry run black --config pyproject.toml ./
-
-.PHONY: formatting
-formatting: codestyle
-
-#* Linting
-.PHONY: test
-test:
- PYTHONPATH=$(PYTHONPATH) poetry run pytest -c pyproject.toml --cov-report=html --cov=tlc tests/
- poetry run coverage-badge -o assets/images/coverage.svg -f
-
-.PHONY: check-codestyle
-check-codestyle:
- poetry run isort --diff --check-only --settings-path pyproject.toml ./
- poetry run black --diff --check --config pyproject.toml ./
- poetry run darglint --verbosity 2 tlc tests
-
-.PHONY: mypy
-mypy:
- poetry run mypy --config-file pyproject.toml ./
-
-.PHONY: check-safety
-check-safety:
- poetry check
- poetry run safety check --full-report
- poetry run bandit -ll --recursive tlc tests
-
-.PHONY: lint
-lint: test check-codestyle mypy check-safety
-
-.PHONY: update-dev-deps
-update-dev-deps:
- poetry add -D bandit@latest darglint@latest "isort[colors]@latest" mypy@latest pre-commit@latest pydocstyle@latest pylint@latest pytest@latest pyupgrade@latest safety@latest coverage@latest coverage-badge@latest pytest-html@latest pytest-cov@latest
- poetry add -D --allow-prereleases black@latest
-
-#* Docker
-.PHONY: docker-build docker-remove
-docker-build:
- @echo Building docker $(IMAGE):$(VERSION) ...
- docker build \
- -t $(IMAGE):$(VERSION) . \
- -f ./docker/Dockerfile --no-cache
-
-docker-remove:
- @echo Removing docker $(IMAGE):$(VERSION) ...
- docker rmi -f $(IMAGE):$(VERSION)
-
-
-#* Cleaning
-.PHONY: clean .clean-build clean-pyc clean-test
-clean: clean-build clean-pyc clean-test ## remove all build, test, coverage and Python artifacts
-
-clean-build: ## remove build artifacts
- rm -fr build/
- rm -fr dist/
- rm -fr .eggs/
- find . -name '*.egg-info' -exec rm -fr {} +
- find . -name '*.egg' -exec rm -f {} +
-
-clean-pyc: ## remove Python file artifacts
- find . -name '*.pyc' -exec rm -f {} +
- find . -name '*.pyo' -exec rm -f {} +
- find . -name '*~' -exec rm -f {} +
- find . -name '__pycache__' -exec rm -fr {} +
- find . | grep -E ".pytest_cache" | xargs rm -rf
- find . | grep -E ".mypy_cache" | xargs rm -rf
-
-clean-test: ## remove test and coverage artifacts
- rm -fr .tox/
- rm -f .coverage
- rm -fr htmlcov/
diff --git a/tools/tlc/poetry.lock b/tools/tlc/poetry.lock
index 839f236..decec59 100644
--- a/tools/tlc/poetry.lock
+++ b/tools/tlc/poetry.lock
@@ -45,33 +45,33 @@
[[package]]
name = "black"
-version = "24.4.2"
+version = "24.8.0"
description = "The uncompromising code formatter."
optional = false
python-versions = ">=3.8"
files = [
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+ {file = "black-24.8.0.tar.gz", hash = "sha256:2500945420b6784c38b9ee885af039f5e7471ef284ab03fa35ecdde4688cd83f"},
]
[package.dependencies]
@@ -90,14 +90,25 @@
uvloop = ["uvloop (>=0.15.2)"]
[[package]]
+name = "cachetools"
+version = "5.5.0"
+description = "Extensible memoizing collections and decorators"
+optional = false
+python-versions = ">=3.7"
+files = [
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+ {file = "cachetools-5.5.0.tar.gz", hash = "sha256:2cc24fb4cbe39633fb7badd9db9ca6295d766d9c2995f245725a46715d050f2a"},
+]
+
+[[package]]
name = "certifi"
-version = "2024.7.4"
+version = "2024.8.30"
description = "Python package for providing Mozilla's CA Bundle."
optional = false
python-versions = ">=3.6"
files = [
- {file = "certifi-2024.7.4-py3-none-any.whl", hash = "sha256:c198e21b1289c2ab85ee4e67bb4b4ef3ead0892059901a8d5b622f24a1101e90"},
- {file = "certifi-2024.7.4.tar.gz", hash = "sha256:5a1e7645bc0ec61a09e26c36f6106dd4cf40c6db3a1fb6352b0244e7fb057c7b"},
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+ {file = "certifi-2024.8.30.tar.gz", hash = "sha256:bec941d2aa8195e248a60b31ff9f0558284cf01a52591ceda73ea9afffd69fd9"},
]
[[package]]
@@ -112,6 +123,17 @@
]
[[package]]
+name = "chardet"
+version = "5.2.0"
+description = "Universal encoding detector for Python 3"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "chardet-5.2.0-py3-none-any.whl", hash = "sha256:e1cf59446890a00105fe7b7912492ea04b6e6f06d4b742b2c788469e34c82970"},
+ {file = "chardet-5.2.0.tar.gz", hash = "sha256:1b3b6ff479a8c414bc3fa2c0852995695c4a026dcd6d0633b2dd092ca39c1cf7"},
+]
+
+[[package]]
name = "charset-normalizer"
version = "3.3.2"
description = "The Real First Universal Charset Detector. Open, modern and actively maintained alternative to Chardet."
@@ -316,17 +338,18 @@
[[package]]
name = "coverage-badge"
-version = "1.1.1"
+version = "1.1.2"
description = "Generate coverage badges for Coverage.py."
optional = false
python-versions = "*"
files = [
- {file = "coverage-badge-1.1.1.tar.gz", hash = "sha256:42252df917404af6147380861228a4ace3d9a29804df8fc2d34a22b2bc4f45b6"},
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+ {file = "coverage_badge-1.1.2.tar.gz", hash = "sha256:fe7ed58a3b72dad85a553b64a99e963dea3847dcd0b8ddd2b38a00333618642c"},
]
[package.dependencies]
coverage = "*"
+setuptools = "*"
[[package]]
name = "darglint"
@@ -400,29 +423,29 @@
[[package]]
name = "filelock"
-version = "3.15.4"
+version = "3.16.1"
description = "A platform independent file lock."
optional = false
python-versions = ">=3.8"
files = [
- {file = "filelock-3.15.4-py3-none-any.whl", hash = "sha256:6ca1fffae96225dab4c6eaf1c4f4f28cd2568d3ec2a44e15a08520504de468e7"},
- {file = "filelock-3.15.4.tar.gz", hash = "sha256:2207938cbc1844345cb01a5a95524dae30f0ce089eba5b00378295a17e3e90cb"},
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+ {file = "filelock-3.16.1.tar.gz", hash = "sha256:c249fbfcd5db47e5e2d6d62198e565475ee65e4831e2561c8e313fa7eb961435"},
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[package.extras]
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-testing = ["covdefaults (>=2.3)", "coverage (>=7.3.2)", "diff-cover (>=8.0.1)", "pytest (>=7.4.3)", "pytest-asyncio (>=0.21)", "pytest-cov (>=4.1)", "pytest-mock (>=3.12)", "pytest-timeout (>=2.2)", "virtualenv (>=20.26.2)"]
-typing = ["typing-extensions (>=4.8)"]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-autodoc-typehints (>=2.4.1)"]
+testing = ["covdefaults (>=2.3)", "coverage (>=7.6.1)", "diff-cover (>=9.2)", "pytest (>=8.3.3)", "pytest-asyncio (>=0.24)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-timeout (>=2.3.1)", "virtualenv (>=20.26.4)"]
+typing = ["typing-extensions (>=4.12.2)"]
[[package]]
name = "identify"
-version = "2.6.0"
+version = "2.6.1"
description = "File identification library for Python"
optional = false
python-versions = ">=3.8"
files = [
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]
[package.extras]
@@ -430,15 +453,18 @@
[[package]]
name = "idna"
-version = "3.7"
+version = "3.10"
description = "Internationalized Domain Names in Applications (IDNA)"
optional = false
-python-versions = ">=3.5"
+python-versions = ">=3.6"
files = [
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+ {file = "idna-3.10.tar.gz", hash = "sha256:12f65c9b470abda6dc35cf8e63cc574b1c52b11df2c86030af0ac09b01b13ea9"},
]
+[package.extras]
+all = ["flake8 (>=7.1.1)", "mypy (>=1.11.2)", "pytest (>=8.3.2)", "ruff (>=0.6.2)"]
+
[[package]]
name = "iniconfig"
version = "2.0.0"
@@ -696,30 +722,30 @@
[[package]]
name = "pbr"
-version = "6.0.0"
+version = "6.1.0"
description = "Python Build Reasonableness"
optional = false
python-versions = ">=2.6"
files = [
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+ {file = "pbr-6.1.0-py2.py3-none-any.whl", hash = "sha256:a776ae228892d8013649c0aeccbb3d5f99ee15e005a4cbb7e61d55a067b28a2a"},
+ {file = "pbr-6.1.0.tar.gz", hash = "sha256:788183e382e3d1d7707db08978239965e8b9e4e5ed42669bf4758186734d5f24"},
]
[[package]]
name = "platformdirs"
-version = "4.2.2"
+version = "4.3.6"
description = "A small Python package for determining appropriate platform-specific dirs, e.g. a `user data dir`."
optional = false
python-versions = ">=3.8"
files = [
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+ {file = "platformdirs-4.3.6.tar.gz", hash = "sha256:357fb2acbc885b0419afd3ce3ed34564c13c9b95c89360cd9563f73aa5e2b907"},
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-test = ["appdirs (==1.4.4)", "covdefaults (>=2.3)", "pytest (>=7.4.3)", "pytest-cov (>=4.1)", "pytest-mock (>=3.12)"]
-type = ["mypy (>=1.8)"]
+docs = ["furo (>=2024.8.6)", "proselint (>=0.14)", "sphinx (>=8.0.2)", "sphinx-autodoc-typehints (>=2.4)"]
+test = ["appdirs (==1.4.4)", "covdefaults (>=2.3)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)"]
+type = ["mypy (>=1.11.2)"]
[[package]]
name = "pluggy"
@@ -815,14 +841,33 @@
testutils = ["gitpython (>3)"]
[[package]]
+name = "pyproject-api"
+version = "1.8.0"
+description = "API to interact with the python pyproject.toml based projects"
+optional = false
+python-versions = ">=3.8"
+files = [
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+ {file = "pyproject_api-1.8.0.tar.gz", hash = "sha256:77b8049f2feb5d33eefcc21b57f1e279636277a8ac8ad6b5871037b243778496"},
+]
+
+[package.dependencies]
+packaging = ">=24.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx-autodoc-typehints (>=2.4.1)"]
+testing = ["covdefaults (>=2.3)", "pytest (>=8.3.3)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "setuptools (>=75.1)"]
+
+[[package]]
name = "pytest"
-version = "7.4.4"
+version = "8.3.3"
description = "pytest: simple powerful testing with Python"
optional = false
-python-versions = ">=3.7"
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+ {file = "PyYAML-6.0.2-cp39-cp39-musllinux_1_1_aarch64.whl", hash = "sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e"},
+ {file = "PyYAML-6.0.2-cp39-cp39-musllinux_1_1_x86_64.whl", hash = "sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725"},
+ {file = "PyYAML-6.0.2-cp39-cp39-win32.whl", hash = "sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631"},
+ {file = "PyYAML-6.0.2-cp39-cp39-win_amd64.whl", hash = "sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8"},
+ {file = "pyyaml-6.0.2.tar.gz", hash = "sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e"},
]
[[package]]
@@ -1107,19 +1154,23 @@
[[package]]
name = "setuptools"
-version = "72.1.0"
+version = "75.1.0"
description = "Easily download, build, install, upgrade, and uninstall Python packages"
optional = false
python-versions = ">=3.8"
files = [
- {file = "setuptools-72.1.0-py3-none-any.whl", hash = "sha256:5a03e1860cf56bb6ef48ce186b0e557fdba433237481a9a625176c2831be15d1"},
- {file = "setuptools-72.1.0.tar.gz", hash = "sha256:8d243eff56d095e5817f796ede6ae32941278f542e0f941867cc05ae52b162ec"},
+ {file = "setuptools-75.1.0-py3-none-any.whl", hash = "sha256:35ab7fd3bcd95e6b7fd704e4a1539513edad446c097797f2985e0e4b960772f2"},
+ {file = "setuptools-75.1.0.tar.gz", hash = "sha256:d59a21b17a275fb872a9c3dae73963160ae079f1049ed956880cd7c09b120538"},
]
[package.extras]
-core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.text (>=3.7)", "more-itertools (>=8.8)", "ordered-set (>=3.1.1)", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
-doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier"]
-test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "importlib-metadata", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "mypy (==1.11.*)", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-home (>=0.5)", "pytest-mypy", "pytest-perf", "pytest-ruff (<0.4)", "pytest-ruff (>=0.2.1)", "pytest-ruff (>=0.3.2)", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel"]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)", "ruff (>=0.5.2)"]
+core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.collections", "jaraco.functools", "jaraco.text (>=3.7)", "more-itertools", "more-itertools (>=8.8)", "packaging", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
+cover = ["pytest-cov"]
+doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier", "towncrier (<24.7)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-home (>=0.5)", "pytest-perf", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel (>=0.44.0)"]
+type = ["importlib-metadata (>=7.0.2)", "jaraco.develop (>=7.21)", "mypy (==1.11.*)", "pytest-mypy"]
[[package]]
name = "shellingham"
@@ -1145,17 +1196,17 @@
[[package]]
name = "stevedore"
-version = "5.2.0"
+version = "5.3.0"
description = "Manage dynamic plugins for Python applications"
optional = false
python-versions = ">=3.8"
files = [
- {file = "stevedore-5.2.0-py3-none-any.whl", hash = "sha256:1c15d95766ca0569cad14cb6272d4d31dae66b011a929d7c18219c176ea1b5c9"},
- {file = "stevedore-5.2.0.tar.gz", hash = "sha256:46b93ca40e1114cea93d738a6c1e365396981bb6bb78c27045b7587c9473544d"},
+ {file = "stevedore-5.3.0-py3-none-any.whl", hash = "sha256:1efd34ca08f474dad08d9b19e934a22c68bb6fe416926479ba29e5013bcc8f78"},
+ {file = "stevedore-5.3.0.tar.gz", hash = "sha256:9a64265f4060312828151c204efbe9b7a9852a0d9228756344dbc7e4023e375a"},
]
[package.dependencies]
-pbr = ">=2.0.0,<2.1.0 || >2.1.0"
+pbr = ">=2.0.0"
[[package]]
name = "tokenize-rt"
@@ -1192,16 +1243,43 @@
[[package]]
name = "tomlkit"
-version = "0.13.0"
+version = "0.13.2"
description = "Style preserving TOML library"
optional = false
python-versions = ">=3.8"
files = [
- {file = "tomlkit-0.13.0-py3-none-any.whl", hash = "sha256:7075d3042d03b80f603482d69bf0c8f345c2b30e41699fd8883227f89972b264"},
- {file = "tomlkit-0.13.0.tar.gz", hash = "sha256:08ad192699734149f5b97b45f1f18dad7eb1b6d16bc72ad0c2335772650d7b72"},
+ {file = "tomlkit-0.13.2-py3-none-any.whl", hash = "sha256:7a974427f6e119197f670fbbbeae7bef749a6c14e793db934baefc1b5f03efde"},
+ {file = "tomlkit-0.13.2.tar.gz", hash = "sha256:fff5fe59a87295b278abd31bec92c15d9bc4a06885ab12bcea52c71119392e79"},
]
[[package]]
+name = "tox"
+version = "4.20.0"
+description = "tox is a generic virtualenv management and test command line tool"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "tox-4.20.0-py3-none-any.whl", hash = "sha256:21a8005e3d3fe5658a8e36b8ca3ed13a4230429063c5cc2a2fdac6ee5aa0de34"},
+ {file = "tox-4.20.0.tar.gz", hash = "sha256:5b78a49b6eaaeab3ae4186415e7c97d524f762ae967c63562687c3e5f0ec23d5"},
+]
+
+[package.dependencies]
+cachetools = ">=5.5"
+chardet = ">=5.2"
+colorama = ">=0.4.6"
+filelock = ">=3.15.4"
+packaging = ">=24.1"
+platformdirs = ">=4.2.2"
+pluggy = ">=1.5"
+pyproject-api = ">=1.7.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+virtualenv = ">=20.26.3"
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-argparse-cli (>=1.17)", "sphinx-autodoc-typehints (>=2.4)", "sphinx-copybutton (>=0.5.2)", "sphinx-inline-tabs (>=2023.4.21)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=24.8)"]
+testing = ["build[virtualenv] (>=1.2.2)", "covdefaults (>=2.3)", "detect-test-pollution (>=1.2)", "devpi-process (>=1)", "diff-cover (>=9.1.1)", "distlib (>=0.3.8)", "flaky (>=3.8.1)", "hatch-vcs (>=0.4)", "hatchling (>=1.25)", "psutil (>=6)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-xdist (>=3.6.1)", "re-assert (>=1.1)", "setuptools (>=74.1.2)", "time-machine (>=2.15)", "wheel (>=0.44)"]
+
+[[package]]
name = "typer"
version = "0.4.2"
description = "Typer, build great CLIs. Easy to code. Based on Python type hints."
@@ -1236,13 +1314,13 @@
[[package]]
name = "urllib3"
-version = "2.2.2"
+version = "2.2.3"
description = "HTTP library with thread-safe connection pooling, file post, and more."
optional = false
python-versions = ">=3.8"
files = [
- {file = "urllib3-2.2.2-py3-none-any.whl", hash = "sha256:a448b2f64d686155468037e1ace9f2d2199776e17f0a46610480d311f73e3472"},
- {file = "urllib3-2.2.2.tar.gz", hash = "sha256:dd505485549a7a552833da5e6063639d0d177c04f23bc3864e41e5dc5f612168"},
+ {file = "urllib3-2.2.3-py3-none-any.whl", hash = "sha256:ca899ca043dcb1bafa3e262d73aa25c465bfb49e0bd9dd5d59f1d0acba2f8fac"},
+ {file = "urllib3-2.2.3.tar.gz", hash = "sha256:e7d814a81dad81e6caf2ec9fdedb284ecc9c73076b62654547cc64ccdcae26e9"},
]
[package.extras]
@@ -1253,13 +1331,13 @@
[[package]]
name = "virtualenv"
-version = "20.26.3"
+version = "20.26.5"
description = "Virtual Python Environment builder"
optional = false
python-versions = ">=3.7"
files = [
- {file = "virtualenv-20.26.3-py3-none-any.whl", hash = "sha256:8cc4a31139e796e9a7de2cd5cf2489de1217193116a8fd42328f1bd65f434589"},
- {file = "virtualenv-20.26.3.tar.gz", hash = "sha256:4c43a2a236279d9ea36a0d76f98d84bd6ca94ac4e0f4a3b9d46d05e10fea542a"},
+ {file = "virtualenv-20.26.5-py3-none-any.whl", hash = "sha256:4f3ac17b81fba3ce3bd6f4ead2749a72da5929c01774948e243db9ba41df4ff6"},
+ {file = "virtualenv-20.26.5.tar.gz", hash = "sha256:ce489cac131aa58f4b25e321d6d186171f78e6cb13fafbf32a840cee67733ff4"},
]
[package.dependencies]
@@ -1353,4 +1431,4 @@
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "cfcb196cda412f6139302937640455aa8154d7979c69017fe45ddd528e4a1bf2"
+content-hash = "aac9123f3fa544b8c3e9b085f41f5a1c6c4ed2d59ce3236dcda6ea2aef5a694c"
diff --git a/tools/tlc/pyproject.toml b/tools/tlc/pyproject.toml
index 5661abf..b606238 100644
--- a/tools/tlc/pyproject.toml
+++ b/tools/tlc/pyproject.toml
@@ -38,9 +38,15 @@
rich = "^10.14.0"
click = "^8.1.7"
pyyaml = "^6.0.1"
+tox = "^4.18.0"
+jinja2 = "^3.1.4"
-[tool.poetry.dev-dependencies]
+[tool.poetry.group.dev]
+optional = true
+
+[tool.poetry.group.dev.dependencies]
bandit = "^1.7.1"
+tox = "^4.18.0"
darglint = "^1.8.1"
black = "^24.4.2"
isort = {extras = ["colors"], version = "^5.10.1"}
@@ -49,13 +55,13 @@
pre-commit = "^2.15.0"
pydocstyle = "^6.1.1"
pylint = "^2.11.1"
-pytest = "^7.0.0"
+pytest = "^8.0.0"
pyupgrade = "^2.29.1"
safety = "^2.2.0"
coverage = "^6.1.2"
coverage-badge = "^1.1.0"
pytest-html = "^4.1.1"
-pytest-cov = "^3.0.0"
+pytest-cov = "5.0.0"
[tool.black]
# https://github.com/psf/black
@@ -135,13 +141,11 @@
[tool.coverage.run]
source = ["tests"]
-
-[coverage.paths]
-source = "tlc"
-
-[coverage.run]
branch = true
-[coverage.report]
+[tool.coverage.paths]
+source = ["tlc"]
+
+[tool.coverage.report]
fail_under = 50
show_missing = true
diff --git a/tools/tlc/tests/test_cli.py b/tools/tlc/tests/test_cli.py
index 99b5816..a5ef30e 100644
--- a/tools/tlc/tests/test_cli.py
+++ b/tools/tlc/tests/test_cli.py
@@ -9,12 +9,12 @@
"""Contains unit tests for the CLI functionality."""
+from math import ceil, log2
from pathlib import Path
+from re import findall, search
from unittest import mock
-from math import log2, ceil
import pytest
-import pytest
import yaml
from click.testing import CliRunner
@@ -384,6 +384,69 @@
assert actual == expected
+@pytest.mark.parametrize("option", ["-O", "--output"])
+def test_gen_tl_header_with_output_name(tlcrunner, tmptlstr, option, filename="test.h"):
+ with tlcrunner.isolated_filesystem():
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ option,
+ filename,
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path(filename).exists()
+
+
+def test_gen_tl_with_fdt_header(tmptlstr, tmpfdt):
+ tlcrunner = CliRunner()
+
+ with tlcrunner.isolated_filesystem():
+ tlcrunner.invoke(cli, ["create", "--size", 1000, "--fdt", tmpfdt, tmptlstr])
+
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path("header.h").exists()
+
+ with open("header.h", "r") as f:
+ dtb_match = search(r"DTB_OFFSET\s+(\d+)", "".join(f.readlines()))
+ assert dtb_match and dtb_match[1].isnumeric()
+
+
+def test_gen_empty_tl_c_header(tlcrunner, tmptlstr):
+ with tlcrunner.isolated_filesystem():
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path("header.h").exists()
+
+ with open("header.h", "r") as f:
+ lines = "".join(f.readlines())
+
+ assert TransferList.hdr_size == int(
+ findall(r"SIZE\s+(0x[0-9a-fA-F]+|\d+)", lines)[0], 16
+ )
+ assert TransferList.version == int(
+ findall(r"VERSION.+(0x[0-9a-fA-F]+|\d+)", lines)[0]
+ )
+
+
def bytes_to_hex(data: bytes) -> str:
"""Convert bytes to a hex string in the same format as the debugger in
ArmDS
diff --git a/tools/tlc/tlc/cli.py b/tools/tlc/tlc/cli.py
index 1d4949d..3d60938 100644
--- a/tools/tlc/tlc/cli.py
+++ b/tools/tlc/tlc/cli.py
@@ -12,6 +12,7 @@
from pathlib import Path
import click
+import jinja2
import yaml
from tlc.tl import *
@@ -166,6 +167,34 @@
@cli.command()
@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "--output",
+ "-O",
+ type=click.Path(exists=False),
+ help="Output filename for the header",
+ default=Path("header.h"),
+)
+def gen_header(filename, output):
+ """Generate a header with common definitions."""
+ tl = TransferList.fromfile(filename)
+ tmp_keys = tl.__dict__
+ tmp_keys["header_guard"] = Path(output).name.replace(".", "_").upper()
+
+ dtb_te = tl.get_entry(1)
+
+ if dtb_te:
+ tmp_keys["dtb_offset"] = dtb_te.offset + dtb_te.hdr_size
+
+ env = jinja2.Environment(
+ loader=jinja2.PackageLoader("tlc", "templates"),
+ )
+ template = env.get_template("header.h.j2")
+ with open(output, "w") as f:
+ f.write(template.render(tmp_keys))
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
def validate(filename):
"""Validate the contents of an existing Transfer List."""
TransferList.fromfile(filename)
diff --git a/tools/tlc/tlc/templates/header.h.j2 b/tools/tlc/tlc/templates/header.h.j2
new file mode 100644
index 0000000..87707ce
--- /dev/null
+++ b/tools/tlc/tlc/templates/header.h.j2
@@ -0,0 +1,16 @@
+/*
+ * Auto-generated by TLC, this file includes declarations and macros
+ * derived from a Transfer List input.
+ */
+
+#ifndef {{ header_guard }}
+#define {{ header_guard }}
+
+{% if dtb_offset -%}
+#define TRANSFER_LIST_DTB_OFFSET {{ "0x%x" % dtb_offset }}
+{%- endif %}
+#define TRANSFER_LIST_CONVENTION_VERSION {{ version }}
+#define TRANSFER_LIST_HEADER_SIZE {{ "0x%x" % hdr_size }}
+#define TRANSFER_LIST_SIZE {{ "0x%x" % size }}
+
+#endif /* {{ header_guard }} */
diff --git a/tools/tlc/tlc/tl.py b/tools/tlc/tlc/tl.py
index 3f0065d..98d2205 100644
--- a/tools/tlc/tlc/tl.py
+++ b/tools/tlc/tlc/tl.py
@@ -8,7 +8,7 @@
"""Module containing definitions pertaining to the 'Transfer List' (TL) type."""
-import typing
+from typing import Any, Dict, List, Optional
import math
import struct
@@ -24,7 +24,7 @@
# used in struct.pack to encode the TE), and a list of field names that can
# appear in the yaml file for that TE. Some fields are missing, if that TE has
# to be processed differently, or if it can only be added with a blob file.
-transfer_entry_formats = {
+transfer_entry_formats: Dict[int, Any] = {
0: {
"tag_name": "empty",
"format": "4x",
@@ -93,7 +93,7 @@
self.size = self.hdr_size
self.total_size = max_size
self.flags = flags
- self.entries: typing.List["TransferEntry"] = []
+ self.entries: List[TransferEntry] = []
self.update_checksum()
def __str__(self) -> str:
@@ -152,7 +152,7 @@
return tl
@classmethod
- def from_dict(cls, config: dict):
+ def from_dict(cls, config: Dict[str, Any]) -> "TransferList":
"""Create a TL from data in a dictionary
The dictionary should have the same format as the yaml config files.
@@ -197,15 +197,23 @@
sum(self.header_to_bytes()) + sum(te.sum_of_bytes for te in self.entries)
) % 256
- def get_entry_data_offset(self, tag_id: int) -> int:
- """Returns offset of data of a TE from the base of the TL."""
+ def get_entry(self, tag_id: int) -> Optional[TransferEntry]:
for te in self.entries:
if te.id == tag_id:
- return te.offset + te.hdr_size
+ return te
+
+ return None
+
+ def get_entry_data_offset(self, tag_id: int) -> int:
+ """Returns offset of data of a TE from the base of the TL."""
+ te = self.get_entry(tag_id)
+
+ if not te:
+ raise ValueError(f"Tag {tag_id} not found in TL!")
- raise ValueError(f"Tag {tag_id} not found in TL!")
+ return te.offset + te.hdr_size
- def add_transfer_entry(self, tag_id: int, data: bytes) -> "TransferEntry":
+ def add_transfer_entry(self, tag_id: int, data: bytes) -> TransferEntry:
"""Appends a TransferEntry into the internal list of TE's."""
if not (self.total_size >= self.size + TransferEntry.hdr_size + len(data)):
raise MemoryError(
@@ -219,13 +227,15 @@
return te
def add_transfer_entry_from_struct_format(
- self, tag_id: int, struct_format: str, *args
- ):
+ self, tag_id: int, struct_format: str, *args: Any
+ ) -> TransferEntry:
struct_format = "<" + struct_format
data = struct.pack(struct_format, *args)
return self.add_transfer_entry(tag_id, data)
- def add_entry_point_info_transfer_entry(self, entry: dict) -> "TransferEntry":
+ def add_entry_point_info_transfer_entry(
+ self, entry: Dict[str, Any]
+ ) -> TransferEntry:
"""Add entry_point_info transfer entry
:param entry: Dictionary of the transfer entry, in the same format as
@@ -282,8 +292,8 @@
def add_transfer_entry_from_dict(
self,
- entry: dict,
- ) -> "TransferEntry":
+ entry: Dict[str, Any],
+ ) -> TransferEntry:
"""Add a transfer entry from data in a dictionary
The dictionary should have the same format as the entries in the yaml
@@ -318,7 +328,7 @@
else:
raise ValueError(f"Invalid transfer entry {entry}.")
- def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> "TransferEntry":
+ def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> TransferEntry:
with open(path, "rb") as f:
return self.add_transfer_entry(tag_id, f.read())
diff --git a/tools/tlc/tox.ini b/tools/tlc/tox.ini
new file mode 100644
index 0000000..4fd141f
--- /dev/null
+++ b/tools/tlc/tox.ini
@@ -0,0 +1,26 @@
+[tox]
+envlist = py38, py39, py310, py311, py312, lint
+
+[testenv]
+allowlist_externals = poetry
+commands =
+ poetry install -v --with dev
+ poetry run pytest
+
+[testenv:format]
+description = Run linters and type checks
+skip_install = true
+allowlist_externals = poetry
+commands =
+ poetry run black .
+ poetry run isort .
+
+[testenv:lint]
+description = Run linters and type checks
+skip_install = true
+allowlist_externals = poetry
+commands =
+ poetry run black --check .
+ poetry run isort --check-only .
+ poetry run mypy .
+ poetry run darglint tlc tests