gic: Fix types
Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c
index 421669f..221f1b5 100644
--- a/drivers/arm/gic/v2/gicv2_helpers.c
+++ b/drivers/arm/gic/v2/gicv2_helpers.c
@@ -94,24 +94,24 @@
num_ints = gicd_read_typer(gicd_base);
num_ints &= TYPER_IT_LINES_NO_MASK;
- num_ints = (num_ints + 1) << 5;
+ num_ints = (num_ints + 1U) << 5;
/*
* Treat all SPIs as G1NS by default. The number of interrupts is
* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
*/
- for (index = MIN_SPI_ID; index < num_ints; index += 32)
+ for (index = MIN_SPI_ID; index < num_ints; index += 32U)
gicd_write_igroupr(gicd_base, index, ~0U);
/* Setup the default SPI priorities doing four at a time */
- for (index = MIN_SPI_ID; index < num_ints; index += 4)
+ for (index = MIN_SPI_ID; index < num_ints; index += 4U)
gicd_write_ipriorityr(gicd_base,
index,
GICD_IPRIORITYR_DEF_VAL);
/* Treat all SPIs as level triggered by default, 16 at a time */
- for (index = MIN_SPI_ID; index < num_ints; index += 16)
- gicd_write_icfgr(gicd_base, index, 0);
+ for (index = MIN_SPI_ID; index < num_ints; index += 16U)
+ gicd_write_icfgr(gicd_base, index, 0U);
}
#if !ERROR_DEPRECATED
@@ -125,7 +125,8 @@
unsigned int index, irq_num;
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- assert(num_ints ? (uintptr_t)sec_intr_list : 1);
+ if (num_ints != 0U)
+ assert(sec_intr_list != NULL);
for (index = 0; index < num_ints; index++) {
irq_num = sec_intr_list[index];
@@ -161,7 +162,8 @@
const interrupt_prop_t *prop_desc;
/* Make sure there's a valid property array */
- assert(interrupt_props_num != 0 ? (uintptr_t) interrupt_props : 1);
+ if (interrupt_props_num != 0U)
+ assert(interrupt_props != NULL);
for (i = 0; i < interrupt_props_num; i++) {
prop_desc = &interrupt_props[i];
@@ -252,20 +254,21 @@
const interrupt_prop_t *prop_desc;
/* Make sure there's a valid property array */
- assert(interrupt_props_num != 0 ? (uintptr_t) interrupt_props : 1);
+ if (interrupt_props_num != 0U)
+ assert(interrupt_props != NULL);
/*
* Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
* more scalable approach as it avoids clearing the enable bits in the
* GICD_CTLR.
*/
- gicd_write_icenabler(gicd_base, 0, ~0);
+ gicd_write_icenabler(gicd_base, 0U, ~0U);
/* Setup the default PPI/SGI priorities doing four at a time */
- for (i = 0; i < MIN_SPI_ID; i += 4)
+ for (i = 0U; i < MIN_SPI_ID; i += 4U)
gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
- for (i = 0; i < interrupt_props_num; i++) {
+ for (i = 0U; i < interrupt_props_num; i++) {
prop_desc = &interrupt_props[i];
if (prop_desc->intr_num >= MIN_SPI_ID)
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 7cf6c76..311e77e 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -12,6 +12,8 @@
#include <gicv2.h>
#include <interrupt_props.h>
#include <spinlock.h>
+#include <stdbool.h>
+
#include "../common/gic_common_private.h"
#include "gicv2_private.h"
@@ -32,8 +34,8 @@
{
unsigned int val;
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
/*
* Enable the Group 0 interrupts, FIQEn and disable Group 0/1
@@ -55,8 +57,8 @@
{
unsigned int val;
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
/* Disable secure, non-secure interrupts and disable their bypass */
val = gicc_read_ctlr(driver_data->gicc_base);
@@ -74,8 +76,8 @@
{
unsigned int ctlr;
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
#if !ERROR_DEPRECATED
if (driver_data->interrupt_props != NULL) {
@@ -101,7 +103,7 @@
/* Enable G0 interrupts if not already */
ctlr = gicd_read_ctlr(driver_data->gicd_base);
- if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) {
+ if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) {
gicd_write_ctlr(driver_data->gicd_base,
ctlr | CTLR_ENABLE_G0_BIT);
}
@@ -116,8 +118,8 @@
{
unsigned int ctlr;
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
/* Disable the distributor before going further */
ctlr = gicd_read_ctlr(driver_data->gicd_base);
@@ -162,9 +164,10 @@
void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
{
unsigned int gic_version;
- assert(plat_driver_data);
- assert(plat_driver_data->gicd_base);
- assert(plat_driver_data->gicc_base);
+
+ assert(plat_driver_data != NULL);
+ assert(plat_driver_data->gicd_base != 0U);
+ assert(plat_driver_data->gicc_base != 0U);
#if !ERROR_DEPRECATED
if (plat_driver_data->interrupt_props == NULL) {
@@ -212,7 +215,8 @@
* - interrupt priority drop.
* - interrupt signal bypass.
*/
- assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
+ assert((gic_version == ARCH_REV_GICV2) ||
+ (gic_version == ARCH_REV_GICV1));
driver_data = plat_driver_data;
@@ -238,11 +242,11 @@
{
unsigned int gicc_ctlr;
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base);
- return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1;
+ return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U;
}
/*******************************************************************************
@@ -255,8 +259,8 @@
******************************************************************************/
unsigned int gicv2_get_pending_interrupt_type(void)
{
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
}
@@ -270,8 +274,8 @@
{
unsigned int id;
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
@@ -292,8 +296,8 @@
******************************************************************************/
unsigned int gicv2_acknowledge_interrupt(void)
{
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
return gicc_read_IAR(driver_data->gicc_base);
}
@@ -304,8 +308,8 @@
******************************************************************************/
void gicv2_end_of_interrupt(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
gicc_write_EOIR(driver_data->gicc_base, id);
}
@@ -318,8 +322,8 @@
******************************************************************************/
unsigned int gicv2_get_interrupt_group(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
return gicd_get_igroupr(driver_data->gicd_base, id);
}
@@ -330,8 +334,8 @@
******************************************************************************/
unsigned int gicv2_get_running_priority(void)
{
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
return gicc_read_rpr(driver_data->gicc_base);
}
@@ -344,21 +348,21 @@
******************************************************************************/
void gicv2_set_pe_target_mask(unsigned int proc_num)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
- assert(driver_data->target_masks);
- assert(proc_num < GICV2_MAX_TARGET_PE);
- assert(proc_num < driver_data->target_masks_num);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
+ assert(driver_data->target_masks != NULL);
+ assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+ assert((unsigned int)proc_num < driver_data->target_masks_num);
/* Return if the target mask is already populated */
- if (driver_data->target_masks[proc_num])
+ if (driver_data->target_masks[proc_num] != 0U)
return;
/*
* Update target register corresponding to this CPU and flush for it to
* be visible to other CPUs.
*/
- if (driver_data->target_masks[proc_num] == 0) {
+ if (driver_data->target_masks[proc_num] == 0U) {
driver_data->target_masks[proc_num] =
gicv2_get_cpuif_id(driver_data->gicd_base);
#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
@@ -382,8 +386,8 @@
******************************************************************************/
unsigned int gicv2_get_interrupt_active(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
assert(id <= MAX_SPI_ID);
return gicd_get_isactiver(driver_data->gicd_base, id);
@@ -394,8 +398,8 @@
******************************************************************************/
void gicv2_enable_interrupt(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
assert(id <= MAX_SPI_ID);
/*
@@ -411,8 +415,8 @@
******************************************************************************/
void gicv2_disable_interrupt(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
assert(id <= MAX_SPI_ID);
/*
@@ -429,8 +433,8 @@
******************************************************************************/
void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
assert(id <= MAX_SPI_ID);
gicd_set_ipriorityr(driver_data->gicd_base, id, priority);
@@ -442,8 +446,8 @@
******************************************************************************/
void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
assert(id <= MAX_SPI_ID);
/* Serialize read-modify-write to Distributor registers */
@@ -456,7 +460,7 @@
gicd_clr_igroupr(driver_data->gicd_base, id);
break;
default:
- assert(0);
+ assert(false);
break;
}
spin_unlock(&gic_lock);
@@ -472,20 +476,20 @@
{
unsigned int sgir_val, target;
- assert(driver_data);
- assert(proc_num < GICV2_MAX_TARGET_PE);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+ assert(driver_data->gicd_base != 0U);
/*
* Target masks array must have been supplied, and the core position
* should be valid.
*/
- assert(driver_data->target_masks);
- assert(proc_num < driver_data->target_masks_num);
+ assert(driver_data->target_masks != NULL);
+ assert((unsigned int)proc_num < driver_data->target_masks_num);
/* Don't raise SGI if the mask hasn't been populated */
target = driver_data->target_masks[proc_num];
- assert(target != 0);
+ assert(target != 0U);
sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num);
@@ -505,20 +509,20 @@
******************************************************************************/
void gicv2_set_spi_routing(unsigned int id, int proc_num)
{
- int target;
+ unsigned int target;
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
- assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
+ assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
/*
* Target masks array must have been supplied, and the core position
* should be valid.
*/
- assert(driver_data->target_masks);
- assert(proc_num < GICV2_MAX_TARGET_PE);
- assert(proc_num < driver_data->target_masks_num);
+ assert(driver_data->target_masks != NULL);
+ assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+ assert((unsigned int)proc_num < driver_data->target_masks_num);
if (proc_num < 0) {
/* Target all PEs */
@@ -526,7 +530,7 @@
} else {
/* Don't route interrupt if the mask hasn't been populated */
target = driver_data->target_masks[proc_num];
- assert(target != 0);
+ assert(target != 0U);
}
gicd_set_itargetsr(driver_data->gicd_base, id, target);
@@ -537,8 +541,8 @@
******************************************************************************/
void gicv2_clear_interrupt_pending(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
/* SGIs can't be cleared pending */
assert(id >= MIN_PPI_ID);
@@ -556,8 +560,8 @@
******************************************************************************/
void gicv2_set_interrupt_pending(unsigned int id)
{
- assert(driver_data);
- assert(driver_data->gicd_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicd_base != 0U);
/* SGIs can't be cleared pending */
assert(id >= MIN_PPI_ID);
@@ -578,8 +582,8 @@
{
unsigned int old_mask;
- assert(driver_data);
- assert(driver_data->gicc_base);
+ assert(driver_data != NULL);
+ assert(driver_data->gicc_base != 0U);
old_mask = gicc_read_pmr(driver_data->gicc_base);
diff --git a/drivers/arm/gic/v2/gicv2_private.h b/drivers/arm/gic/v2/gicv2_private.h
index 25600de..fadc960 100644
--- a/drivers/arm/gic/v2/gicv2_private.h
+++ b/drivers/arm/gic/v2/gicv2_private.h
@@ -50,7 +50,9 @@
static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id,
unsigned int target)
{
- mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
+ uint8_t val = target & GIC_TARGET_CPU_MASK;
+
+ mmio_write_8(base + GICD_ITARGETSR + id, val);
}
static inline void gicd_write_sgir(uintptr_t base, unsigned int val)