plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts

/*
 * Copyright (c) 2020, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
/dts-v1/;

#define	AFF	00

#include "fvp-defs.dtsi"
#undef POST
#define	POST \
	};

/ {
	compatible = "arm,ffa-core-manifest-1.0";
	#address-cells = <2>;
	#size-cells = <1>;

	attribute {
		spmc_id = <0x8000>;
		maj_ver = <0x1>;
		min_ver = <0x0>;
		exec_state = <0x0>;
		load_address = <0x0 0xfd000000>;
		entrypoint = <0x0 0xfd000000>;
		binary_size = <0x80000>;
	};

	/*
	 * temporary: This entry is added based on v2.4 hafnium and will be
	 * removed when rebased to upstream master.
	 */
	chosen {
	       linux,initrd-start = <0>;
	       linux,initrd-end = <0>;
	};

	hypervisor {
		compatible = "hafnium,hafnium";
		vm1 {
			is_ffa_partition;
			debug_name = "op-tee";
			load_address = <0xfd280000>;
		};
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		CPU_0

		/*
		 * SPMC (Hafnium) requires secondary core nodes are declared
		 * in descending order.
		 */
		CPU_3
		CPU_2
		CPU_1
	};

	/*
	 * temporary: This device-memory region is added based on v2.4 hafnium
	 * and will be removed when rebased to upstream master. As first
	 * Secure Partition no longer maps device memory.
	 */
	device-memory@21000000 {
		device_type = "device-memory";
		reg = <0x0 0x21000000 0x5f000000>;
	};

	/* 32MB of TC0_TZC_DRAM1_BASE */
	memory@fd000000 {
		device_type = "memory";
		reg = <0x0 0xfd000000 0x2000000>;
	};
};