Merge "refactor(fvp_r): remove duplicated macro definitions" into integration
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index ab0bc6f..a5fd1d6 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -101,6 +101,19 @@
| None at this time. | | | |
+--------------------------------+-------------+---------+---------------------------------------------------------+
+Build Options deprecated/removed
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Populated table provides details about build options that were removed or deprecated.
+
++-----------------------+--------------------------------+
+| Build Option | Deprecated from TF-A Version |
++=======================+================================+
+| CTX_INCLUDE_MTE_REGS | 2.11 |
++-----------------------+--------------------------------+
+| ENABLE_FEAT_MTE | 2.11 |
++-----------------------+--------------------------------+
+
--------------
*Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 5733214..a8e8d61 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -826,6 +826,10 @@
feature is enabled and can assist the Kernel in the process of
mitigation of the erratum.
+- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed
+ in r0p2.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
@@ -916,6 +920,10 @@
Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
It is fixed in r1p1.
+- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to
+ Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0
+ and r1p1. It is fixed in r1p2.
+
For Cortex-A720, the following errata build flags are defined :
- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 6c31d9d..5508ebb 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -131,7 +131,6 @@
#define MPAMVPM6_EL2 S3_4_C10_C6_6
#define MPAMVPM7_EL2 S3_4_C10_C6_7
#define MPAMVPMV_EL2 S3_4_C10_C4_1
-#define TRFCR_EL2 S3_4_C1_C2_1
#define VNCR_EL2 S3_4_C2_C2_0
#define PMSCR_EL2 S3_4_C9_C9_0
#define TFSR_EL2 S3_4_C5_C6_0
@@ -1337,6 +1336,8 @@
#define GPTBR_EL3 S3_6_C2_C1_4
#define SCXTNUM_EL2 S3_4_C13_C0_7
+#define SCXTNUM_EL1 S3_0_C13_C0_7
+#define SCXTNUM_EL0 S3_3_C13_C0_7
/*******************************************************************************
* RAS system registers
@@ -1459,10 +1460,19 @@
#define GCSCR_EL2 S3_4_C2_C5_0
#define GCSPR_EL2 S3_4_C2_C5_1
#define GCSCR_EL1 S3_0_C2_C5_0
+#define GCSCRE0_EL1 S3_0_C2_C5_2
+#define GCSPR_EL1 S3_0_C2_C5_1
+#define GCSPR_EL0 S3_3_C2_C5_1
#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6)
/*******************************************************************************
+ * FEAT_TRF - Trace Filter Control Registers
+ ******************************************************************************/
+#define TRFCR_EL2 S3_4_C1_C2_1
+#define TRFCR_EL1 S3_0_C1_C2_1
+
+/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/
#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index ab32b18..57dbc06 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -569,6 +569,8 @@
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
/* Armv8.1 VHE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
@@ -606,6 +608,7 @@
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
/* Armv8.5 MTE Registers */
@@ -656,6 +659,9 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 74790d1..4f11ad2 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -191,10 +191,35 @@
#define CTX_TCR2_REGS_END CTX_S2POE_REGS_END
#endif /* ENABLE_FEAT_TCR2 */
+#if ENABLE_TRF_FOR_NS
+#define CTX_TRFCR_EL1 (CTX_TCR2_REGS_END + U(0x0))
+#define CTX_TRF_REGS_END (CTX_TCR2_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_TRF_REGS_END CTX_TCR2_REGS_END
+#endif /* ENABLE_TRF_FOR_NS */
+
+#if ENABLE_FEAT_CSV2_2
+#define CTX_SCXTNUM_EL0 (CTX_TRF_REGS_END + U(0x0))
+#define CTX_SCXTNUM_EL1 (CTX_TRF_REGS_END + U(0x8))
+#define CTX_CSV2_2_REGS_END (CTX_TRF_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_CSV2_2_REGS_END CTX_TRF_REGS_END
+#endif /* ENABLE_FEAT_CSV2_2 */
+
+#if ENABLE_FEAT_GCS
+#define CTX_GCSCR_EL1 (CTX_CSV2_2_REGS_END + U(0x0))
+#define CTX_GCSCRE0_EL1 (CTX_CSV2_2_REGS_END + U(0x8))
+#define CTX_GCSPR_EL1 (CTX_CSV2_2_REGS_END + U(0x10))
+#define CTX_GCSPR_EL0 (CTX_CSV2_2_REGS_END + U(0x18))
+#define CTX_GCS_REGS_END (CTX_CSV2_2_REGS_END + U(0x20)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_GCS_REGS_END CTX_CSV2_2_REGS_END
+#endif /* ENABLE_FEAT_GCS */
+
/*
- * End of system registers.
+ * End of EL1 system registers.
*/
-#define CTX_EL1_SYSREGS_END CTX_TCR2_REGS_END
+#define CTX_EL1_SYSREGS_END CTX_GCS_REGS_END
/*******************************************************************************
* Constants that allow assembler code to access members of and the 'fp_regs'
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index a5be22d..16be161 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -94,6 +94,27 @@
check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
+workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106
+ mov x0, #3
+ msr CORTEX_A715_CPUPSELR_EL3, x0
+ isb
+ ldr x0, =0xd503339f
+ msr CORTEX_A715_CPUPOR_EL3, x0
+ ldr x0, =0xfffff3ff
+ msr CORTEX_A715_CPUPMR_EL3, x0
+ mov x0, #1
+ orr x0, x0, #(3<<4)
+ orr x0, x0, #(0xf<<6)
+ orr x0, x0, #(1<<13)
+ orr x0, x0, #(1<<20)
+ orr x0, x0, #(1<<22)
+ orr x0, x0, #(1<<31)
+ orr x0, x0, #(1<<50)
+ msr CORTEX_A715_CPUPCR_EL3, x0
+workaround_reset_end cortex_a715, ERRATUM(2728106)
+
+check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1)
+
workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 7619f9c..29c7a4a 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end cortex_x4, ERRATUM(2740089)
+
+check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
+
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
@@ -53,6 +60,9 @@
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
+ apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
+
isb
ret
endfunc cortex_x4_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 872f6c7..5478e57 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -823,6 +823,10 @@
# cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_X4_2701112
+# Flag to apply erratum 2740089 workaround during powerdown. This erratum
+# applies to all revisions <= r0p1 of the Cortex-X4 cpu, it is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_2740089
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
@@ -940,6 +944,10 @@
# only to revision r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2561034
+# Flag to apply erratum 2728106 workaround during reset. This erratum applies
+# only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_A715_2728106
+
# Flag to apply erratum 2926083 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2926083
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index be75e53..35c98f5 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1549,6 +1549,28 @@
write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1());
}
#endif
+
+#if ENABLE_TRF_FOR_NS
+ if (is_feat_trf_supported()) {
+ write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+ if (is_feat_csv2_2_supported()) {
+ write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0());
+ write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_GCS
+ if (is_feat_gcs_supported()) {
+ write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1());
+ write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1());
+ write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1());
+ write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0());
+ }
+#endif
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@@ -1636,6 +1658,28 @@
write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1));
}
#endif
+
+#if ENABLE_TRF_FOR_NS
+ if (is_feat_trf_supported()) {
+ write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+ if (is_feat_csv2_2_supported()) {
+ write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0));
+ write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_GCS
+ if (is_feat_gcs_supported()) {
+ write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1));
+ write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1));
+ write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1));
+ write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0));
+ }
+#endif
}
/*******************************************************************************
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index 16187ef..ed95bc6 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -88,8 +88,8 @@
#
# We go v8.0 by default and will enable all features we want
-ARM_ARCH_MAJOR := 8
-ARM_ARCH_MINOR := 0
+ARM_ARCH_MAJOR ?= 8
+ARM_ARCH_MINOR ?= 0
# 8.0
ENABLE_FEAT_CSV2_2 := 2
@@ -106,6 +106,7 @@
# 8.4
ENABLE_FEAT_SEL2 := 2
ENABLE_FEAT_DIT := 2
+ENABLE_TRF_FOR_NS := 2
# 8.5
ENABLE_FEAT_RNG := 2
@@ -114,6 +115,7 @@
ENABLE_FEAT_SB := 0
# 8.6
+ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
# 8.7
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index a627ed7..0a70cc2 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -161,7 +161,7 @@
unsigned int plat_get_syscnt_freq2(void)
{
- return SYS_COUNTER_FREQ_IN_TICKS;
+ return read_cntfrq_el0();
}
/*******************************************************************************
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index cafee6f..068c69c 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -5,6 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <string.h>
+
#include <platform_def.h>
#include <arch_helpers.h>
@@ -226,46 +228,76 @@
uint64_t checksum;
uintptr_t base;
uint64_t size;
+ size_t num_banks = 1;
+ size_t num_consoles = 1;
struct ns_dram_bank *bank_ptr;
+ struct console_info *console_ptr;
assert(manifest != NULL);
manifest->version = RMMD_MANIFEST_VERSION;
manifest->padding = 0U; /* RES0 */
manifest->plat_data = (uintptr_t)NULL;
- manifest->plat_dram.num_banks = 1;
+ manifest->plat_dram.num_banks = num_banks;
+ manifest->plat_console.num_consoles = num_consoles;
/*
- * Array ns_dram_banks[] follows ns_dram_info structure:
+ * Boot manifest structure illustration:
*
- * +-----------------------------------+
- * | offset | field | comment |
- * +----------+-----------+------------+
- * | 0 | version | 0x00000002 |
- * +----------+-----------+------------+
- * | 4 | padding | 0x00000000 |
- * +----------+-----------+------------+
- * | 8 | plat_data | NULL |
- * +----------+-----------+------------+
- * | 16 | num_banks | |
- * +----------+-----------+ |
- * | 24 | banks | plat_dram |
- * +----------+-----------+ |
- * | 32 | checksum | |
- * +----------+-----------+------------+
- * | 40 | base 0 | |
- * +----------+-----------+ bank[0] |
- * | 48 | size 0 | |
- * +----------+-----------+------------+
+ * +----------------------------------------+
+ * | offset | field | comment |
+ * +----------+--------------+--------------+
+ * | 0 | version | 0x00000003 |
+ * +----------+--------------+--------------+
+ * | 4 | padding | 0x00000000 |
+ * +----------+--------------+--------------+
+ * | 8 | plat_data | NULL |
+ * +----------+--------------+--------------+
+ * | 16 | num_banks | |
+ * +----------+--------------+ |
+ * | 24 | banks | plat_dram |
+ * +----------+--------------+ |
+ * | 32 | checksum | |
+ * +----------+--------------+--------------+
+ * | 40 | num_consoles | |
+ * +----------+--------------+ |
+ * | 48 | consoles | plat_console |
+ * +----------+--------------+ |
+ * | 56 | checksum | |
+ * +----------+--------------+--------------+
+ * | 64 | base 0 | |
+ * +----------+--------------+ bank[0] |
+ * | 72 | size 0 | |
+ * +----------+--------------+--------------+
+ * | 80 | base | |
+ * +----------+--------------+ |
+ * | 88 | map_pages | |
+ * +----------+--------------+ |
+ * | 96 | name | |
+ * +----------+--------------+ consoles[0] |
+ * | 104 | clk_in_hz | |
+ * +----------+--------------+ |
+ * | 112 | baud_rate | |
+ * +----------+--------------+ |
+ * | 120 | flags | |
+ * +----------+--------------+--------------+
*/
bank_ptr = (struct ns_dram_bank *)
- ((uintptr_t)&manifest->plat_dram.checksum +
- sizeof(manifest->plat_dram.checksum));
+ (((uintptr_t)manifest) + sizeof(*manifest));
+
+ console_ptr = (struct console_info *)
+ ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
manifest->plat_dram.banks = bank_ptr;
+ manifest->plat_console.consoles = console_ptr;
+
+ /* Ensure the manifest is not larger than the shared buffer */
+ assert((sizeof(struct rmm_manifest) +
+ (sizeof(struct console_info) * num_consoles) +
+ (sizeof(struct ns_dram_bank) * num_banks)) <= RMM_SHARED_SIZE);
/* Calculate checksum of plat_dram structure */
- checksum = 1 + (uint64_t)bank_ptr;
+ checksum = num_banks + (uint64_t)bank_ptr;
base = NS_DRAM0_BASE;
size = NS_DRAM0_SIZE;
@@ -276,6 +308,26 @@
/* Checksum must be 0 */
manifest->plat_dram.checksum = ~checksum + 1UL;
+ /* Calculate the checksum of the plat_consoles structure */
+ checksum = num_consoles + (uint64_t)console_ptr;
+
+ /* Zero out the console info struct */
+ memset((void *)console_ptr, 0, sizeof(struct console_info) * num_consoles);
+
+ console_ptr[0].map_pages = 1;
+ console_ptr[0].base = PLAT_QEMU_BOOT_UART_BASE;
+ console_ptr[0].clk_in_hz = PLAT_QEMU_BOOT_UART_CLK_IN_HZ;
+ console_ptr[0].baud_rate = PLAT_QEMU_CONSOLE_BAUDRATE;
+
+ strlcpy(console_ptr[0].name, "pl011", sizeof(console_ptr[0].name));
+
+ /* Update checksum */
+ checksum += console_ptr[0].base + console_ptr[0].map_pages +
+ console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+
+ /* Checksum must be 0 */
+ manifest->plat_console.checksum = ~checksum + 1UL;
+
return 0;
}
#endif /* ENABLE_RME */
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 4e0b50a..95620d3 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -302,11 +302,6 @@
#define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0
/*
- * System counter
- */
-#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
-
-/*
* Maximum size of Event Log buffer used in Measured Boot Event Log driver
*/
#define PLAT_EVENT_LOG_MAX_SIZE UL(0x400)
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index e8f0344..d230095 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -266,11 +266,6 @@
#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
#define PLAT_QEMU_DT_MAX_SIZE 0x100000
-/*
- * System counter
- */
-#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
-
#if SPM_MM
#define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE
#define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000)