Merge "feat(cpufeat): initialize HFG*_EL2 registers" into integration
diff --git a/.gitignore b/.gitignore
index ac9a11d..e07d997 100644
--- a/.gitignore
+++ b/.gitignore
@@ -22,6 +22,7 @@
tools/renesas/rzg_layout_create/*.elf
tools/fiptool/fiptool
tools/fiptool/fiptool.exe
+tools/memory/memory/__pycache__/
tools/cert_create/src/*.o
tools/cert_create/src/**/*.o
tools/cert_create/cert_create
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 6207066..7b6a1f5 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -15,6 +15,7 @@
python: "3.10"
apt_packages:
- plantuml
+ - librsvg2-bin
jobs:
post_create_environment:
- pip install poetry=="1.3.2"
@@ -24,3 +25,8 @@
sphinx:
configuration: docs/conf.py
+
+# Auxiliary formats to export to (in addition to the default HTML output).
+formats:
+ - pdf
+
diff --git a/Makefile b/Makefile
index 4b96be1..8e2fd81 100644
--- a/Makefile
+++ b/Makefile
@@ -139,6 +139,7 @@
SPTOOLPATH ?= tools/sptool
SPTOOL ?= ${SPTOOLPATH}/sptool.py
SP_MK_GEN ?= ${SPTOOLPATH}/sp_mk_generator.py
+SP_DTS_LIST_FRAGMENT ?= ${BUILD_PLAT}/sp_list_fragment.dts
# Variables for use with ROMLIB
ROMLIBPATH ?= lib/romlib
@@ -623,6 +624,15 @@
# over the sources.
endif #(SPD=none)
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq (${SPD},spmd)
+ $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
+endif
+ifeq ($(SPMC_AT_EL3),1)
+ $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
+endif
+endif
+
ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
ifeq (${SPD},none)
ifeq (${ENABLE_RME},0)
@@ -758,8 +768,8 @@
ifeq (${AARCH32_SP_MAKE},)
$(error Error: No bl32/${AARCH32_SP}/${AARCH32_SP}.mk located)
endif
- $(info Including ${AARCH32_SP_MAKE})
- include ${AARCH32_SP_MAKE}
+ $(info Including ${AARCH32_SP_MAKE})
+ include ${AARCH32_SP_MAKE}
endif
endif #(ARCH=aarch32)
@@ -1181,6 +1191,7 @@
SPM_MM \
SPMC_AT_EL3 \
SPMD_SPM_AT_SEL2 \
+ ENABLE_SPMD_LP \
TRUSTED_BOARD_BOOT \
USE_COHERENT_MEM \
USE_DEBUGFS \
@@ -1397,6 +1408,7 @@
CONDITIONAL_CMO \
IMPDEF_SYSREG_TRAP \
SVE_VECTOR_LEN \
+ ENABLE_SPMD_LP \
)))
ifeq (${SANITIZE_UB},trap)
@@ -1542,8 +1554,8 @@
# Add Secure Partition packages
ifeq (${NEED_SP_PKG},yes)
-$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
- ${Q}${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT}
+$(BUILD_PLAT)/sp_gen.mk : ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
+ ${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} ${SP_DTS_LIST_FRAGMENT}
sp: $(DTBS) $(BUILD_PLAT)/sp_gen.mk $(SP_PKGS)
@${ECHO_BLANK_LINE}
@echo "Built SP Images successfully"
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index f102967..693dd4b 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,11 +62,8 @@
* The Cold boot/Reset entrypoint for SP_MIN
*/
func sp_min_entrypoint
-#if !RESET_TO_SP_MIN
/* ---------------------------------------------------------------
- * Preceding bootloader has populated r0 with a pointer to a
- * 'bl_params_t' structure & r1 with a pointer to platform
- * specific structure
+ * Stash the previous bootloader arguments r0 - r3 for later use.
* ---------------------------------------------------------------
*/
mov r9, r0
@@ -74,6 +71,7 @@
mov r11, r2
mov r12, r3
+#if !RESET_TO_SP_MIN
/* ---------------------------------------------------------------------
* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
@@ -91,11 +89,6 @@
_init_c_runtime=1 \
_exception_vectors=sp_min_vector_table \
_pie_fixup_size=FIXUP_SIZE
-
- /* ---------------------------------------------------------------------
- * Relay the previous bootloader's arguments to the platform layer
- * ---------------------------------------------------------------------
- */
#else
/* ---------------------------------------------------------------------
* For RESET_TO_SP_MIN systems which have a programmable reset address,
@@ -111,24 +104,16 @@
_init_c_runtime=1 \
_exception_vectors=sp_min_vector_table \
_pie_fixup_size=FIXUP_SIZE
-
- /* ---------------------------------------------------------------------
- * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
- * to run so there's no argument to relay from a previous bootloader.
- * Zero the arguments passed to the platform layer to reflect that.
- * ---------------------------------------------------------------------
- */
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
-
#endif /* RESET_TO_SP_MIN */
#if SP_MIN_WITH_SECURE_FIQ
route_fiq_to_sp_min r4
#endif
+ /* ---------------------------------------------------------------------
+ * Relay the previous bootloader's arguments to the platform layer
+ * ---------------------------------------------------------------------
+ */
mov r0, r9
mov r1, r10
mov r2, r11
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 0b7bc57..065468c 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -17,6 +17,7 @@
bl32/sp_min/aarch32/entrypoint.S \
common/runtime_svc.c \
plat/common/aarch32/plat_sp_min_common.c\
+ services/arm_arch_svc/arm_arch_svc_setup.c \
services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index f050160..26cf207 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -134,6 +134,7 @@
assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
INFO("SP_MIN: Preparing exit to normal world\n");
+ print_entry_point_info(next_image_info);
psci_prepare_next_non_secure_ctx(next_image_info);
smc_set_next_ctx(NON_SECURE);
diff --git a/changelog.yaml b/changelog.yaml
index 47cfc1e..3534cb0 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -628,6 +628,13 @@
- plat/zynqmp
- plat/xilinx/zynqmp
+ - title: Nuvoton
+ scope: nuvoton
+
+ subsections:
+ - title: npcm845x
+ scope: npcm845x
+
- title: Bootloader Images
scope: bl
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2aa0c5c..a1ffc39 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -203,7 +203,7 @@
check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
/* v8.9 features */
- check_feature(ENABLE_FEAT_TCR2, read_feat_tcrx_id_field(),
+ check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
"TCR2", 1, 1);
check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
"S2PIE", 1, 1);
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 3de09c7..20c56fd 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -585,6 +585,20 @@
:|F|: drivers/marvell/
:|F|: tools/marvell/
+Nuvoton npcm845x platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
+:|G|: `hilamirandakuzi1`_
+:|M|: Margarita Glushkin <rutigl@gmail.com>
+:|G|: `rutigl`_
+:|M|: Avi Fishman <avi.fishman@nuvoton.com>
+:|G|: `avifishman`_
+:|F|: docs/plat/npcm845x.rst
+:|F|: drivers/nuvoton/
+:|F|: include/drivers/nuvoton/
+:|F|: include/plat/nuvoton/
+:|F|: plat/nuvoton/
+
NVidia platform ports
^^^^^^^^^^^^^^^^^^^^^
:|M|: Varun Wadekar <vwadekar@nvidia.com>
@@ -1002,3 +1016,6 @@
.. _Neal-liu: https://github.com/neal-liu
.. _amit-nagal: https://github.com/amit-nagal
.. _Akshay-Belsare: https://github.com/Akshay-Belsare
+.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
+.. _rutigl: https://github.com/rutigl
+.. _avifishman: https://github.com/avifishman
diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst
index 919eea5..f228e6b 100644
--- a/docs/components/realm-management-extension.rst
+++ b/docs/components/realm-management-extension.rst
@@ -157,7 +157,7 @@
git clone https://git.trustedfirmware.org/TF-A/tf-a-tests.git
cd tf-a-tests
- make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 all pack_realm
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 ENABLE_REALM_PAYLOAD_TESTS=1 all
This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged
and **sp_layout.json** in the **build/fvp/debug** directory.
diff --git a/docs/conf.py b/docs/conf.py
index 345f53b..9e7a5f8 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -26,7 +26,7 @@
"myst_parser",
"sphinx.ext.autosectionlabel",
"sphinxcontrib.plantuml",
- "sphinxcontrib.inkscapeconverter",
+ "sphinxcontrib.rsvgconverter",
]
# Add any paths that contain templates here, relative to this directory.
@@ -108,4 +108,5 @@
latex_elements = {
"maxlistdepth": "10",
"pointsize": "11pt",
+ "extraclassoptions": "openany"
}
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index df0cfc0..69d3722 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -117,7 +117,8 @@
- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
- r0p4 and onwards, this errata is enabled by default in hardware.
+ r0p4 and onwards, this errata is enabled by default in hardware. Identical to
+ ``A53_DISABLE_NON_TEMPORAL_HINT``.
- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
to Cortex-A53 CPU. This needs to be enabled for some variants of revision
@@ -601,47 +602,50 @@
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
- r0p1.
+ CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.
- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
+- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
in r0p3.
@@ -651,6 +655,10 @@
interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
It is fixed in r0p3.
+- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 8130d7d..c4e5213 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst
@@ -204,6 +204,28 @@
In FVP, Non volatile counters get measured and recorded as Critical data
using the backend via this interface.
+#. **Function : plat_mboot_measure_key()**
+
+ .. code-block:: c
+
+ int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len);
+
+ - This function is used by the platform to measure the passed key and
+ publicise it using any of the supported backends.
+ - The authentication module within the trusted boot framework calls this
+ function for every ROTPK involved in verifying the signature of a root
+ certificate and for every subsidiary key that gets extracted from a key
+ certificate for later authentication of a content certificate.
+ - A cookie, passed as the first argument, serves as a key-OID pointer
+ associated with the public key data, passed as the second argument.
+ - Public key data size is passed as the third argument to this function.
+ - This function must return 0 on success, a signed integer error code
+ otherwise.
+ - In FVP platform, this function is used to calculate the hash of the given
+ key and forward this hash to RSS alongside the measurement of the image
+ which the key signs.
+
--------------
*Copyright (c) 2023, Arm Limited. All rights reserved.*
diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rss.rst
index 2be8067..18d5436 100644
--- a/docs/design_documents/rss.rst
+++ b/docs/design_documents/rss.rst
@@ -134,12 +134,10 @@
- ``Delegated attestation``: Query the platform attestation token and derive a
delegated attestation key. More info on the delegated attestation service
in RSS can be found in the ``delegated_attestation_integration_guide`` [4]_ .
-- ``OTP assets management``: RSS provides access for AP to assets in OTP.
- These are keys for image signature verification and non-volatile counters
- for anti-rollback protection. Only RSS has direct access to the OTP. Public
- keys used by AP during the trusted boot process can be requested from RSS.
- Furthermore, AP can request RSS to increase a non-volatile counter. Please
- refer to the ``RSS key management`` [5]_ document for more details.
+- ``OTP assets management``: Public keys used by AP during the trusted boot
+ process can be requested from RSS. Furthermore, AP can request RSS to
+ increase a non-volatile counter. Please refer to the
+ ``RSS key management`` [5]_ document for more details.
Runtime service API
^^^^^^^^^^^^^^^^^^^
@@ -262,7 +260,8 @@
- ``SW type``: Optional. Short text description (e.g.: BL1, BL2, BL31, etc.)
.. Note::
- Signer-id and version info is not implemented in TF-A yet.
+ Version info is not implemented in TF-A yet.
+
The caller must specify in which measurement slot to extend a certain
measurement and metadata. A measurement slot can be extended by multiple
@@ -321,9 +320,38 @@
size_t version_size;
uint8_t sw_type[SW_TYPE_MAX_SIZE];
size_t sw_type_size;
+ void *pk_oid;
bool lock_measurement;
};
+Signer-ID API
+^^^^^^^^^^^^^
+
+This function calculates the hash of a public key (signer-ID) using the
+``Measurement algorithm`` and stores it in the ``rss_mboot_metadata`` field
+named ``signer_id``.
+Prior to calling this function, the caller must ensure that the ``signer_id``
+field points to the zero-filled buffer.
+
+Defined here:
+
+- ``include/drivers/measured_boot/rss/rss_measured_boot.h``
+
+.. code-block:: c
+
+ int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+ const void *pk_oid,
+ const void *pk_ptr,
+ size_t pk_len)
+
+
+- First parameter is the pointer to the ``rss_mboot_metadata`` structure.
+- Second parameter is the pointer to the key-OID of the public key.
+- Third parameter is the pointer to the public key buffer.
+- Fourth parameter is the size of public key buffer.
+- This function returns 0 on success, a signed integer error code
+ otherwise.
+
Build time config options
^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -361,8 +389,8 @@
INFO: Image id=24 loaded: 0x4001300 - 0x400153a
INFO: Measured boot extend measurement:
INFO: - slot : 7
- INFO: - signer_id : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ INFO: - signer_id : b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 73
+ INFO: : e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da
INFO: - version :
INFO: - version_size: 0
INFO: - sw_type : TB_FW_CONFIG
@@ -377,8 +405,8 @@
INFO: Image id=1 loaded: 0x404d000 - 0x406412a
INFO: Measured boot extend measurement:
INFO: - slot : 8
- INFO: - signer_id : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ INFO: - signer_id : b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 73
+ INFO: : e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da
INFO: - version :
INFO: - version_size: 0
INFO: - sw_type : BL_2
@@ -483,31 +511,31 @@
INFO: a2 6a df 34 c3 29 48 9a dc 38 04 67 31 2e 35 2e
INFO: 30 2b 30 01 60 02 58 20 b8 01 65 a7 78 8b c6 59
INFO: 42 8d 33 10 85 d1 49 0a dc 9e c3 ee df 85 1b d2
- INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 04 60 01 6a
+ INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 b0 f3 82 09
+ INFO: 12 97 d8 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2
+ INFO: 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6a
INFO: 46 57 5f 43 4f 4e 46 49 47 00 02 58 20 21 9e a0
INFO: 13 82 e6 d7 97 5a 11 13 a3 5f 45 39 68 b1 d9 a3
INFO: ea 6a ab 84 23 3b 8c 06 16 98 20 ba b9 a4 05 58
- INFO: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49
+ INFO: 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32
+ INFO: 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a
+ INFO: da 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49
INFO: 47 00 02 58 20 41 39 f6 c2 10 84 53 c5 17 ae 9a
INFO: e5 be c1 20 7b cc 24 24 f3 9d 20 a8 fb c7 b3 10
- INFO: e3 ee af 1b 05 a4 05 58 20 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 04 60 01 65 42 4c 5f
+ INFO: e3 ee af 1b 05 a4 05 58 20 b0 f3 82 09 12 97 d8
+ INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6
+ INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 65 42 4c 5f
INFO: 32 00 02 58 20 5c 96 20 e1 e3 3b 0f 2c eb c1 8e
INFO: 1a 02 a6 65 86 dd 34 97 a7 4c 98 13 bf 74 14 45
- INFO: 2d 30 28 05 c3 a4 05 58 20 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 04 60 01 6e 53 45 43
+ INFO: 2d 30 28 05 c3 a4 05 58 20 b0 f3 82 09 12 97 d8
+ INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6
+ INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6e 53 45 43
INFO: 55 52 45 5f 52 54 5f 45 4c 33 00 02 58 20 f6 fb
INFO: 62 99 a5 0c df db 02 0b 72 5b 1c 0b 63 6e 94 ee
INFO: 66 50 56 3a 29 9c cb 38 f0 ec 59 99 d4 2e a4 05
- INFO: 58 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00
+ INFO: 58 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec
+ INFO: 32 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22
+ INFO: 9a da 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00
INFO: 02 58 20 98 5d 87 21 84 06 33 9d c3 1f 91 f5 68
INFO: 8d a0 5a f0 d7 7e 20 51 ce 3b f2 a5 c3 05 2e 3c
INFO: 8b 52 31 19 01 09 78 1c 68 74 74 70 3a 2f 2f 61
@@ -559,31 +587,31 @@
"MEASUREMENT_VALUE": "b'B80165A7788BC659428D331085D1490ADC9EC3EEDF851BD2F073736A0C0711B8'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "FW_CONFIG\u0000",
"MEASUREMENT_VALUE": "b'219EA01382E6D7975A1113A35F453968B1D9A3EA6AAB84233B8C06169820BAB9'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "TB_FW_CONFIG\u0000",
"MEASUREMENT_VALUE": "b'4139F6C2108453C517AE9AE5BEC1207BCC2424F39D20A8FBC7B310E3EEAF1B05'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "BL_2\u0000",
"MEASUREMENT_VALUE": "b'5C9620E1E33B0F2CEBC18E1A02A66586DD3497A74C9813BF7414452D302805C3'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "SECURE_RT_EL3\u0000",
"MEASUREMENT_VALUE": "b'F6FB6299A50CDFDB020B725B1C0B636E94EE6650563A299CCB38F0EC5999D42E'"
},
{
- "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'",
+ "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
"SW_COMPONENT_VERSION": "",
"SW_COMPONENT_TYPE": "HW_CONFIG\u0000",
"MEASUREMENT_VALUE": "b'985D87218406339DC31F91F5688DA05AF0D77E2051CE3BF2A5C3052E3C8B5231'"
@@ -595,6 +623,57 @@
"CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org"
}
+RSS OTP Assets Management
+-------------------------
+
+RSS provides access for AP to assets in OTP, which include keys for image
+signature verification and non-volatile counters for anti-rollback protection.
+
+Non-Volatile Counter API
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+AP/RSS interface for retrieving and incrementing non-volatile counters API is
+as follows.
+
+Defined here:
+
+- ``include/lib/psa/rss_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rss_platform_nv_counter_increment(uint32_t counter_id)
+
+ psa_status_t rss_platform_nv_counter_read(uint32_t counter_id,
+ uint32_t size, uint8_t *val)
+
+Through this service, we can read/increment any of the 3 non-volatile
+counters used on an Arm CCA platform:
+
+- ``Non-volatile counter for CCA firmware (BL2, BL31, RMM).``
+- ``Non-volatile counter for secure firmware.``
+- ``Non-volatile counter for non-secure firmware.``
+
+Public Key API
+^^^^^^^^^^^^^^
+
+AP/RSS interface for reading the ROTPK is as follows.
+
+Defined here:
+
+- ``include/lib/psa/rss_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rss_platform_key_read(enum rss_key_id_builtin_t key,
+ uint8_t *data, size_t data_size, size_t *data_length)
+
+Through this service, we can read any of the 3 ROTPKs used on an
+Arm CCA platform:
+
+- ``ROTPK for CCA firmware (BL2, BL31, RMM).``
+- ``ROTPK for secure firmware.``
+- ``ROTPK for non-secure firmware.``
+
References
----------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index c410a8e..2c018c3 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -519,6 +519,20 @@
Firmware as error. It can take the value 1 (flag the use of deprecated
APIs as error) or 0. The default is 0.
+- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
+ configure an Arm® Ethos™-N NPU. To use this service the target platform's
+ ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
+ the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
+ only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
+
+- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
+ Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and
+ ``TRUSTED_BOARD_BOOT`` to be enabled.
+
+- ``ETHOSN_NPU_FW``: location of the NPU firmware binary
+ (```ethosn.bin```). This firmware image will be included in the FIP and
+ loaded at runtime.
+
- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
targeted at EL3. When set ``0`` (default), no exceptions are expected or
handled at EL3, and a panic will result. The exception to this rule is when
@@ -899,6 +913,12 @@
support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
extension).
+- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM
+ Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support
+ for logical partitions in EL3, managed by the SPMD as defined in the FF-A
+ 1.2 specification. This flag is disabled by default. This flag must not be
+ used if ``SPMC_AT_EL3`` is enabled. This is an experimental feature.
+
- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Partition Manager (SPM) implementation. The default value is ``0``
(disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index aa8c2bb..50fff57 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -74,6 +74,26 @@
poetry run make -C docs help
+To build the documentation in PDF format, additionally ensure that the following
+packages are installed:
+
+- FreeSerif font
+- latexmk
+- librsvg2-bin
+- xelatex
+- xindy
+
+Below is an example set of instructions to install the required packages
+(tested on Ubuntu):
+
+.. code:: shell
+
+ sudo apt install fonts-freefont-otf latexmk librsvg2-bin texlive-xetex xindy
+
+Once all the dependencies are installed, run the command ``poetry run make -C
+docs latexpdf`` to build the documentation. Output from the build process
+(``trustedfirmware-a.pdf``) can be found in ``docs/build/latex``.
+
Building rendered documentation from Poetry's virtual environment
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 3179267..e81052b 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -95,20 +95,6 @@
platforms. If this option is specified, then the path to the CryptoCell
SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
-- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
- configure an Arm® Ethos™-N NPU. To use this service the target platform's
- ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
- the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
- only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
-
-- ``ARM_ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
- Arm® Ethos™-N NPU. Requires ``ARM_ETHOSN_NPU_DRIVER`` and
- ``TRUSTED_BOARD_BOOT`` to be enabled.
-
-- ``ARM_ETHOSN_NPU_FW``: location of the NPU firmware binary
- (```ethosn.bin```). This firmware image will be included in the FIP and
- loaded at runtime.
-
- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
the various partitions present in the GPT image. This support is available
only for the BL2 component, and it is disabled by default.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index fe2cc44..2eec68c 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -28,6 +28,7 @@
imx8
imx8m
imx9
+ npcm845x
nxp/index
poplar
qemu
diff --git a/docs/plat/npcm845x.rst b/docs/plat/npcm845x.rst
new file mode 100644
index 0000000..91dbfd9
--- /dev/null
+++ b/docs/plat/npcm845x.rst
@@ -0,0 +1,21 @@
+Nuvoton NPCM845X
+================
+
+Nuvoton NPCM845X is the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC.
+
+The Nuvoton Arbel NPCM845X SoC is a fourth-generation BMC.
+The NPCM845X computing subsystem comprises a quadcore Arm Cortex-A35 CPU.
+
+This SoC includes secured components, i.e., bootblock stored in ROM,
+u-boot, OPTEE-OS, trusted-firmware-a and Linux.
+Every stage is measured and validated by the bootblock.
+This SoC was tested on the Arbel NPCM845X evaluation board.
+
+
+How to Build
+------------
+
+.. code:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=npcm845x all SPD=opteed
+
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index f074021..5a017ce 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -591,32 +591,32 @@
If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support
enabled, the following constants and configuration must also be defined:
-- **ARM_ETHOSN_NPU_PROT_FW_NSAID**
+- **ETHOSN_NPU_PROT_FW_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
access the protected memory that contains the NPU's firmware.
-- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID**
+- **ETHOSN_NPU_PROT_DATA_RW_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read/write access to the protected memory that contains inference data.
-- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID**
+- **ETHOSN_NPU_PROT_DATA_RO_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read-only access to the protected memory that contains inference data.
-- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID**
+- **ETHOSN_NPU_NS_RW_DATA_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read/write access to the non-protected memory.
-- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID**
+- **ETHOSN_NPU_NS_RO_DATA_NSAID**
Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
read-only access to the non-protected memory.
-- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT**
+- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT**
Defines the physical address range that the NPU's firmware will be loaded
into and executed from.
@@ -634,10 +634,10 @@
- Add MMU mappings such that:
- BL2 can write the NPU firmware into the region defined by
- ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT``
+ ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT``
- BL31 (SiP service) can read the NPU firmware from the same region
-- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
+- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
loaded by BL2.
Please see the reference implementation code for the Juno platform as an example.
diff --git a/drivers/arm/ethosn/ethosn_big_fw.c b/drivers/arm/ethosn/ethosn_big_fw.c
index 628f5d9..ea48a24 100644
--- a/drivers/arm/ethosn/ethosn_big_fw.c
+++ b/drivers/arm/ethosn/ethosn_big_fw.c
@@ -12,7 +12,7 @@
#define ETHOSN_BIG_FW_MAGIC ('E' | ('N' << 8) | ('F' << 16) | ('W' << 24))
/* Supported big firmware version */
-#define ETHOSN_BIG_FW_VERSION_MAJOR 11
+#define ETHOSN_BIG_FW_VERSION_MAJOR 12
#define ETHOSN_ARCH_VER_MAJOR_MASK U(0xF000)
#define ETHOSN_ARCH_VER_MAJOR_SHIFT U(0xC)
diff --git a/drivers/arm/ethosn/ethosn_npu.mk b/drivers/arm/ethosn/ethosn_npu.mk
new file mode 100644
index 0000000..4a31b59
--- /dev/null
+++ b/drivers/arm/ethosn/ethosn_npu.mk
@@ -0,0 +1,49 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Arm(R) Ethos(TM)-N NPU SiP service
+ETHOSN_NPU_DRIVER := 0
+
+$(eval $(call assert_boolean,ETHOSN_NPU_DRIVER))
+$(eval $(call add_define,ETHOSN_NPU_DRIVER))
+
+#Ethos-N NPU TZMP1
+ETHOSN_NPU_TZMP1 := 0
+$(eval $(call assert_boolean,ETHOSN_NPU_TZMP1))
+$(eval $(call add_define,ETHOSN_NPU_TZMP1))
+ifeq (${ETHOSN_NPU_TZMP1},1)
+ ifeq (${ETHOSN_NPU_DRIVER},0)
+ $(error "ETHOSN_NPU_TZMP1 is only available if ETHOSN_NPU_DRIVER=1)
+ endif
+ ifeq (${PLAT},juno)
+ $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
+ else
+ $(error "ETHOSN_NPU_TZMP1 only supported on Juno platform, not ", ${PLAT})
+ endif
+
+ ifeq (${TRUSTED_BOARD_BOOT},0)
+ # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
+ # tampered with, which is required to protect the confidentiality of protected
+ # inference data.
+ $(error "ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
+ endif
+
+ # We need the FW certificate and key certificate
+ $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
+ $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
+ # We need the firmware to be built into the FIP
+ $(eval $(call TOOL_ADD_IMG,ETHOSN_NPU_FW,--npu-fw))
+
+ # Needed for our OIDs to be available in tbbr_cot_bl2.c
+ $(eval $(call add_define, PLAT_DEF_OID))
+
+ # Needed so that UUIDs from the FIP are available in BL2
+ $(eval $(call add_define,PLAT_DEF_FIP_UUID))
+
+ PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
+ PLAT_INCLUDES += -Iinclude/drivers/arm/
+ PLAT_INCLUDES += -I${PLAT_DIR}fip
+endif
diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c
index 85a12c5..42158e4 100644
--- a/drivers/arm/ethosn/ethosn_smc.c
+++ b/drivers/arm/ethosn/ethosn_smc.c
@@ -17,9 +17,9 @@
#include <platform_def.h>
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#include "ethosn_big_fw.h"
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
/*
* Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
@@ -51,11 +51,11 @@
#define SEC_AUXCTLR_STASHING_VAL U(0xA5000000)
#define SEC_DEL_REG U(0x0004)
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#define SEC_DEL_VAL U(0x808)
#else
#define SEC_DEL_VAL U(0x80C)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#define SEC_DEL_EXCC_MASK U(0x20)
#define SEC_SECCTLR_REG U(0x0010)
@@ -69,7 +69,7 @@
#define SEC_SYSCTRL0_CPU_WAIT U(1)
#define SEC_SYSCTRL0_SLEEPING U(1U << 4)
#define SEC_SYSCTRL0_INITVTOR_MASK U(0x1FFFFF80)
-#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
+#define SEC_SYSCTRL0_SOFT_RESET U(1U << 29)
#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
#define SEC_SYSCTRL1_REG U(0x001C)
@@ -104,8 +104,8 @@
#define TO_EXTEND_ADDR(addr) \
((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK)
-#if ARM_ETHOSN_NPU_TZMP1
-CASSERT(ARM_ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
+#if ETHOSN_NPU_TZMP1
+CASSERT(ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
static const struct ethosn_big_fw *big_fw;
#define FW_INITVTOR_ADDR(big_fw) \
@@ -115,7 +115,7 @@
#define SYSCTRL0_INITVTOR_ADDR(value) \
(value & SEC_SYSCTRL0_INITVTOR_MASK)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
static bool ethosn_get_device_and_core(uintptr_t core_addr,
const struct ethosn_device_t **dev_match,
@@ -142,7 +142,7 @@
return false;
}
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr)
{
uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr,
@@ -155,23 +155,23 @@
bool is_protected)
{
size_t i;
- uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID};
+ uint32_t streams[9] = {[0 ... 8] = ETHOSN_NPU_NS_RO_DATA_NSAID};
- streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
- streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
+ streams[FIRMWARE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
+ streams[PLE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
- streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
+ streams[WORKING_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
if (is_protected) {
- streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID;
+ streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RO_DATA_NSAID;
streams[INTERMEDIATE_STREAM_INDEX] =
- ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
- streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
+ ETHOSN_NPU_PROT_RW_DATA_NSAID;
+ streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RW_DATA_NSAID;
} else {
- streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID;
+ streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RO_DATA_NSAID;
streams[INTERMEDIATE_STREAM_INDEX] =
- ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
- streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
+ ETHOSN_NPU_NS_RW_DATA_NSAID;
+ streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
}
for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
@@ -188,7 +188,7 @@
FW_INITVTOR_ADDR(big_fw));
}
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
static void ethosn_configure_events(uintptr_t core_addr)
{
@@ -343,7 +343,7 @@
static int ethosn_core_boot_fw(uintptr_t core_addr)
{
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
const uint32_t sysctrl0_val = mmio_read_32(sysctrl0_reg);
const bool waiting = (sysctrl0_val & SEC_SYSCTRL0_CPU_WAIT);
@@ -363,7 +363,7 @@
return ETHOSN_SUCCESS;
#else
return ETHOSN_NOT_SUPPORTED;
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
}
static int ethosn_core_full_reset(const struct ethosn_device_t *device,
@@ -392,17 +392,17 @@
if (!device->has_reserved_memory) {
ethosn_configure_smmu_streams(device, core, asset_alloc_idx);
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
ethosn_configure_stream_nsaid(core, is_protected);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
}
ethosn_configure_stream_addr_extends(device, core->addr);
ethosn_configure_stream_attr_ctlr(core->addr);
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
ethosn_configure_vector_table(core->addr);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
ethosn_delegate_to_ns(core->addr);
@@ -481,7 +481,7 @@
static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property,
void *handle)
{
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
switch (fw_property) {
case ETHOSN_FW_PROP_VERSION:
SMC_RET4(handle, ETHOSN_SUCCESS,
@@ -507,7 +507,7 @@
}
#else
SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
}
uintptr_t ethosn_smc_handler(uint32_t smc_fid,
@@ -554,17 +554,17 @@
int ethosn_smc_setup(void)
{
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
struct ethosn_device_t *dev;
uint32_t arch_ver;
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
if (ETHOSN_NUM_DEVICES == 0U) {
ERROR("ETHOSN: No NPU found\n");
return ETHOSN_FAILURE;
}
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
/* Only one NPU core is supported in the TZMP1 setup */
if ((ETHOSN_NUM_DEVICES != 1U) ||
@@ -580,7 +580,7 @@
}
arch_ver = ethosn_core_read_arch_version(dev->cores[0U].addr);
- big_fw = (struct ethosn_big_fw *)ARM_ETHOSN_NPU_FW_IMAGE_BASE;
+ big_fw = (struct ethosn_big_fw *)ETHOSN_NPU_FW_IMAGE_BASE;
if (!ethosn_big_fw_verify_header(big_fw, arch_ver)) {
return ETHOSN_FAILURE;
@@ -591,7 +591,7 @@
big_fw->fw_ver_patch);
#else
NOTICE("ETHOSN: Setup succeeded\n");
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
return 0;
}
diff --git a/drivers/arm/fvp/fvp_pwrc.c b/drivers/arm/fvp/fvp_pwrc.c
index 75a2b66..fb77f77 100644
--- a/drivers/arm/fvp/fvp_pwrc.c
+++ b/drivers/arm/fvp/fvp_pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,22 +10,39 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
+#define FVP_PWRC_ID_MASK U(0x00FFFFFF)
+
/*
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
ARM_INSTANTIATE_LOCK;
+/*
+ * Core ID field is 24 bits wide and extracted from MPIDR.
+ * Bits[23:16] represent Affinity Level 2
+ * Bits[15:8] represent Affinity Level 1
+ * Bits[7:0] represent Affinity Level 0
+ */
+static unsigned int fvp_pwrc_core_id(u_register_t mpidr)
+{
+ return (unsigned int)(mpidr & FVP_PWRC_ID_MASK);
+}
+
unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
{
- return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
+ return PSYSR_WK(fvp_pwrc_read_psysr(id));
}
unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
{
unsigned int rc;
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PSYSR_OFF, id);
rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
arm_lock_release();
return rc;
@@ -33,38 +50,47 @@
void fvp_pwrc_write_pponr(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PPONR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_write_ppoffr(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PPOFFR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_set_wen(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
- (unsigned int) (PWKUPR_WEN | mpidr));
+ (unsigned int) (PWKUPR_WEN | id));
arm_lock_release();
}
void fvp_pwrc_clr_wen(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PWKUPR_OFF,
- (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PWKUPR_OFF, id);
arm_lock_release();
}
void fvp_pwrc_write_pcoffr(u_register_t mpidr)
{
+ unsigned int id = fvp_pwrc_core_id(mpidr);
+
arm_lock_get();
- mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
+ mmio_write_32(PWRC_BASE + PCOFFR_OFF, id);
arm_lock_release();
}
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 7a9cca8..105dc05 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -20,6 +20,8 @@
#include <lib/fconf/fconf_tbbr_getter.h>
#include <plat/common/platform.h>
+#include <tools_share/zero_oid.h>
+
/* ASN.1 tags */
#define ASN1_INTEGER 0x02
@@ -148,7 +150,7 @@
const auth_img_desc_t *img_desc,
void *img, unsigned int img_len)
{
- void *data_ptr, *pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr;
+ void *data_ptr, *pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr, *pk_oid;
unsigned int data_len, pk_len, pk_plat_len, sig_len, sig_alg_len;
unsigned int flags = 0;
int rc = 0;
@@ -226,6 +228,25 @@
return -1;
}
}
+
+ /*
+ * Set Zero-OID for ROTPK(subject key) as a the certificate
+ * does not hold Key-OID information for ROTPK.
+ */
+ if (param->pk->cookie != NULL) {
+ pk_oid = param->pk->cookie;
+ } else {
+ pk_oid = ZERO_OID;
+ }
+
+ /*
+ * Public key is verified at this stage, notify platform
+ * to measure and publish it.
+ */
+ rc = plat_mboot_measure_key(pk_oid, pk_ptr, pk_len);
+ if (rc != 0) {
+ WARN("Public Key measurement failure = %d\n", rc);
+ }
}
/* Ask the crypto module to verify the signature */
@@ -381,6 +402,7 @@
unsigned int img_len)
{
const auth_img_desc_t *img_desc = NULL;
+ const auth_param_type_desc_t *type_desc = NULL;
const auth_method_desc_t *auth_method = NULL;
void *param_ptr;
unsigned int param_len;
@@ -462,6 +484,21 @@
/* Copy the parameter for later use */
memcpy((void *)img_desc->authenticated_data[i].data.ptr,
(void *)param_ptr, param_len);
+
+ /*
+ * If this is a public key then measure and publicise
+ * it.
+ */
+ type_desc = img_desc->authenticated_data[i].type_desc;
+ if (type_desc->type == AUTH_PARAM_PUB_KEY) {
+ rc = plat_mboot_measure_key(type_desc->cookie,
+ param_ptr,
+ param_len);
+ if (rc != 0) {
+ WARN("Public Key measurement "
+ "failure = %d\n", rc);
+ }
+ }
}
}
diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rss/rss_measured_boot.c
index 1b2f177..258aa8d 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.c
+++ b/drivers/measured_boot/rss/rss_measured_boot.c
@@ -32,6 +32,19 @@
# error Invalid Measured Boot algorithm.
#endif /* MBOOT_ALG_ID */
+#if ENABLE_ASSERTIONS
+static bool null_arr(const uint8_t *signer_id, size_t signer_id_size)
+{
+ for (size_t i = 0U; i < signer_id_size; i++) {
+ if (signer_id[i] != 0U) {
+ return false;
+ }
+ }
+
+ return true;
+}
+#endif /* ENABLE_ASSERTIONS */
+
/* Functions' declarations */
void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr)
{
@@ -39,6 +52,7 @@
/* Init the non-const members of the metadata structure */
while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+ assert(null_arr(metadata_ptr->signer_id, MBOOT_DIGEST_SIZE));
metadata_ptr->sw_type_size =
strlen((const char *)&metadata_ptr->sw_type) + 1;
metadata_ptr++;
@@ -93,36 +107,53 @@
}
int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
- unsigned int img_id,
+ const void *pk_oid,
const void *pk_ptr,
size_t pk_len)
{
unsigned char hash_data[CRYPTO_MD_MAX_SIZE];
int rc;
+ bool hash_calc_done = false;
assert(metadata_ptr != NULL);
- /* Get the metadata associated with this image. */
- while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) &&
- (metadata_ptr->id != img_id)) {
- metadata_ptr++;
- }
+ /*
+ * Do an exhaustive search over the platform metadata to find
+ * all images whose key OID matches the one passed in argument.
+ *
+ * Note that it is not an error if do not get any matches.
+ * The platform may decide not to measure all of the images
+ * in the system.
+ */
+ while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+ /* Get the metadata associated with this key-oid */
+ if (metadata_ptr->pk_oid == pk_oid) {
+ if (!hash_calc_done) {
+ /* Calculate public key hash */
+ rc = crypto_mod_calc_hash(CRYPTO_MD_ID,
+ (void *)pk_ptr,
+ pk_len, hash_data);
+ if (rc != 0) {
+ return rc;
+ }
- /* If image is not present in metadata array then skip */
- if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) {
- return 0;
- }
+ hash_calc_done = true;
+ }
- /* Calculate public key hash */
- rc = crypto_mod_calc_hash(CRYPTO_MD_ID, (void *)pk_ptr,
- pk_len, hash_data);
- if (rc != 0) {
- return rc;
- }
+ /*
+ * Fill the signer-ID field with the newly/already
+ * computed hash of the public key and update its
+ * signer ID size field with compile-time decided
+ * digest size.
+ */
+ (void)memcpy(metadata_ptr->signer_id,
+ hash_data,
+ MBOOT_DIGEST_SIZE);
+ metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE;
+ }
- /* Update metadata struct with the received signer_id */
- (void)memcpy(metadata_ptr->signer_id, hash_data, MBOOT_DIGEST_SIZE);
- metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE;
+ metadata_ptr++;
+ }
return 0;
}
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index b8137c2..5ba5eb0 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -540,6 +540,7 @@
query_upiu->trans_type = QUERY_REQUEST_UPIU;
query_upiu->task_tag = utrd->task_tag;
+ query_upiu->data_segment_len = htobe16(length);
query_upiu->ts.desc.opcode = op;
query_upiu->ts.desc.idn = idn;
query_upiu->ts.desc.index = index;
diff --git a/fdts/juno.dts b/fdts/juno.dts
index 56fe167..8e373e7 100644
--- a/fdts/juno.dts
+++ b/fdts/juno.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,6 @@
};
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
#include "juno-ethosn.dtsi"
#endif
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 61b5763..f207c06 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -35,6 +35,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu1: cpu1@100 {
compatible = "arm,armv8";
@@ -42,6 +51,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu2: cpu2@10000 {
compatible = "arm,armv8";
@@ -49,6 +67,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu3: cpu3@10100 {
compatible = "arm,armv8";
@@ -56,6 +83,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
};
@@ -194,10 +230,12 @@
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dpu_aclk>;
- hdmi-transmitter@70 {
+ hdmi_tx: hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
video-ports = <0x234501>;
+ #sound-dai-cells = <0>;
+ audio-ports = <2 0x03>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&dp_pl0_out0>;
@@ -253,7 +291,139 @@
reg = <0x14>;
#clock-cells = <1>;
};
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
+
+ thermal-zones {
+ clus0-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 0>;
+
+ trips {
+ clus0_alarm: clus0-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ clus0_shutdown: clus0-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&clus0_alarm>;
+ cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
+ };
+ };
};
+ clus1-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 1>;
+ trips {
+ clus1_alarm: clus1-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ clus1_shutdown: clus1-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&clus1_alarm>;
+ cooling-device = <&cpu2 4 4>, <&cpu3 4 4>;
+ };
+ };
+ };
+ sys-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 2>;
+ trips {
+ sys_alarm: sys-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ sys_shutdown: sys-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&sys_alarm>;
+ cooling-device = <&cpu0 4 4>,
+ <&cpu1 4 4>,
+ <&cpu2 4 4>,
+ <&cpu3 4 4>;
+ };
+ };
+ };
+ };
+
+ iofpga_i2s: xlnx-i2s@1c150000 {
+ #sound-dai-cells = <0>;
+ compatible = "xlnx,i2s-transmitter-1.0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1c150000 0x0 0x10000>;
+ xlnx,dwidth = <0x18>;
+ xlnx,num-channels = <1>;
+ };
+
+ audio_formatter: audio-formatter@1c100000 {
+ compatible = "xlnx,audio-formatter-1.0";
+ reg = <0x0 0x1c000000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
+ interrupt-names = "irq_mm2s";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk";
+ clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&audio_master>;
+ simple-audio-card,frame-master = <&audio_master>;
+ audio_master: simple-audio-card,cpu {
+ sound-dai = <&iofpga_i2s>;
+ clocks = <&i2s_audclk>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi_tx>;
+ };
+
+ simple-audio-card,plat {
+ sound-dai = <&audio_formatter>;
+ };
+ };
+
+ i2s_audclk: i2s_audclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ clock-output-names = "iofpga:i2s_audclk";
};
};
diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi
index 20640c5..7f39d75 100644
--- a/fdts/morello.dtsi
+++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,13 @@
clock-output-names = "apb_pclk";
};
+ soc_refclk85mhz: refclk85mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <85000000>;
+ clock-output-names = "iofpga:aclk";
+ };
+
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index ce1c10c..c10102a 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -157,6 +157,8 @@
#define DCCSW U(0x2)
#endif
+#define ID_REG_FIELD_MASK ULL(0xf)
+
/* ID_AA64PFR0_EL1 definitions */
#define ID_AA64PFR0_EL0_SHIFT U(0)
#define ID_AA64PFR0_EL1_SHIFT U(4)
@@ -435,6 +437,7 @@
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 9f11f15..bd41fef 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -13,49 +13,37 @@
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+ ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
-static inline bool is_armv7_gentimer_present(void)
-{
- /* The Generic Timer is always present in an ARMv8-A implementation */
- return true;
+#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func() >= (idvalue); \
}
-static inline unsigned int read_feat_pan_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN);
-}
-
-static inline bool is_feat_pan_supported(void)
-{
- if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
- return false;
- }
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
+static unsigned int read_ ## name ## _id_field(void) \
+{ \
+ return ISOLATE_FIELD(read_ ## idreg(), idfield); \
+} \
+CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
- if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_pan_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_vhe_id_field(void)
+static inline bool is_armv7_gentimer_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE);
+ /* The Generic Timer is always present in an ARMv8-A implementation */
+ return true;
}
-static inline bool is_feat_vhe_supported(void)
-{
- if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_vhe_id_field() != 0U;
-}
+CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
+ ENABLE_FEAT_PAN)
+CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
+ ENABLE_FEAT_VHE)
static inline bool is_armv8_2_ttcnp_present(void)
{
@@ -107,278 +95,51 @@
ID_AA64PFR1_EL1_MTE_MASK);
}
-static inline unsigned int read_feat_sel2_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2);
-}
-
-static inline bool is_feat_sel2_supported(void)
-{
- if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sel2_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_twed_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED);
-}
-
-static inline bool is_feat_twed_supported(void)
-{
- if (ENABLE_FEAT_TWED == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_twed_id_field() != 0U;
-}
-
-static unsigned int read_feat_fgt_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT);
-}
-
-static unsigned int read_feat_mte_perm_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_MTEPERM);
-}
-
-static inline bool is_feat_fgt_supported(void)
-{
- if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_fgt_id_field() != 0U;
-}
-
-static inline bool is_feat_mte_perm_supported(void)
-{
- if (ENABLE_FEAT_MTE_PERM == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_MTE_PERM == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_mte_perm_id_field() != 0U;
-}
-
-static unsigned int read_feat_ecv_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV);
-}
-
-static inline bool is_feat_ecv_supported(void)
-{
- if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ecv_id_field() != 0U;
-}
-
-static inline bool is_feat_ecv_v2_supported(void)
-{
- if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH;
-}
-
-static unsigned int read_feat_rng_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR);
-}
-
-static inline bool is_feat_rng_supported(void)
-{
- if (ENABLE_FEAT_RNG == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_rng_id_field() != 0U;
-}
-
-static unsigned int read_feat_tcrx_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX);
-}
-
-static inline bool is_feat_tcr2_supported(void)
-{
- if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_tcrx_id_field() != 0U;
-}
+CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
+ ENABLE_FEAT_SEL2)
+CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
+ ENABLE_FEAT_TWED)
+CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
+ ENABLE_FEAT_FGT)
+CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
+ ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
+CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ENABLE_FEAT_ECV)
+CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
+ ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
-static unsigned int read_feat_s2poe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE);
-}
-
-static inline bool is_feat_s2poe_supported(void)
-{
- if (ENABLE_FEAT_S2POE == FEAT_STATE_DISABLED) {
- return false;
- }
+CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
+ ENABLE_FEAT_RNG)
+CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
+ ENABLE_FEAT_TCR2)
- if (ENABLE_FEAT_S2POE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s2poe_id_field() != 0U;
-}
-
-static unsigned int read_feat_s1poe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE);
-}
-
-static inline bool is_feat_s1poe_supported(void)
-{
- if (ENABLE_FEAT_S1POE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S1POE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s1poe_id_field() != 0U;
-}
-
+CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
+ ENABLE_FEAT_S2POE)
+CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
+ ENABLE_FEAT_S1POE)
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
}
-static unsigned int read_feat_s2pie_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE);
-}
-
-static inline bool is_feat_s2pie_supported(void)
-{
- if (ENABLE_FEAT_S2PIE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S2PIE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s2pie_id_field() != 0U;
-}
-
-static unsigned int read_feat_s1pie_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE);
-}
-
-static inline bool is_feat_s1pie_supported(void)
-{
- if (ENABLE_FEAT_S1PIE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S1PIE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s1pie_id_field() != 0U;
-}
-
+CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
+ ENABLE_FEAT_S2PIE)
+CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+ ENABLE_FEAT_S1PIE)
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
}
-static unsigned int read_feat_gcs_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS);
-}
-
-static inline bool is_feat_gcs_supported(void)
-{
- if (ENABLE_FEAT_GCS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_GCS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_gcs_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Functions to identify the presence of the Activity Monitors Extension
- ******************************************************************************/
-static unsigned int read_feat_amu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU);
-}
-
-static inline bool is_feat_amu_supported(void)
-{
- if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_GCS: Guarded Control Stack */
+CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
+ ENABLE_FEAT_GCS)
- return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1;
-}
-
-static inline bool is_feat_amuv1p1_supported(void)
-{
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1;
-}
+/* FEAT_AMU: Activity Monitors Extension */
+CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
+ ENABLE_FEAT_AMU)
+CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
+ ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/*
* Return MPAM version:
@@ -397,36 +158,12 @@
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
}
-static inline bool is_feat_mpam_supported(void)
-{
- if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_mpam_version() != 0U;
-}
-
-static inline unsigned int read_feat_hcx_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX);
-}
-
-static inline bool is_feat_hcx_supported(void)
-{
- if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) {
- return true;
- }
+CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
+ ENABLE_MPAM_FOR_LOWER_ELS)
- return read_feat_hcx_id_field() != 0U;
-}
+/* FEAT_HCX: Extended Hypervisor Configuration Register */
+CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
+ ENABLE_FEAT_HCX)
static inline bool is_feat_rng_trap_present(void)
{
@@ -451,251 +188,60 @@
********************************************************************************/
static inline unsigned int read_feat_sb_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB);
-}
-
-/*********************************************************************************
- * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2)
- ********************************************************************************/
-static inline unsigned int read_feat_csv2_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2);
-}
-
-static inline bool is_feat_csv2_2_supported(void)
-{
- if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED;
-}
-
-/**********************************************************************************
- * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension)
- *********************************************************************************/
-static inline unsigned int read_feat_spe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS);
-}
-
-static inline bool is_feat_spe_supported(void)
-{
- if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_spe_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_SVE (Scalable Vector Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_sve_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE);
-}
-
-static inline bool is_feat_sve_supported(void)
-{
- if (ENABLE_SVE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SVE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED;
-}
-
-static unsigned int read_feat_ras_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS);
-}
-
-static inline bool is_feat_ras_supported(void)
-{
- if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ras_id_field() != 0U;
-}
-
-static unsigned int read_feat_dit_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT);
-}
-
-static inline bool is_feat_dit_supported(void)
-{
- if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_dit_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_tracever_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER);
-}
-
-static inline bool is_feat_sys_reg_trace_supported(void)
-{
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_tracever_id_field() != 0U;
-}
-
-/*************************************************************************
- * Function to identify the presence of FEAT_TRF (TraceLift)
- ************************************************************************/
-static inline unsigned int read_feat_trf_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT);
+ return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
}
-static inline bool is_feat_trf_supported(void)
-{
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_CSV2_2: Cache Speculation Variant 2 */
+CREATE_FEATURE_FUNCS(feat_csv2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 0)
+CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
+ ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_SPE: Statistical Profiling Extension */
+CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
+ ENABLE_SPE_FOR_NS)
- return read_feat_trf_id_field() != 0U;
-}
+/* FEAT_SVE: Scalable Vector Extension */
+CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
+ ENABLE_SVE_FOR_NS)
-/********************************************************************************
- * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
- * Support)
- *******************************************************************************/
-static inline unsigned int read_feat_nv_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV);
-}
+/* FEAT_RAS: Reliability, Accessibility, Serviceability */
+CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
+ ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
-static inline bool is_feat_nv2_supported(void)
-{
- if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_DIT: Data Independent Timing instructions */
+CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
+ ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
- if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) {
- return true;
- }
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
+ ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
- return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED;
-}
+/* FEAT_TRF: TraceFilter */
+CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
+ ENABLE_TRF_FOR_NS)
-/*******************************************************************************
- * Function to identify the presence of FEAT_BRBE (Branch Record Buffer
- * Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_brbe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE);
-}
+/* FEAT_NV2: Enhanced Nested Virtualization */
+CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
+CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
+ ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
-static inline bool is_feat_brbe_supported(void)
-{
- if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_BRBE: Branch Record Buffer Extension */
+CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
+ ENABLE_BRBE_FOR_NS)
- if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_TRBE: Trace Buffer Extension */
+CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
+ ENABLE_TRBE_FOR_NS)
- return read_feat_brbe_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_trbe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER);
-}
-
-static inline bool is_feat_trbe_supported(void)
-{
- if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_trbe_id_field() != 0U;
-
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_SMEx (Scalar Matrix Extension)
- ******************************************************************************/
static inline unsigned int read_feat_sme_fa64_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64smfr0_el1(), ID_AA64SMFR0_EL1_SME_FA64);
+ return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
+ ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
}
-
-static inline unsigned int read_feat_sme_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME);
-}
-
-static inline bool is_feat_sme_supported(void)
-{
- if (ENABLE_SME_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SME_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME_SUPPORTED;
-}
-
-static inline bool is_feat_sme2_supported(void)
-{
- if (ENABLE_SME2_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SME2_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME2_SUPPORTED;
-}
+/* FEAT_SMEx: Scalar Matrix Extension */
+CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
+ ENABLE_SME_FOR_NS)
+CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
+ ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
/*******************************************************************************
* Function to get hardware granularity support
@@ -703,29 +249,30 @@
static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_TGRAN4);
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN16);
+ ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN64);
+ ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
}
static inline unsigned int read_feat_pmuv3_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER);
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
}
static inline unsigned int read_feat_mtpmu_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU);
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
}
static inline bool is_feat_mtpmu_supported(void)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 3121079..6fdc7e8 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -487,6 +487,13 @@
DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(hacr_el2)
+DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
+DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
+
DEFINE_SYSREG_READ_FUNC(isr_el1)
DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
@@ -585,6 +592,7 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
/* Armv8.5 FEAT_RNG Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 539280e..4c8a17c 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -85,6 +85,10 @@
#define __EL3_LP_DESCS_START__ Load$$__EL3_LP_DESCS__$$Base
#define __EL3_LP_DESCS_END__ Load$$__EL3_LP_DESCS__$$Limit
#endif
+#if ENABLE_SPMD_LP
+#define __SPMD_LP_DESCS_START__ Load$$__SPMD_LP_DESCS__$$Base
+#define __SPMD_LP_DESCS_END__ Load$$__SPMD_LP_DESCS__$$Limit
+#endif
#define __RW_START__ Load$$LR$$LR_RW_DATA$$Base
#define __RW_END__ Load$$LR$$LR_END$$Base
#define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h
index c9bed1a..b6dd0f0 100644
--- a/include/common/bl_common.ld.h
+++ b/include/common/bl_common.ld.h
@@ -49,6 +49,15 @@
#define EL3_LP_DESCS
#endif
+#if ENABLE_SPMD_LP
+#define SPMD_LP_DESCS \
+ . = ALIGN(STRUCT_ALIGN); \
+ __SPMD_LP_DESCS_START__ = .; \
+ KEEP(*(.spmd_lp_descs)) \
+ __SPMD_LP_DESCS_END__ = .;
+#else
+#define SPMD_LP_DESCS
+#endif
#define PMF_SVC_DESCS \
. = ALIGN(STRUCT_ALIGN); \
__PMF_SVC_DESCS_START__ = .; \
@@ -100,7 +109,8 @@
CPU_OPS \
GOT \
BASE_XLAT_TABLE_RO \
- EL3_LP_DESCS
+ EL3_LP_DESCS \
+ SPMD_LP_DESCS
/*
* .data must be placed at a lower address than the stacks if the stack
diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rss/rss_measured_boot.h
index 76affd8..7ab517c 100644
--- a/include/drivers/measured_boot/rss/rss_measured_boot.h
+++ b/include/drivers/measured_boot/rss/rss_measured_boot.h
@@ -40,6 +40,7 @@
size_t version_size;
uint8_t sw_type[SW_TYPE_MAX_SIZE];
size_t sw_type_size;
+ void *pk_oid;
bool lock_measurement;
};
@@ -49,9 +50,8 @@
uintptr_t data_base, uint32_t data_size,
uint32_t data_id);
-/* TODO: These metadata are currently not available during TF-A boot */
int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
- unsigned int img_id, const void *pk_ptr,
+ const void *pk_oid, const void *pk_ptr,
size_t pk_len);
#endif /* RSS_MEASURED_BOOT_H */
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_clock.h b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h
new file mode 100644
index 0000000..3c457d7
--- /dev/null
+++ b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ARBEL_CLOCK_H_
+#define __ARBEL_CLOCK_H_
+
+struct clk_ctl {
+ unsigned int clken1;
+ unsigned int clksel;
+ unsigned int clkdiv1;
+ unsigned int pllcon0;
+ unsigned int pllcon1;
+ unsigned int swrstr;
+ unsigned char res1[0x8];
+ unsigned int ipsrst1;
+ unsigned int ipsrst2;
+ unsigned int clken2;
+ unsigned int clkdiv2;
+ unsigned int clken3;
+ unsigned int ipsrst3;
+ unsigned int wd0rcr;
+ unsigned int wd1rcr;
+ unsigned int wd2rcr;
+ unsigned int swrstc1;
+ unsigned int swrstc2;
+ unsigned int swrstc3;
+ unsigned int tiprstc;
+ unsigned int pllcon2;
+ unsigned int clkdiv3;
+ unsigned int corstc;
+ unsigned int pllcong;
+ unsigned int ahbckfi;
+ unsigned int seccnt;
+ unsigned int cntr25m;
+ unsigned int clken4;
+ unsigned int ipsrst4;
+ unsigned int busto;
+ unsigned int clkdiv4;
+ unsigned int wd0rcrb;
+ unsigned int wd1rcrb;
+ unsigned int wd2rcrb;
+ unsigned int swrstc1b;
+ unsigned int swrstc2b;
+ unsigned int swrstc3b;
+ unsigned int tiprstcb;
+ unsigned int corstcb;
+ unsigned int ipsrstdis1;
+ unsigned int ipsrstdis2;
+ unsigned int ipsrstdis3;
+ unsigned int ipsrstdis4;
+ unsigned char res2[0x10];
+ unsigned int thrtl_cnt;
+};
+
+#endif /* __ARBEL_CLOCK_H_ */
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h
new file mode 100644
index 0000000..b9f3048
--- /dev/null
+++ b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __NPCM845x_GCR_H_
+#define __NPCM845x_GCR_H_
+
+struct npcm845x_gcr {
+ unsigned int pdid;
+ unsigned int pwron;
+ unsigned int swstrps;
+ unsigned int rsvd1[2];
+ unsigned int miscpe;
+ unsigned int spldcnt;
+ unsigned int rsvd2[1];
+ unsigned int flockr2;
+ unsigned int flockr3;
+ unsigned int rsvd3[3];
+ unsigned int a35_mode;
+ unsigned int spswc;
+ unsigned int intcr;
+ unsigned int intsr;
+ unsigned int obscr1;
+ unsigned int obsdr1;
+ unsigned int rsvd4[1];
+ unsigned int hifcr;
+ unsigned int rsvd5[3];
+ unsigned int intcr2;
+ unsigned int rsvd6[1];
+ unsigned int srcnt;
+ unsigned int ressr;
+ unsigned int rlockr1;
+ unsigned int flockr1;
+ unsigned int dscnt;
+ unsigned int mdlr;
+ unsigned int scrpad_c;
+ unsigned int scrpad_b;
+ unsigned int rsvd7[4];
+ unsigned int daclvlr;
+ unsigned int intcr3;
+ unsigned int pcirctl;
+ unsigned int rsvd8[2];
+ unsigned int vsintr;
+ unsigned int rsvd9[1];
+ unsigned int sd2sur1;
+ unsigned int sd2sur2;
+ unsigned int sd2irv3;
+ unsigned int intcr4;
+ unsigned int obscr2;
+ unsigned int obsdr2;
+ unsigned int rsvd10[5];
+ unsigned int i2csegsel;
+ unsigned int i2csegctl;
+ unsigned int vsrcr;
+ unsigned int mlockr;
+ unsigned int rsvd11[8];
+ unsigned int etsr;
+ unsigned int dft1r;
+ unsigned int dft2r;
+ unsigned int dft3r;
+ unsigned int edffsr;
+ unsigned int rsvd12[1];
+ unsigned int intcrpce3;
+ unsigned int intcrpce2;
+ unsigned int intcrpce0;
+ unsigned int intcrpce1;
+ unsigned int dactest;
+ unsigned int scrpad;
+ unsigned int usb1phyctl;
+ unsigned int usb2phyctl;
+ unsigned int usb3phyctl;
+ unsigned int intsr2;
+ unsigned int intcrpce2b;
+ unsigned int intcrpce0b;
+ unsigned int intcrpce1b;
+ unsigned int intcrpce3b;
+ unsigned int rsvd13[4];
+ unsigned int intcrpce2c;
+ unsigned int intcrpce0c;
+ unsigned int intcrpce1c;
+ unsigned int intcrpce3c;
+ unsigned int rsvd14[40];
+ unsigned int sd2irv4;
+ unsigned int sd2irv5;
+ unsigned int sd2irv6;
+ unsigned int sd2irv7;
+ unsigned int sd2irv8;
+ unsigned int sd2irv9;
+ unsigned int sd2irv10;
+ unsigned int sd2irv11;
+ unsigned int rsvd15[8];
+ unsigned int mfsel1;
+ unsigned int mfsel2;
+ unsigned int mfsel3;
+ unsigned int mfsel4;
+ unsigned int mfsel5;
+ unsigned int mfsel6;
+ unsigned int mfsel7;
+ unsigned int rsvd16[1];
+ unsigned int mfsel_lk1;
+ unsigned int mfsel_lk2;
+ unsigned int mfsel_lk3;
+ unsigned int mfsel_lk4;
+ unsigned int mfsel_lk5;
+ unsigned int mfsel_lk6;
+ unsigned int mfsel_lk7;
+ unsigned int rsvd17[1];
+ unsigned int mfsel_set1;
+ unsigned int mfsel_set2;
+ unsigned int mfsel_set3;
+ unsigned int mfsel_set4;
+ unsigned int mfsel_set5;
+ unsigned int mfsel_set6;
+ unsigned int mfsel_set7;
+ unsigned int rsvd18[1];
+ unsigned int mfsel_clr1;
+ unsigned int mfsel_clr2;
+ unsigned int mfsel_clr3;
+ unsigned int mfsel_clr4;
+ unsigned int mfsel_clr5;
+ unsigned int mfsel_clr6;
+ unsigned int mfsel_clr7;
+};
+
+#endif
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h
new file mode 100644
index 0000000..8962b90
--- /dev/null
+++ b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+
+struct npcmX50_uart {
+ union {
+ unsigned int rbr;
+ unsigned int thr;
+ unsigned int dll;
+ };
+ union {
+ unsigned int ier;
+ unsigned int dlm;
+ };
+ union {
+ unsigned int iir;
+ unsigned int fcr;
+ };
+ unsigned int lcr;
+ unsigned int mcr;
+ unsigned int lsr;
+ unsigned int msr;
+ unsigned int tor;
+};
+
+typedef enum {
+ /*
+ * UART0 is a general UART block without modem-I/O-control
+ * connection to external signals.
+ */
+ UART0_DEV = 0,
+ /*
+ * UART1-3 are each a general UART with modem-I/O-control
+ * connection to external signals.
+ */
+ UART1_DEV,
+ UART2_DEV,
+ UART3_DEV,
+} UART_DEV_T;
+
+typedef enum {
+ /*
+ * 0 0 0: Mode 1:
+ * HSP1 connected to SI2,
+ * HSP2 connected to UART2,
+ * UART1 snoops HSP1,
+ * UART3 snoops SI2
+ */
+ UART_MUX_MODE1 = 0,
+ /*
+ * 0 0 1: Mode 2:
+ * HSP1 connected to UART1,
+ * HSP2 connected to SI2,
+ * UART2 snoops HSP2,
+ * UART3 snoops SI2
+ */
+ UART_MUX_MODE2,
+ /*
+ * 0 1 0: Mode 3:
+ * HSP1 connected to UART1,
+ * HSP2 connected to UART2,
+ * UART3 connected to SI2
+ */
+ UART_MUX_MODE3,
+ /*
+ * 0 1 1: Mode 4:
+ * HSP1 connected to SI1,
+ * HSP2 connected to SI2,
+ * UART1 snoops SI1,
+ * UART3 snoops SI2,
+ * UART2 snoops HSP1 (default)
+ */
+ UART_MUX_MODE4,
+ /*
+ * 1 0 0: Mode 5:
+ * HSP1 connected to SI1,
+ * HSP2 connected to UART2,
+ * UART1 snoops HSP1,
+ * UART3 snoops SI1
+ */
+ UART_MUX_MODE5,
+ /*
+ * 1 0 1: Mode 6:
+ * HSP1 connected to SI1,
+ * HSP2 connected to SI2,
+ * UART1 snoops SI1,
+ * UART3 snoops SI2,
+ * UART2 snoops HSP2
+ */
+ UART_MUX_MODE6,
+ /*
+ * 1 1 0: Mode 7:
+ * HSP1 connected to SI1,
+ * HSP2 connected to UART2,
+ * UART1 snoops HSP1,
+ * UART3 connected to SI2
+ */
+ UART_MUX_MODE7,
+ /* Skip UART mode configuration. */
+ UART_MUX_RESERVED,
+ /*
+ * A SW option to allow config of UART
+ * without touching the UART mux.
+ */
+ UART_MUX_SKIP_CONFIG
+} UART_MUX_T;
+
+/*---------------------------------------------------------------------------*/
+/* Common baudrate definitions */
+/*---------------------------------------------------------------------------*/
+typedef enum {
+ UART_BAUDRATE_110 = 110,
+ UART_BAUDRATE_300 = 300,
+ UART_BAUDRATE_600 = 600,
+ UART_BAUDRATE_1200 = 1200,
+ UART_BAUDRATE_2400 = 2400,
+ UART_BAUDRATE_4800 = 4800,
+ UART_BAUDRATE_9600 = 9600,
+ UART_BAUDRATE_14400 = 14400,
+ UART_BAUDRATE_19200 = 19200,
+ UART_BAUDRATE_38400 = 38400,
+ UART_BAUDRATE_57600 = 57600,
+ UART_BAUDRATE_115200 = 115200,
+ UART_BAUDRATE_230400 = 230400,
+ UART_BAUDRATE_380400 = 380400,
+ UART_BAUDRATE_460800 = 460800,
+} UART_BAUDRATE_T;
+
+/*---------------------------------------------------------------------------*/
+/* UART parity types */
+/*---------------------------------------------------------------------------*/
+typedef enum {
+ UART_PARITY_NONE = 0,
+ UART_PARITY_EVEN,
+ UART_PARITY_ODD,
+} UART_PARITY_T;
+
+/*---------------------------------------------------------------------------*/
+/* Uart stop bits */
+/*---------------------------------------------------------------------------*/
+typedef enum {
+ UART_STOPBIT_1 = 0x00,
+ UART_STOPBIT_DYNAMIC,
+} UART_STOPBIT_T;
+
+enum FCR_RFITL_TYPE {
+ FCR_RFITL_1B = 0x0,
+ FCR_RFITL_4B = 0x4,
+ FCR_RFITL_8B = 0x8,
+ FCR_RFITL_14B = 0xC,
+};
+
+enum LCR_WLS_TYPE {
+ LCR_WLS_5bit = 0x0,
+ LCR_WLS_6bit = 0x1,
+ LCR_WLS_7bit = 0x2,
+ LCR_WLS_8bit = 0x3,
+};
+
+#define IER_DBGACK (1 << 4)
+#define IER_MSIE (1 << 3)
+#define IER_RLSE (1 << 2)
+#define IER_THREIE (1 << 1)
+#define IER_RDAIE (1 << 0)
+
+#define IIR_FMES (1 << 7)
+#define IIR_RFTLS (1 << 5)
+#define IIR_DMS (1 << 4)
+#define IIR_IID (1 << 1)
+#define IIR_NIP (1 << 0)
+
+#define FCR_RFITL_1B (0 << 4)
+#define FCR_RFITL_4B (4 << 4)
+#define FCR_RFITL_8B (8 << 4)
+#define FCR_RFITL_14B (12 << 4)
+#define FCR_DMS (1 << 3)
+#define FCR_TFR (1 << 2)
+#define FCR_RFR (1 << 1)
+#define FCR_FME (1 << 0)
+
+#define LCR_DLAB (1 << 7)
+#define LCR_BCB (1 << 6)
+#define LCR_SPE (1 << 5)
+#define LCR_EPS (1 << 4)
+#define LCR_PBE (1 << 3)
+#define LCR_NSB (1 << 2)
+#define LCR_WLS_8b (3 << 0)
+#define LCR_WLS_7b (2 << 0)
+#define LCR_WLS_6b (1 << 0)
+#define LCR_WLS_5b (0 << 0)
+
+#define MCR_LBME (1 << 4)
+#define MCR_OUT2 (1 << 3)
+#define MCR_RTS (1 << 1)
+#define MCR_DTR (1 << 0)
+
+#define LSR_ERR_RX (1 << 7)
+#define LSR_TE (1 << 6)
+#define LSR_THRE (1 << 5)
+#define LSR_BII (1 << 4)
+#define LSR_FEI (1 << 3)
+#define LSR_PEI (1 << 2)
+#define LSR_OEI (1 << 1)
+#define LSR_RFDR (1 << 0)
+
+#define MSR_DCD (1 << 7)
+#define MSR_RI (1 << 6)
+#define MSR_DSR (1 << 5)
+#define MSR_CTS (1 << 4)
+#define MSR_DDCD (1 << 3)
+#define MSR_DRI (1 << 2)
+#define MSR_DDSR (1 << 1)
+#define MSR_DCTS (1 << 0)
+
+#endif /* __ASSEMBLY__ */
+
+uintptr_t npcm845x_get_base_uart(UART_DEV_T dev);
+void CLK_ResetUART(void);
+int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate);
+
+#endif /* __ASM_ARCH_UART_H_ */
diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
index 7391dec..5ae1d64 100644
--- a/include/export/lib/bl_aux_params/bl_aux_params_exp.h
+++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h
index 2ee5769..8c58cbb 100644
--- a/include/export/lib/utils_def_exp.h
+++ b/include/export/lib/utils_def_exp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index 2cf2b44..5d165c9 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h
index 072a29d..c2da96c 100644
--- a/include/lib/bl_aux_params/bl_aux_params.h
+++ b/include/lib/bl_aux_params/bl_aux_params.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cassert.h b/include/lib/cassert.h
index bbfdfdb..512a2ad 100644
--- a/include/lib/cassert.h
+++ b/include/lib/cassert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h
index 42d4149..c8e1b2d 100644
--- a/include/lib/coreboot.h
+++ b/include/lib/coreboot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h
index 1d40cec..f631f26 100644
--- a/include/lib/cpus/aarch32/aem_generic.h
+++ b/include/lib/cpus/aarch32/aem_generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h
index abacdba..789b4cf 100644
--- a/include/lib/cpus/aarch32/cortex_a12.h
+++ b/include/lib/cpus/aarch32/cortex_a12.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h
index 9526a9c..aca4d34 100644
--- a/include/lib/cpus/aarch32/cortex_a15.h
+++ b/include/lib/cpus/aarch32/cortex_a15.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h
index 89a8eb6..b9e754a 100644
--- a/include/lib/cpus/aarch32/cortex_a17.h
+++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h
index 6ddd533..841898a 100644
--- a/include/lib/cpus/aarch32/cortex_a32.h
+++ b/include/lib/cpus/aarch32/cortex_a32.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h
index 76703b7..c0763f9 100644
--- a/include/lib/cpus/aarch32/cortex_a5.h
+++ b/include/lib/cpus/aarch32/cortex_a5.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index 8dd0192..b9bb310 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index ffabd61..bb977ff 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h
index 730fdb5..16fbfaa 100644
--- a/include/lib/cpus/aarch32/cortex_a7.h
+++ b/include/lib/cpus/aarch32/cortex_a7.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 954f736..0a3a23a 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h
index a8c978a..337bad9 100644
--- a/include/lib/cpus/aarch32/cortex_a9.h
+++ b/include/lib/cpus/aarch32/cortex_a9.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h
index 6bb30a2..acb6adb 100644
--- a/include/lib/cpus/aarch64/aem_generic.h
+++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index 5421478..cef2960 100644
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
index 6af85a8..337aac3 100644
--- a/include/lib/cpus/aarch64/cortex_a510.h
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,11 +14,13 @@
******************************************************************************/
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
+#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1)
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
-#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3)
/*******************************************************************************
* CPU Power Control register specific definitions
@@ -30,6 +32,12 @@
* Complex auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2)
/*******************************************************************************
* Auxiliary control register specific definitions
@@ -37,5 +45,11 @@
#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1)
-#endif /* CORTEX_A510_H */
\ No newline at end of file
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 54e646c..18796ee 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index 60ed957..0a1593a 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index dc40e31..19ac513 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index bef9337..a00f6d6 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 271a333..ede76d1 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index e5ca1ba..ca79991 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index 74fb6e9..b2ec8aa 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,6 +36,7 @@
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index a9b4546..39717a3 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 66f565d..2984f82 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
index b68ec1e..4ada845 100644
--- a/include/lib/cpus/aarch64/cortex_a78_ae.h
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cortex_gelas.h b/include/lib/cpus/aarch64/cortex_gelas.h
new file mode 100644
index 0000000..90bb78f
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_gelas.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_GELAS_H
+#define CORTEX_GELAS_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_GELAS_MIDR U(0x410FD8B0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+/*******************************************************************************
+ * SME Control registers
+ ******************************************************************************/
+#define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3
+#define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3
+
+#endif /* CORTEX_GELAS_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 404b7f9..6faef5d 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -444,6 +444,19 @@
.endm
/*
+ * BFI : Inserts bitfield into a system register.
+ *
+ * BFI{cond} Rd, Rn, #lsb, #width
+ */
+.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req
+ /* Source value for BFI */
+ mov x1, #\_src
+ mrs x0, \_reg
+ bfi x0, x1, #\_lsb, #\_width
+ msr \_reg, x0
+.endm
+
+/*
* Apply erratum
*
* _cpu:
@@ -459,15 +472,25 @@
* _chosen:
* Compile time flag on whether the erratum is included
*
+ * _get_rev:
+ * Optional parameter that determines whether to insert a call to the CPU revision fetching
+ * procedure. Stores the result of this in the temporary register x10.
+ *
- * clobbers: x0-x9 (PCS compliant)
+ * clobbers: x0-x10 (PCS compliant)
*/
-.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req
- .if \_chosen
+.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req, _get_rev=GET_CPU_REV
+ .if (\_chosen & \_get_rev)
mov x9, x30
bl cpu_get_rev_var
+ mov x10, x0
+ .elseif (\_chosen)
+ mov x9, x30
+ mov x0, x10
+ .endif
+
+ .if \_chosen
bl erratum_\_cpu\()_\_id\()_wa
mov x30, x9
-
.endif
.endm
diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h
index 463f890..cb004bf 100644
--- a/include/lib/cpus/aarch64/cpuamu.h
+++ b/include/lib/cpus/aarch64/cpuamu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 24b6a87..84ab6bb 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h
index 96b4661..6e784f6 100644
--- a/include/lib/cpus/aarch64/neoverse_e1.h
+++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index b6b8d8d..0ba5ad1 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index cb1be5b..0d50854 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -43,9 +43,17 @@
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
+ * CPU Auxiliary Control register 3 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2
+#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
+
+/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
index 798ecd1..202ef5c 100644
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 3d48623..d618994 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,7 +42,10 @@
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
+#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/nevis.h b/include/lib/cpus/aarch64/nevis.h
new file mode 100644
index 0000000..7006a29
--- /dev/null
+++ b/include/lib/cpus/aarch64/nevis.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEVIS_H
+#define NEVIS_H
+
+#define NEVIS_MIDR U(0x410FD8A0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define NEVIS_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+
+#endif /* NEVIS_H */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
index 14da170..58923d2 100644
--- a/include/lib/cpus/aarch64/qemu_max.h
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index b280435..2080898 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -66,6 +66,9 @@
#define NO_ASSERT 0
#define NO_APPLY_AT_RESET 0
#define APPLY_AT_RESET 1
+#define GET_CPU_REV 1
+#define NO_GET_CPU_REV 0
+
/* useful for errata that end up always being worked around */
#define ERRATUM_ALWAYS_CHOSEN 1
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
index 940fc65..2ad56e1 100644
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ b/include/lib/cpus/wa_cve_2017_5715.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
index e37db37..5a7c9bf 100644
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ b/include/lib/cpus/wa_cve_2018_3639.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
index 35b3fd8..50c0f76 100644
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ b/include/lib/cpus/wa_cve_2022_23960.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h
index df77c0f..3b698e3 100644
--- a/include/lib/el3_runtime/aarch32/context.h
+++ b/include/lib/el3_runtime/aarch32/context.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e6af43e..ebd0e30 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -516,15 +516,6 @@
void el1_sysregs_context_save(el1_sysregs_t *regs);
void el1_sysregs_context_restore(el1_sysregs_t *regs);
-#if CTX_INCLUDE_EL2_REGS
-void el2_sysregs_context_save_common(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_common(el2_sysregs_t *regs);
-#if CTX_INCLUDE_MTE_REGS
-void el2_sysregs_context_save_mte(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
-#endif /* CTX_INCLUDE_MTE_REGS */
-#endif /* CTX_INCLUDE_EL2_REGS */
-
#if CTX_INCLUDE_FPREGS
void fpregs_context_save(fp_regs_t *regs);
void fpregs_context_restore(fp_regs_t *regs);
diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h
index 5012082..d0c0502 100644
--- a/include/lib/el3_runtime/pubsub_events.h
+++ b/include/lib/el3_runtime/pubsub_events.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index 80ad68c..09d8dee 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h
index 2e780de..dbc2226 100644
--- a/include/lib/extensions/pauth.h
+++ b/include/lib/extensions/pauth.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h
index 793ab9f..6997da0 100644
--- a/include/lib/extensions/ras.h
+++ b/include/lib/extensions/ras.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h
index 55760b0..e0aee50 100644
--- a/include/lib/extensions/ras_arch.h
+++ b/include/lib/extensions/ras_arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h
index 3762021..5b54c04 100644
--- a/include/lib/fconf/fconf.h
+++ b/include/lib/fconf/fconf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/fconf/fconf_tbbr_getter.h b/include/lib/fconf/fconf_tbbr_getter.h
index db98b68..541a396 100644
--- a/include/lib/fconf/fconf_tbbr_getter.h
+++ b/include/lib/fconf/fconf_tbbr_getter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch32/endian_.h b/include/lib/libc/aarch32/endian_.h
index 0cf2c75..edca496 100644
--- a/include/lib/libc/aarch32/endian_.h
+++ b/include/lib/libc/aarch32/endian_.h
@@ -32,7 +32,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h
index ef3fb8f..0888bf0 100644
--- a/include/lib/libc/aarch32/inttypes_.h
+++ b/include/lib/libc/aarch32/inttypes_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch32/limits_.h b/include/lib/libc/aarch32/limits_.h
index a67ec53..5b0516a 100644
--- a/include/lib/libc/aarch32/limits_.h
+++ b/include/lib/libc/aarch32/limits_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h
index 36dc20b..14ed094 100644
--- a/include/lib/libc/aarch32/stddef_.h
+++ b/include/lib/libc/aarch32/stddef_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h
index dafe142..6e2deed 100644
--- a/include/lib/libc/aarch32/stdint_.h
+++ b/include/lib/libc/aarch32/stdint_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h
index 5e49425..7042664 100644
--- a/include/lib/libc/aarch32/stdio_.h
+++ b/include/lib/libc/aarch32/stdio_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/endian_.h b/include/lib/libc/aarch64/endian_.h
index 7c79fd4..58273d7 100644
--- a/include/lib/libc/aarch64/endian_.h
+++ b/include/lib/libc/aarch64/endian_.h
@@ -32,7 +32,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h
index f25882f..6109084 100644
--- a/include/lib/libc/aarch64/inttypes_.h
+++ b/include/lib/libc/aarch64/inttypes_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch64/limits_.h b/include/lib/libc/aarch64/limits_.h
index 1bb0681..834439e 100644
--- a/include/lib/libc/aarch64/limits_.h
+++ b/include/lib/libc/aarch64/limits_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h
index f880a17..a7d0b5c 100644
--- a/include/lib/libc/aarch64/setjmp_.h
+++ b/include/lib/libc/aarch64/setjmp_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h
index 6ecc606..963048e 100644
--- a/include/lib/libc/aarch64/stddef_.h
+++ b/include/lib/libc/aarch64/stddef_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h
index 56e9f1b..34a75ec 100644
--- a/include/lib/libc/aarch64/stdint_.h
+++ b/include/lib/libc/aarch64/stdint_.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h
index afaeadc..331bcaa 100644
--- a/include/lib/libc/aarch64/stdio_.h
+++ b/include/lib/libc/aarch64/stdio_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h
index eb08552..d1bc0f9 100644
--- a/include/lib/libc/arm_acle.h
+++ b/include/lib/libc/arm_acle.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 ARM Limited
+ * Copyright (c) 2021 Arm Limited
*
* SPDX-License-Identifier: BSD-3-Clause
*
diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h
index 462bb43..acfd147 100644
--- a/include/lib/libc/assert.h
+++ b/include/lib/libc/assert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h
index 2423f38..b11d072 100644
--- a/include/lib/libc/cdefs.h
+++ b/include/lib/libc/cdefs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/endian.h b/include/lib/libc/endian.h
index 4100f57..9c9fd58 100644
--- a/include/lib/libc/endian.h
+++ b/include/lib/libc/endian.h
@@ -28,7 +28,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/errno.h b/include/lib/libc/errno.h
index 029912f..b536fe9 100644
--- a/include/lib/libc/errno.h
+++ b/include/lib/libc/errno.h
@@ -37,7 +37,7 @@
* $FreeBSD$
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h
index 6ad1c9e..344b71c 100644
--- a/include/lib/libc/inttypes.h
+++ b/include/lib/libc/inttypes.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/limits.h b/include/lib/libc/limits.h
index 41bb658..c5c8764 100644
--- a/include/lib/libc/limits.h
+++ b/include/lib/libc/limits.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h
index be8e2c0..871c868 100644
--- a/include/lib/libc/setjmp.h
+++ b/include/lib/libc/setjmp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/stdarg.h b/include/lib/libc/stdarg.h
index e260b9b..2d1f785 100644
--- a/include/lib/libc/stdarg.h
+++ b/include/lib/libc/stdarg.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h
index b58334c..c2c9b22 100644
--- a/include/lib/libc/stdbool.h
+++ b/include/lib/libc/stdbool.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h
index 58a519e..aaad673 100644
--- a/include/lib/libc/stddef.h
+++ b/include/lib/libc/stddef.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h
index e96a25c..88502e7 100644
--- a/include/lib/libc/stdint.h
+++ b/include/lib/libc/stdint.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h
index ba13683..5ceaf68 100644
--- a/include/lib/libc/stdio.h
+++ b/include/lib/libc/stdio.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h
index 4641e56..4e5a824 100644
--- a/include/lib/libc/stdlib.h
+++ b/include/lib/libc/stdlib.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h
index 7ddeed9..8129404 100644
--- a/include/lib/libc/string.h
+++ b/include/lib/libc/string.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2020, Arm Limited and Contributors.
* Portions copyright (c) 2023, Intel Corporation. All rights reserved.
* All rights reserved.
*/
diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h
index c1c95e5..e1eb2a5 100644
--- a/include/lib/libc/time.h
+++ b/include/lib/libc/time.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/include/lib/mmio.h b/include/lib/mmio.h
index 3242a7c..591d7b6 100644
--- a/include/lib/mmio.h
+++ b/include/lib/mmio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h
index 66e8c47..49584eb 100644
--- a/include/lib/object_pool.h
+++ b/include/lib/object_pool.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/optee_utils.h b/include/lib/optee_utils.h
index 8224d50..e1e9d80 100644
--- a/include/lib/optee_utils.h
+++ b/include/lib/optee_utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/pmf/aarch64/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S
index 5f3e6b7..792ede9 100644
--- a/include/lib/pmf/aarch64/pmf_asm_macros.S
+++ b/include/lib/pmf/aarch64/pmf_asm_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index fa990d2..9d901e2 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h
index 01cc179..f5f040b 100644
--- a/include/lib/pmf/pmf_helpers.h
+++ b/include/lib/pmf/pmf_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 01dc3cb..c40f955 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h
index 303f27e..65fafa7 100644
--- a/include/lib/runtime_instr.h
+++ b/include/lib/runtime_instr.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h
index 24b030c..5c72e8b 100644
--- a/include/lib/semihosting.h
+++ b/include/lib/semihosting.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index fb2b3a2..8fd6093 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 0bf3ee0..9fd3fc6 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/utils.h b/include/lib/utils.h
index 17ee936..ce76de2 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 63eda63..ba52bc6 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h
index 252b92c..3a470ad 100644
--- a/include/lib/xlat_mpu/xlat_mpu.h
+++ b/include/lib/xlat_mpu/xlat_mpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
index 30eb5e9..42a48f4 100644
--- a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
+++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
index 3014c8f..6c0d73b 100644
--- a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
+++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index 269afd2..fabc494 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index a156969..24f833c 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h
index 0ce0cac..46e058c 100644
--- a/include/lib/xlat_tables/xlat_tables_arch.h
+++ b/include/lib/xlat_tables/xlat_tables_arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h
index 5f28195..3877c91 100644
--- a/include/lib/xlat_tables/xlat_tables_compat.h
+++ b/include/lib/xlat_tables/xlat_tables_compat.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 4d16ced..64fe5ef 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
index 62f853d..992c94e 100644
--- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h
+++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/zlib/tf_gunzip.h b/include/lib/zlib/tf_gunzip.h
index 741ba50..9435860 100644
--- a/include/lib/zlib/tf_gunzip.h
+++ b/include/lib/zlib/tf_gunzip.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index bf1f93a..9426ac7 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -782,6 +782,9 @@
#define PLAT_SDEI_CRITICAL_PRI 0x60
#define PLAT_SDEI_NORMAL_PRI 0x70
+/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */
+#define PLAT_CORE_FAULT_IRQ 17
+
/* ARM platforms use 3 upper bits of secure interrupt priority */
#define PLAT_PRI_BITS 3
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h
index cafbc3e..d45c269 100644
--- a/include/plat/arm/common/fconf_ethosn_getter.h
+++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -57,8 +57,6 @@
struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX];
};
-int fconf_populate_arm_ethosn(uintptr_t config);
-
extern struct ethosn_config_t ethosn_config;
#endif /* FCONF_ETHOSN_GETTER_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index d146a29..e024d91 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -146,6 +146,8 @@
int plat_mboot_measure_critical_data(unsigned int critical_data_id,
const void *base,
size_t size);
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len);
#else
static inline int plat_mboot_measure_image(unsigned int image_id __unused,
image_info_t *image_data __unused)
@@ -159,6 +161,12 @@
{
return 0;
}
+static inline int plat_mboot_measure_key(const void *pk_oid __unused,
+ const void *pk_ptr __unused,
+ size_t pk_len __unused)
+{
+ return 0;
+}
#endif /* MEASURED_BOOT */
/*******************************************************************************
diff --git a/include/plat/nuvoton/common/npcm845x_arm_def.h b/include/plat/nuvoton/common/npcm845x_arm_def.h
new file mode 100644
index 0000000..faddb88
--- /dev/null
+++ b/include/plat/nuvoton/common/npcm845x_arm_def.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NPCM845x_ARM_DEF_H
+#define NPCM845x_ARM_DEF_H
+
+#include <arch.h>
+#include <common/interrupt_props.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+
+/* This flag will add zones to the MMU so that it will be possible to debug */
+#ifdef NPCM845X_DEBUG
+#define ALLOW_DEBUG_MMU
+#undef ALLOW_DEBUG_MMU
+#endif /* NPCM845X_DEBUG */
+
+#undef CONFIG_TARGET_ARBEL_PALLADIUM
+/******************************************************************************
+ * Definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/*
+ * Root of trust key hash lengths
+ */
+#define ARM_ROTPK_HEADER_LEN 19
+#define ARM_ROTPK_HASH_LEN 32
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
+
+/* No need for system because we have only one cluster */
+#define ARM_SYSTEM_COUNT U(0)
+
+#define ARM_CACHE_WRITEBACK_SHIFT 6
+
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels.
+ * The power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+/* In NPCM845x - refers to cores */
+#define ARM_PWR_LVL0 MPIDR_AFFLVL0
+
+/* In NPCM845x - refers to cluster */
+#define ARM_PWR_LVL1 MPIDR_AFFLVL1
+
+/* No need for additional settings because the platform doesn't have system */
+
+/*
+ * Macros for local power states in ARM platforms encoded by State-ID field
+ * within the power-state parameter.
+ */
+#define NPCM845x_PLAT_PRIMARY_CPU U(0x0)
+#define NPCM845x_CLUSTER_COUNT U(1)
+
+#ifdef SECONDARY_BRINGUP
+#define NPCM845x_MAX_CPU_PER_CLUSTER U(2)
+#define NPCM845x_PLATFORM_CORE_COUNT U(2)
+#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2)
+#else
+#define NPCM845x_MAX_CPU_PER_CLUSTER U(4)
+#define NPCM845x_PLATFORM_CORE_COUNT U(4)
+#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4)
+#endif /* SECONDARY_BRINGUP */
+
+#define NPCM845x_SYSTEM_COUNT U(0)
+
+/* Memory mapping for NPCM845x */
+#define NPCM845x_REG_BASE 0xf0000000
+#define NPCM845x_REG_SIZE 0x0ff16000
+
+/*
+ * DRAM
+ * 0x3fffffff +-------------+
+ * | BL33 | (non-secure)
+ * 0x06200000 +-------------+
+ * | BL32 SHARED | (non-secure)
+ * 0x06000000 +-------------+
+ * | BL32 | (secure)
+ * 0x02100000 +-------------+
+ * | BL31 | (secure)
+ * 0x02000000 +-------------+
+ * | | (non-secure)
+ * 0x00000000 +-------------+
+ *
+ * Trusted ROM
+ * 0xfff50000 +-------------+
+ * | BL1 (ro) |
+ * 0xfff40000 +-------------+
+ */
+
+#define ARM_DRAM1_BASE ULL(0x00000000)
+#ifndef CONFIG_TARGET_ARBEL_PALLADIUM
+/*
+ * Although npcm845x is 4G,
+ * consider only 2G Trusted Firmware memory allocation
+ */
+#define ARM_DRAM1_SIZE ULL(0x37000000)
+#else
+#define ARM_DRAM1_SIZE ULL(0x10000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U)
+#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
+
+/*
+ * The top 16MB of DRAM1 is configured as secure access only using the TZC
+ * - SCP TZC DRAM: If present, DRAM reserved for SCP use
+ * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
+ */
+
+/* Check for redundancy */
+#ifdef NPCM845X_DEBUG
+#define PLAT_ARM_NS_IMAGE_BASE 0x0
+#endif /* NPCM845X_DEBUG */
+
+#define ARM_TZC_DRAM1_SIZE UL(0x01000000)
+#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
+#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
+ ARM_SCP_TZC_DRAM1_SIZE - 1U)
+
+/*
+ * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
+ * firmware. This region is meant to be NOLOAD and will not be zero
+ * initialized. Data sections with the attribute `arm_el3_tzc_dram`
+ * will be placed here.
+ *
+ * NPCM845x - Currently the platform doesn't have EL3 implementation
+ * on secured DRAM.
+ */
+#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \
+ ARM_EL3_TZC_DRAM1_SIZE)
+#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */
+#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
+ ARM_EL3_TZC_DRAM1_SIZE - 1U)
+
+#define ARM_AP_TZC_DRAM1_BASE 0x02100000
+#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
+ (ARM_SCP_TZC_DRAM1_SIZE + \
+ ARM_EL3_TZC_DRAM1_SIZE))
+#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE - 1U)
+
+/* Define the Access permissions for Secure peripherals to NS_DRAM */
+#if ARM_CRYPTOCELL_INTEG
+/*
+ * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
+ * This is required by CryptoCell to authenticate BL33 which is loaded
+ * into the Non Secure DDR.
+ */
+#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
+#else
+#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
+#endif /* ARM_CRYPTOCELL_INTEG */
+
+#ifdef SPD_opteed
+/*
+ * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
+ * load/authenticate the trusted os extra image. The first 512KB of
+ * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
+ * for OPTEE is paged image which only include the paging part using
+ * virtual memory but without "init" data. OPTEE will copy the "init" data
+ * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
+ * extra image behind the "init" data.
+ */
+#define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
+#define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
+#define BL32_BASE ARM_AP_TZC_DRAM1_BASE
+#define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE)
+
+#define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \
+ ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \
+ ARM_OPTEE_PAGEABLE_LOAD_SIZE)
+#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
+#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
+ ARM_OPTEE_PAGEABLE_LOAD_BASE, \
+ ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+/*
+ * Map the memory for the OP-TEE core (also known as OP-TEE pager
+ * when paging support is enabled).
+ */
+#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
+ BL32_BASE, BL32_LIMIT - BL32_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* SPD_opteed */
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ ARM_TZC_DRAM1_SIZE)
+#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
+ ARM_NS_DRAM1_SIZE - 1U)
+
+/* The platform doesn't use DRAM2 but it has to have a value for calculation */
+#define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */
+#define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */
+#define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U)
+
+#define FIRST_EXT_INTERRUPT_NUM U(32)
+#define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM)
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties
+ * as per GICv3 terminology. On a GICv2 system or mode,
+ * the lists will be merged and treated as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
+ PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
+ ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#ifdef ALLOW_DEBUG_MMU
+/* In order to be able to debug,
+ * the platform needs to add BL33 and BL32 to MMU as well.
+ */
+#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#ifdef BL32_BASE
+#define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \
+ BL32_BASE, BL32_LIMIT - BL32_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* BL32_BASE */
+
+#ifdef NPCM845X_DEBUG
+#define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \
+ 0xFFFB0000, 0x20000, \
+ MT_MEMORY | MT_RW | MT_NS)
+#endif /* NPCM845X_DEBUG */
+#endif /* BL32_BASE */
+
+#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
+ ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
+ TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#if ARM_BL31_IN_DRAM
+#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
+ BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* ARM_BL31_IN_DRAM */
+
+/* Currently the platform doesn't have EL3 implementation on secured DRAM. */
+#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
+ ARM_EL3_TZC_DRAM1_BASE, \
+ ARM_EL3_TZC_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#if defined(SPD_spmd)
+#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
+ PLAT_ARM_TRUSTED_DRAM_BASE, \
+ PLAT_ARM_TRUSTED_DRAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* SPD_spmd */
+
+/*
+ * Mapping for the BL1 RW region. This mapping is needed by BL2
+ * in order to share the Mbed TLS heap. Since the heap is allocated
+ * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access
+ * to the BL1 RW region in order to be able to access the heap.
+ */
+#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
+ BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+/*
+ * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region
+ * for each section, otherwise one region containing both sections
+ * is defined.
+ */
+#if SEPARATE_CODE_AND_RODATA
+#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
+ BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \
+ MT_CODE | EL3_PAS), \
+ MAP_REGION_FLAT(BL_RO_DATA_BASE, \
+ BL_RO_DATA_END - BL_RO_DATA_BASE, \
+ MT_RO_DATA | EL3_PAS)
+#else
+#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
+ BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \
+ MT_CODE | EL3_PAS)
+#endif /* SEPARATE_CODE_AND_RODATA */
+
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
+ BL_COHERENT_RAM_BASE, \
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+#endif /* USE_COHERENT_MEM */
+
+#if USE_ROMLIB
+#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
+ ROMLIB_RO_BASE, \
+ ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \
+ MT_CODE | MT_SECURE)
+
+#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
+ ROMLIB_RW_BASE, \
+ ROMLIB_RW_END - ROMLIB_RW_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* USE_ROMLIB */
+
+/*
+ * Map mem_protect flash region with read and write permissions
+ */
+#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \
+ PLAT_ARM_MEM_PROT_ADDR, \
+ V2M_FLASH_BLOCK_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+/*
+ * Map the region for device tree configuration with read and write permissions
+ */
+#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
+ ARM_BL_RAM_BASE, \
+ (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS 10
+
+#define MAX_MMAP_REGIONS ( \
+ PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
+
+/* Memory mapped Generic timer interfaces */
+#define ARM_SYS_CNTCTL_BASE UL(0XF07FC000)
+
+#define ARM_CONSOLE_BAUDRATE 115200
+
+/*
+ * The TBBR document specifies a watchdog timeout of 256 seconds. SP805
+ * asserts reset after two consecutive countdowns (2 x 128 = 256 sec)
+ */
+#define ARM_TWDG_TIMEOUT_SEC 128
+#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
+ ARM_TWDG_TIMEOUT_SEC)
+
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches (64 on Arbel).
+ */
+#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+
+/*
+ * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
+ * and limit. Leave enough space of BL2 meminfo.
+ */
+#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT ( \
+ (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
+#define ARM_BL2_MEM_DESC_LIMIT ( \
+ ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U))
+
+/*
+ * Define limit of firmware configuration memory:
+ * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
+ */
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
+
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need
+ * two sets of addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \
+ (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE))
+/*
+ * Put BL1 RW at the top of the Trusted SRAM.
+ */
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \
+ (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE))
+#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
+ (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
+
+#define ROMLIB_RO_BASE BL1_RO_LIMIT
+#define ROMLIB_RO_LIMIT ( \
+ PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
+
+#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
+#define ROMLIB_RW_END ( \
+ ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
+
+/******************************************************************************
+ * BL2 specific defines.
+ *****************************************************************************/
+#if BL2_AT_EL3
+/* Put BL2 towards the middle of the Trusted SRAM */
+#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
+ PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
+#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#else
+/*
+ * Put BL2 just below BL1.
+ */
+#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_LIMIT BL1_RW_BASE
+#endif /* BL2_AT_EL3 */
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
+/*
+ * Put BL31 at the bottom of TZC secured DRAM
+ */
+#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
+#define BL31_LIMIT ( \
+ ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE)
+
+/*
+ * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
+ * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
+ */
+#if SEPARATE_NOBITS_REGION
+#define BL31_NOBITS_BASE BL2_BASE
+#define BL31_NOBITS_LIMIT BL2_LIMIT
+#endif /* SEPARATE_NOBITS_REGION */
+#elif (RESET_TO_BL31)
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+#if !ENABLE_PIE
+#error "BL31 must be a PIE if RESET_TO_BL31=1."
+#endif /* !ENABLE_PIE */
+/*
+ * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
+ * used for building BL31 and not used for loading BL31.
+ */
+#define NEW_SRAM_ALLOCATION
+
+#ifdef NEW_SRAM_ALLOCATION
+ #define BL31_BASE 0x20001000
+#else
+ #define BL31_BASE 0x20001000
+#endif /* NEW_SRAM_ALLOCATION */
+
+#define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */
+#else
+/* Put BL31 below BL2 in the Trusted SRAM.*/
+#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \
+ PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_PROGBITS_LIMIT BL2_BASE
+
+/*
+ * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE.
+ * This is because in the BL2_AT_EL3 configuration, BL2 is always resident.
+ */
+#if BL2_AT_EL3
+#define BL31_LIMIT BL2_BASE
+#else
+#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#endif /* BL2_AT_EL3 */
+#endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */
+
+/*
+ * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is
+ * no SPD and no SPM-MM, as they are the only ones that can be used as BL32.
+ */
+#if defined(SPD_none) && !SPM_MM
+#undef BL32_BASE
+#endif /* SPD_none && !SPM_MM */
+
+/******************************************************************************
+ * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
+ *****************************************************************************/
+#define BL2U_BASE BL2_BASE
+#define BL2U_LIMIT BL2_LIMIT
+
+#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
+#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
+
+/*
+ * ID of the secure physical generic timer interrupt used by the TSP.
+ */
+#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
+
+/*
+ * One cache line needed for bakery locks on ARM platforms
+ */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+/* Priority levels for ARM platforms */
+#define PLAT_RAS_PRI 0x10
+#define PLAT_SDEI_CRITICAL_PRI 0x60
+#define PLAT_SDEI_NORMAL_PRI 0x70
+
+/* ARM platforms use 3 upper bits of secure interrupt priority */
+#define ARM_PRI_BITS 3
+
+/* SGI used for SDEI signalling */
+#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
+
+#if SDEI_IN_FCONF
+/* ARM SDEI dynamic private event max count */
+#define ARM_SDEI_DP_EVENT_MAX_CNT 3
+
+/* ARM SDEI dynamic shared event max count */
+#define ARM_SDEI_DS_EVENT_MAX_CNT 3
+#else
+/* ARM SDEI dynamic private event numbers */
+#define ARM_SDEI_DP_EVENT_0 1000
+#define ARM_SDEI_DP_EVENT_1 1001
+#define ARM_SDEI_DP_EVENT_2 1002
+
+/* ARM SDEI dynamic shared event numbers */
+#define ARM_SDEI_DS_EVENT_0 2000
+#define ARM_SDEI_DS_EVENT_1 2001
+#define ARM_SDEI_DS_EVENT_2 2002
+
+#define ARM_SDEI_PRIVATE_EVENTS \
+ SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+
+#define ARM_SDEI_SHARED_EVENTS \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+#endif /* SDEI_IN_FCONF */
+
+#endif /* ARM_DEF_H */
diff --git a/include/plat/nuvoton/common/plat_macros.S b/include/plat/nuvoton/common/plat_macros.S
new file mode 100644
index 0000000..08f9feb
--- /dev/null
+++ b/include/plat/nuvoton/common/plat_macros.S
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (c) 2017-2023 Nuvoton Technology Corp.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <arm_macros.S>
+#include <cci_macros.S>
+#include <platform_def.h>
+
+/*
+ * The below macro prints out relevant GIC
+ * registers whenever an unhandled exception is
+ * taken in BL3-1.
+ * Clobbers: x0 - x10, x16, x17, sp
+ */
+.macro plat_print_gic_regs
+mov_imm x17, BASE_GICC_BASE
+mov_imm x16, BASE_GICD_BASE
+arm_print_gic_regs
+.endm
+
+/*
+ * the below macros print out relevant interconnect
+ * registers whenever an unhandled exception is
+ * taken in BL3-1
+ */
+.macro plat_print_interconnect_regs
+ /* TODO */
+.endm
+
+/*
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ */
+.macro plat_crash_print_regs
+ /* TODO */
+.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/include/plat/nuvoton/common/plat_npcm845x.h b/include/plat/nuvoton/common/plat_npcm845x.h
new file mode 100644
index 0000000..d90952a
--- /dev/null
+++ b/include/plat/nuvoton/common/plat_npcm845x.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (c) 2017-2023 Nuvoton Technology Corp.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_NPCM845X_H
+#define PLAT_NPCM845X_H
+
+#include <drivers/arm/gicv2.h>
+#include <lib/psci/psci.h>
+
+unsigned int plat_calc_core_pos(uint64_t mpidr);
+void npcm845x_mailbox_init(uintptr_t base_addr);
+void plat_gic_driver_init(void);
+void plat_gic_init(void);
+void plat_gic_cpuif_enable(void);
+void plat_gic_cpuif_disable(void);
+void plat_gic_pcpu_init(void);
+
+void __dead2 npcm845x_system_off(void);
+void __dead2 npcm845x_system_reset(void);
+void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state);
+bool npcm845x_is_wakeup_src_irqsteer(void);
+void __dead2 npcm845x_pwr_down_wfi(const psci_power_state_t *target_state);
+void npcm845x_cpu_standby(plat_local_state_t cpu_state);
+int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint);
+int npcm845x_pwr_domain_on(u_register_t mpidr);
+int npcm845x_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state);
+
+#if !ARM_BL31_IN_DRAM
+void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state);
+#endif
+
+void __dead2 npcm845x_pwr_domain_pwr_down_wfi(
+ const psci_power_state_t *target_state);
+void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state);
+void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state);
+void npcm845x_pwr_domain_off(const psci_power_state_t *target_state);
+void __init npcm845x_bl31_plat_arch_setup(void);
+
+#endif /* PLAT_NPCM845X_H */
diff --git a/include/plat/nuvoton/npcm845x/platform_def.h b/include/plat/nuvoton/npcm845x/platform_def.h
new file mode 100644
index 0000000..09da36b
--- /dev/null
+++ b/include/plat/nuvoton/npcm845x/platform_def.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (c) 2017-2023 Nuvoton Technology Corp.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/interrupt_props.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <npcm845x_arm_def.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+
+#define VALUE_TO_STRING(x) #x
+#define VALUE(x) VALUE_TO_STRING(x)
+#define VAR_NAME_VALUE(var) #var "=" VALUE(var)
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define PLATFORM_STACK_SIZE 0x400
+
+#define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT
+#define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT
+#define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER
+#define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU
+#define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET U(1)
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF U(2)
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF
+#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Required ARM standard platform porting definitions
+ */
+#define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL
+
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+#ifdef BL32_BASE
+
+#ifndef CONFIG_TARGET_ARBEL_PALLADIUM
+#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE
+#else
+#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE
+#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
+
+#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
+#endif /* BL32_BASE */
+
+#define PWR_DOMAIN_AT_MAX_LVL U(1)
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
+#define MAX_XLAT_TABLES 16
+#define PLAT_ARM_MMAP_ENTRIES 17
+
+#ifdef NPCM845X_DEBUG
+#define MAX_MMAP_REGIONS 8
+#define NPCM845X_TZ1_BASE 0xFFFB0000
+#endif /* NPCM845X_DEBUG */
+
+#define FIQ_SMP_CALL_SGI 10
+
+/* (0x00040000) 128 KB, the rest 128K if it is non secured */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000)
+
+#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
+
+/* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */
+#define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE)
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
+
+/*
+ * PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000
+ * because only half is secured in this specific implementation
+ */
+#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
+
+#if RESET_TO_BL31
+/* Size of Trusted SRAM - the first 4KB of shared memory */
+#define PLAT_ARM_MAX_BL31_SIZE \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
+#else
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE
+ * is calculated using the current BL31 PROGBITS debug size plus the sizes
+ * of BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL31_SIZE \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
+#endif /* RESET_TO_BL31 */
+/*
+ * Load address of BL33 for this platform port
+ */
+#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000))
+
+#ifdef NPCM845X_DEBUG
+#define COUNTER_FREQUENCY 0x07735940 /* f/4 = 125MHz */
+#endif /* NPCM845X_DEBUG */
+
+#define COUNTER_FREQUENCY 0x0EE6B280 /* f/2 = 250MHz */
+#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
+
+/* GIC parameters */
+
+/* Base compatible GIC memory map */
+#define NT_GIC_BASE (0xDFFF8000)
+#define BASE_GICD_BASE (NT_GIC_BASE + 0x1000)
+#define BASE_GICC_BASE (NT_GIC_BASE + 0x2000)
+#define BASE_GICR_BASE (NT_GIC_BASE + 0x200000)
+#define BASE_GICH_BASE (NT_GIC_BASE + 0x4000)
+#define BASE_GICV_BASE (NT_GIC_BASE + 0x6000)
+
+#define DEVICE1_BASE BASE_GICD_BASE
+#define DEVICE1_SIZE 0x7000
+
+#ifdef NPCM845X_DEBUG
+/* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */
+#define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4)
+#endif /* NPCM845X_DEBUG */
+
+#define PLAT_REG_BASE NPCM845x_REG_BASE
+#define PLAT_REG_SIZE NPCM845x_REG_SIZE
+
+/* MMU entry for internal (register) space access */
+#define MAP_DEVICE0 \
+ MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS)
+
+#define MAP_DEVICE1 \
+ MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties
+ * as per GICv3 terminology. On a GICv2 system or mode,
+ * the lists will be merged and treated as Group 0 interrupts.
+ */
+#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
+#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)
+
+/* Required for compilation: */
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
+#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
+#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
+#endif /* USE_ROMLIB */
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size
+ * plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+#define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION)
+#else
+/* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */
+#define PLAT_ARM_MAX_BL2_SIZE 0
+#endif /* TRUSTED_BOARD_BOOT */
+
+#undef NPCM_PRINT_ONCE
+#ifdef NPCM_PRINT_ONCE
+#define PRINT_ONLY_ONCE
+#pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE))
+#pragma message(VAR_NAME_VALUE(BL31_BASE))
+#pragma message(VAR_NAME_VALUE(BL31_LIMIT))
+#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE))
+#pragma message(VAR_NAME_VALUE(BL32_BASE))
+#pragma message(VAR_NAME_VALUE(BL32_LIMIT))
+#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE)
+#pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO))
+#endif /* NPCM_PRINT_ONCE */
+
+#define MAX_IO_DEVICES 4
+#define MAX_IO_HANDLES 4
+
+#define PLAT_ARM_FIP_BASE 0x0
+#define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE
+
+#define PLAT_ARM_BOOT_UART_BASE 0xF0000000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200
+#define PLAT_ARM_RUN_UART_BASE 0xF0000000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200
+#define PLAT_ARM_CRASH_UART_BASE 0xF0000000
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200
+
+/*
+ * Mailbox to control the secondary cores.All secondary cores are held in a wait
+ * loop in cold boot. To release them perform the following steps (plus any
+ * additional barriers that may be needed):
+ *
+ * uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT;
+ * *entrypoint = ADDRESS_TO_JUMP_TO;
+ *
+ * uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE;
+ * mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE;
+ *
+ * sev();
+ */
+#define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE
+
+/* The secure entry point to be used on warm reset by all CPUs. */
+#define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE
+#define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8)
+
+/* Hold entries for each CPU. */
+#define PLAT_NPCM_TM_HOLD_BASE \
+ (PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE)
+#define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8)
+#define PLAT_NPCM_TM_HOLD_SIZE \
+ (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT)
+#define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \
+ (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE)
+
+#define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8)
+
+#define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \
+ (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT)
+
+#define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \
+ (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \
+ PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE)
+
+#define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0)
+#define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1)
+#define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2)
+
+#define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA)
+#define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC)
+
+#ifdef NPCM845X_DEBUG
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000
+#endif /* NPCM845X_DEBUG */
+
+#endif /* PLATFORM_DEF_H */
diff --git a/include/services/el3_spmd_logical_sp.h b/include/services/el3_spmd_logical_sp.h
new file mode 100644
index 0000000..1f9ef0d
--- /dev/null
+++ b/include/services/el3_spmd_logical_sp.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef EL3_SPMD_LOGICAL_SP_H
+#define EL3_SPMD_LOGICAL_SP_H
+
+#include <common/bl_common.h>
+#include <lib/cassert.h>
+#include <services/ffa_svc.h>
+
+/*******************************************************************************
+ * Structure definition, typedefs & constants for the SPMD Logical Partitions.
+ ******************************************************************************/
+typedef struct spmd_spm_core_context spmd_spm_core_context_t;
+
+/* Prototype for SPMD logical partition initializing function. */
+typedef int32_t (*ffa_spmd_lp_init_t)(void);
+
+/* SPMD Logical Partition Descriptor. */
+struct spmd_lp_desc {
+ ffa_spmd_lp_init_t init;
+ uint16_t sp_id;
+ uint32_t properties;
+ uint32_t uuid[4]; /* Little Endian. */
+ const char *debug_name;
+};
+
+struct ffa_value {
+ uint64_t func;
+ uint64_t arg1;
+ uint64_t arg2;
+ uint64_t arg3;
+ uint64_t arg4;
+ uint64_t arg5;
+ uint64_t arg6;
+ uint64_t arg7;
+ uint64_t arg8;
+ uint64_t arg9;
+ uint64_t arg10;
+ uint64_t arg11;
+ uint64_t arg12;
+ uint64_t arg13;
+ uint64_t arg14;
+ uint64_t arg15;
+ uint64_t arg16;
+ uint64_t arg17;
+};
+
+/* Convenience macro to declare a SPMD logical partition descriptor. */
+#define DECLARE_SPMD_LOGICAL_PARTITION(_name, _init, _sp_id, _uuid, _properties) \
+ static const struct spmd_lp_desc __partition_desc_ ## _name \
+ __section(".spmd_lp_descs") __used = { \
+ .debug_name = #_name, \
+ .init = (_init), \
+ .sp_id = (_sp_id), \
+ .uuid = _uuid, \
+ .properties = (_properties), \
+ }
+
+IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_START__, SPMD_LP_DESCS_START);
+IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_END__, SPMD_LP_DESCS_END);
+
+#define SPMD_LP_DESCS_COUNT ((SPMD_LP_DESCS_END - SPMD_LP_DESCS_START) \
+ / sizeof(struct spmd_lp_desc))
+CASSERT(sizeof(struct spmd_lp_desc) == 40, assert_spmd_lp_desc_size_mismatch);
+
+/*
+ * Reserve 63 IDs for SPMD Logical Partitions. Currently, 0xFFC0 to 0xFFFE
+ * is reserved.
+ */
+#define SPMD_LP_ID_END (SPMD_DIRECT_MSG_ENDPOINT_ID - 1)
+#define SPMD_LP_ID_START (SPMD_LP_ID_END - 62)
+
+/*
+ * TODO: Arbitrary number. Can make this platform specific in the future,
+ * no known use cases for more LPs at this point.
+ */
+#define EL3_SPMD_MAX_NUM_LP U(5)
+
+static inline bool is_spmd_lp_id(unsigned int id)
+{
+#if ENABLE_SPMD_LP
+ return (id >= SPMD_LP_ID_START && id <= SPMD_LP_ID_END);
+#else
+ return false;
+#endif
+}
+
+static inline bool is_ffa_error(struct ffa_value *retval)
+{
+ return retval->func == FFA_ERROR;
+}
+
+static inline bool is_ffa_success(struct ffa_value *retval)
+{
+ return (retval->func == FFA_SUCCESS_SMC32) ||
+ (retval->func == FFA_SUCCESS_SMC64);
+}
+
+static inline bool is_ffa_direct_msg_resp(struct ffa_value *retval)
+{
+ return (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC32) ||
+ (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC64);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_last_idx(
+ struct ffa_value args)
+{
+ return (uint16_t)(args.arg2 & 0xFFFFU);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_curr_idx(
+ struct ffa_value args)
+{
+ return (uint16_t)((args.arg2 >> 16) & 0xFFFFU);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_tag(struct ffa_value args)
+{
+ return (uint16_t)((args.arg2 >> 32) & 0xFFFFU);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_desc_size(
+ struct ffa_value args)
+{
+ return (uint16_t)(args.arg2 >> 48);
+}
+
+uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1,
+ uint64_t x2, uint64_t x3);
+
+bool ffa_partition_info_regs_get_part_info(
+ struct ffa_value args, uint8_t idx,
+ struct ffa_partition_info_v1_1 *partition_info);
+
+bool spmd_el3_invoke_partition_info_get(
+ const uint32_t target_uuid[4],
+ const uint16_t start_index,
+ const uint16_t tag,
+ struct ffa_value *retval);
+void spmd_logical_sp_set_spmc_initialized(void);
+void spmc_logical_sp_set_spmc_failure(void);
+
+int32_t spmd_logical_sp_init(void);
+bool is_spmd_logical_sp_dir_req_in_progress(
+ spmd_spm_core_context_t *ctx);
+
+bool is_spmd_logical_sp_info_regs_req_in_progress(
+ spmd_spm_core_context_t *ctx);
+
+bool spmd_el3_ffa_msg_direct_req(uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *handle,
+ struct ffa_value *retval);
+
+uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags);
+
+#endif /* EL3_SPMD_LOGICAL_SP_H */
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index 64af437..de56638 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -343,4 +343,28 @@
uint64_t reserved;
};
+/* FF-A Partition Info Get related macros. */
+#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7)
+#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8)
+#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0)
+#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1)
+
+/**
+ * Holds information returned for each partition by the FFA_PARTITION_INFO_GET
+ * interface.
+ */
+struct ffa_partition_info_v1_0 {
+ uint16_t ep_id;
+ uint16_t execution_ctx_count;
+ uint32_t properties;
+};
+
+/* Extended structure for FF-A v1.1. */
+struct ffa_partition_info_v1_1 {
+ uint16_t ep_id;
+ uint16_t execution_ctx_count;
+ uint32_t properties;
+ uint32_t uuid[4];
+};
+
#endif /* FFA_SVC_H */
diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h
index 2ca12c9..8c53ef9 100644
--- a/include/tools_share/cca_oid.h
+++ b/include/tools_share/cca_oid.h
@@ -28,4 +28,17 @@
/* CCAFirmwareNVCounter - Non-volatile counter extension */
#define CCA_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.3"
+/*
+ * First undef previous definitions from tbbr_oid.h.
+ * CCA ROTPK authenticates BL31 and its configuration image in
+ * CCA CoT.
+ **/
+#undef BL31_IMAGE_KEY_OID
+#undef SOC_FW_CONFIG_KEY_OID
+#undef HW_CONFIG_KEY_OID
+#define BL31_IMAGE_KEY_OID ZERO_OID
+#define SOC_FW_CONFIG_KEY_OID ZERO_OID
+#define HW_CONFIG_KEY_OID ZERO_OID
+#define RMM_IMAGE_KEY_OID ZERO_OID
+
#endif /* CCA_OID_H */
diff --git a/include/tools_share/dualroot_oid.h b/include/tools_share/dualroot_oid.h
index 3e88a6d..3762c79 100644
--- a/include/tools_share/dualroot_oid.h
+++ b/include/tools_share/dualroot_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h
index 52b43ab..9881d1a 100644
--- a/include/tools_share/tbbr_oid.h
+++ b/include/tools_share/tbbr_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,8 @@
#ifndef TBBR_OID_H
#define TBBR_OID_H
+#include "zero_oid.h"
+
#define MAX_OID_NAME_LEN 30
/*
@@ -160,6 +162,14 @@
#define SP_PKG7_HASH_OID "1.3.6.1.4.1.4128.2100.1307"
#define SP_PKG8_HASH_OID "1.3.6.1.4.1.4128.2100.1308"
+/*
+ * Public Keys present in SOC FW content certificates authenticate BL31 and
+ * its configuration.
+ */
+#define BL31_IMAGE_KEY_OID SOC_FW_CONTENT_CERT_PK_OID
+#define SOC_FW_CONFIG_KEY_OID SOC_FW_CONTENT_CERT_PK_OID
+#define HW_CONFIG_KEY_OID ZERO_OID
+
#ifdef PLAT_DEF_OID
#include <platform_oid.h>
#endif
diff --git a/include/tools_share/zero_oid.h b/include/tools_share/zero_oid.h
new file mode 100644
index 0000000..9b83094
--- /dev/null
+++ b/include/tools_share/zero_oid.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ZERO_OID_H
+#define ZERO_OID_H
+
+#define ZERO_OID "0.0.0.0.0.0.0.0.0"
+
+#endif /* ZERO_OID_H */
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c
index ea8e2bb..89a9033 100644
--- a/lib/aarch32/arm32_aeabi_divmod.c
+++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch32/arm32_aeabi_divmod_a32.S b/lib/aarch32/arm32_aeabi_divmod_a32.S
index 6915dcd..9155100 100644
--- a/lib/aarch32/arm32_aeabi_divmod_a32.S
+++ b/lib/aarch32/arm32_aeabi_divmod_a32.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch32/armclang_printf.S b/lib/aarch32/armclang_printf.S
index 2b87bf7..e736a11 100644
--- a/lib/aarch32/armclang_printf.S
+++ b/lib/aarch32/armclang_printf.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index 59e15bd..c010cbc 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/aarch64/armclang_printf.S b/lib/aarch64/armclang_printf.S
index 52a6976..f9326fd 100644
--- a/lib/aarch64/armclang_printf.S
+++ b/lib/aarch64/armclang_printf.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/bl_aux_params/bl_aux_params.c b/lib/bl_aux_params/bl_aux_params.c
index 7f357b7..6e30ecf 100644
--- a/lib/bl_aux_params/bl_aux_params.c
+++ b/lib/bl_aux_params/bl_aux_params.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk
index b41c4d0..2b16504 100644
--- a/lib/compiler-rt/compiler-rt.mk
+++ b/lib/compiler-rt/compiler-rt.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
diff --git a/lib/coreboot/coreboot.mk b/lib/coreboot/coreboot.mk
index 4201823..e07d28c 100644
--- a/lib/coreboot/coreboot.mk
+++ b/lib/coreboot/coreboot.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c
index 43e9835..c954e97 100644
--- a/lib/coreboot/coreboot_table.c
+++ b/lib/coreboot/coreboot_table.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S
index 7bd586a..9f45e38 100644
--- a/lib/cpus/aarch32/aem_generic.S
+++ b/lib/cpus/aarch32/aem_generic.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch32/cortex_a12.S b/lib/cpus/aarch32/cortex_a12.S
index 5300fe0..8eec27c 100644
--- a/lib/cpus/aarch32/cortex_a12.S
+++ b/lib/cpus/aarch32/cortex_a12.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,19 +64,16 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a12_disable_smp
endfunc cortex_a12_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A12. Must follow AAPCS.
- */
-func cortex_a12_errata_report
- bx lr
-endfunc cortex_a12_errata_report
-#endif
+errata_report_shim cortex_a12
declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \
cortex_a12_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S
index 1143e9b..b41676d 100644
--- a/lib/cpus/aarch32/cortex_a15.S
+++ b/lib/cpus/aarch32/cortex_a15.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,6 +62,7 @@
bx lr
endfunc check_errata_816470
+add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470
/* ----------------------------------------------------
* Errata Workaround for Cortex A15 Errata #827671.
* This applies only to revision >= r3p0 of Cortex A15.
@@ -91,6 +92,8 @@
b cpu_rev_var_hs
endfunc check_errata_827671
+add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671
+
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@@ -100,6 +103,8 @@
bx lr
endfunc check_errata_cve_2017_5715
+add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov r0, #ERRATA_APPLIES
@@ -109,29 +114,7 @@
bx lr
endfunc check_errata_cve_2022_23960
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A15. Must follow AAPCS.
- */
-func cortex_a15_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A15_816470, cortex_a15, 816470
- report_errata ERRATA_A15_827671, cortex_a15, 827671
- report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715
- report_errata WORKAROUND_CVE_2022_23960, cortex_a15, cve_2022_23960
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a15_errata_report
-#endif
+add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
func cortex_a15_reset_func
mov r5, lr
@@ -180,11 +163,17 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a15_disable_smp
endfunc cortex_a15_cluster_pwr_dwn
+errata_report_shim cortex_a15
+
declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
cortex_a15_reset_func, \
cortex_a15_core_pwr_dwn, \
diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S
index b8abd33..1877570 100644
--- a/lib/cpus/aarch32/cortex_a17.S
+++ b/lib/cpus/aarch32/cortex_a17.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,6 +63,8 @@
b cpu_rev_var_ls
endfunc check_errata_852421
+add_erratum_entry cortex_a17, ERRATUM(852421), ERRATA_A17_852421
+
/* ----------------------------------------------------
* Errata Workaround for Cortex A17 Errata #852423.
* This applies only to revision <= r1p2 of Cortex A17.
@@ -91,6 +93,8 @@
b cpu_rev_var_ls
endfunc check_errata_852423
+add_erratum_entry cortex_a17, ERRATUM(852423), ERRATA_A17_852423
+
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@@ -100,28 +104,9 @@
bx lr
endfunc check_errata_cve_2017_5715
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A17. Must follow AAPCS.
- */
-func cortex_a17_errata_report
- push {r12, lr}
+add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A17_852421, cortex_a17, 852421
- report_errata ERRATA_A17_852423, cortex_a17, 852423
- report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a17_errata_report
-#endif
+errata_report_shim cortex_a17
func cortex_a17_reset_func
mov r5, lr
@@ -139,7 +124,7 @@
#endif
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
- ldr r0, =workaround_bpiall_runtime_exceptions
+ ldr r0, =wa_cve_2017_5715_bpiall_vbar
stcopr r0, VBAR
stcopr r0, MVBAR
/* isb will be applied in the course of the reset func */
@@ -174,6 +159,10 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a17_disable_smp
diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S
index dfa159f..d08b4ff 100644
--- a/lib/cpus/aarch32/cortex_a32.S
+++ b/lib/cpus/aarch32/cortex_a32.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch32/cortex_a5.S b/lib/cpus/aarch32/cortex_a5.S
index 8abb66f..625ea7b 100644
--- a/lib/cpus/aarch32/cortex_a5.S
+++ b/lib/cpus/aarch32/cortex_a5.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,14 +69,7 @@
b cortex_a5_disable_smp
endfunc cortex_a5_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A5. Must follow AAPCS.
- */
-func cortex_a5_errata_report
- bx lr
-endfunc cortex_a5_errata_report
-#endif
+errata_report_shim cortex_a5
declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
cortex_a5_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index 6e3ff81..89b238a 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,6 +44,8 @@
bx lr
endfunc check_errata_819472
+add_erratum_entry cortex_a53, ERRATUM(819472), ERRATA_A53_819472
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #824069.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -59,6 +61,8 @@
bx lr
endfunc check_errata_824069
+add_erratum_entry cortex_a53, ERRATUM(824069), ERRATA_A53_824069
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #826319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -89,6 +93,8 @@
b cpu_rev_var_ls
endfunc check_errata_826319
+add_erratum_entry cortex_a53, ERRATUM(826319), ERRATA_A53_826319
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #827319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -104,6 +110,8 @@
bx lr
endfunc check_errata_827319
+add_erratum_entry cortex_a53, ERRATUM(827319), ERRATA_A53_827319
+
/* ---------------------------------------------------------------------
* Disable the cache non-temporal hint.
*
@@ -142,6 +150,9 @@
b cpu_rev_var_ls
endfunc check_errata_disable_non_temporal_hint
+add_erratum_entry cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT, \
+ disable_non_temporal_hint
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #855873.
*
@@ -176,6 +187,8 @@
b cpu_rev_var_hs
endfunc check_errata_855873
+add_erratum_entry cortex_a53, ERRATUM(855873), ERRATA_A53_855873
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A53.
* Shall clobber: r0-r6
@@ -284,31 +297,7 @@
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A53. Must follow AAPCS.
- */
-func cortex_a53_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A53_819472, cortex_a53, 819472
- report_errata ERRATA_A53_824069, cortex_a53, 824069
- report_errata ERRATA_A53_826319, cortex_a53, 826319
- report_errata ERRATA_A53_827319, cortex_a53, 827319
- report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
- report_errata ERRATA_A53_855873, cortex_a53, 855873
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a53_errata_report
-#endif
+errata_report_shim cortex_a53
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
cortex_a53_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S
index 18ee1f9..1e5377b 100644
--- a/lib/cpus/aarch32/cortex_a57.S
+++ b/lib/cpus/aarch32/cortex_a57.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -86,6 +86,8 @@
b cpu_rev_var_ls
endfunc check_errata_806969
+add_erratum_entry cortex_a57, ERRATUM(806969), ERRATA_A57_806969
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #813419.
* This applies only to revision r0p0 of Cortex A57.
@@ -101,6 +103,8 @@
bx lr
endfunc check_errata_813419
+add_erratum_entry cortex_a57, ERRATUM(813419), ERRATA_A57_813419
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #813420.
* This applies only to revision r0p0 of Cortex A57.
@@ -130,6 +134,8 @@
b cpu_rev_var_ls
endfunc check_errata_813420
+add_erratum_entry cortex_a57, ERRATUM(813420), ERRATA_A57_813420
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #814670.
* This applies only to revision r0p0 of Cortex A57.
@@ -159,6 +165,8 @@
b cpu_rev_var_ls
endfunc check_errata_814670
+add_erratum_entry cortex_a57, ERRATUM(814670), ERRATA_A57_814670
+
/* ----------------------------------------------------
* Errata Workaround for Cortex A57 Errata #817169.
* This applies only to revision <= r0p1 of Cortex A57.
@@ -173,6 +181,8 @@
bx lr
endfunc check_errata_817169
+add_erratum_entry cortex_a57, ERRATUM(817169), ERRATA_A57_817169
+
/* --------------------------------------------------------------------
* Disable the over-read from the LDNP instruction.
*
@@ -205,6 +215,8 @@
b cpu_rev_var_ls
endfunc check_errata_disable_ldnp_overread
+add_erratum_entry cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT, disable_ldnp_overread
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #826974.
* This applies only to revision <= r1p1 of Cortex A57.
@@ -234,6 +246,8 @@
b cpu_rev_var_ls
endfunc check_errata_826974
+add_erratum_entry cortex_a57, ERRATUM(826974), ERRATA_A57_826974
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #826977.
* This applies only to revision <= r1p1 of Cortex A57.
@@ -263,6 +277,8 @@
b cpu_rev_var_ls
endfunc check_errata_826977
+add_erratum_entry cortex_a57, ERRATUM(826977), ERRATA_A57_826977
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #828024.
* This applies only to revision <= r1p1 of Cortex A57.
@@ -298,6 +314,8 @@
b cpu_rev_var_ls
endfunc check_errata_828024
+add_erratum_entry cortex_a57, ERRATUM(828024), ERRATA_A57_828024
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #829520.
* This applies only to revision <= r1p2 of Cortex A57.
@@ -327,6 +345,8 @@
b cpu_rev_var_ls
endfunc check_errata_829520
+add_erratum_entry cortex_a57, ERRATUM(829520), ERRATA_A57_829520
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #833471.
* This applies only to revision <= r1p2 of Cortex A57.
@@ -356,6 +376,8 @@
b cpu_rev_var_ls
endfunc check_errata_833471
+add_erratum_entry cortex_a57, ERRATUM(833471), ERRATA_A57_833471
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #859972.
* This applies only to revision <= r1p3 of Cortex A57.
@@ -382,11 +404,15 @@
b cpu_rev_var_ls
endfunc check_errata_859972
+add_erratum_entry cortex_a57, ERRATUM(859972), ERRATA_A57_859972
+
func check_errata_cve_2017_5715
mov r0, #ERRATA_MISSING
bx lr
endfunc check_errata_cve_2017_5715
+add_erratum_entry cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov r0, #ERRATA_APPLIES
@@ -396,11 +422,15 @@
bx lr
endfunc check_errata_cve_2018_3639
+add_erratum_entry cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+
func check_errata_cve_2022_23960
mov r0, #ERRATA_MISSING
bx lr
endfunc check_errata_cve_2022_23960
+add_erratum_entry cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57.
* Shall clobber: r0-r6
@@ -576,41 +606,7 @@
b cortex_a57_disable_ext_debug
endfunc cortex_a57_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A57. Must follow AAPCS.
- */
-func cortex_a57_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A57_806969, cortex_a57, 806969
- report_errata ERRATA_A57_813419, cortex_a57, 813419
- report_errata ERRATA_A57_813420, cortex_a57, 813420
- report_errata ERRATA_A57_814670, cortex_a57, 814670
- report_errata ERRATA_A57_817169, cortex_a57, 817169
- report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
- disable_ldnp_overread
- report_errata ERRATA_A57_826974, cortex_a57, 826974
- report_errata ERRATA_A57_826977, cortex_a57, 826977
- report_errata ERRATA_A57_828024, cortex_a57, 828024
- report_errata ERRATA_A57_829520, cortex_a57, 829520
- report_errata ERRATA_A57_833471, cortex_a57, 833471
- report_errata ERRATA_A57_859972, cortex_a57, 859972
- report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a57_errata_report
-#endif
+errata_report_shim cortex_a57
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
cortex_a57_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a7.S b/lib/cpus/aarch32/cortex_a7.S
index 4d4bb77..4842ca6 100644
--- a/lib/cpus/aarch32/cortex_a7.S
+++ b/lib/cpus/aarch32/cortex_a7.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,19 +64,16 @@
bl plat_disable_acp
+ /* Flush L2 caches */
+ mov r0, #DC_OP_CISW
+ bl dcsw_op_level2
+
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a7_disable_smp
endfunc cortex_a7_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A7. Must follow AAPCS.
- */
-func cortex_a7_errata_report
- bx lr
-endfunc cortex_a7_errata_report
-#endif
+errata_report_shim cortex_a7
declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
cortex_a7_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a9.S b/lib/cpus/aarch32/cortex_a9.S
index 7200343..1e9757a 100644
--- a/lib/cpus/aarch32/cortex_a9.S
+++ b/lib/cpus/aarch32/cortex_a9.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -35,14 +35,16 @@
bx lr
endfunc cortex_a9_enable_smp
-func check_errata_a9_794073
+func check_errata_794073
#if ERRATA_A9_794073
mov r0, #ERRATA_APPLIES
#else
mov r0, #ERRATA_MISSING
#endif
bx lr
-endfunc check_errata_cve_2017_5715
+endfunc check_errata_794073
+
+add_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
@@ -53,31 +55,13 @@
bx lr
endfunc check_errata_cve_2017_5715
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A9. Must follow AAPCS.
- */
-func cortex_a9_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
+add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715
- report_errata ERRATA_A9_794073, cortex_a9, a9_79407
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a9_errata_report
-#endif
+errata_report_shim cortex_a9
func cortex_a9_reset_func
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
- ldr r0, =workaround_bpiall_runtime_exceptions
+ ldr r0, =wa_cve_2017_5715_bpiall_vbar
stcopr r0, VBAR
stcopr r0, MVBAR
/* isb will be applied in the course of the reset func */
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 05bc5d9..83e3e49 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 6291e43..d47279a 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index be3c652..6ffb944 100644
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,9 +16,7 @@
* ---------------------------------------------
*/
func cortex_a35_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a35_disable_dcache
@@ -28,65 +26,29 @@
* ---------------------------------------------
*/
func cortex_a35_disable_smp
- mrs x0, CORTEX_A35_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- msr CORTEX_A35_CPUECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
isb
dsb sy
ret
endfunc cortex_a35_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A35 Errata #855472.
- * This applies to revisions r0p0 of Cortex A35.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a35_855472_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_855472
- cbz x0, 1f
- mrs x1, CORTEX_A35_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
- msr CORTEX_A35_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a35_855472_wa
+workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
+ sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
+workaround_reset_end cortex_a35, ERRATUM(855472)
-func check_errata_855472
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_855472
+check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A35.
- * Clobbers: x0
* -------------------------------------------------
*/
-func cortex_a35_reset_func
- mov x19, x30
- bl cpu_get_rev_var
-
-#if ERRATA_A35_855472
- bl errata_a35_855472_wa
-#endif
-
+cpu_reset_func_start cortex_a35
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CORTEX_A35_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- msr CORTEX_A35_CPUECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a35_reset_func
+ sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
+cpu_reset_func_end cortex_a35
func cortex_a35_core_pwr_dwn
mov x18, x30
@@ -149,27 +111,7 @@
b cortex_a35_disable_smp
endfunc cortex_a35_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A35. Must follow AAPCS.
- */
-func cortex_a35_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A35_855472, cortex_a35, 855472
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a35_errata_report
-#endif
-
+errata_report_shim cortex_a35
/* ---------------------------------------------
* This function provides cortex_a35 specific
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index e10ebb0..6fce24e 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -21,110 +21,15 @@
#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #1922240.
- * This applies only to revision r0p0 (fixed in r0p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_1922240_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1922240
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- mov x1, #3
- bfi x0, x1, #10, #2
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_1922240_wa
-
-func check_errata_1922240
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1922240
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2288014.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0. (fixed in r1p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2288014_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2288014
- cbz x0, 1f
-
- /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- mov x1, #1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2288014_wa
-
-func check_errata_2288014
- /* Applies to r1p0 and below */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2288014
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2042739.
- * This applies only to revisions r0p0, r0p1 and r0p2.
- * (fixed in r0p3)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2042739_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2042739
- cbz x0, 1f
-
- /* Apply the workaround by disabling ReadPreferUnique. */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2042739_wa
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(1922240)
-func check_errata_2042739
- /* Applies to revisions r0p0 - r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2042739
+check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2041909.
- * This applies only to revision r0p2 and it is fixed in
- * r0p3. The issue is also present in r0p0 and r0p1 but
- * there is no workaround in those revisions.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2041909_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2041909
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909
/* Apply workaround */
mov x0, xzr
msr S3_6_C15_C4_0, x0
@@ -140,39 +45,55 @@
mov x0, #0x3F1
movk x0, #0x110, lsl #16
msr S3_6_C15_C4_1, x0
- isb
+workaround_reset_end cortex_a510, ERRATUM(2041909)
+
+check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2)
+
+workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739
+ /* Apply the workaround by disabling ReadPreferUnique. */
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2042739)
-1:
- ret x17
-endfunc errata_cortex_a510_2041909_wa
+check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
-func check_errata_2041909
- /* Applies only to revision r0p2 */
- mov x1, #0x02
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2041909
+workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
+ /*
+ * Force L2 allocation of transient lines by setting
+ * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+ */
+ mrs x0, CORTEX_A510_CPUECTLR_EL1
+ mov x1, #1
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+ msr CORTEX_A510_CPUECTLR_EL1, x0
+workaround_reset_end cortex_a510, ERRATUM(2172148)
+
+check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950
+ /* Set bit 18 in CPUACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+ /* Set bit 25 in CMPXACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+workaround_reset_end cortex_a510, ERRATUM(2218950)
+
+check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0)
/* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2250311.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
* This workaround is not a typical errata fix. MPMM
* is disabled here, but this conflicts with the BL31
* MPMM support. So in addition to simply disabling
* the feature, a flag is set in the MPMM library
* indicating that it should not be enabled even if
* ENABLE_MPMM=1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
-func errata_cortex_a510_2250311_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2250311
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311
/* Disable MPMM */
mrs x0, CPUMPMMCR_EL3
bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
@@ -182,227 +103,68 @@
/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
bl mpmm_errata_disable
#endif
-
-1:
- ret x17
-endfunc errata_cortex_a510_2250311_wa
-
-func check_errata_2250311
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2250311
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2218950.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2218950_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2218950
- cbz x0, 1f
-
- /* Source register for BFI */
- mov x1, #1
-
- /* Set bit 18 in CPUACTLR_EL1 */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
- /* Set bit 25 in CMPXACTLR_EL1 */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- bfi x0, x1, #25, #1
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2218950_wa
+workaround_reset_end cortex_a510, ERRATUM(2250311)
-func check_errata_2218950
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2218950
+check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2172148.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2172148_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2172148
- cbz x0, 1f
-
- /*
- * Force L2 allocation of transient lines by setting
- * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
- */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #1
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2172148_wa
-
-func check_errata_2172148
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2172148
+workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014
+ /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2288014)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2347730.
- * This applies to revisions r0p0 - r0p3, r1p0, r1p1.
- * It is fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_cortex_a510_2347730_wa
- mov x17, x30
- bl check_errata_2347730
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
+workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
/*
* Set CPUACTLR_EL1[17] to 1'b1, which disables
* specific microarchitectural clock gating
* behaviour.
*/
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2347730_wa
-
-func check_errata_2347730
- /* Applies to revisions r1p1 and lower. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2347730
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17
+workaround_reset_end cortex_a510, ERRATUM(2347730)
- /*---------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2371937.
- * This applies to revisions r1p1 and lower, and is
- * fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- *---------------------------------------------------
- */
-func errata_cortex_a510_2371937_wa
- mov x17, x30
- bl check_errata_2371937
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1)
+workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937
/*
* Cacheable atomic operations can be forced
* to be executed near by setting
* IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found
* in [40:38] of CPUECTLR_EL1.
*/
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR
- bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3
- msr CORTEX_A510_CPUECTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_a510_2371937_wa
-
-func check_errata_2371937
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2371937
-
- /* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2666669
- * This applies to revisions r1p1 and lower, and is fixed
- * in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ------------------------------------------------------
- */
-func errata_cortex_a510_2666669_wa
- mov x17, x30
- bl check_errata_2666669
- cbz x0, 1f
-
- /*
- * Workaround will set IMP_CPUACTLR_EL1[38]
- * to 0b1.
- */
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2666669_wa
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \
+ CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2371937)
-func check_errata_2666669
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2666669
+check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1)
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
- */
- .globl errata_cortex_a510_2684597_wa
-func errata_cortex_a510_2684597_wa
- mov x17, x30
- /* Ensure this errata is only applied to Cortex-A510 cores */
- jump_if_cpu_midr CORTEX_A510_MIDR, 1f
- b 2f
+workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38
+workaround_reset_end cortex_a510, ERRATUM(2666669)
-1:
- /* Check workaround compatibility. */
- mov x0, x18
- bl check_errata_2684597
- cbz x0, 2f
+check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1)
+.global erratum_cortex_a510_2684597_wa
+workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR
/*
* Many assemblers do not yet understand the "tsb csync" mnemonic,
* so use the equivalent hint instruction.
*/
hint #18 /* tsb csync */
-2:
- ret x17
-endfunc errata_cortex_a510_2684597_wa
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
+workaround_runtime_end cortex_a510, ERRATUM(2684597)
+
+check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
+
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a510
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func check_errata_2684597
- /* Applies to revision < r1p3 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2684597
+.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -413,112 +175,17 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A510_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a510_core_pwr_dwn
- /*
- * Errata printing function for Cortex-A510. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a510_errata_report
- stp x8, x30, [sp, #-16]!
+errata_report_shim cortex_a510
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A510_1922240, cortex_a510, 1922240
- report_errata ERRATA_A510_2041909, cortex_a510, 2041909
- report_errata ERRATA_A510_2042739, cortex_a510, 2042739
- report_errata ERRATA_A510_2172148, cortex_a510, 2172148
- report_errata ERRATA_A510_2218950, cortex_a510, 2218950
- report_errata ERRATA_A510_2250311, cortex_a510, 2250311
- report_errata ERRATA_A510_2288014, cortex_a510, 2288014
- report_errata ERRATA_A510_2347730, cortex_a510, 2347730
- report_errata ERRATA_A510_2371937, cortex_a510, 2371937
- report_errata ERRATA_A510_2666669, cortex_a510, 2666669
- report_errata ERRATA_A510_2684597, cortex_a510, 2684597
- report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a510_errata_report
-#endif
-
-func cortex_a510_reset_func
- mov x19, x30
-
+cpu_reset_func_start cortex_a510
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A510_1922240
- mov x0, x18
- bl errata_cortex_a510_1922240_wa
-#endif
-
-#if ERRATA_A510_2288014
- mov x0, x18
- bl errata_cortex_a510_2288014_wa
-#endif
-
-#if ERRATA_A510_2042739
- mov x0, x18
- bl errata_cortex_a510_2042739_wa
-#endif
-
-#if ERRATA_A510_2041909
- mov x0, x18
- bl errata_cortex_a510_2041909_wa
-#endif
-
-#if ERRATA_A510_2250311
- mov x0, x18
- bl errata_cortex_a510_2250311_wa
-#endif
-
-#if ERRATA_A510_2218950
- mov x0, x18
- bl errata_cortex_a510_2218950_wa
-#endif
-
-#if ERRATA_A510_2371937
- mov x0, x18
- bl errata_cortex_a510_2371937_wa
-#endif
-
-#if ERRATA_A510_2172148
- mov x0, x18
- bl errata_cortex_a510_2172148_wa
-#endif
-
-#if ERRATA_A510_2347730
- mov x0, x18
- bl errata_cortex_a510_2347730_wa
-#endif
-
-#if ERRATA_A510_2666669
- mov x0, x18
- bl errata_cortex_a510_2666669_wa
-#endif
-
- isb
- ret x19
-endfunc cortex_a510_reset_func
+cpu_reset_func_end cortex_a510
/* ---------------------------------------------
* This function provides Cortex-A510 specific
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index 5bbe862..6c2f33e 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -30,28 +30,17 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A520_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A520_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a520_core_pwr_dwn
- /*
- * Errata printing function for Cortex A520. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a520_errata_report
- ret
-endfunc cortex_a520_errata_report
-#endif
+errata_report_shim cortex_a520
-func cortex_a520_reset_func
+cpu_reset_func_start cortex_a520
/* Disable speculative loads */
msr SSBS, xzr
- isb
- ret
-endfunc cortex_a520_reset_func
+cpu_reset_func_end cortex_a520
/* ---------------------------------------------
* This function provides Cortex A520 specific
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index ecaf422..e6fb08a 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,19 +12,12 @@
#include <plat_macros.S>
#include <lib/cpus/errata.h>
-#if A53_DISABLE_NON_TEMPORAL_HINT
-#undef ERRATA_A53_836870
-#define ERRATA_A53_836870 1
-#endif
-
/* ---------------------------------------------
* Disable L1 data cache and unified L2 cache
* ---------------------------------------------
*/
func cortex_a53_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a53_disable_dcache
@@ -34,169 +27,38 @@
* ---------------------------------------------
*/
func cortex_a53_disable_smp
- mrs x0, CORTEX_A53_ECTLR_EL1
- bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
- msr CORTEX_A53_ECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT
isb
dsb sy
ret
endfunc cortex_a53_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A53 Errata #819472.
- * This applies only to revision <= r0p1 of Cortex A53.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * ---------------------------------------------------
- */
-func check_errata_819472
-#if ERRATA_A53_819472
- mov x0, #ERRATA_APPLIES
- ret
-#else
- mov x1, #0x01
- b cpu_rev_var_ls
-#endif
-endfunc check_errata_819472
+/* Due to the nature of the errata it is applied unconditionally when chosen */
+check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1)
+/* erratum workaround is interleaved with generic code */
+add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A53 Errata #824069.
- * This applies only to revision <= r0p2 of Cortex A53.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * ---------------------------------------------------
- */
-func check_errata_824069
-#if ERRATA_A53_824069
- mov x0, #ERRATA_APPLIES
- ret
-#else
- mov x1, #0x02
- b cpu_rev_var_ls
-#endif
-endfunc check_errata_824069
+/* Due to the nature of the errata it is applied unconditionally when chosen */
+check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2)
+/* erratum workaround is interleaved with generic code */
+add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
- /* --------------------------------------------------
- * Errata Workaround for Cortex A53 Errata #826319.
- * This applies only to revision <= r0p2 of Cortex A53.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a53_826319_wa
- /*
- * Compare x0 against revision r0p2
- */
- mov x17, x30
- bl check_errata_826319
- cbz x0, 1f
+workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319
mrs x1, CORTEX_A53_L2ACTLR_EL1
bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
msr CORTEX_A53_L2ACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a53_826319_wa
-
-func check_errata_826319
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_826319
-
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A53 Errata #827319.
- * This applies only to revision <= r0p2 of Cortex A53.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * ---------------------------------------------------
- */
-func check_errata_827319
-#if ERRATA_A53_827319
- mov x0, #ERRATA_APPLIES
- ret
-#else
- mov x1, #0x02
- b cpu_rev_var_ls
-#endif
-endfunc check_errata_827319
-
- /* ---------------------------------------------------------------------
- * Disable the cache non-temporal hint.
- *
- * This ignores the Transient allocation hint in the MAIR and treats
- * allocations the same as non-transient allocation types. As a result,
- * the LDNP and STNP instructions in AArch64 behave the same as the
- * equivalent LDP and STP instructions.
- *
- * This is relevant only for revisions <= r0p3 of Cortex-A53.
- * From r0p4 and onwards, the bit to disable the hint is enabled by
- * default at reset.
- *
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func a53_disable_non_temporal_hint
- /*
- * Compare x0 against revision r0p3
- */
- mov x17, x30
- bl check_errata_disable_non_temporal_hint
- cbz x0, 1f
- mrs x1, CORTEX_A53_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
- msr CORTEX_A53_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc a53_disable_non_temporal_hint
-
-func check_errata_disable_non_temporal_hint
- mov x1, #0x03
- b cpu_rev_var_ls
-endfunc check_errata_disable_non_temporal_hint
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A53 Errata #855873.
- *
- * This applies only to revisions >= r0p3 of Cortex A53.
- * Earlier revisions of the core are affected as well, but don't
- * have the chicken bit in the CPUACTLR register. It is expected that
- * the rich OS takes care of that, especially as the workaround is
- * shared with other erratas in those revisions of the CPU.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a53_855873_wa
- /*
- * Compare x0 against revision r0p3 and higher
- */
- mov x17, x30
- bl check_errata_855873
- cbz x0, 1f
+workaround_reset_end cortex_a53, ERRATUM(826319)
- mrs x1, CORTEX_A53_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
- msr CORTEX_A53_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a53_855873_wa
+check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2)
-func check_errata_855873
- mov x1, #0x03
- b cpu_rev_var_hs
-endfunc check_errata_855873
+/* Due to the nature of the errata it is applied unconditionally when chosen */
+check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2)
+/* erratum workaround is interleaved with generic code */
+add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
-/*
- * Errata workaround for Cortex A53 Errata #835769.
- * This applies to revisions <= r0p4 of Cortex A53.
- * This workaround is statically enabled at build time.
- */
-func check_errata_835769
- cmp x0, #0x04
+check_erratum_custom_start cortex_a53, ERRATUM(835769)
+ cmp x0, CPU_REV(0, 4)
b.hi errata_not_applies
/*
* Fix potentially available for revisions r0p2, r0p3 and r0p4.
@@ -213,17 +75,29 @@
mov x0, #ERRATA_NOT_APPLIES
exit_check_errata_835769:
ret
-endfunc check_errata_835769
+check_erratum_custom_end cortex_a53, ERRATUM(835769)
-/*
- * Errata workaround for Cortex A53 Errata #843419.
- * This applies to revisions <= r0p4 of Cortex A53.
- * This workaround is statically enabled at build time.
- */
-func check_errata_843419
+/* workaround at build time */
+add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET
+
+ /*
+ * Disable the cache non-temporal hint.
+ *
+ * This ignores the Transient allocation hint in the MAIR and treats
+ * allocations the same as non-transient allocation types. As a result,
+ * the LDNP and STNP instructions in AArch64 behave the same as the
+ * equivalent LDP and STP instructions.
+ */
+workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT
+ sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH
+workaround_reset_end cortex_a53, ERRATUM(836870)
+
+check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3)
+
+check_erratum_custom_start cortex_a53, ERRATUM(843419)
mov x1, #ERRATA_APPLIES
mov x2, #ERRATA_NOT_APPLIES
- cmp x0, #0x04
+ cmp x0, CPU_REV(0, 4)
csel x0, x1, x2, ls
/*
* Fix potentially available for revision r0p4.
@@ -237,58 +111,32 @@
mov x0, x2
exit_check_errata_843419:
ret
-endfunc check_errata_843419
+check_erratum_custom_end cortex_a53, ERRATUM(843419)
- /* --------------------------------------------------
- * Errata workaround for Cortex A53 Errata #1530924.
- * This applies to all revisions of Cortex A53.
- * --------------------------------------------------
- */
-func check_errata_1530924
-#if ERRATA_A53_1530924
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_1530924
+/* workaround at build time */
+add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A53.
- * Shall clobber: x0-x19
- * -------------------------------------------------
+ /*
+ * Earlier revisions of the core are affected as well, but don't
+ * have the chicken bit in the CPUACTLR register. It is expected that
+ * the rich OS takes care of that, especially as the workaround is
+ * shared with other erratas in those revisions of the CPU.
*/
-func cortex_a53_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873
+ sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
+workaround_reset_end cortex_a53, ERRATUM(855873)
+check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3)
-#if ERRATA_A53_826319
- mov x0, x18
- bl errata_a53_826319_wa
-#endif
+check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924
-#if ERRATA_A53_836870
- mov x0, x18
- bl a53_disable_non_temporal_hint
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET
-#if ERRATA_A53_855873
- mov x0, x18
- bl errata_a53_855873_wa
-#endif
-
- /* ---------------------------------------------
- * Enable the SMP bit.
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A53_ECTLR_EL1
- orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
- msr CORTEX_A53_ECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a53_reset_func
+cpu_reset_func_start cortex_a53
+ /* Enable the SMP bit. */
+ sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT
+cpu_reset_func_end cortex_a53
func cortex_a53_core_pwr_dwn
mov x18, x30
@@ -351,34 +199,7 @@
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A53. Must follow AAPCS.
- */
-func cortex_a53_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A53_819472, cortex_a53, 819472
- report_errata ERRATA_A53_824069, cortex_a53, 824069
- report_errata ERRATA_A53_826319, cortex_a53, 826319
- report_errata ERRATA_A53_827319, cortex_a53, 827319
- report_errata ERRATA_A53_835769, cortex_a53, 835769
- report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
- report_errata ERRATA_A53_843419, cortex_a53, 843419
- report_errata ERRATA_A53_855873, cortex_a53, 855873
- report_errata ERRATA_A53_1530924, cortex_a53, 1530924
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a53_errata_report
-#endif
+errata_report_shim cortex_a53
/* ---------------------------------------------
* This function provides cortex_a53 specific
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 0e0388b..712b6e0 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,63 +18,37 @@
.globl cortex_a55_reset_func
.globl cortex_a55_core_pwr_dwn
- /* --------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #768277.
- * This applies only to revision r0p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a55_768277_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_768277
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_768277_wa
-func check_errata_768277
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_768277
+/* ERRATA_DSU_798953:
+ * The errata is defined in dsu_helpers.S but applies to cortex_a55
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953
+.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa
+add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
- /* ------------------------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #778703.
- * This applies only to revision r0p0 of Cortex A55 where L2 cache is
- * not configured.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ------------------------------------------------------------------
- */
-func errata_a55_778703_wa
- /*
- * Compare x0 against revision r0p0 and check that no private L2 cache
- * is configured
- */
- mov x17, x30
- bl check_errata_778703
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
- msr CORTEX_A55_CPUECTLR_EL1, x1
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_778703_wa
+/* ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S but applies to cortex_a55
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184
+.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+
+workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+workaround_reset_end cortex_a55, ERRATUM(768277)
-func check_errata_778703
+check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
+
+workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
+ sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
+workaround_reset_end cortex_a55, ERRATUM(778703)
+
+check_erratum_custom_start cortex_a55, ERRATUM(778703)
mov x16, x30
mov x1, #0x00
bl cpu_rev_var_ls
@@ -87,111 +61,27 @@
mov x2, #ERRATA_NOT_APPLIES
csel x0, x0, x2, eq
ret x16
-endfunc check_errata_778703
+check_erratum_custom_end cortex_a55, ERRATUM(778703)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #798797.
- * This applies only to revision r0p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a55_798797_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_798797
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_798797_wa
+workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+workaround_reset_end cortex_a55, ERRATUM(798797)
-func check_errata_798797
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_798797
+check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
- /* --------------------------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #846532.
- * This applies only to revisions <= r0p1 of Cortex A55.
- * Disabling dual-issue has a small impact on performance. Disabling a
- * power optimization feature is an alternate workaround with no impact
- * on performance but with an increase in power consumption (see errata
- * notice).
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------------------------
- */
-func errata_a55_846532_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_846532
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_846532_wa
+workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+workaround_reset_end cortex_a55, ERRATUM(846532)
-func check_errata_846532
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_846532
+check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
- /* -----------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #903758.
- * This applies only to revisions <= r0p1 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------
- */
-func errata_a55_903758_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_903758
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_903758_wa
+workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+workaround_reset_end cortex_a55, ERRATUM(903758)
-func check_errata_903758
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_903758
+check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
- /* -----------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #1221012.
- * This applies only to revisions <= r1p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------
- */
-func errata_a55_1221012_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1221012
- cbz x0, 1f
+workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
mov x0, #0x0020
movk x0, #0x0850, lsl #16
msr CPUPOR_EL3, x0
@@ -214,121 +104,30 @@
mov x0, #0x03fd
movk x0, #0x0110, lsl #16
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_a55_1221012_wa
+workaround_reset_end cortex_a55, ERRATUM(1221012)
-func check_errata_1221012
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1221012
+check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata workaround for Cortex A55 Errata #1530923.
- * This applies to all revisions of Cortex A55.
- * --------------------------------------------------
- */
-func check_errata_1530923
-#if ERRATA_A55_1530923
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_1530923
-
-func cortex_a55_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_798953
- bl errata_dsu_798953_wa
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A55_768277
- mov x0, x18
- bl errata_a55_768277_wa
-#endif
-
-#if ERRATA_A55_778703
- mov x0, x18
- bl errata_a55_778703_wa
-#endif
-
-#if ERRATA_A55_798797
- mov x0, x18
- bl errata_a55_798797_wa
-#endif
+check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
-#if ERRATA_A55_846532
- mov x0, x18
- bl errata_a55_846532_wa
-#endif
-
-#if ERRATA_A55_903758
- mov x0, x18
- bl errata_a55_903758_wa
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
-#if ERRATA_A55_1221012
- mov x0, x18
- bl errata_a55_1221012_wa
-#endif
+cpu_reset_func_start cortex_a55
+cpu_reset_func_end cortex_a55
- ret x19
-endfunc cortex_a55_reset_func
+errata_report_shim cortex_a55
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a55_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A55_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
- msr CORTEX_A55_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a55_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
- */
-func cortex_a55_errata_report
- stp x8, x30, [sp, #-16]!
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision variant information is at x8, where
- * "report_errata" is expecting it and it doesn't corrupt it.
- */
- report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
- report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
- report_errata ERRATA_A55_768277, cortex_a55, 768277
- report_errata ERRATA_A55_778703, cortex_a55, 778703
- report_errata ERRATA_A55_798797, cortex_a55, 798797
- report_errata ERRATA_A55_846532, cortex_a55, 846532
- report_errata ERRATA_A55_903758, cortex_a55, 903758
- report_errata ERRATA_A55_1221012, cortex_a55, 1221012
- report_errata ERRATA_A55_1530923, cortex_a55, 1530923
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a55_errata_report
-#endif
-
/* ---------------------------------------------
* This function provides cortex_a55 specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 3766ec7..8fafaca 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -18,9 +18,7 @@
* ---------------------------------------------
*/
func cortex_a57_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a57_disable_dcache
@@ -46,9 +44,7 @@
* ---------------------------------------------
*/
func cortex_a57_disable_smp
- mrs x0, CORTEX_A57_ECTLR_EL1
- bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
- msr CORTEX_A57_ECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
ret
endfunc cortex_a57_disable_smp
@@ -60,227 +56,66 @@
mov x0, #1
msr osdlr_el1, x0
isb
-#if ERRATA_A57_817169
- /*
- * Invalidate any TLB address
- */
- mov x0, #0
- tlbi vae3, x0
-#endif
+
+ apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169
+
dsb sy
ret
endfunc cortex_a57_disable_ext_debug
- /* --------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #806969.
- * This applies only to revision r0p0 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a57_806969_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_806969
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_806969_wa
+/*
+ * Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't
+ * provide and erratum number, so assign it an obvious 1
+ */
+workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
+workaround_reset_end cortex_a57, ERRATUM(1)
-func check_errata_806969
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_806969
+check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #813419.
- * This applies only to revision r0p0 of Cortex A57.
- * ---------------------------------------------------
- */
-func check_errata_813419
- /*
- * Even though this is only needed for revision r0p0, it
- * is always applied due to limitations of the current
- * errata framework.
- */
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_errata_813419
+workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+workaround_reset_end cortex_a57, ERRATUM(806969)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #813420.
- * This applies only to revision r0p0 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_813420_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_813420
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_813420_wa
+check_erratum_ls cortex_a57, ERRATUM(806969), CPU_REV(0, 0)
-func check_errata_813420
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_813420
+/* erratum always worked around, but report it correctly */
+check_erratum_ls cortex_a57, ERRATUM(813419), CPU_REV(0, 0)
+add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #814670.
- * This applies only to revision r0p0 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_814670_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_814670
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
- msr CORTEX_A57_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a57_814670_wa
+workaround_reset_start cortex_a57, ERRATUM(813420), ERRATA_A57_813420
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
+workaround_reset_end cortex_a57, ERRATUM(813420)
-func check_errata_814670
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_814670
+check_erratum_ls cortex_a57, ERRATUM(813420), CPU_REV(0, 0)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #817169.
- * This applies only to revision <= r0p1 of Cortex A57.
- * ----------------------------------------------------
- */
-func check_errata_817169
- /*
- * Even though this is only needed for revision <= r0p1, it
- * is always applied because of the low cost of the workaround.
- */
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_errata_817169
+workaround_reset_start cortex_a57, ERRATUM(814670), ERRATA_A57_814670
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
+workaround_reset_end cortex_a57, ERRATUM(814670)
- /* --------------------------------------------------------------------
- * Disable the over-read from the LDNP instruction.
- *
- * This applies to all revisions <= r1p2. The performance degradation
- * observed with LDNP/STNP has been fixed on r1p3 and onwards.
- *
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func a57_disable_ldnp_overread
- /*
- * Compare x0 against revision r1p2
- */
- mov x17, x30
- bl check_errata_disable_ldnp_overread
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc a57_disable_ldnp_overread
+check_erratum_ls cortex_a57, ERRATUM(814670), CPU_REV(0, 0)
-func check_errata_disable_ldnp_overread
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_disable_ldnp_overread
+workaround_runtime_start cortex_a57, ERRATUM(817169), ERRATA_A57_817169, CORTEX_A57_MIDR
+ /* Invalidate any TLB address */
+ mov x0, #0
+ tlbi vae3, x0
+workaround_runtime_end cortex_a57, ERRATUM(817169), NO_ISB
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #826974.
- * This applies only to revision <= r1p1 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_826974_wa
- /*
- * Compare x0 against revision r1p1
- */
- mov x17, x30
- bl check_errata_826974
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_826974_wa
+check_erratum_ls cortex_a57, ERRATUM(817169), CPU_REV(0, 1)
-func check_errata_826974
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_826974
+workaround_reset_start cortex_a57, ERRATUM(826974), ERRATA_A57_826974
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
+workaround_reset_end cortex_a57, ERRATUM(826974)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #826977.
- * This applies only to revision <= r1p1 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_826977_wa
- /*
- * Compare x0 against revision r1p1
- */
- mov x17, x30
- bl check_errata_826977
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_826977_wa
+check_erratum_ls cortex_a57, ERRATUM(826974), CPU_REV(1, 1)
-func check_errata_826977
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_826977
+workaround_reset_start cortex_a57, ERRATUM(826977), ERRATA_A57_826977
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
+workaround_reset_end cortex_a57, ERRATUM(826977)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #828024.
- * This applies only to revision <= r1p1 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_828024_wa
- /*
- * Compare x0 against revision r1p1
- */
- mov x17, x30
- bl check_errata_828024
- cbz x0, 1f
+check_erratum_ls cortex_a57, ERRATUM(826977), CPU_REV(1, 1)
+
+workaround_reset_start cortex_a57, ERRATUM(828024), ERRATA_A57_828024
mrs x1, CORTEX_A57_CPUACTLR_EL1
/*
* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
@@ -291,234 +126,64 @@
orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_828024_wa
-
-func check_errata_828024
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_828024
-
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #829520.
- * This applies only to revision <= r1p2 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_829520_wa
- /*
- * Compare x0 against revision r1p2
- */
- mov x17, x30
- bl check_errata_829520
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_829520_wa
-
-func check_errata_829520
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_829520
-
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #833471.
- * This applies only to revision <= r1p2 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a57_833471_wa
- /*
- * Compare x0 against revision r1p2
- */
- mov x17, x30
- bl check_errata_833471
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_833471_wa
-
-func check_errata_833471
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_833471
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A57 Errata #859972.
- * This applies only to revision <= r1p3 of Cortex A57.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber:
- * --------------------------------------------------
- */
-func errata_a57_859972_wa
- mov x17, x30
- bl check_errata_859972
- cbz x0, 1f
- mrs x1, CORTEX_A57_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH
- msr CORTEX_A57_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a57_859972_wa
-
-func check_errata_859972
- mov x1, #0x13
- b cpu_rev_var_ls
-endfunc check_errata_859972
-
-func check_errata_cve_2017_5715
-#if WORKAROUND_CVE_2017_5715
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2017_5715
+workaround_reset_end cortex_a57, ERRATUM(828024)
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
+check_erratum_ls cortex_a57, ERRATUM(828024), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata workaround for Cortex A57 Errata #1319537.
- * This applies to all revisions of Cortex A57.
- * --------------------------------------------------
- */
-func check_errata_1319537
-#if ERRATA_A57_1319537
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_1319537
+workaround_reset_start cortex_a57, ERRATUM(829520), ERRATA_A57_829520
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
+workaround_reset_end cortex_a57, ERRATUM(829520)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A57.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a57_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_ls cortex_a57, ERRATUM(829520), CPU_REV(1, 2)
-#if ERRATA_A57_806969
- mov x0, x18
- bl errata_a57_806969_wa
-#endif
+workaround_reset_start cortex_a57, ERRATUM(833471), ERRATA_A57_833471
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
+workaround_reset_end cortex_a57, ERRATUM(833471)
-#if ERRATA_A57_813420
- mov x0, x18
- bl errata_a57_813420_wa
-#endif
+check_erratum_ls cortex_a57, ERRATUM(833471), CPU_REV(1, 2)
-#if ERRATA_A57_814670
- mov x0, x18
- bl errata_a57_814670_wa
-#endif
+workaround_reset_start cortex_a57, ERRATUM(859972), ERRATA_A57_859972
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH
+workaround_reset_end cortex_a57, ERRATUM(859972)
-#if A57_DISABLE_NON_TEMPORAL_HINT
- mov x0, x18
- bl a57_disable_ldnp_overread
-#endif
+check_erratum_ls cortex_a57, ERRATUM(859972), CPU_REV(1, 3)
-#if ERRATA_A57_826974
- mov x0, x18
- bl errata_a57_826974_wa
-#endif
+check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537, NO_APPLY_AT_RESET
-#if ERRATA_A57_826977
- mov x0, x18
- bl errata_a57_826977_wa
+workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_mmu_vbar
#endif
+workaround_reset_end cortex_a57, CVE(2017, 5715)
-#if ERRATA_A57_828024
- mov x0, x18
- bl errata_a57_828024_wa
-#endif
+check_erratum_chosen cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
-#if ERRATA_A57_829520
- mov x0, x18
- bl errata_a57_829520_wa
-#endif
-
-#if ERRATA_A57_833471
- mov x0, x18
- bl errata_a57_833471_wa
-#endif
-
-#if ERRATA_A57_859972
- mov x0, x18
- bl errata_a57_859972_wa
-#endif
-
-#if IMAGE_BL31 && ( WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 )
- /* ---------------------------------------------------------------
- * Override vector table & enable existing workaround if either of
- * the build flags are enabled
- * ---------------------------------------------------------------
- */
- adr x0, wa_cve_2017_5715_mmu_vbar
- msr vbar_el3, x0
- /* isb will be performed before returning from this function */
-#endif
-
-#if WORKAROUND_CVE_2018_3639
- mrs x0, CORTEX_A57_CPUACTLR_EL1
- orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
- msr CORTEX_A57_CPUACTLR_EL1, x0
+workaround_reset_start cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
isb
dsb sy
-#endif
+workaround_reset_end cortex_a57, CVE(2018, 3639)
-#if A57_ENABLE_NONCACHEABLE_LOAD_FWD
- /* ---------------------------------------------
- * Enable higher performance non-cacheable load
- * forwarding
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A57_CPUACTLR_EL1
- orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD
- msr CORTEX_A57_CPUACTLR_EL1, x0
+check_erratum_chosen cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_mmu_vbar
#endif
+workaround_reset_end cortex_a57, CVE(2022, 23960)
- /* ---------------------------------------------
- * Enable the SMP bit.
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A57_ECTLR_EL1
- orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
- msr CORTEX_A57_ECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a57_reset_func
+check_erratum_chosen cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
+cpu_reset_func_start cortex_a57
+#if A57_ENABLE_NONCACHEABLE_LOAD_FWD
+ /* Enable higher performance non-cacheable load forwarding */
+ sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD
#endif
- ret
-endfunc check_errata_cve_2022_23960
+ /* Enable the SMP bit. */
+ sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
+cpu_reset_func_end cortex_a57
func check_smccc_arch_workaround_3
mov x0, #ERRATA_APPLIES
@@ -619,42 +284,7 @@
b cortex_a57_disable_ext_debug
endfunc cortex_a57_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A57. Must follow AAPCS.
- */
-func cortex_a57_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A57_806969, cortex_a57, 806969
- report_errata ERRATA_A57_813419, cortex_a57, 813419
- report_errata ERRATA_A57_813420, cortex_a57, 813420
- report_errata ERRATA_A57_814670, cortex_a57, 814670
- report_errata ERRATA_A57_817169, cortex_a57, 817169
- report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
- disable_ldnp_overread
- report_errata ERRATA_A57_826974, cortex_a57, 826974
- report_errata ERRATA_A57_826977, cortex_a57, 826977
- report_errata ERRATA_A57_828024, cortex_a57, 828024
- report_errata ERRATA_A57_829520, cortex_a57, 829520
- report_errata ERRATA_A57_833471, cortex_a57, 833471
- report_errata ERRATA_A57_859972, cortex_a57, 859972
- report_errata ERRATA_A57_1319537, cortex_a57, 1319537
- report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a57_errata_report
-#endif
+errata_report_shim cortex_a57
/* ---------------------------------------------
* This function provides cortex_a57 specific
@@ -679,7 +309,7 @@
declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
cortex_a57_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_cortex_a57_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a57_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
index ac6583e..85d1894 100644
--- a/lib/cpus/aarch64/cortex_a65ae.S
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,49 +22,26 @@
#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-/* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A65.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a65ae_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+ /*
+ * ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a65ae
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184
+.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc cortex_a65ae_reset_func
+cpu_reset_func_start cortex_a65ae
+cpu_reset_func_end cortex_a65ae
func cortex_a65ae_cpu_pwr_dwn
- mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a65ae_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A65AE. Must follow AAPCS.
- */
-func cortex_a65ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a65ae_errata_report
-#endif
+errata_report_shim cortex_a65ae
.section .rodata.cortex_a65ae_regs, "aS"
cortex_a65ae_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index cebd6f0..eab5ada 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,22 +26,7 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 1987031.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still
- * open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a710_1987031_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1987031
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
+workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
ldr x0,=0xF3A08002
@@ -58,33 +43,53 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000001003f3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a710_1987031_wa
+workaround_reset_end cortex_a710, ERRATUM(1987031)
-func check_errata_1987031
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1987031
+check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2081180.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a710_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
+workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+ /* Stash ERRSELR_EL1 in x2 */
+ mrs x2, ERRSELR_EL1
+
+ /* Select error record 0 and clear ED bit */
+ msr ERRSELR_EL1, xzr
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
- /* Apply instruction patching sequence */
+ /* Select error record 1 and clear ED bit */
+ mov x0, #1
+ msr ERRSELR_EL1, x0
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
+
+ /* Restore ERRSELR_EL1 from x2 */
+ msr ERRSELR_EL1, x2
+workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB
+
+check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096
+ sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_a710, ERRATUM(2017096)
+
+check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002
+ sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46
+workaround_reset_end cortex_a710, ERRATUM(2055002)
+
+check_erratum_ls cortex_a710, ERRATUM(2055002), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
+ sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+ CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_a710, ERRATUM(2058056)
+
+check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
ldr x0,=0xF3A08002
@@ -101,238 +106,30 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003F3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a710_2081180_wa
-
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2055002.
- * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2055002_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2055002
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
- msr CORTEX_A710_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2055002_wa
-
-func check_errata_2055002
- /* Applies to r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2055002
-
-/* -------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2017096.
- * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------------
- */
-func errata_a710_2017096_wa
- /* Compare x0 against revision r0p0 to r2p0 */
- mov x17, x30
- bl check_errata_2017096
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUECTLR_EL1
- orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
- msr CORTEX_A710_CPUECTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_a710_2017096_wa
-
-func check_errata_2017096
- /* Applies to r0p0, r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2017096
-
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2083908.
- * This applies to revision r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2083908_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2083908
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
- msr CORTEX_A710_CPUACTLR5_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2083908_wa
-
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #CPU_REV(2, 0)
- mov x2, #CPU_REV(2, 0)
- b cpu_rev_var_range
-endfunc check_errata_2083908
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2058056.
- * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still
- * open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2058056_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2058056
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUECTLR2_EL1
- mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
- msr CORTEX_A710_CPUECTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2058056_wa
+workaround_reset_end cortex_a710, ERRATUM(2081180)
-func check_errata_2058056
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2267065.
- * This applies to revisions r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a710_2267065_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2267065
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
- msr CORTEX_A710_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2267065_wa
+workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908
+ sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
+workaround_reset_end cortex_a710, ERRATUM(2083908)
-func check_errata_2267065
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2267065
+check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2136059.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2136059_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2136059
- cbz x0, 1f
+workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059
+ sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
+workaround_reset_end cortex_a710, ERRATUM(2136059)
- /* Apply the workaround */
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
- msr CORTEX_A710_CPUACTLR5_EL1, x1
+check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_a710_2136059_wa
+workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715
+ sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_a710, ERRATUM(2147715)
-func check_errata_2136059
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2136059
+check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
-/* ----------------------------------------------------------------
- * Errata workaround for Cortex-A710 Erratum 2147715.
- * This applies to revision r2p0, and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ----------------------------------------------------------------
- */
-func errata_a710_2147715_wa
- mov x17, x30
- bl check_errata_2147715
- cbz x0, 1f
-
- /* Apply workaround; set CPUACTLR_EL1[22]
- * to 1, which will cause the CFP instruction
- * to invalidate all branch predictor resources
- * regardless of context.
- */
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
- msr CORTEX_A710_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2147715_wa
-
-func check_errata_2147715
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2147715
-
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2216384.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2216384_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2216384
- cbz x0, 1f
-
- /* Apply workaround: set CPUACTLR5_EL1[17]
- * to 1 and the following instruction
- * patching sequence.
- */
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
- msr CORTEX_A710_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384
+ sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
ldr x0,=0x5
msr CORTEX_A710_CPUPSELR_EL3, x0
@@ -342,338 +139,88 @@
msr CORTEX_A710_CPUPMR_EL3, x0
ldr x0,=0x80000000003FF
msr CORTEX_A710_CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_a710_2216384_wa
+workaround_reset_end cortex_a710, ERRATUM(2216384)
-func check_errata_2216384
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2282622_wa
- /* Compare x0 against revision r2p1 */
- mov x17, x30
- bl check_errata_2282622
- cbz x0, 1f
+workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065
+ sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_a710, ERRATUM(2267065)
- /* Apply the workaround */
- mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_A710_CPUACTLR2_EL1, x1
+check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_a710_2282622_wa
+workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622
+ sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_a710, ERRATUM(2282622)
-func check_errata_2282622
- /* Applies to r0p0, r1p0, r2p0 and r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2282622
+check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1)
-/* ------------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request.
- * This applies to revision <= r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ------------------------------------------------------------------------
- */
-func errata_a710_2291219_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2291219
- cbz x0, 1f
-
+workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
/* Set bit 36 in ACTLR2_EL1 */
- mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36
- msr CORTEX_A710_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a710_2291219_wa
+ sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB
-func check_errata_2291219
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2291219
+check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2008768.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * ---------------------------------------------------------------
+/*
+ * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as
+ * well. Create a symbollic link to existing errata workaround to get them
+ * registered under the Errata Framework.
*/
-func errata_a710_2008768_wa
- mov x17, x30
- bl check_errata_2008768
- cbz x0, 1f
-
- /* Stash ERRSELR_EL1 in x2 */
- mrs x2, ERRSELR_EL1
+.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
- /* Select error record 0 and clear ED bit */
- msr ERRSELR_EL1, xzr
- mrs x1, ERXCTLR_EL1
- bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
- msr ERXCTLR_EL1, x1
-
- /* Select error record 1 and clear ED bit */
- mov x0, #1
- msr ERRSELR_EL1, x0
- mrs x1, ERXCTLR_EL1
- bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
- msr ERXCTLR_EL1, x1
-
- /* Restore ERRSELR_EL1 from x2 */
- msr ERRSELR_EL1, x2
-
-1:
- ret x17
-endfunc errata_a710_2008768_wa
-
-func check_errata_2008768
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2008768
-
-/* -------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_a710_2371105_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2371105
- cbz x0, 1f
-
+workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105
/* Set bit 40 in CPUACTLR2_EL1 */
- mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40
- msr CORTEX_A710_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a710_2371105_wa
+ sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a710, ERRATUM(2371105)
-func check_errata_2371105
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0)
-/* ----------------------------------------------------
- * Errata Workaround for Cortex-A710 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a710_2768515_wa
- mov x17, x30
- bl check_errata_2768515
- cbz x0, 1f
-
+workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a710_2768515_wa
+workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB
-func check_errata_2768515
- /* Applies to all revisions <= r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2768515
+check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-A710 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_cortex_a710
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a710, CVE(2022, 23960)
+
+check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a710_core_pwr_dwn
-
-#if ERRATA_A710_2008768
- mov x4, x30
- bl cpu_get_rev_var
- bl errata_a710_2008768_wa
- mov x30, x4
-#endif
-
-#if ERRATA_A710_2291219
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a710_2291219_wa
- mov x30, x15
-#endif /* ERRATA_A710_2291219 */
+ apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+ apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A710_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A710_CPUPWRCTLR_EL1, x0
-#if ERRATA_A710_2768515
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a710_2768515_wa
- mov x30, x15
-#endif /* ERRATA_A710_2768515 */
+ sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV
isb
ret
endfunc cortex_a710_core_pwr_dwn
-#if REPORT_ERRATA
- /*
- * Errata printing function for Cortex-A710. Must follow AAPCS.
- */
-func cortex_a710_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A710_1987031, cortex_a710, 1987031
- report_errata ERRATA_A710_2081180, cortex_a710, 2081180
- report_errata ERRATA_A710_2055002, cortex_a710, 2055002
- report_errata ERRATA_A710_2017096, cortex_a710, 2017096
- report_errata ERRATA_A710_2083908, cortex_a710, 2083908
- report_errata ERRATA_A710_2058056, cortex_a710, 2058056
- report_errata ERRATA_A710_2267065, cortex_a710, 2267065
- report_errata ERRATA_A710_2136059, cortex_a710, 2136059
- report_errata ERRATA_A710_2282622, cortex_a710, 2282622
- report_errata ERRATA_A710_2008768, cortex_a710, 2008768
- report_errata ERRATA_A710_2147715, cortex_a710, 2147715
- report_errata ERRATA_A710_2216384, cortex_a710, 2216384
- report_errata ERRATA_A710_2291219, cortex_a710, 2291219
- report_errata ERRATA_A710_2371105, cortex_a710, 2371105
- report_errata ERRATA_A710_2768515, cortex_a710, 2768515
- report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960
- report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a710_errata_report
-#endif
+errata_report_shim cortex_a710
-func cortex_a710_reset_func
- mov x19, x30
-
+cpu_reset_func_start cortex_a710
/* Disable speculative loads */
msr SSBS, xzr
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A710_1987031
- mov x0, x18
- bl errata_a710_1987031_wa
-#endif
-
-#if ERRATA_A710_2081180
- mov x0, x18
- bl errata_a710_2081180_wa
-#endif
-
-#if ERRATA_A710_2055002
- mov x0, x18
- bl errata_a710_2055002_wa
-#endif
-
-#if ERRATA_A710_2017096
- mov x0, x18
- bl errata_a710_2017096_wa
-#endif
-
-#if ERRATA_A710_2083908
- mov x0, x18
- bl errata_a710_2083908_wa
-#endif
-
-#if ERRATA_A710_2058056
- mov x0, x18
- bl errata_a710_2058056_wa
-#endif
-
-#if ERRATA_A710_2267065
- mov x0, x18
- bl errata_a710_2267065_wa
-#endif
-
-#if ERRATA_A710_2136059
- mov x0, x18
- bl errata_a710_2136059_wa
-#endif
-
-#if ERRATA_A710_2147715
- mov x0, x18
- bl errata_a710_2147715_wa
-#endif
-
-#if ERRATA_A710_2216384
- mov x0, x18
- bl errata_a710_2216384_wa
-#endif /* ERRATA_A710_2216384 */
-
-#if ERRATA_A710_2282622
- mov x0, x18
- bl errata_a710_2282622_wa
-#endif
-
-#if ERRATA_A710_2371105
- mov x0, x18
- bl errata_a710_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A710 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a710
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a710_reset_func
+cpu_reset_func_end cortex_a710
/* ---------------------------------------------
* This function provides Cortex-A710 specific
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index 12d969f..dd4c307 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_a715_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A715 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a715
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a715
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a715, CVE(2022, 23960)
- isb
- ret
-endfunc cortex_a715_reset_func
+check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_a715
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_a715
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -68,26 +59,7 @@
ret
endfunc cortex_a715_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A715. Must follow AAPCS.
- */
-func cortex_a715_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a715, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a715_errata_report
-#endif
+errata_report_shim cortex_a715
/* ---------------------------------------------
* This function provides Cortex-A715 specific
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index de2d36e..997f261 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,9 +47,7 @@
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- mrs x0, CORTEX_A72_CPUACTLR_EL1
- orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
- msr CORTEX_A72_CPUACTLR_EL1, x0
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
isb
dsb ish
ret
@@ -60,9 +58,7 @@
* ---------------------------------------------
*/
func cortex_a72_disable_smp
- mrs x0, CORTEX_A72_ECTLR_EL1
- bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
- msr CORTEX_A72_ECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
ret
endfunc cortex_a72_disable_smp
@@ -78,139 +74,95 @@
ret
endfunc cortex_a72_disable_ext_debug
- /* --------------------------------------------------
- * Errata Workaround for Cortex A72 Errata #859971.
- * This applies only to revision <= r0p3 of Cortex A72.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber:
- * --------------------------------------------------
- */
-func errata_a72_859971_wa
- mov x17,x30
- bl check_errata_859971
- cbz x0, 1f
- mrs x1, CORTEX_A72_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
- msr CORTEX_A72_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a72_859971_wa
-
-func check_errata_859971
- mov x1, #0x03
- b cpu_rev_var_ls
-endfunc check_errata_859971
-
-func check_errata_cve_2017_5715
+func check_smccc_arch_workaround_3
cpu_check_csv2 x0, 1f
-#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
-endfunc check_errata_cve_2017_5715
+endfunc check_smccc_arch_workaround_3
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
+workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
+workaround_reset_end cortex_a72, ERRATUM(859971)
- /* --------------------------------------------------
- * Errata workaround for Cortex A72 Errata #1319367.
- * This applies to all revisions of Cortex A72.
- * --------------------------------------------------
- */
-func check_errata_1319367
-#if ERRATA_A72_1319367
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
+check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3)
+
+/* Due to the nature of the errata it is applied unconditionally when chosen */
+check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
+/* erratum workaround is interleaved with generic code */
+add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET
+
+workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_mmu_vbar
#endif
- ret
-endfunc check_errata_1319367
+workaround_reset_end cortex_a72, CVE(2017, 5715)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
+check_erratum_custom_start cortex_a72, CVE(2017, 5715)
+ cpu_check_csv2 x0, 1f
+#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
-endfunc check_errata_cve_2022_23960
-
-func check_smccc_arch_workaround_3
- cpu_check_csv2 x0, 1f
- mov x0, #ERRATA_APPLIES
- ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
-endfunc check_smccc_arch_workaround_3
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A72.
- * -------------------------------------------------
- */
-func cortex_a72_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A72_859971
- mov x0, x18
- bl errata_a72_859971_wa
-#endif
+check_erratum_custom_end cortex_a72, CVE(2017, 5715)
-#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
- cpu_check_csv2 x0, 1f
- adr x0, wa_cve_2017_5715_mmu_vbar
- msr vbar_el3, x0
- /* isb will be performed before returning from this function */
+workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
+ isb
+ dsb sy
+workaround_reset_end cortex_a72, CVE(2018, 3639)
+check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
- /* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */
- b 2f
-1:
-#if WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /* Skip installing vector table again if already done for CVE(2017, 5715) */
/*
* The Cortex-A72 generic vectors are overridden to apply the
- * mitigation on exception entry from lower ELs for revisions >= r1p0
+ * mitigation on exception entry from lower ELs for revisions >= r1p0
* which has CSV2 implemented.
*/
adr x0, wa_cve_vbar_cortex_a72
+ mrs x1, vbar_el3
+ cmp x0, x1
+ b.eq 1f
msr vbar_el3, x0
+1:
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a72, CVE(2022, 23960)
- /* isb will be performed before returning from this function */
+check_erratum_custom_start cortex_a72, CVE(2022, 23960)
+#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
+ cpu_check_csv2 x0, 1f
+ mov x0, #ERRATA_APPLIES
+ ret
+1:
+#if WORKAROUND_CVE_2022_23960
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
#endif /* WORKAROUND_CVE_2022_23960 */
-2:
-#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
+ ret
+#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
+ mov x0, #ERRATA_MISSING
+ ret
+check_erratum_custom_end cortex_a72, CVE(2022, 23960)
-#if WORKAROUND_CVE_2018_3639
- mrs x0, CORTEX_A72_CPUACTLR_EL1
- orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
- msr CORTEX_A72_CPUACTLR_EL1, x0
- isb
- dsb sy
-#endif
+cpu_reset_func_start cortex_a72
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CORTEX_A72_ECTLR_EL1
- orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
- msr CORTEX_A72_ECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a72_reset_func
+ sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
+
+cpu_reset_func_end cortex_a72
/* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A72.
@@ -319,30 +271,7 @@
b cortex_a72_disable_ext_debug
endfunc cortex_a72_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A72. Must follow AAPCS.
- */
-func cortex_a72_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A72_859971, cortex_a72, 859971
- report_errata ERRATA_A72_1319367, cortex_a72, 1319367
- report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a72_errata_report
-#endif
+errata_report_shim cortex_a72
/* ---------------------------------------------
* This function provides cortex_a72 specific
@@ -367,7 +296,7 @@
declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
cortex_a72_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_cortex_a72_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a72_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index 529ab50..4b28fdb 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_a720_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex A720 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a720
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a720
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a720, CVE(2022, 23960)
- isb
- ret
-endfunc cortex_a720_reset_func
+check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_a720
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_a720
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -61,33 +52,13 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A720_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A720_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
isb
ret
endfunc cortex_a720_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A720. Must follow AAPCS.
- */
-func cortex_a720_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a720, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a720_errata_report
-#endif
+errata_report_shim cortex_a720
/* ---------------------------------------------
* This function provides Cortex A720-specific
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index edcd1f5..3a6b922 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,9 +15,7 @@
* ---------------------------------------------
*/
func cortex_a73_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a73_disable_dcache
@@ -27,124 +25,97 @@
* ---------------------------------------------
*/
func cortex_a73_disable_smp
- mrs x0, CORTEX_A73_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
- msr CORTEX_A73_CPUECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
isb
dsb sy
ret
endfunc cortex_a73_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A73 Errata #852427.
- * This applies only to revision r0p0 of Cortex A73.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a73_852427_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_852427
- cbz x0, 1f
- mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER
- orr x1, x1, #(1 << 12)
- msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1
- isb
-1:
- ret x17
-endfunc errata_a73_852427_wa
+func check_smccc_arch_workaround_3
+ mov x0, #ERRATA_APPLIES
+ ret
+endfunc check_smccc_arch_workaround_3
-func check_errata_852427
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_852427
+workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
+ sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
+workaround_reset_end cortex_a73, ERRATUM(852427)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A73 Errata #855423.
- * This applies only to revision <= r0p1 of Cortex A73.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a73_855423_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_855423
- cbz x0, 1f
- mrs x1, CORTEX_A73_IMP_DEF_REG2
- orr x1, x1, #(1 << 7)
- msr CORTEX_A73_IMP_DEF_REG2, x1
- isb
-1:
- ret x17
-endfunc errata_a73_855423_wa
+check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0)
-func check_errata_855423
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_855423
+workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423
+ sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7)
+workaround_reset_end cortex_a73, ERRATUM(855423)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A73.
- * -------------------------------------------------
- */
+check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1)
-func cortex_a73_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_bpiall_vbar
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2017, 5715)
-#if ERRATA_A73_852427
- mov x0, x18
- bl errata_a73_852427_wa
+check_erratum_custom_start cortex_a73, CVE(2017, 5715)
+ cpu_check_csv2 x0, 1f
+#if WORKAROUND_CVE_2017_5715
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
#endif
+ ret
+1:
+ mov x0, #ERRATA_NOT_APPLIES
+ ret
+check_erratum_custom_end cortex_a73, CVE(2017, 5715)
-#if ERRATA_A73_855423
- mov x0, x18
- bl errata_a73_855423_wa
-#endif
+workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+ sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
+workaround_reset_end cortex_a73, CVE(2018, 3639)
-#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
- cpu_check_csv2 x0, 1f
- adr x0, wa_cve_2017_5715_bpiall_vbar
- msr vbar_el3, x0
- isb
+check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/* Skip installing vector table again for CVE_2022_23960 */
- b 2f
+ adr x0, wa_cve_2017_5715_bpiall_vbar
+ mrs x1, vbar_el3
+
+ cmp x0, x1
+ b.eq 1f
+ msr vbar_el3, x0
1:
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2022, 23960)
+
+check_erratum_custom_start cortex_a73, CVE(2022, 23960)
+#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
+ cpu_check_csv2 x0, 1f
+ mov x0, #ERRATA_APPLIES
+ ret
+ 1:
#if WORKAROUND_CVE_2022_23960
- adr x0, wa_cve_2017_5715_bpiall_vbar
- msr vbar_el3, x0
- isb
-#endif
-2:
-#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
+#endif /* WORKAROUND_CVE_2022_23960 */
+ ret
+#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
+ mov x0, #ERRATA_MISSING
+ ret
+check_erratum_custom_end cortex_a73, CVE(2022, 23960)
-#if WORKAROUND_CVE_2018_3639
- mrs x0, CORTEX_A73_IMP_DEF_REG1
- orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A73_IMP_DEF_REG1, x0
- isb
-#endif
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A73.
+ * -------------------------------------------------
+ */
+cpu_reset_func_start cortex_a73
/* ---------------------------------------------
* Enable the SMP bit.
* Clobbers : x0
* ---------------------------------------------
*/
- mrs x0, CORTEX_A73_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
- msr CORTEX_A73_CPUECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a73_reset_func
+ sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
+cpu_reset_func_end cortex_a73
func cortex_a73_core_pwr_dwn
mov x18, x30
@@ -207,74 +178,8 @@
b cortex_a73_disable_smp
endfunc cortex_a73_cluster_pwr_dwn
-func check_errata_cve_2017_5715
- cpu_check_csv2 x0, 1f
-#if WORKAROUND_CVE_2017_5715
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_errata_cve_2017_5715
-
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
- cpu_check_csv2 x0, 1f
- mov x0, #ERRATA_APPLIES
- ret
- 1:
-# if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-# else
- mov x0, #ERRATA_MISSING
-# endif /* WORKAROUND_CVE_2022_23960 */
- ret
-#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
- mov x0, #ERRATA_MISSING
- ret
-endfunc check_errata_cve_2022_23960
-
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A75. Must follow AAPCS.
- */
-func cortex_a73_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A73_852427, cortex_a73, 852427
- report_errata ERRATA_A73_855423, cortex_a73, 855423
- report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a73_errata_report
-#endif
+errata_report_shim cortex_a73
/* ---------------------------------------------
* This function provides cortex_a73 specific
@@ -298,7 +203,7 @@
declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_cortex_a73_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 0a7b9fb..c90be67 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index bd2c697..11190c8 100644
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 36507de..8b3d730 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -298,154 +298,50 @@
endfunc apply_cve_2018_3639_sync_wa
#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1073348.
- * This applies only to revision <= r1p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1073348_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1073348_wa
+workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
+workaround_reset_end cortex_a76, ERRATUM(1073348)
-func check_errata_1073348
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
+check_erratum_ls cortex_a76, ERRATUM(1073348), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1130799.
- * This applies only to revision <= r2p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1130799_wa
- /*
- * Compare x0 against revision r2p0
- */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR2_EL1
- orr x1, x1 ,#(1 << 59)
+workaround_reset_start cortex_a76, ERRATUM(1130799), ERRATA_A76_1130799
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_59
msr CORTEX_A76_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1130799_wa
+workaround_reset_end cortex_a76, ERRATUM(1130799)
-func check_errata_1130799
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
+check_erratum_ls cortex_a76, ERRATUM(1130799), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1220197.
- * This applies only to revision <= r2p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1220197_wa
-/*
- * Compare x0 against revision r2p0
- */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1220197_wa
+workaround_reset_start cortex_a76, ERRATUM(1220197), ERRATA_A76_1220197
+ sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
+workaround_reset_end cortex_a76, ERRATUM(1220197)
-func check_errata_1220197
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+check_erratum_ls cortex_a76, ERRATUM(1220197), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1257314.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1257314_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR3_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
- msr CORTEX_A76_CPUACTLR3_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1257314_wa
+workaround_reset_start cortex_a76, ERRATUM(1257314), ERRATA_A76_1257314
+ sysreg_bit_set CORTEX_A76_CPUACTLR3_EL1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
+workaround_reset_end cortex_a76, ERRATUM(1257314)
-func check_errata_1257314
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+check_erratum_ls cortex_a76, ERRATUM(1257314), CPU_REV(3, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1262888.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1262888_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1262888_wa
+workaround_reset_start cortex_a76, ERRATUM(1262606), ERRATA_A76_1262606
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1262606)
-func check_errata_1262888
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+check_erratum_ls cortex_a76, ERRATUM(1262606), CPU_REV(3, 0)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1286807.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * ---------------------------------------------------
- */
-func check_errata_1286807
+workaround_reset_start cortex_a76, ERRATUM(1262888), ERRATA_A76_1262888
+ sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_BIT_51
+workaround_reset_end cortex_a76, ERRATUM(1262888)
+
+check_erratum_ls cortex_a76, ERRATUM(1262888), CPU_REV(3, 0)
+
+workaround_reset_start cortex_a76, ERRATUM(1275112), ERRATA_A76_1275112
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1275112)
+
+check_erratum_ls cortex_a76, ERRATUM(1275112), CPU_REV(3, 0)
+
+check_erratum_custom_start cortex_a76, ERRATUM(1286807)
#if ERRATA_A76_1286807
mov x0, #ERRATA_APPLIES
ret
@@ -453,100 +349,21 @@
mov x1, #0x30
b cpu_rev_var_ls
#endif
-endfunc check_errata_1286807
-
- /* --------------------------------------------------
- * Errata workaround for Cortex A76 Errata #1791580.
- * This applies to revisions <= r4p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1791580_wa
- /* Compare x0 against revision r4p0 */
- mov x17, x30
- bl check_errata_1791580
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR2_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
- msr CORTEX_A76_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1791580_wa
-
-func check_errata_1791580
- /* Applies to everything <=r4p0. */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1791580
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1262606,
- * #1275112, and #1868343. #1262606 and #1275112
- * apply to revisions <= r3p0 and #1868343 applies to
- * revisions <= r4p0.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+check_erratum_custom_end cortex_a76, ERRATUM(1286807)
-func errata_a76_1262606_1275112_1868343_wa
- mov x17, x30
+workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a76, ERRATUM(1791580)
-/* Check for <= r3p0 cases and branch if check passes. */
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112
- bl check_errata_1262606
- cbnz x0, 1f
-#endif
-
-/* Check for <= r4p0 cases and branch if check fails. */
-#if ERRATA_A76_1868343
- bl check_errata_1868343
- cbz x0, 2f
-#endif
-1:
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A76_CPUACTLR_EL1_BIT_13
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-2:
- ret x17
-endfunc errata_a76_1262606_1275112_1868343_wa
+check_erratum_ls cortex_a76, ERRATUM(1791580), CPU_REV(4, 0)
-func check_errata_1262606
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start cortex_a76, ERRATUM(1868343), ERRATA_A76_1868343
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1868343)
-func check_errata_1275112
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+check_erratum_ls cortex_a76, ERRATUM(1868343), CPU_REV(4, 0)
-func check_errata_1868343
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
-
-/* --------------------------------------------------
- * Errata Workaround for A76 Erratum 1946160.
- * This applies to revisions r3p0 - r4p1 of A76.
- * It also exists in r0p0 - r2p0 but there is no fix
- * in those revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1946160_wa
- /* Compare x0 against revisions r3p0 - r4p1 */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start cortex_a76, ERRATUM(1946160), ERRATA_A76_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -573,68 +390,33 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
- isb
-1:
- ret x17
-endfunc errata_a76_1946160_wa
+workaround_reset_end cortex_a76, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to revisions r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
-
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A76 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a76_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
+check_erratum_range cortex_a76, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
+workaround_runtime_start cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a76_2743102_wa
+workaround_runtime_end cortex_a76, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
+check_erratum_ls cortex_a76, ERRATUM(2743102), CPU_REV(4, 1)
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
+check_erratum_chosen cortex_a76, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
func cortex_a76_disable_wa_cve_2018_3639
- mrs x0, CORTEX_A76_CPUACTLR2_EL1
- bic x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A76_CPUACTLR2_EL1, x0
+ sysreg_bit_clear CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
isb
ret
endfunc cortex_a76_disable_wa_cve_2018_3639
- /* --------------------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1165522.
- * This applies only to revisions <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * --------------------------------------------------------------
- */
-func check_errata_1165522
+/* --------------------------------------------------------------
+ * Errata Workaround for Cortex A76 Errata #1165522.
+ * This applies only to revisions <= r3p0 of Cortex A76.
+ * Due to the nature of the errata it is applied unconditionally
+ * when built in, report it as applicable in this case
+ * --------------------------------------------------------------
+ */
+check_erratum_custom_start cortex_a76, ERRATUM(1165522)
#if ERRATA_A76_1165522
mov x0, #ERRATA_APPLIES
ret
@@ -642,66 +424,32 @@
mov x1, #0x30
b cpu_rev_var_ls
#endif
-endfunc check_errata_1165522
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_custom_end cortex_a76, ERRATUM(1165522)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A76.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a76_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A76_1073348
- mov x0, x18
- bl errata_a76_1073348_wa
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960, NO_APPLY_AT_RESET
-#if ERRATA_A76_1130799
- mov x0, x18
- bl errata_a76_1130799_wa
-#endif
-
-#if ERRATA_A76_1220197
- mov x0, x18
- bl errata_a76_1220197_wa
-#endif
-
-#if ERRATA_A76_1257314
- mov x0, x18
- bl errata_a76_1257314_wa
-#endif
-
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112 || ERRATA_A76_1868343
- mov x0, x18
- bl errata_a76_1262606_1275112_1868343_wa
-#endif
-
-#if ERRATA_A76_1262888
- mov x0, x18
- bl errata_a76_1262888_wa
-#endif
+/* ERRATA_DSU_798953 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a76
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a76_798953, check_errata_dsu_798953
+.equ erratum_cortex_a76_798953_wa, errata_dsu_798953_wa
+add_erratum_entry cortex_a76, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
-#if ERRATA_A76_1791580
- mov x0, x18
- bl errata_a76_1791580_wa
-#endif
+/* ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a76
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a76_936184, check_errata_dsu_936184
+.equ erratum_cortex_a76_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a76, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
-#if ERRATA_A76_1946160
- mov x0, x18
- bl errata_a76_1946160_wa
-#endif
+cpu_reset_func_start cortex_a76
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
@@ -714,9 +462,7 @@
#endif
#if DYNAMIC_WORKAROUND_CVE_2018_3639
cbnz x0, 1f
- mrs x0, CORTEX_A76_CPUACTLR2_EL1
- orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A76_CPUACTLR2_EL1, x0
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
isb
#ifdef IMAGE_BL31
@@ -727,8 +473,7 @@
* If the below vector table is used, skip overriding it again for
* CVE_2022_23960 as both use the same vbar.
*/
- adr x0, cortex_a76_wa_cve_vbar
- msr vbar_el3, x0
+ override_vector_table cortex_a76_wa_cve_vbar
isb
b 2f
#endif /* IMAGE_BL31 */
@@ -743,22 +488,11 @@
* mitigation on exception entry from lower ELs. This will be bypassed
* if DYNAMIC_WORKAROUND_CVE_2018_3639 has overridden the vectors.
*/
- adr x0, cortex_a76_wa_cve_vbar
- msr vbar_el3, x0
+ override_vector_table cortex_a76_wa_cve_vbar
isb
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
2:
-
-#if ERRATA_DSU_798953
- bl errata_dsu_798953_wa
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
-
- ret x19
-endfunc cortex_a76_reset_func
+cpu_reset_func_end cortex_a76
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -769,55 +503,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_A76_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK
- msr CORTEX_A76_CPUPWRCTLR_EL1, x0
-#if ERRATA_A76_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a76_2743102_wa
- mov x30, x15
-#endif /* ERRATA_A76_2743102 */
+ sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
+
+ apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
+
isb
ret
endfunc cortex_a76_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A76. Must follow AAPCS.
- */
-func cortex_a76_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A76_1073348, cortex_a76, 1073348
- report_errata ERRATA_A76_1130799, cortex_a76, 1130799
- report_errata ERRATA_A76_1165522, cortex_a76, 1165522
- report_errata ERRATA_A76_1220197, cortex_a76, 1220197
- report_errata ERRATA_A76_1257314, cortex_a76, 1257314
- report_errata ERRATA_A76_1262606, cortex_a76, 1262606
- report_errata ERRATA_A76_1262888, cortex_a76, 1262888
- report_errata ERRATA_A76_1275112, cortex_a76, 1275112
- report_errata ERRATA_A76_1286807, cortex_a76, 1286807
- report_errata ERRATA_A76_1791580, cortex_a76, 1791580
- report_errata ERRATA_A76_1868343, cortex_a76, 1868343
- report_errata ERRATA_A76_1946160, cortex_a76, 1946160
- report_errata ERRATA_A76_2743102, cortex_a76, 2743102
- report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
- report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
- report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, cortex_a76, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a76_errata_report
-#endif
+errata_report_shim cortex_a76
/* ---------------------------------------------
* This function provides cortex_a76 specific
diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S
index 5c19548..08a6ef9 100644
--- a/lib/cpus/aarch64/cortex_a76ae.S
+++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,71 +25,34 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- /* --------------------------------------------
- * The CPU Ops reset function for Cortex-A76AE.
- * Shall clobber: x0-x19
- * --------------------------------------------
- */
-func cortex_a76ae_reset_func
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A76ae generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a76ae
- msr vbar_el3, x0
+ override_vector_table wa_cve_vbar_cortex_a76ae
isb
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a76ae, CVE(2022, 23960)
- ret
-endfunc cortex_a76ae_reset_func
+cpu_reset_func_start cortex_a76ae
+cpu_reset_func_end cortex_a76ae
+
+errata_report_shim cortex_a76ae
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a76ae_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
- msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a76ae_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A76AE. Must follow AAPCS.
- */
-func cortex_a76ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a76ae_errata_report
-#endif /* REPORT_ERRATA */
-
/* ---------------------------------------------
* This function provides cortex_a76ae specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 2882df7..86c2561 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,26 +26,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1508412.
- * This applies only to revision <= r1p0 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1508412_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1508412
- cbz x0, 3f
- /*
- * Compare x0 against revision r0p0
- */
- bl check_errata_1508412_0
+workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
+ /* move cpu revision in again and compare against r0p0 */
+ mov x0, x7
+ mov x1, #CPU_REV(0, 0)
+ bl cpu_rev_var_ls
cbz x0, 1f
+
ldr x0, =0x0
msr CORTEX_A77_CPUPSELR_EL3, x0
ldr x0, =0x00E8400000
@@ -75,64 +62,30 @@
2:
ldr x0, =0x04004003FF
msr CORTEX_A77_CPUPCR_EL3, x0
- isb
-3:
- ret x17
-endfunc errata_a77_1508412_wa
+workaround_reset_end cortex_a77, ERRATUM(1508412)
-func check_errata_1508412
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1508412
+check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
-func check_errata_1508412_0
- mov x1, #0x0
- b cpu_rev_var_ls
-endfunc check_errata_1508412_0
+workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
+ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a77, ERRATUM(1791578)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1925769.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1925769_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1925769
- cbz x0, 1f
+check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
- /* Set bit 8 in ECTLR_EL1 */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1925769_wa
+workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
+ /* Disable allocation of splintered pages in the L2 TLB */
+ sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53
+workaround_reset_end cortex_a77, ERRATUM(1800714)
-func check_errata_1925769
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1925769
+check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1946167.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1946167_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1946167
- cbz x0, 1f
+workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
+ sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a77, ERRATUM(1925769)
+
+check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
+workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
ldr x0,=0x4
msr CORTEX_A77_CPUPSELR_EL3,x0
ldr x0,=0x10E3900002
@@ -159,188 +112,42 @@
msr CORTEX_A77_CPUPMR_EL3,x0
ldr x0,=0x2001003FF
msr CORTEX_A77_CPUPCR_EL3,x0
+workaround_reset_end cortex_a77, ERRATUM(1946167)
- isb
-1:
- ret x17
-endfunc errata_a77_1946167_wa
+check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
-func check_errata_1946167
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1946167
+workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
+ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a77, ERRATUM(2356587)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1791578.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1791578_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1791578
- cbz x0, 1f
+check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
- /* Set bit 2 in ACTLR2_EL1 */
- mrs x1, CORTEX_A77_ACTLR2_EL1
- orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
- msr CORTEX_A77_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1791578_wa
-
-func check_errata_1791578
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1791578
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #2356587.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_2356587_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2356587
- cbz x0, 1f
-
- /* Set bit 0 in ACTLR2_EL1 */
- mrs x1, CORTEX_A77_ACTLR2_EL1
- orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0
- msr CORTEX_A77_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_2356587_wa
-
-func check_errata_2356587
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2356587
-
- /* -----------------------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #2743100
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------------------
- */
-func errata_a77_2743100_wa
- mov x17, x30
- bl check_errata_2743100
- cbz x0, 1f
-
+workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a77_2743100_wa
+workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
-func check_errata_2743100
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2743100
+check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1800714.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1800714_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1800714
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1800714_wa
-
-func check_errata_1800714
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1800714
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A77.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a77_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A77_1508412
- mov x0, x18
- bl errata_a77_1508412_wa
-#endif
-
-#if ERRATA_A77_1925769
- mov x0, x18
- bl errata_a77_1925769_wa
-#endif
-
-#if ERRATA_A77_1946167
- mov x0, x18
- bl errata_a77_1946167_wa
-#endif
-
-#if ERRATA_A77_1791578
- mov x0, x18
- bl errata_a77_1791578_wa
-#endif
-
-#if ERRATA_A77_2356587
- mov x0, x18
- bl errata_a77_2356587_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A77 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a77
msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a77, CVE(2022, 23960)
-#if ERRATA_A77_1800714
- mov x0, x18
- bl errata_a77_1800714_wa
-#endif
+check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- isb
- ret x19
-endfunc cortex_a77_reset_func
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
+ * -------------------------------------------------
+ */
+cpu_reset_func_start cortex_a77
+cpu_reset_func_end cortex_a77
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -351,48 +158,16 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A77_CPUPWRCTLR_EL1, x0
-#if ERRATA_A77_2743100
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a77_2743100_wa
- mov x30, x15
-#endif /* ERRATA_A77_2743100 */
- isb
- ret
-endfunc cortex_a77_core_pwr_dwn
+ sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
+ CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A77. Must follow AAPCS.
- */
-func cortex_a77_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A77_1508412, cortex_a77, 1508412
- report_errata ERRATA_A77_1791578, cortex_a77, 1791578
- report_errata ERRATA_A77_1800714, cortex_a77, 1800714
- report_errata ERRATA_A77_1925769, cortex_a77, 1925769
- report_errata ERRATA_A77_1946167, cortex_a77, 1946167
- report_errata ERRATA_A77_2356587, cortex_a77, 2356587
- report_errata ERRATA_A77_2743100, cortex_a77, 2743100
- report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
+ apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
- ldp x8, x30, [sp], #16
+ isb
ret
-endfunc cortex_a77_errata_report
-#endif
-
+endfunc cortex_a77_core_pwr_dwn
+errata_report_shim cortex_a77
/* ---------------------------------------------
* This function provides Cortex-A77 specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 69d7ab0..b5c24e1 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,77 +24,25 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of A78.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
- msr CORTEX_A78_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1688305_wa
+workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
+workaround_reset_end cortex_a78, ERRATUM(1688305)
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
+check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1941498.
- * This applies to revisions r0p0, r1p0, and r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1941498_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1941498
- cbz x0, 1f
+workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a78, ERRATUM(1821534)
- /* Set bit 8 in ECTLR_EL1 */
- mrs x1, CORTEX_A78_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
- msr CORTEX_A78_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1941498_wa
+check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0)
-func check_errata_1941498
- /* Check for revision <= r1p1, might need to be updated later. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1941498
+workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498
+ sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a78, ERRATUM(1941498)
-/* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1951500.
- * This applies to revisions r1p0 and r1p1 of A78.
- * The issue also exists in r0p0 but there is no fix
- * in that revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1951500_wa
- /* Compare x0 against revisions r1p0 - r1p1 */
- mov x17, x30
- bl check_errata_1951500
- cbz x0, 1f
+check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1)
+workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@@ -120,60 +68,11 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
-
- isb
-1:
- ret x17
-endfunc errata_a78_1951500_wa
-
-func check_errata_1951500
- /* Applies to revisions r1p0 and r1p1. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 1)
- b cpu_rev_var_range
-endfunc check_errata_1951500
-
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1821534.
- * This applies to revisions r0p0 and r1p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1821534_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1821534
- cbz x0, 1f
-
- /* Set bit 2 in ACTLR2_EL1 */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
- msr CORTEX_A78_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1821534_wa
+workaround_reset_end cortex_a78, ERRATUM(1951500)
-func check_errata_1821534
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1821534
+check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 1952683.
- * This applies to revision r0p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1952683_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1952683
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683
ldr x0,=0x5
msr S3_6_c15_c8_0,x0
ldr x0,=0xEEE10A10
@@ -194,61 +93,21 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000080023ff
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a78_1952683_wa
+workaround_reset_end cortex_a78, ERRATUM(1952683)
-func check_errata_1952683
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1952683
+check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2132060.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2132060_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2132060
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
/* Apply the workaround. */
mrs x1, CORTEX_A78_CPUECTLR_EL1
mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
msr CORTEX_A78_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2132060_wa
+workaround_reset_end cortex_a78, ERRATUM(2132060)
-func check_errata_2132060
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2132060
+check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
-/* --------------------------------------------------------------------
- * Errata Workaround for A78 Erratum 2242635.
- * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
- * processor and is still open.
- * The issue also exists in r0p0 but there is no fix in that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------------------------
- */
-func errata_a78_2242635_wa
- /* Compare x0 against revisions r1p0 - r1p2 */
- mov x17, x30
- bl check_errata_2242635
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@@ -257,242 +116,64 @@
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end cortex_a78, ERRATUM(2242635)
- isb
-1:
- ret x17
-endfunc errata_a78_2242635_wa
+check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2)
-func check_errata_2242635
- /* Applies to revisions r1p0 through r1p2. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 2)
- b cpu_rev_var_range
-endfunc check_errata_2242635
+workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_a78, ERRATUM(2376745)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2376745.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2376745_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2376745
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_A78_ACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2376745_wa
+check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2)
-func check_errata_2376745
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2376745
+workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40)
+workaround_reset_end cortex_a78, ERRATUM(2395406)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2395406.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2395406_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2395406
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #BIT(40)
- msr CORTEX_A78_ACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2395406_wa
+check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2)
-func check_errata_2395406
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2395406
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2742426.
- * This applies to revisions r0p0, r1p0, r1p1 and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_a78_2742426_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2742426
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426
/* Apply the workaround */
mrs x1, CORTEX_A78_ACTLR5_EL1
bic x1, x1, #BIT(56)
orr x1, x1, #BIT(55)
msr CORTEX_A78_ACTLR5_EL1, x1
+workaround_reset_end cortex_a78, ERRATUM(2742426)
-1:
- ret x17
-endfunc errata_a78_2742426_wa
+check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2)
-func check_errata_2742426
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2742426
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex-A78 Errata 2772019
- * This applies to revisions <= r1p2 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a78_2772019_wa
- mov x17, x30
- bl check_errata_2772019
- cbz x0, 1f
-
-
+workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a78_2772019_wa
-
-func check_errata_2772019
- /* Applies to all revisions <= r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2772019
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2779479.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_a78_2779479_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779479
- cbz x0, 1f
+workaround_runtime_end cortex_a78, ERRATUM(2772019)
- /* Apply the workaround */
- mrs x1, CORTEX_A78_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr CORTEX_A78_ACTLR3_EL1, x1
-
-1:
- ret x17
-endfunc errata_a78_2779479_wa
+check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2)
-func check_errata_2779479
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2779479
+workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479
+ sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_a78, ERRATUM(2779479)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78
- * -------------------------------------------------
+workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func cortex_a78_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A78_1688305
- mov x0, x18
- bl errata_a78_1688305_wa
-#endif
-
-#if ERRATA_A78_1941498
- mov x0, x18
- bl errata_a78_1941498_wa
-#endif
-
-#if ERRATA_A78_1951500
- mov x0, x18
- bl errata_a78_1951500_wa
-#endif
-
-#if ERRATA_A78_1821534
- mov x0, x18
- bl errata_a78_1821534_wa
-#endif
-
-#if ERRATA_A78_1952683
- mov x0, x18
- bl errata_a78_1952683_wa
-#endif
-
-#if ERRATA_A78_2132060
- mov x0, x18
- bl errata_a78_2132060_wa
-#endif
+ override_vector_table wa_cve_vbar_cortex_a78
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78, CVE(2022, 23960)
-#if ERRATA_A78_2242635
- mov x0, x18
- bl errata_a78_2242635_wa
-#endif
-
-#if ERRATA_A78_2376745
- mov x0, x18
- bl errata_a78_2376745_wa
-#endif
+check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A78_2395406
- mov x0, x18
- bl errata_a78_2395406_wa
-#endif
-
-#if ERRATA_A78_2742426
- mov x0, x18
- bl errata_a78_2742426_wa
-#endif
-
-#if ERRATA_A78_2779479
- mov x0, x18
- bl errata_a78_2779479_wa
-#endif
-
+cpu_reset_func_start cortex_a78
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el3, x0
+ sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el2, x0
+ sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@@ -502,74 +183,22 @@
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A78 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a78
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a78_reset_func
+cpu_reset_func_end cortex_a78
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a78_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78_CPUPWRCTLR_EL1, x0
-#if ERRATA_A78_2772019
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a78_2772019_wa
- mov x30, x15
-#endif /* ERRATA_A78_2772019 */
+ sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+
+ apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
+
isb
ret
endfunc cortex_a78_core_pwr_dwn
- /*
- * Errata printing function for cortex_a78. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a78_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78_1688305, cortex_a78, 1688305
- report_errata ERRATA_A78_1941498, cortex_a78, 1941498
- report_errata ERRATA_A78_1951500, cortex_a78, 1951500
- report_errata ERRATA_A78_1821534, cortex_a78, 1821534
- report_errata ERRATA_A78_1952683, cortex_a78, 1952683
- report_errata ERRATA_A78_2132060, cortex_a78, 2132060
- report_errata ERRATA_A78_2242635, cortex_a78, 2242635
- report_errata ERRATA_A78_2376745, cortex_a78, 2376745
- report_errata ERRATA_A78_2395406, cortex_a78, 2395406
- report_errata ERRATA_A78_2742426, cortex_a78, 2742426
- report_errata ERRATA_A78_2772019, cortex_a78, 2772019
- report_errata ERRATA_A78_2779479, cortex_a78, 2779479
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78_errata_report
-#endif
+errata_report_shim cortex_a78
/* ---------------------------------------------
* This function provides cortex_a78 specific
diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
index d56f835..9f729c1 100644
--- a/lib/cpus/aarch64/cortex_a78_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,50 +22,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 1941500.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_1941500_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_1941500
- cbz x0, 1f
-
- /* Set bit 8 in ECTLR_EL1 */
- mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
- msr CORTEX_A78_AE_CPUECTLR_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_1941500_wa
+workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
+ sysreg_bit_clear CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
-func check_errata_1941500
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_1941500
+check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 1951502.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_1951502_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_1951502
- cbz x0, 1f
-
+workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@@ -91,33 +54,11 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
+workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
- isb
-1:
- ret x17
-endfunc errata_a78_ae_1951502_wa
+check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1)
-func check_errata_1951502
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_1951502
-
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 2376748.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_2376748_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2376748
- cbz x0, 1f
-
+workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
/* -------------------------------------------------------
* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
* behave like PLD/PRFM LD and not cause invalidations to
@@ -126,104 +67,42 @@
* that share data.
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A78_AE_ACTLR2_EL1
- orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
- msr CORTEX_A78_AE_ACTLR2_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_2376748_wa
-
-func check_errata_2376748
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_2376748
+ sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 2395408.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_2395408_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2395408
- cbz x0, 1f
+check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 1)
+workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
/* --------------------------------------------------------
* Disable folding of demand requests into older prefetches
* with L2 miss requests outstanding by setting the
* CPUACTLR2_EL1[40] to 1.
* --------------------------------------------------------
*/
- mrs x0, CORTEX_A78_AE_ACTLR2_EL1
- orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
- msr CORTEX_A78_AE_ACTLR2_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_2395408_wa
-
-func check_errata_2395408
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_2395408
+ sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78-AE
- * -------------------------------------------------
+workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-A78AE generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func cortex_a78_ae_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+ override_vector_table wa_cve_vbar_cortex_a78_ae
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
-#if ERRATA_A78_AE_1941500
- mov x0, x18
- bl errata_a78_ae_1941500_wa
-#endif
+check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A78_AE_1951502
- mov x0, x18
- bl errata_a78_ae_1951502_wa
-#endif
-
-#if ERRATA_A78_AE_2376748
- mov x0, x18
- bl errata_a78_ae_2376748_wa
-#endif
-
-#if ERRATA_A78_AE_2395408
- mov x0, x18
- bl errata_a78_ae_2395408_wa
-#endif
-
+cpu_reset_func_start cortex_a78_ae
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el3, x0
+ sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el2, x0
+ sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@@ -233,19 +112,7 @@
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A78AE generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a78_ae
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a78_ae_reset_func
+cpu_reset_func_end cortex_a78_ae
/* -------------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -256,37 +123,12 @@
* Enable CPU power down bit in power control register
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
ret
endfunc cortex_a78_ae_core_pwr_dwn
- /*
- * Errata printing function for cortex_a78_ae. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a78_ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
- report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
- report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
- report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78_ae_errata_report
-#endif
+errata_report_shim cortex_a78_ae
/* -------------------------------------------------------
* This function provides cortex_a78_ae specific
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index fddd24f..d19c693 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -17,174 +17,37 @@
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 1827430.
- * This applies to revision r0p0 of the Cortex A78C
- * processor and is fixed in r0p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_1827430_wa
- mov x17, x30
- bl check_errata_1827430
- cbz x0, 1f
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
+#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
/* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A78C_CPUECTLR_EL1
- orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
- msr CORTEX_A78C_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_1827430_wa
+ sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
+workaround_reset_end cortex_a78c, ERRATUM(1827430)
-func check_errata_1827430
- /* Applies to revision r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1827430
+check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 1827440.
- * This applies to revision r0p0 of the Cortex A78C
- * processor and is fixed in r0p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_1827440_wa
- mov x17, x30
- bl check_errata_1827440
- cbz x0, 1f
-
+workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440
/* Force Atomic Store to WB memory be done in L1 data cache */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #BIT(2)
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_1827440_wa
-
-func check_errata_1827440
- /* Applies to revision r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1827440
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2)
+workaround_reset_end cortex_a78c, ERRATUM(1827440)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Erratum 2376749.
- * This applies to revision r0p1 and r0p2 of the A78C
- * and is currently open. It is a Cat B erratum.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x4, x17
- * --------------------------------------------------
- */
-func errata_a78c_2376749_wa
- /* Check revision */
- mov x17, x30
- bl check_errata_2376749
- cbz x0, 1f
- /* Set CPUACTLR2_EL1[0] to 1. */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_2376749_wa
+check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
-func check_errata_2376749
- /* Applies to r0p1 and r0p2*/
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2376749
-
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Erratum 2395411.
- * This applies to revision r0p1 and r0p2 of the A78C
- * and is currently open. It is a Cat B erratum.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x4, x17
- * --------------------------------------------------
- */
-func errata_a78c_2395411_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2395411
- cbz x0, 1f
-
- /* Set CPUACTRL2_EL1[40] to 1. */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_2395411_wa
-
-func check_errata_2395411
- /* Applies to r0p1 and r0p2 */
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2395411
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
-#endif /* WORKAROUND_CVE_2022_23960 */
-
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 2132064.
- * This applies to revisions r0p1 and r0p2 of A78C
- * and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_2132064_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2132064
- cbz x0, 1f
-
+workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
/* --------------------------------------------------------
* Place the data prefetcher in the most conservative mode
* to reduce prefetches by writing the following bits to
* the value indicated: ecltr[7:6], PF_MODE = 2'b11
* --------------------------------------------------------
*/
- mrs x0, CORTEX_A78C_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
- orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
- msr CORTEX_A78C_CPUECTLR_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78c_2132064_wa
-
-func check_errata_2132064
- /* Applies to revisions r0p1 and r0p2. */
- mov x1, #CPU_REV(0, 1)
- mov x2, #CPU_REV(0, 2)
- b cpu_rev_var_range
-endfunc check_errata_2132064
+ sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
+workaround_reset_end cortex_a78c, ERRATUM(2132064)
-/* ----------------------------------------------------------
- * Errata Workaround for A78C Erratum 2242638.
- * This applies to revisions r0p1 and r0p2 of the Cortex A78C
- * processor and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------------
- */
-func errata_a78c_2242638_wa
- /* Compare x0 against revisions r0p1 - r0p2 */
- mov x17, x30
- bl check_errata_2242638
- cbz x0, 1f
+check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
+workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
ldr x0, =0x5
msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
ldr x0, =0x10F600E000
@@ -193,139 +56,51 @@
msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
-
- isb
-1:
- ret x17
-endfunc errata_a78c_2242638_wa
-
-func check_errata_2242638
- /* Applies to revisions r0p1-r0p2. */
- mov x1, #CPU_REV(0, 1)
- mov x2, #CPU_REV(0, 2)
- b cpu_rev_var_range
-endfunc check_errata_2242638
-
-/* ----------------------------------------------------------------
- * Errata Workaround for A78C Erratum 2772121.
- * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
- * processor and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------------------
- */
-func errata_a78c_2772121_wa
- mov x17, x30
- bl check_errata_2772121
- cbz x0, 1f
-
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_a78c_2772121_wa
-
-func check_errata_2772121
- /* Applies to all revisions <= r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2772121
+workaround_reset_end cortex_a78c, ERRATUM(2242638)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Errata 2779484.
- * This applies to revisions r0p1 and r0p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78c_2779484_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779484
- cbz x0, 1f
+check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2)
- /* Apply the workaround */
- mrs x1, CORTEX_A78C_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr CORTEX_A78C_ACTLR3_EL1, x1
+workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a78c, ERRATUM(2376749)
-1:
- ret x17
-endfunc errata_a78c_2779484_wa
+check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2)
-func check_errata_2779484
- /* Applies to r0p1 and r0p2*/
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2779484
+workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a78c, ERRATUM(2395411)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78C
- * -------------------------------------------------
- */
-func cortex_a78c_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A78C_1827430
- mov x0, x18
- bl errata_a78c_1827430_wa
-#endif
-
-#if ERRATA_A78C_1827440
- mov x0, x18
- bl errata_a78c_1827440_wa
-#endif
-
-#if ERRATA_A78C_2132064
- mov x0, x18
- bl errata_a78c_2132064_wa
-#endif
+workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end cortex_a78c, ERRATUM(2772121)
-#if ERRATA_A78C_2242638
- mov x0, x18
- bl errata_a78c_2242638_wa
-#endif
+check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2)
-#if ERRATA_A78C_2376749
- mov x0, x18
- bl errata_a78c_2376749_wa
-#endif
+workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484
+ sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_a78c, ERRATUM(2779484)
-#if ERRATA_A78C_2395411
- mov x0, x18
- bl errata_a78c_2395411_wa
-#endif
+check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2)
-#if ERRATA_A78C_2779484
- mov x0, x18
- bl errata_a78c_2779484_wa
-#endif
+check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A78c generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a78c
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a78c
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78c, CVE(2022, 23960)
- isb
- ret x19
-endfunc cortex_a78c_reset_func
+cpu_reset_func_start cortex_a78c
+cpu_reset_func_end cortex_a78c
+
+errata_report_shim cortex_a78c
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -336,48 +111,14 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
-#if ERRATA_A78C_2772121
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a78c_2772121_wa
- mov x30, x15
-#endif /* ERRATA_A78C_2772121 */
+ sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+
+ apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+
isb
ret
endfunc cortex_a78c_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A78C. Must follow AAPCS.
- */
-func cortex_a78c_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430
- report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440
- report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
- report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
- report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
- report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
- report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
- report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78c_errata_report
-#endif
-
/* ---------------------------------------------
* This function provides cortex_a78c specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_blackhawk.S b/lib/cpus/aarch64/cortex_blackhawk.S
index 8dac4e9..b7b7a2d 100644
--- a/lib/cpus/aarch64/cortex_blackhawk.S
+++ b/lib/cpus/aarch64/cortex_blackhawk.S
@@ -21,12 +21,10 @@
#error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-func cortex_blackhawk_reset_func
+cpu_reset_func_start cortex_blackhawk
/* Disable speculative loads */
msr SSBS, xzr
- isb
- ret
-endfunc cortex_blackhawk_reset_func
+cpu_reset_func_end cortex_blackhawk
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -37,21 +35,12 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_blackhawk_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Blackhawk. Must follow AAPCS.
- */
-func cortex_blackhawk_errata_report
- ret
-endfunc cortex_blackhawk_errata_report
-#endif
+errata_report_shim cortex_blackhawk
/* ---------------------------------------------
* This function provides Cortex Blackhawk specific
diff --git a/lib/cpus/aarch64/cortex_chaberton.S b/lib/cpus/aarch64/cortex_chaberton.S
index 2c47bd3..596fe4a 100644
--- a/lib/cpus/aarch64/cortex_chaberton.S
+++ b/lib/cpus/aarch64/cortex_chaberton.S
@@ -21,12 +21,10 @@
#error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-func cortex_chaberton_reset_func
+cpu_reset_func_start cortex_chaberton
/* Disable speculative loads */
msr SSBS, xzr
- isb
- ret
-endfunc cortex_chaberton_reset_func
+cpu_reset_func_end cortex_chaberton
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -37,21 +35,12 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_CHABERTON_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_CHABERTON_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_chaberton_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Chaberton. Must follow AAPCS.
- */
-func cortex_chaberton_errata_report
- ret
-endfunc cortex_chaberton_errata_report
-#endif
+errata_report_shim cortex_chaberton
/* ---------------------------------------------
* This function provides Cortex Chaberton specific
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
new file mode 100644
index 0000000..dc704f2
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_gelas.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Gelas must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_gelas
+ /* ----------------------------------------------------
+ * Disable speculative loads
+ * ----------------------------------------------------
+ */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_gelas
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_gelas_core_pwr_dwn
+#if ENABLE_SME_FOR_NS
+ /* ---------------------------------------------------
+ * Disable SME if enabled and supported
+ * ---------------------------------------------------
+ */
+ mrs x0, ID_AA64PFR1_EL1
+ ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
+ #ID_AA64PFR1_EL1_SME_WIDTH
+ cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ b.eq 1f
+ msr CORTEX_GELAS_SVCRSM, xzr
+ msr CORTEX_GELAS_SVCRZA, xzr
+1:
+#endif
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_GELAS_CPUPWRCTLR_EL1, \
+ CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc cortex_gelas_core_pwr_dwn
+
+errata_report_shim cortex_gelas
+
+ /* ---------------------------------------------
+ * This function provides Gelas specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_gelas_regs, "aS"
+cortex_gelas_regs: /* The ASCII list of register names to be reported */
+ .asciz "imp_cpuectlr_el1", ""
+
+func cortex_gelas_cpu_reg_dump
+ adr x6, cortex_gelas_regs
+ mrs x8, CORTEX_GELAS_IMP_CPUECTLR_EL1
+ ret
+endfunc cortex_gelas_cpu_reg_dump
+
+declare_cpu_ops cortex_gelas, CORTEX_GELAS_MIDR, \
+ cortex_gelas_reset_func, \
+ cortex_gelas_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S
index de65365..42634f1 100644
--- a/lib/cpus/aarch64/cortex_x1.S
+++ b/lib/cpus/aarch64/cortex_x1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Google LLC. All rights reserved.
+ * Copyright (c) 2022-2023, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,175 +23,50 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1821534.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1821534_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1821534
- cbz x0, 1f
- mrs x1, CORTEX_X1_ACTLR2_EL1
- orr x1, x1, #BIT(2)
- msr CORTEX_X1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x1_1821534_wa
-
-func check_errata_1821534
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1821534
-
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x0, CORTEX_X1_ACTLR2_EL1
- orr x0, x0, #BIT(1)
- msr CORTEX_X1_ACTLR2_EL1, x0
- isb
-
-1:
- ret x17
-endfunc errata_x1_1688305_wa
-
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
+workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305
+ sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1)
+workaround_reset_end cortex_x1, ERRATUM(1688305)
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1827429.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1827429_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1827429
- cbz x0, 1f
- mrs x0, CORTEX_X1_CPUECTLR_EL1
- orr x0, x0, #BIT(53)
- msr CORTEX_X1_CPUECTLR_EL1, x0
- isb
+check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0)
-1:
- ret x17
-endfunc errata_x1_1827429_wa
+workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534
+ sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2)
+workaround_reset_end cortex_x1, ERRATUM(1821534)
-func check_errata_1827429
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1827429
+check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429
+ sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53)
+workaround_reset_end cortex_x1, ERRATUM(1827429)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-X1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_x1_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0)
-#if ERRATA_X1_1821534
- mov x0, x18
- bl errata_x1_1821534_wa
-#endif
+check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_X1_1688305
- mov x0, x18
- bl errata_x1_1688305_wa
-#endif
-
-#if ERRATA_X1_1827429
- mov x0, x18
- bl errata_x1_1827429_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-X1 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_x1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_x1
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x1, CVE(2022, 23960)
- isb
- ret x19
-endfunc cortex_x1_reset_func
+cpu_reset_func_start cortex_x1
+cpu_reset_func_end cortex_x1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_x1_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
- msr CORTEX_X1_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_x1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex X1. Must follow AAPCS.
- */
-func cortex_x1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X1_1821534, cortex_x1, 1821534
- report_errata ERRATA_X1_1688305, cortex_x1, 1688305
- report_errata ERRATA_X1_1827429, cortex_x1, 1827429
- report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x1_errata_report
-#endif
+errata_report_shim cortex_x1
/* ---------------------------------------------
* This function provides Cortex X1 specific
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 497bd52..816a58f 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2002765.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2002765_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2002765
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
ldr x0, =0x6
msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0xF3A08002
@@ -48,119 +35,24 @@
msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x40000001003ff
msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
- isb
-
-1:
- ret x17
-endfunc errata_cortex_x2_2002765_wa
-
-func check_errata_2002765
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2002765
+workaround_reset_end cortex_x2, ERRATUM(2002765)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2058056.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2058056_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2058056
- cbz x0, 1f
-
- mrs x1, CORTEX_X2_CPUECTLR2_EL1
- mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
- msr CORTEX_X2_CPUECTLR2_EL1, x1
+check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_cortex_x2_2058056_wa
+workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096
+ sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_x2, ERRATUM(2017096)
-func check_errata_2058056
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2083908.
- * This applies to revision r2p0 and is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2083908_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2083908
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
+ sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+ CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_x2, ERRATUM(2058056)
- /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, #BIT(13)
- msr CORTEX_X2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_cortex_x2_2083908_wa
+check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0)
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2083908
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2017096.
- * This applies only to revisions r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2017096_wa
- /* Compare x0 against revision r0p0 to r2p0 */
- mov x17, x30
- bl check_errata_2017096
- cbz x0, 1f
- mrs x1, CORTEX_X2_CPUECTLR_EL1
- orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr CORTEX_X2_CPUECTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2017096_wa
-
-func check_errata_2017096
- /* Applies to r0p0, r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2017096
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2081180.
- * This applies to revision r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
/* Apply instruction patching sequence */
ldr x0, =0x3
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
@@ -178,34 +70,26 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x10002001003F3
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_x2_2081180_wa
+workaround_reset_end cortex_x2, ERRATUM(2081180)
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
+check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata 2216384.
- * This applies to revisions r0p0, r1p0, and r2p0
- * and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2216384_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216384
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908
+ /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13)
+workaround_reset_end cortex_x2, ERRATUM(2083908)
+
+check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
+
+workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715
+ /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_x2, ERRATUM(2147715)
+
+check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
- msr CORTEX_X2_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
/* Apply instruction patching sequence */
ldr x0, =0x5
@@ -216,138 +100,52 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-
-1:
- ret x17
-endfunc errata_x2_2216384_wa
+workaround_reset_end cortex_x2, ERRATUM(2216384)
-func check_errata_2216384
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* ---------------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2147715.
- * This applies only to revisions r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------
- */
-func errata_x2_2147715_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2147715
- cbz x0, 1f
-
- /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22
- msr CORTEX_X2_CPUACTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2147715_wa
-
-func check_errata_2147715
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2147715
-
- /* ---------------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_x2_2282622_wa
- /* Compare x0 against revision r2p1 */
- mov x17, x30
- bl check_errata_2282622
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622
/* Apply the workaround */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_X2_CPUACTLR2_EL1, x1
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_x2, ERRATUM(2282622)
-1:
- ret x17
-endfunc errata_x2_2282622_wa
+check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
-func check_errata_2282622
- /* Applies to r0p0, r1p0, r2p0 and r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2282622
+workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
+ /* Set bit 40 in CPUACTLR2_EL1 */
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_x2, ERRATUM(2371105)
- /* -------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_x2_2371105_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2371105
- cbz x0, 1f
+check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
- /* Set bit 40 in CPUACTLR2_EL1 */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40
- msr CORTEX_X2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x2_2371105_wa
+workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_reset_end cortex_x2, ERRATUM(2768515)
-func check_errata_2371105
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
+workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_x2_2768515_wa
- mov x17, x30
- bl check_errata_2768515
- cbz x0, 1f
+ override_vector_table wa_cve_vbar_cortex_x2
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x2, CVE(2022, 23960)
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_x2_2768515_wa
+check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-func check_errata_2768515
- /* Applies to all revisions <= r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2768515
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_x2
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -358,122 +156,24 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
#if ERRATA_X2_2768515
mov x15, x30
bl cpu_get_rev_var
- bl errata_x2_2768515_wa
+ bl erratum_cortex_x2_2768515_wa
mov x30, x15
#endif /* ERRATA_X2_2768515 */
isb
ret
endfunc cortex_x2_core_pwr_dwn
- /*
- * Errata printing function for Cortex X2. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_x2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X2_2002765, cortex_x2, 2002765
- report_errata ERRATA_X2_2017096, cortex_x2, 2017096
- report_errata ERRATA_X2_2058056, cortex_x2, 2058056
- report_errata ERRATA_X2_2081180, cortex_x2, 2081180
- report_errata ERRATA_X2_2083908, cortex_x2, 2083908
- report_errata ERRATA_X2_2147715, cortex_x2, 2147715
- report_errata ERRATA_X2_2216384, cortex_x2, 2216384
- report_errata ERRATA_X2_2282622, cortex_x2, 2282622
- report_errata ERRATA_X2_2371105, cortex_x2, 2371105
- report_errata ERRATA_X2_2768515, cortex_x2, 2768515
- report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x2_errata_report
-#endif
-
-func cortex_x2_reset_func
- mov x19, x30
+errata_report_shim cortex_x2
+cpu_reset_func_start cortex_x2
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_X2_2002765
- mov x0, x18
- bl errata_cortex_x2_2002765_wa
-#endif
-
-#if ERRATA_X2_2058056
- mov x0, x18
- bl errata_cortex_x2_2058056_wa
-#endif
-
-#if ERRATA_X2_2083908
- mov x0, x18
- bl errata_cortex_x2_2083908_wa
-#endif
-
-#if ERRATA_X2_2017096
- mov x0, x18
- bl errata_x2_2017096_wa
-#endif
-
-#if ERRATA_X2_2081180
- mov x0, x18
- bl errata_x2_2081180_wa
-#endif
-
-#if ERRATA_X2_2216384
- mov x0, x18
- bl errata_x2_2216384_wa
-#endif
-
-#if ERRATA_X2_2147715
- mov x0, x18
- bl errata_x2_2147715_wa
-#endif
-
-#if ERRATA_X2_2282622
- mov x0, x18
- bl errata_x2_2282622_wa
-#endif
-
-#if ERRATA_X2_2371105
- mov x0, x18
- bl errata_x2_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_x2_reset_func
+cpu_reset_func_end cortex_x2
/* ---------------------------------------------
* This function provides Cortex X2 specific
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index f104b48..c781d38 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,141 +26,51 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_x3_core_pwr_dwn
-#if ERRATA_X3_2313909
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_cortex_x3_2313909_wa
- mov x30, x15
-#endif /* ERRATA_X3_2313909 */
+workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X3_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_x3_core_pwr_dwn
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_x3_reset_func
- mov x19, x30
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X3 generic vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x3
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
- bl cpu_get_rev_var
-
-#if ERRATA_X3_2615812
- bl errata_cortex_x3_2615812_wa
-#endif /* ERRATA_X3_2615812 */
-
- isb
- ret x19
-endfunc cortex_x3_reset_func
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
- * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2313909_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2313909
- cbz x0, 1f
-
- /* Set bit 36 in ACTLR2_EL1 */
- mrs x1, CORTEX_X3_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
- msr CORTEX_X3_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_x3_2313909_wa
-
-func check_errata_2313909
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2313909
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
- * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2615812_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2615812
- cbz x0, 1f
-
+workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
/* Disable retention control for WFI and WFE. */
mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
msr CORTEX_X3_CPUPWRCTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_x3_2615812_wa
+workaround_reset_end cortex_x3, ERRATUM(2615812)
-func check_errata_2615812
- /* Applies to r1p1 and below. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2615812
+check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
-#if REPORT_ERRATA
- /*
- * Errata printing function for Cortex-X3. Must follow AAPCS.
- */
-func cortex_x3_errata_report
- stp x8, x30, [sp, #-16]!
+workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ override_vector_table wa_cve_vbar_cortex_x3
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x3, CVE(2022, 23960)
- bl cpu_get_rev_var
- mov x8, x0
+check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X3_2313909, cortex_x3, 2313909
- report_errata ERRATA_X3_2615812, cortex_x3, 2615812
- report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
+cpu_reset_func_start cortex_x3
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_x3
- ldp x8, x30, [sp], #16
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_x3_core_pwr_dwn
+apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
ret
-endfunc cortex_x3_errata_report
-#endif
+endfunc cortex_x3_core_pwr_dwn
+
+errata_report_shim cortex_x3
/* ---------------------------------------------
* This function provides Cortex-X3-
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index db87008..7619f9c 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_x4_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex X4 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_x4
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_x4
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x4, CVE(2022, 23960)
- isb
- ret
-endfunc cortex_x4_reset_func
+check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_x4
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_x4
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -61,33 +52,12 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_X4_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X4_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_x4_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex X4. Must follow AAPCS.
- */
-func cortex_x4_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_x4, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x4_errata_report
-#endif
+errata_report_shim cortex_x4
/* ---------------------------------------------
* This function provides Cortex X4-specific
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index a4285ed..1ae3180 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -33,6 +33,15 @@
/* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr
+#if ENABLE_ASSERTIONS
+ /*
+ * Assert if invalid cpu_ops obtained. If this is not valid, it may
+ * suggest that the proper CPU file hasn't been included.
+ */
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif
+
/* Get the cpu_ops reset handler */
ldr x2, [x0, #CPU_RESET_FUNC]
mov x30, x19
diff --git a/lib/cpus/aarch64/cpuamu_helpers.S b/lib/cpus/aarch64/cpuamu_helpers.S
index 5a77fc7..e71e345 100644
--- a/lib/cpus/aarch64/cpuamu_helpers.S
+++ b/lib/cpus/aarch64/cpuamu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 3c54a6f..884281d 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -207,7 +207,14 @@
2: ret
endfunc denver_disable_dco
-func check_errata_cve_2017_5715
+workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ adr x1, workaround_bpflush_runtime_exceptions
+ msr vbar_el3, x1
+#endif
+workaround_reset_end denver, CVE(2017, 5715)
+
+check_erratum_custom_start denver, CVE(2017, 5715)
mov x0, #ERRATA_MISSING
#if WORKAROUND_CVE_2017_5715
/*
@@ -224,43 +231,9 @@
1:
#endif
ret
-endfunc check_errata_cve_2017_5715
-
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Denver.
- * -------------------------------------------------
- */
-func denver_reset_func
-
- mov x19, x30
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
- /*
- * Check if the CPU supports the special instruction
- * required to flush the indirect branch predictor and
- * RSB. Support for this operation can be determined by
- * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
- */
- mrs x0, id_afr0_el1
- mov x1, #0x10000
- and x0, x0, x1
- cmp x0, #0
- adr x1, workaround_bpflush_runtime_exceptions
- mrs x2, vbar_el3
- csel x0, x1, x2, ne
- msr vbar_el3, x0
-#endif
+check_erratum_custom_end denver, CVE(2017, 5715)
-#if WORKAROUND_CVE_2018_3639
+workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
/*
* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
* bits in the ACTLR_EL3 register to disable speculative
@@ -277,8 +250,11 @@
msr actlr_el3, x0
isb
dsb sy
-#endif
+workaround_reset_end denver, CVE(2018, 3639)
+
+check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+cpu_reset_func_start denver
/* ----------------------------------------------------
* Reset ACTLR.PMSTATE to C1 state
* ----------------------------------------------------
@@ -293,9 +269,7 @@
* ----------------------------------------------------
*/
bl denver_enable_dco
-
- ret x19
-endfunc denver_reset_func
+cpu_reset_func_end denver
/* ----------------------------------------------------
* The CPU Ops core power down function for Denver.
@@ -322,27 +296,7 @@
ret
endfunc denver_cluster_pwr_dwn
-#if REPORT_ERRATA
- /*
- * Errata printing function for Denver. Must follow AAPCS.
- */
-func denver_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
-
- ldp x8, x30, [sp], #16
- ret
-endfunc denver_errata_report
-#endif
+errata_report_shim denver
/* ---------------------------------------------
* This function provides Denver specific
@@ -367,7 +321,7 @@
.macro denver_cpu_ops_wa midr
declare_cpu_ops_wa denver, \midr, \
denver_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_denver_5715, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
denver_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
index 96b63cf..45bd8d3 100644
--- a/lib/cpus/aarch64/neoverse_e1.S
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,20 +21,18 @@
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* -------------------------------------------------
- * The CPU Ops reset function for Neoverse-E1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func neoverse_e1_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to neoverse_e1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc neoverse_e1_reset_func
+cpu_reset_func_start neoverse_e1
+cpu_reset_func_end neoverse_e1
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
@@ -44,27 +42,7 @@
ret
endfunc neoverse_e1_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_e1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_e1_errata_report
-#endif
-
+errata_report_shim neoverse_e1
.section .rodata.neoverse_e1_regs, "aS"
neoverse_e1_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 2cf94c7..36a7ee7 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,20 +27,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1043202.
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n1_1043202_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1043202
- cbz x0, 1f
+.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -50,314 +47,72 @@
msr CPUPMR_EL3, x0
ldr x0, =0x800200071
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_n1_1043202_wa
+workaround_reset_end neoverse_n1, ERRATUM(1043202)
-func check_errata_1043202
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1043202
+check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Disable speculative loads if Neoverse N1 supports
- * SSBS.
- *
- * Shall clobber: x0.
- * --------------------------------------------------
- */
-func neoverse_n1_disable_speculative_loads
- /* Check if the PE implements SSBS */
- mrs x0, id_aa64pfr1_el1
- tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
- b.eq 1f
+workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
+workaround_reset_end neoverse_n1, ERRATUM(1073348)
- /* Disable speculative loads */
- msr SSBS, xzr
+check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
-1:
- ret
-endfunc neoverse_n1_disable_speculative_loads
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1073348
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1073348_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1073348_wa
-
-func check_errata_1073348
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1130799
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1130799_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1130799_wa
-
-func check_errata_1130799
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1165347
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1165347_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1165347
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1165347_wa
+workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
+workaround_reset_end neoverse_n1, ERRATUM(1130799)
-func check_errata_1165347
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1165347
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1207823
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1207823_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1207823
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1207823_wa
+check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
-func check_errata_1207823
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1207823
+workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
+workaround_reset_end neoverse_n1, ERRATUM(1165347)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1220197
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1220197_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1220197_wa
+check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
-func check_errata_1220197
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
+workaround_reset_end neoverse_n1, ERRATUM(1207823)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1257314
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1257314_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
- msr NEOVERSE_N1_CPUACTLR3_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1257314_wa
+check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
-func check_errata_1257314
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK
+workaround_reset_end neoverse_n1, ERRATUM(1220197)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262606
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262606_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262606
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262606_wa
+check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
-func check_errata_1262606
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
+workaround_reset_end neoverse_n1, ERRATUM(1257314)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262888
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262888_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262888_wa
+check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
-func check_errata_1262888
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1262606)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1275112
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1275112_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1275112
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1275112_wa
+check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
-func check_errata_1275112
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
+workaround_reset_end neoverse_n1, ERRATUM(1262888)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1315703.
- * This applies to revision <= r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1315703_wa
- /* Compare x0 against revision r3p1 */
- mov x17, x30
- bl check_errata_1315703
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
+workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1275112)
-1:
- ret x17
-endfunc errata_n1_1315703_wa
+check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
-func check_errata_1315703
- /* Applies to everything <= r3p0. */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1315703
+workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
+workaround_reset_end neoverse_n1, ERRATUM(1315703)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1542419.
- * This applies to revisions r3p0 - r4p0 of Neoverse N1
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1542419_wa
- /* Compare x0 against revision r3p0 and r4p0 */
- mov x17, x30
- bl check_errata_1542419
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
+workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -368,67 +123,17 @@
ldr x0, =0x08000020007D
msr CPUPCR_EL3, x0
isb
-1:
- ret x17
-endfunc errata_n1_1542419_wa
+workaround_reset_end neoverse_n1, ERRATUM(1542419)
-func check_errata_1542419
- /* Applies to everything r3p0 - r4p0. */
- mov x1, #0x30
- mov x2, #0x40
- b cpu_rev_var_range
-endfunc check_errata_1542419
+check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1868343.
- * This applies to revision <= r4p0 of Neoverse N1.
- * This workaround is the same as the workaround for
- * errata 1262606 and 1275112 but applies to a wider
- * revision range.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1868343_wa
- /*
- * Compare x0 against revision r4p0
- */
- mov x17, x30
- bl check_errata_1868343
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n1_1868343_wa
+workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1868343)
-func check_errata_1868343
- /* Applies to everything <= r4p0 */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
+check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1946160.
- * This applies to revisions r3p0, r3p1, r4p0, and
- * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
- * and r2p0 but there is no fix in these revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1946160_wa
- /*
- * Compare x0 against r3p0 - r4p1
- */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -437,7 +142,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #4
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800082
@@ -446,7 +150,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #5
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800200
@@ -455,147 +158,62 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
isb
-1:
- ret x17
-endfunc errata_n1_1946160_wa
+workaround_reset_end neoverse_n1, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
+check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_n1_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
-
+workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n1_2743102_wa
+workaround_runtime_end neoverse_n1, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_n1_reset_func
- mov x19, x30
+check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
- bl neoverse_n1_disable_speculative_loads
-
- /* Forces all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
- isb
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_N1_1043202
- mov x0, x18
- bl errata_n1_1043202_wa
-#endif
-
-#if ERRATA_N1_1073348
- mov x0, x18
- bl errata_n1_1073348_wa
-#endif
-
-#if ERRATA_N1_1130799
- mov x0, x18
- bl errata_n1_1130799_wa
-#endif
-
-#if ERRATA_N1_1165347
- mov x0, x18
- bl errata_n1_1165347_wa
-#endif
-
-#if ERRATA_N1_1207823
- mov x0, x18
- bl errata_n1_1207823_wa
-#endif
-
-#if ERRATA_N1_1220197
- mov x0, x18
- bl errata_n1_1220197_wa
-#endif
-
-#if ERRATA_N1_1257314
- mov x0, x18
- bl errata_n1_1257314_wa
-#endif
-
-#if ERRATA_N1_1262606
- mov x0, x18
- bl errata_n1_1262606_wa
-#endif
+workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n1, CVE(2022, 23960)
-#if ERRATA_N1_1262888
- mov x0, x18
- bl errata_n1_1262888_wa
-#endif
+check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_N1_1275112
- mov x0, x18
- bl errata_n1_1275112_wa
-#endif
+/* --------------------------------------------------
+ * Disable speculative loads if Neoverse N1 supports
+ * SSBS.
+ *
+ * Shall clobber: x0.
+ * --------------------------------------------------
+ */
+func neoverse_n1_disable_speculative_loads
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
-#if ERRATA_N1_1315703
- mov x0, x18
- bl errata_n1_1315703_wa
-#endif
+ /* Disable speculative loads */
+ msr SSBS, xzr
-#if ERRATA_N1_1542419
- mov x0, x18
- bl errata_n1_1542419_wa
-#endif
+1:
+ ret
+endfunc neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1868343
- mov x0, x18
- bl errata_n1_1868343_wa
-#endif
+cpu_reset_func_start neoverse_n1
+ bl neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1946160
- mov x0, x18
- bl errata_n1_1946160_wa
-#endif
+ /* Forces all cacheable atomic instructions to be near */
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
+ isb
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el3, x0
-
+ sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el2, x0
-
+ sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Enable group0 counters */
mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0
@@ -603,27 +221,9 @@
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N1_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n1_reset_func
+cpu_reset_func_end neoverse_n1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -634,55 +234,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
- msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
-#if ERRATA_N1_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n1_2743102_wa
- mov x30, x15
-#endif /* ERRATA_N1_2743102 */
+ sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
+
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
+
isb
ret
endfunc neoverse_n1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_n1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
- report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
- report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
- report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
- report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
- report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
- report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
- report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
- report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
- report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
- report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
- report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
- report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
- report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
- report_errata ERRATA_N1_2743102, neoverse_n1, 2743102
- report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n1_errata_report
-#endif
+errata_report_shim neoverse_n1
/*
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
diff --git a/lib/cpus/aarch64/neoverse_n1_pubsub.c b/lib/cpus/aarch64/neoverse_n1_pubsub.c
index b1b7bb8..ecfb501 100644
--- a/lib/cpus/aarch64/neoverse_n1_pubsub.c
+++ b/lib/cpus/aarch64/neoverse_n1_pubsub.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 60d322f..acf8dee 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,20 +24,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2002655.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_2313941:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N2.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n2_2002655_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2002655
- cbz x0, 1f
+.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941
+.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
+workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
/* Apply instruction patching sequence */
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
@@ -55,111 +52,33 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000001003f3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_n2_2002655_wa
-
-func check_errata_2002655
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2002655
+workaround_reset_end neoverse_n2, ERRATUM(2002655)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2067956.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2067956_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2067956
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2067956_wa
+check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
-func check_errata_2067956
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2067956
+workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
+ sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end neoverse_n2, ERRATUM(2025414)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2025414.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2025414_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2025414
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x1
+check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
-1:
- ret x17
-endfunc errata_n2_2025414_wa
+workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
+workaround_reset_end neoverse_n2, ERRATUM(2067956)
-func check_errata_2025414
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2025414
+check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2189731.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2189731_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2189731
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_n2_2189731_wa
-
-func check_errata_2189731
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2189731
+workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
+ /* Apply instruction patching sequence */
+ mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
+ mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_N2_CPUECTLR2_EL1, x1
+workaround_reset_end neoverse_n2, ERRATUM(2138953)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138956.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n2_2138956_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138956
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3)
+workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
/* Apply instruction patching sequence */
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
@@ -177,120 +96,27 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003F3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_n2_2138956_wa
+workaround_reset_end neoverse_n2, ERRATUM(2138956)
-func check_errata_2138956
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138956
+check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2242415.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2242415_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2242415
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958
/* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2242415_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
+workaround_reset_end neoverse_n2, ERRATUM(2138958)
-func check_errata_2242415
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2242415
+check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138953.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2138953_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138953
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
+workaround_reset_end neoverse_n2, ERRATUM(2189731)
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
- mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
- msr NEOVERSE_N2_CPUECTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2138953_wa
+check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0)
-func check_errata_2138953
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138953
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138958.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2138958_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138958
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2138958_wa
-
-func check_errata_2138958
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138958
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2242400.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2242400_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2242400
- cbz x0, 1f
-
+workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400
/* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
ldr x0, =0x2
msr S3_6_c15_c8_0, x0
ldr x0, =0x10F600E000
@@ -299,174 +125,86 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0
- isb
-1:
- ret x17
-endfunc errata_n2_2242400_wa
+workaround_reset_end neoverse_n2, ERRATUM(2242400)
-func check_errata_2242400
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2242400
+check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2280757.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2280757_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2280757
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+workaround_reset_end neoverse_n2, ERRATUM(2242415)
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2280757_wa
+check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0)
-func check_errata_2280757
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2280757
+workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757
+ /* Apply instruction patching sequence */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+workaround_reset_end neoverse_n2, ERRATUM(2280757)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2326639.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2326639_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2326639
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
+workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* Set bit 36 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2326639_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end neoverse_n2, ERRATUM(2326639)
-func check_errata_2326639
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2326639
+check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2376738.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current CPU.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2376738_wa
- mov x17, x30
- bl check_errata_2376738
- cbz x0, 1f
-
+workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738
/* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
* ST to behave like PLD/PFRM LD and not cause
* invalidations to other PE caches.
*/
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2376738_wa
-
-func check_errata_2376738
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, 0x00
- b cpu_rev_var_ls
-endfunc check_errata_2376738
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_n2, ERRATUM(2376738)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2388450.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2388450_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2388450
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3)
+workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450
/*Set bit 40 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n2_2388450_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end neoverse_n2, ERRATUM(2388450)
-func check_errata_2388450
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2388450
+check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0)
-/* -------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2743089.
- * This applies to revisions <= r0p2 and is fixed in r0p3.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_n2_2743089_wa
- mov x17, x30
- bl check_errata_2743089
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014
+ /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55
+ sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56
+workaround_reset_end neoverse_n2, ERRATUM(2743014)
+check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2)
+
+workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n2_2743089_wa
+workaround_runtime_end neoverse_n2, ERRATUM(2743089)
-func check_errata_2743089
- /* Applies to all revisions <= r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2743089
+check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511
+ /* Set bit 47 in ACTLR3_EL1 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_n2, ERRATUM(2779511)
+
+check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
+
+workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n2
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n2, CVE(2022,23960)
+
+check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* -------------------------------------------
* The CPU Ops reset function for Neoverse N2.
* -------------------------------------------
*/
-func neoverse_n2_reset_func
- mov x19, x30
+cpu_reset_func_start neoverse_n2
/* Check if the PE implements SSBS */
mrs x0, id_aa64pfr1_el1
@@ -477,174 +215,39 @@
msr SSBS, xzr
1:
/* Force all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N2_CPUACTLR2_EL1, x0
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_N2_2067956
- mov x0, x18
- bl errata_n2_2067956_wa
-#endif
-
-#if ERRATA_N2_2025414
- mov x0, x18
- bl errata_n2_2025414_wa
-#endif
-
-#if ERRATA_N2_2189731
- mov x0, x18
- bl errata_n2_2189731_wa
-#endif
-
-
-#if ERRATA_N2_2138956
- mov x0, x18
- bl errata_n2_2138956_wa
-#endif
-
-#if ERRATA_N2_2138953
- mov x0, x18
- bl errata_n2_2138953_wa
-#endif
-
-#if ERRATA_N2_2242415
- mov x0, x18
- bl errata_n2_2242415_wa
-#endif
-
-#if ERRATA_N2_2138958
- mov x0, x18
- bl errata_n2_2138958_wa
-#endif
-
-#if ERRATA_N2_2242400
- mov x0, x18
- bl errata_n2_2242400_wa
-#endif
-
-#if ERRATA_N2_2280757
- mov x0, x18
- bl errata_n2_2280757_wa
-#endif
-
-#if ERRATA_N2_2376738
- mov x0, x18
- bl errata_n2_2376738_wa
-#endif
-
-#if ERRATA_N2_2388450
- mov x0, x18
- bl errata_n2_2388450_wa
-#endif
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, cptr_el3
- orr x0, x0, #TAM_BIT
- msr cptr_el3, x0
-
+ sysreg_bit_set cptr_el3, TAM_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, cptr_el2
- orr x0, x0, #TAM_BIT
- msr cptr_el2, x0
-
+ sysreg_bit_set cptr_el2, TAM_BIT
/* No need to enable the counters as this would be done at el3 exit */
#endif
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some systems may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N2_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_N2_2002655
- mov x0, x18
- bl errata_n2_2002655_wa
+ sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n2_reset_func
+cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
-#if ERRATA_N2_2326639
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n2_2326639_wa
- mov x30, x15
-#endif /* ERRATA_N2_2326639 */
+ apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
* ---------------------------------------------------
*/
- mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
- msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
-#if ERRATA_N2_2743089
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n2_2743089_wa
- mov x30, x15
-#endif /* ERRATA_N2_2743089 */
+ sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
+
+ apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
+
isb
ret
endfunc neoverse_n2_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
- */
-func neoverse_n2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
- report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
- report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
- report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
- report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
- report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
- report_errata ERRATA_N2_2242415, neoverse_n2, 2242415
- report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
- report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
- report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
- report_errata ERRATA_N2_2326639, neoverse_n2, 2326639
- report_errata ERRATA_N2_2376738, neoverse_n2, 2376738
- report_errata ERRATA_N2_2388450, neoverse_n2, 2388450
- report_errata ERRATA_N2_2743089, neoverse_n2, 2743089
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n2_errata_report
-#endif
+errata_report_shim neoverse_n2
/* ---------------------------------------------
* This function provides Neoverse N2 specific
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
index 030293d..3b3245d 100644
--- a/lib/cpus/aarch64/neoverse_poseidon.S
+++ b/lib/cpus/aarch64/neoverse_poseidon.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,19 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-poseidon generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_poseidon
+
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_poseidon, CVE(2022,23960)
+
+check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -35,59 +48,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
+ NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
isb
ret
endfunc neoverse_poseidon_core_pwr_dwn
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_poseidon_reset_func
+cpu_reset_func_start neoverse_poseidon
/* Disable speculative loads */
msr SSBS, xzr
+cpu_reset_func_end neoverse_poseidon
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse Poseidon generic vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_poseidon
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret
-endfunc neoverse_poseidon_reset_func
-
-#if REPORT_ERRATA
- /*
- * Errata printing function for Neoverse Poseidon. Must follow AAPCS.
- */
-func neoverse_poseidon_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, neoverse_poseidon, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_poseidon_errata_report
-#endif
+errata_report_shim neoverse_poseidon
/* ---------------------------------------------
* This function provides Neoverse-Poseidon specific
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 363c2e6..35d2c48 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1618635.
- * This applies to revision r0p0 and is fixed in
- * r1p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1618635_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1618635
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
/* Inserts a DMB SY before and after MRS PAR_EL1 */
ldr x0, =0x0
msr NEOVERSE_V1_CPUPSELR_EL3, x0
@@ -90,146 +77,39 @@
ldr x0, = 0x4004027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
- /* Synchronize to enable patches */
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1618635_wa
-
-func check_errata_1618635
- /* Applies to revision r0p0. */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1618635
+workaround_reset_end neoverse_v1, ERRATUM(1618635)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1774420.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1774420_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1774420
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0)
+workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420
/* Set bit 53 in CPUECTLR_EL1 */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1774420_wa
+ sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53
+workaround_reset_end neoverse_v1, ERRATUM(1774420)
-func check_errata_1774420
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1774420
+check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1791573.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1791573_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1791573
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573
/* Set bit 2 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1791573_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2
+workaround_reset_end neoverse_v1, ERRATUM(1791573)
-func check_errata_1791573
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1791573
+check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1852267.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1852267_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1852267
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267
/* Set bit 28 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1852267_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28
+workaround_reset_end neoverse_v1, ERRATUM(1852267)
-func check_errata_1852267
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1852267
+check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1925756.
- * This applies to revisions <= r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1925756_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1925756
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756
/* Set bit 8 in CPUECTLR_EL1 */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1925756_wa
+ sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8
+workaround_reset_end neoverse_v1, ERRATUM(1925756)
-func check_errata_1925756
- /* Applies to <= r1p1. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1925756
+check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Erratum #1940577
- * This applies to revisions r1p0 - r1p1 and is open.
- * It also exists in r0p0 but there is no fix in that
- * revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1940577_wa
- /* Compare x0 against revisions r1p0 - r1p1 */
- mov x17, x30
- bl check_errata_1940577
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577
mov x0, #0
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -257,34 +137,11 @@
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1940577_wa
+workaround_reset_end neoverse_v1, ERRATUM(1940577)
-func check_errata_1940577
- /* Applies to revisions r1p0 - r1p1. */
- mov x1, #0x10
- mov x2, #0x11
- b cpu_rev_var_range
-endfunc check_errata_1940577
+check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1966096
- * This applies to revisions r1p0 - r1p1 and is open.
- * It also exists in r0p0 but there is no workaround
- * for that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1966096_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1966096
- cbz x0, 1f
-
- /* Apply the workaround. */
+workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096
mov x0, #0x3
msr S3_6_C15_C8_0, x0
ldr x0, =0xEE010F12
@@ -293,33 +150,20 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x80000000003FF
msr S3_6_C15_C8_1, x0
- isb
+workaround_reset_end neoverse_v1, ERRATUM(1966096)
-1:
- ret x17
-endfunc errata_neoverse_v1_1966096_wa
+check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
-func check_errata_1966096
- mov x1, #0x10
- mov x2, #0x11
- b cpu_rev_var_range
-endfunc check_errata_1966096
+workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
+ mrs x1, NEOVERSE_V1_CPUECTLR_EL1
+ mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_V1_CPUECTLR_EL1, x1
+workaround_reset_end neoverse_v1, ERRATUM(2108267)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2139242.
- * This applies to revisions r0p0, r1p0, and r1p1, it
- * is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2139242_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2139242
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 1)
- /* Apply the workaround. */
+workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
mov x0, #0x3
msr S3_6_C15_C8_0, x0
ldr x0, =0xEE720F14
@@ -328,63 +172,11 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x40000005003FF
msr S3_6_C15_C8_1, x0
- isb
+workaround_reset_end neoverse_v1, ERRATUM(2139242)
-1:
- ret x17
-endfunc errata_neoverse_v1_2139242_wa
+check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1)
-func check_errata_2139242
- /* Applies to r0p0, r1p0, r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2139242
-
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2108267.
- * This applies to revisions r0p0, r1p0, and r1p1, it
- * is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2108267_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2108267
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_neoverse_v1_2108267_wa
-
-func check_errata_2108267
- /* Applies to r0p0, r1p0, r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2108267
-
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2216392.
- * This applies to revisions r1p0 and r1p1 and is
- * still open.
- * This issue is also present in r0p0 but there is no
- * workaround in that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2216392_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216392
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@@ -393,167 +185,56 @@
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end neoverse_v1, ERRATUM(2216392)
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2216392_wa
+check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1)
-func check_errata_2216392
- /* Applies to revisions r1p0 and r1p1. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 1)
- b cpu_rev_var_range
-endfunc check_errata_2216392
-
- /* -----------------------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2294912.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------------------
- */
-func errata_neoverse_v1_2294912_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2294912
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
/* Set bit 0 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2294912_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_v1, ERRATUM(2294912)
-func check_errata_2294912
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2294912
+check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 1)
- /* ---------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2372203.
- * This applies to revisions <= r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v1_2372203_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2372203
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
/* Set bit 40 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2372203_wa
-
-func check_errata_2372203
- /* Applies to <= r1p1. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2372203
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
+workaround_reset_end neoverse_v1, ERRATUM(2372203)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2743093.
- * This applies to revisions <= r1p2 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v1_2743093_wa
- mov x17, x30
- bl check_errata_2743093
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1)
+workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_neoverse_v1_2743093_wa
+workaround_runtime_end neoverse_v1, ERRATUM(2743093)
-func check_errata_2743093
- /* Applies to all revisions <= r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2743093
+check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2)
- /* ---------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2743233.
- * This applies to revisions r0p0, r1p0, r1p1 and r1p2.
- * It is still open.
- * x0: variant[4:7] and revisions[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ---------------------------------------------------
- */
-func errata_neoverse_v1_2743233_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2743233
- cbz x0, 1f
+workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233
+ sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56
+ sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55
+workaround_reset_end neoverse_v1, ERRATUM(2743233)
- /* Apply the workaround */
- mrs x1, NEOVERSE_V1_ACTLR5_EL1
- bic x1, x1, #BIT(56)
- orr x1, x1, #BIT(55)
- msr NEOVERSE_V1_ACTLR5_EL1, x1
+check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2)
-1:
- ret x17
-endfunc errata_neoverse_v1_2743233_wa
+workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461
+ sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_v1, ERRATUM(2779461)
-func check_errata_2743233
- /* Applies to r0p0, r1p0, r1p1 and r1p2 */
- mov x1, #CPU_REV(1,2)
- b cpu_rev_var_ls
-endfunc check_errata_2743233
+check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2779461.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
+workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-V1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_neoverse_v1_2779461_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779461
- cbz x0, 1f
-
- /* Apply the workaround */
- mrs x1, NEOVERSE_V1_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr NEOVERSE_V1_ACTLR3_EL1, x1
+ override_vector_table wa_cve_vbar_neoverse_v1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v1, CVE(2022,23960)
-1:
- ret x17
-endfunc errata_neoverse_v1_2779461_wa
-
-func check_errata_2779461
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2779461
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -564,148 +245,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
-#if ERRATA_V1_2743093
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_neoverse_v1_2743093_wa
- mov x30, x15
-#endif /* ERRATA_V1_2743093 */
+ sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
+
isb
ret
endfunc neoverse_v1_core_pwr_dwn
- /*
- * Errata printing function for Neoverse V1. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func neoverse_v1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
+errata_report_shim neoverse_v1
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_V1_1618635, neoverse_v1, 1618635
- report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
- report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
- report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
- report_errata ERRATA_V1_1925756, neoverse_v1, 1925756
- report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
- report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
- report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
- report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
- report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
- report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
- report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
- report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
- report_errata ERRATA_V1_2743233, neoverse_v1, 2743233
- report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
- report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_v1_errata_report
-#endif
-
-func neoverse_v1_reset_func
- mov x19, x30
-
+cpu_reset_func_start neoverse_v1
/* Disable speculative loads */
msr SSBS, xzr
- isb
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_V1_1618635
- mov x0, x18
- bl errata_neoverse_v1_1618635_wa
-#endif
-
-#if ERRATA_V1_1774420
- mov x0, x18
- bl errata_neoverse_v1_1774420_wa
-#endif
-
-#if ERRATA_V1_1791573
- mov x0, x18
- bl errata_neoverse_v1_1791573_wa
-#endif
-
-#if ERRATA_V1_1852267
- mov x0, x18
- bl errata_neoverse_v1_1852267_wa
-#endif
-
-#if ERRATA_V1_1925756
- mov x0, x18
- bl errata_neoverse_v1_1925756_wa
-#endif
-
-#if ERRATA_V1_1940577
- mov x0, x18
- bl errata_neoverse_v1_1940577_wa
-#endif
-
-#if ERRATA_V1_1966096
- mov x0, x18
- bl errata_neoverse_v1_1966096_wa
-#endif
-
-#if ERRATA_V1_2139242
- mov x0, x18
- bl errata_neoverse_v1_2139242_wa
-#endif
-
-#if ERRATA_V1_2108267
- mov x0, x18
- bl errata_neoverse_v1_2108267_wa
-#endif
-
-#if ERRATA_V1_2216392
- mov x0, x18
- bl errata_neoverse_v1_2216392_wa
-#endif
-
-#if ERRATA_V1_2294912
- mov x0, x18
- bl errata_neoverse_v1_2294912_wa
-#endif
-
-#if ERRATA_V1_2372203
- mov x0, x18
- bl errata_neoverse_v1_2372203_wa
-#endif
-
-#if ERRATA_V1_2743233
- mov x0, x18
- bl errata_neoverse_v1_2743233_wa
-#endif
-
-#if ERRATA_V1_2779461
- mov x0, x18
- bl errata_neoverse_v1_2779461_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-V1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_v1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_v1_reset_func
+cpu_reset_func_end neoverse_v1
/* ---------------------------------------------
* This function provides Neoverse-V1 specific
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 6e00e5e..36ae4de 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,25 @@
#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+
+check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1)
+
+workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-V2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_v2
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v2, CVE(2022,23960)
+
+check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
#endif /* WORKAROUND_CVE_2022_23960 */
@@ -35,90 +54,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
-#if ERRATA_V2_2801372
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_neoverse_v2_2801372_wa
- mov x30, x15
-#endif /* ERRATA_V2_2801372 */
+ sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+
isb
ret
endfunc neoverse_v2_core_pwr_dwn
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V2 Errata #2801372
- * This applies to revisions <= r0p1 and is fixed in r0p2.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v2_2801372_wa
- mov x17, x30
- bl check_errata_2801372
- cbz x0, 1f
-
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_neoverse_v2_2801372_wa
-
-func check_errata_2801372
- /* Applies to all revisions <= r0p1 */
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_2801372
-
-func neoverse_v2_reset_func
+cpu_reset_func_start neoverse_v2
/* Disable speculative loads */
msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse V2 vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_v2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
- isb
- ret
-endfunc neoverse_v2_reset_func
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse V2. Must follow AAPCS.
- */
-func neoverse_v2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
- report_errata ERRATA_V2_2801372, neoverse_v2, 2801372
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_v2_errata_report
-#endif
+cpu_reset_func_end neoverse_v2
+errata_report_shim neoverse_v2
/* ---------------------------------------------
* This function provides Neoverse V2-
* specific register information for crash
diff --git a/lib/cpus/aarch64/nevis.S b/lib/cpus/aarch64/nevis.S
new file mode 100644
index 0000000..36830a9
--- /dev/null
+++ b/lib/cpus/aarch64/nevis.S
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <nevis.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start nevis
+ /* ----------------------------------------------------
+ * Disable speculative loads
+ * ----------------------------------------------------
+ */
+ msr SSBS, xzr
+cpu_reset_func_end nevis
+
+func nevis_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \
+ NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ isb
+ ret
+endfunc nevis_core_pwr_dwn
+
+errata_report_shim nevis
+
+.section .rodata.nevis_regs, "aS"
+nevis_regs: /* The ASCII list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func nevis_cpu_reg_dump
+ adr x6, nevis_regs
+ mrs x8, NEVIS_CPUECTLR_EL1
+ ret
+endfunc nevis_cpu_reg_dump
+
+declare_cpu_ops nevis, NEVIS_MIDR, \
+ nevis_reset_func, \
+ nevis_core_pwr_dwn
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
index 0222818..8d9aa5e 100644
--- a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
+++ b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
index ed0a549..823f849 100644
--- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
+++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
index ceb93f1..bf26658 100644
--- a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
+++ b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4a80bce..8df0a29 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -612,43 +612,43 @@
CPU_FLAG_LIST += ERRATA_A710_2768515
# Flag to apply erratum 2002655 workaround during reset. This erratum applies
-# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
+# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2002655
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2067956
# Flag to apply erratum 2025414 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2025414
# Flag to apply erratum 2189731 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2189731
# Flag to apply erratum 2138956 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138956
# Flag to apply erratum 2138953 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2138953
# Flag to apply erratum 2242415 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242415
# Flag to apply erratum 2138958 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138958
# Flag to apply erratum 2242400 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242400
# Flag to apply erratum 2280757 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2280757
# Flag to apply erraturm 2326639 workaroud during powerdown. This erratum
@@ -656,7 +656,7 @@
CPU_FLAG_LIST += ERRATA_N2_2326639
# Flag to apply erratum 2376738 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
+# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2376738
# Flag to apply erratum 2388450 workaround during reset. This erratum applies
@@ -668,10 +668,18 @@
# r0p3.
CPU_FLAG_LIST += ERRATA_N2_2728475
+# Flag to apply erratum 2743014 workaround during reset. This erratum applies
+# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2743014
+
# Flag to apply erratum 2743089 workaround during during powerdown. This erratum
# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2743089
+# Flag to apply erratum 2779511 workaround during reset. This erratum applies
+# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2779511
+
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765
diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk
index 138fc72..caa9fcf 100644
--- a/lib/debugfs/debugfs.mk
+++ b/lib/debugfs/debugfs.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c
index 13ced3d..64c64f8 100644
--- a/lib/debugfs/debugfs_smc.c
+++ b/lib/debugfs/debugfs_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S
index bdad2c1..e59b7fd 100644
--- a/lib/el3_runtime/aarch32/cpu_data.S
+++ b/lib/el3_runtime/aarch32/cpu_data.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 771fcdc..f47e779 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -10,15 +10,6 @@
#include <context.h>
#include <el3_common_macros.S>
-#if CTX_INCLUDE_EL2_REGS
- .global el2_sysregs_context_save_common
- .global el2_sysregs_context_restore_common
-#if CTX_INCLUDE_MTE_REGS
- .global el2_sysregs_context_save_mte
- .global el2_sysregs_context_restore_mte
-#endif /* CTX_INCLUDE_MTE_REGS */
-#endif /* CTX_INCLUDE_EL2_REGS */
-
.global el1_sysregs_context_save
.global el1_sysregs_context_restore
#if CTX_INCLUDE_FPREGS
@@ -30,183 +21,6 @@
.global save_and_update_ptw_el1_sys_regs
.global el3_exit
-#if CTX_INCLUDE_EL2_REGS
-
-/* -----------------------------------------------------
- * The following functions strictly follow the AArch64
- * PCS to use x9-x16 (temporary caller-saved registers)
- * to save/restore EL2 system register context.
- * el2_sysregs_context_save/restore_common functions
- * save and restore registers that are common to all
- * configurations. The rest of the functions save and
- * restore EL2 system registers that are present when a
- * particular feature is enabled. All functions assume
- * that 'x0' is pointing to a 'el2_sys_regs' structure
- * where the register context will be saved/restored.
- *
- * The following registers are not added.
- * AMEVCNTVOFF0<n>_EL2
- * AMEVCNTVOFF1<n>_EL2
- * ICH_AP0R<n>_EL2
- * ICH_AP1R<n>_EL2
- * ICH_LR<n>_EL2
- * -----------------------------------------------------
- */
-func el2_sysregs_context_save_common
- mrs x9, actlr_el2
- mrs x10, afsr0_el2
- stp x9, x10, [x0, #CTX_ACTLR_EL2]
-
- mrs x11, afsr1_el2
- mrs x12, amair_el2
- stp x11, x12, [x0, #CTX_AFSR1_EL2]
-
- mrs x13, cnthctl_el2
- mrs x14, cntvoff_el2
- stp x13, x14, [x0, #CTX_CNTHCTL_EL2]
-
- mrs x15, cptr_el2
- str x15, [x0, #CTX_CPTR_EL2]
-
-#if CTX_INCLUDE_AARCH32_REGS
- mrs x16, dbgvcr32_el2
- str x16, [x0, #CTX_DBGVCR32_EL2]
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
- mrs x9, elr_el2
- mrs x10, esr_el2
- stp x9, x10, [x0, #CTX_ELR_EL2]
-
- mrs x11, far_el2
- mrs x12, hacr_el2
- stp x11, x12, [x0, #CTX_FAR_EL2]
-
- mrs x13, hcr_el2
- mrs x14, hpfar_el2
- stp x13, x14, [x0, #CTX_HCR_EL2]
-
- mrs x15, hstr_el2
- mrs x16, ICC_SRE_EL2
- stp x15, x16, [x0, #CTX_HSTR_EL2]
-
- mrs x9, ICH_HCR_EL2
- mrs x10, ICH_VMCR_EL2
- stp x9, x10, [x0, #CTX_ICH_HCR_EL2]
-
- mrs x11, mair_el2
- mrs x12, mdcr_el2
- stp x11, x12, [x0, #CTX_MAIR_EL2]
-
- mrs x14, sctlr_el2
- str x14, [x0, #CTX_SCTLR_EL2]
-
- mrs x15, spsr_el2
- mrs x16, sp_el2
- stp x15, x16, [x0, #CTX_SPSR_EL2]
-
- mrs x9, tcr_el2
- mrs x10, tpidr_el2
- stp x9, x10, [x0, #CTX_TCR_EL2]
-
- mrs x11, ttbr0_el2
- mrs x12, vbar_el2
- stp x11, x12, [x0, #CTX_TTBR0_EL2]
-
- mrs x13, vmpidr_el2
- mrs x14, vpidr_el2
- stp x13, x14, [x0, #CTX_VMPIDR_EL2]
-
- mrs x15, vtcr_el2
- mrs x16, vttbr_el2
- stp x15, x16, [x0, #CTX_VTCR_EL2]
- ret
-endfunc el2_sysregs_context_save_common
-
-func el2_sysregs_context_restore_common
- ldp x9, x10, [x0, #CTX_ACTLR_EL2]
- msr actlr_el2, x9
- msr afsr0_el2, x10
-
- ldp x11, x12, [x0, #CTX_AFSR1_EL2]
- msr afsr1_el2, x11
- msr amair_el2, x12
-
- ldp x13, x14, [x0, #CTX_CNTHCTL_EL2]
- msr cnthctl_el2, x13
- msr cntvoff_el2, x14
-
- ldr x15, [x0, #CTX_CPTR_EL2]
- msr cptr_el2, x15
-
-#if CTX_INCLUDE_AARCH32_REGS
- ldr x16, [x0, #CTX_DBGVCR32_EL2]
- msr dbgvcr32_el2, x16
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
- ldp x9, x10, [x0, #CTX_ELR_EL2]
- msr elr_el2, x9
- msr esr_el2, x10
-
- ldp x11, x12, [x0, #CTX_FAR_EL2]
- msr far_el2, x11
- msr hacr_el2, x12
-
- ldp x13, x14, [x0, #CTX_HCR_EL2]
- msr hcr_el2, x13
- msr hpfar_el2, x14
-
- ldp x15, x16, [x0, #CTX_HSTR_EL2]
- msr hstr_el2, x15
- msr ICC_SRE_EL2, x16
-
- ldp x9, x10, [x0, #CTX_ICH_HCR_EL2]
- msr ICH_HCR_EL2, x9
- msr ICH_VMCR_EL2, x10
-
- ldp x11, x12, [x0, #CTX_MAIR_EL2]
- msr mair_el2, x11
- msr mdcr_el2, x12
-
- ldr x14, [x0, #CTX_SCTLR_EL2]
- msr sctlr_el2, x14
-
- ldp x15, x16, [x0, #CTX_SPSR_EL2]
- msr spsr_el2, x15
- msr sp_el2, x16
-
- ldp x9, x10, [x0, #CTX_TCR_EL2]
- msr tcr_el2, x9
- msr tpidr_el2, x10
-
- ldp x11, x12, [x0, #CTX_TTBR0_EL2]
- msr ttbr0_el2, x11
- msr vbar_el2, x12
-
- ldp x13, x14, [x0, #CTX_VMPIDR_EL2]
- msr vmpidr_el2, x13
- msr vpidr_el2, x14
-
- ldp x15, x16, [x0, #CTX_VTCR_EL2]
- msr vtcr_el2, x15
- msr vttbr_el2, x16
- ret
-endfunc el2_sysregs_context_restore_common
-
-#if CTX_INCLUDE_MTE_REGS
-func el2_sysregs_context_save_mte
- mrs x9, TFSR_EL2
- str x9, [x0, #CTX_TFSR_EL2]
- ret
-endfunc el2_sysregs_context_save_mte
-
-func el2_sysregs_context_restore_mte
- ldr x9, [x0, #CTX_TFSR_EL2]
- msr TFSR_EL2, x9
- ret
-endfunc el2_sysregs_context_restore_mte
-#endif /* CTX_INCLUDE_MTE_REGS */
-
-#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
* The following function strictly follows the AArch64 PCS to use
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 70e0ec0..b16c113 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1004,6 +1004,89 @@
}
}
+/* -----------------------------------------------------
+ * The following registers are not added:
+ * AMEVCNTVOFF0<n>_EL2
+ * AMEVCNTVOFF1<n>_EL2
+ * ICH_AP0R<n>_EL2
+ * ICH_AP1R<n>_EL2
+ * ICH_LR<n>_EL2
+ * -----------------------------------------------------
+ */
+static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
+{
+ write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2());
+ write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2());
+ write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2());
+ write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2());
+ write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2());
+ write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2());
+ write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2());
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2());
+ }
+ write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2());
+ write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2());
+ write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2());
+ write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2());
+ write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2());
+ write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2());
+ write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2());
+ write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
+ write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2());
+ write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2());
+ write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2());
+ write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2());
+ write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2());
+ write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2());
+ write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2());
+ write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2());
+ write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2());
+ write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2());
+ write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2());
+ write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2());
+ write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2());
+ write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2());
+ write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2());
+}
+
+static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
+{
+ write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2));
+ write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2));
+ write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2));
+ write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2));
+ write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2));
+ write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2));
+ write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2));
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2));
+ }
+ write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2));
+ write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2));
+ write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2));
+ write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2));
+ write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2));
+ write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2));
+ write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2));
+ write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
+ write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2));
+ write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2));
+ write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2));
+ write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2));
+ write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2));
+ write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2));
+ write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2));
+ write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2));
+ write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2));
+ write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2));
+ write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2));
+ write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2));
+ write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2));
+ write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2));
+ write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2));
+}
+
/*******************************************************************************
* Save EL2 sysreg context
******************************************************************************/
@@ -1027,7 +1110,7 @@
el2_sysregs_context_save_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
- el2_sysregs_context_save_mte(el2_sysregs_ctx);
+ write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
#endif
if (is_feat_mpam_supported()) {
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
@@ -1116,7 +1199,7 @@
el2_sysregs_context_restore_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
- el2_sysregs_context_restore_mte(el2_sysregs_ctx);
+ write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));
#endif
if (is_feat_mpam_supported()) {
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
index 2392d6b..313f882 100644
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ b/lib/el3_runtime/aarch64/cpu_data.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c
index 13d464c..2056182 100644
--- a/lib/el3_runtime/cpu_data_array.c
+++ b/lib/el3_runtime/cpu_data_array.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index 03186d6..351a552 100644
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S
index 8ac7678..7090b2d 100644
--- a/lib/extensions/amu/aarch32/amu_helpers.S
+++ b/lib/extensions/amu/aarch32/amu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index e0d3399..8c5ef0b 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/aarch64/amu_helpers.S b/lib/extensions/amu/aarch64/amu_helpers.S
index 0f6d799..95d4ad6 100644
--- a/lib/extensions/amu/aarch64/amu_helpers.S
+++ b/lib/extensions/amu/aarch64/amu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/amu/amu_private.h b/lib/extensions/amu/amu_private.h
index eb7ff0e..a3b6845 100644
--- a/lib/extensions/amu/amu_private.h
+++ b/lib/extensions/amu/amu_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c
index 622879e..50f3727 100644
--- a/lib/extensions/ras/ras_common.c
+++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/extensions/ras/std_err_record.c b/lib/extensions/ras/std_err_record.c
index c03fbbe..6c1dc9f 100644
--- a/lib/extensions/ras/std_err_record.c
+++ b/lib/extensions/ras/std_err_record.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c
index b1d6eaa..136e056 100644
--- a/lib/fconf/fconf.c
+++ b/lib/fconf/fconf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/fconf/fconf.mk b/lib/fconf/fconf.mk
index fb88910..ff781aa 100644
--- a/lib/fconf/fconf.mk
+++ b/lib/fconf/fconf.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/libc/aarch64/setjmp.S b/lib/libc/aarch64/setjmp.S
index 9d9eb49..9cb31ea 100644
--- a/lib/libc/aarch64/setjmp.S
+++ b/lib/libc/aarch64/setjmp.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/abort.c b/lib/libc/abort.c
index 432b1d0..ac27f62 100644
--- a/lib/libc/abort.c
+++ b/lib/libc/abort.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index 8973ed5..301d142 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/exit.c b/lib/libc/exit.c
index f4ffe27..6de2e93 100644
--- a/lib/libc/exit.c
+++ b/lib/libc/exit.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/libc.mk b/lib/libc/libc.mk
index 5eb8b52..95da68c 100644
--- a/lib/libc/libc.mk
+++ b/lib/libc/libc.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/libc/memchr.c b/lib/libc/memchr.c
index 8cbb715..66d7ba1 100644
--- a/lib/libc/memchr.c
+++ b/lib/libc/memchr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memcmp.c b/lib/libc/memcmp.c
index cd5f0df..db2701b 100644
--- a/lib/libc/memcmp.c
+++ b/lib/libc/memcmp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index 158df9b..af9ed45 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memcpy_s.c b/lib/libc/memcpy_s.c
index 01e88b0..26953bf 100644
--- a/lib/libc/memcpy_s.c
+++ b/lib/libc/memcpy_s.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 63acf26..5c2b661 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/memset.c b/lib/libc/memset.c
index 17f798c..c5bac8d 100644
--- a/lib/libc/memset.c
+++ b/lib/libc/memset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c
index 340bdd8..1f919d1 100644
--- a/lib/libc/putchar.c
+++ b/lib/libc/putchar.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/puts.c b/lib/libc/puts.c
index 2a0ca11..f57fc98 100644
--- a/lib/libc/puts.c
+++ b/lib/libc/puts.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/strchr.c b/lib/libc/strchr.c
index d94bb9e..1cd03ca 100644
--- a/lib/libc/strchr.c
+++ b/lib/libc/strchr.c
@@ -30,7 +30,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libc/strcmp.c b/lib/libc/strcmp.c
index b742f9b..290db4c 100644
--- a/lib/libc/strcmp.c
+++ b/lib/libc/strcmp.c
@@ -33,7 +33,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libc/strlen.c b/lib/libc/strlen.c
index 3c27630..e4b79d9 100644
--- a/lib/libc/strlen.c
+++ b/lib/libc/strlen.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/libc/strncmp.c b/lib/libc/strncmp.c
index ce9e5ed..f0bbadc 100644
--- a/lib/libc/strncmp.c
+++ b/lib/libc/strncmp.c
@@ -30,7 +30,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libc/strnlen.c b/lib/libc/strnlen.c
index b944e95..49e9f7a 100644
--- a/lib/libc/strnlen.c
+++ b/lib/libc/strnlen.c
@@ -27,7 +27,7 @@
*/
/*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
* All rights reserved.
*/
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk
index 1cbbd78..812057d 100644
--- a/lib/libfdt/libfdt.mk
+++ b/lib/libfdt/libfdt.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 748eedd..bcd89ef 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 3c03ae6..9f27322 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/locks/exclusive/aarch32/spinlock.S b/lib/locks/exclusive/aarch32/spinlock.S
index 9492cc0..853d096 100644
--- a/lib/locks/exclusive/aarch32/spinlock.S
+++ b/lib/locks/exclusive/aarch32/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index e941b8a..5144bf7 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 6641db9..14f5533 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c
index ce2f0d9..bf0ad83 100644
--- a/lib/pmf/pmf_main.c
+++ b/lib/pmf/pmf_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c
index 6d79502..71486df 100644
--- a/lib/pmf/pmf_smc.c
+++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index d28d469..4e1013c 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index 61f31e5..3b77ab2 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
index 8d46691..89e3e12 100644
--- a/lib/psci/aarch64/runtime_errata.S
+++ b/lib/psci/aarch64/runtime_errata.S
@@ -20,7 +20,7 @@
mov x18, x0
#if ERRATA_A510_2684597
- bl errata_cortex_a510_2684597_wa
+ bl erratum_cortex_a510_2684597_wa
#endif
ret x19
diff --git a/lib/psci/psci_mem_protect.c b/lib/psci/psci_mem_protect.c
index 481051f..385dcd2 100644
--- a/lib/psci/psci_mem_protect.c
+++ b/lib/psci/psci_mem_protect.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 1f619ae..31875ff 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 1f93cc9..6bf1ff4 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c
index ecef95a..ad88d07 100644
--- a/lib/psci/psci_stat.c
+++ b/lib/psci/psci_stat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 2ff480b..c3ddc5a 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/romlib/gen_combined_bl1_romlib.sh b/lib/romlib/gen_combined_bl1_romlib.sh
index 1e3f73a..3941467 100755
--- a/lib/romlib/gen_combined_bl1_romlib.sh
+++ b/lib/romlib/gen_combined_bl1_romlib.sh
@@ -1,5 +1,5 @@
#!/bin/sh
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/romlib/init.s b/lib/romlib/init.s
index 7d97e4d..2bea15b 100644
--- a/lib/romlib/init.s
+++ b/lib/romlib/init.s
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
index 33710f5..44751a2 100644
--- a/lib/romlib/jmptbl.i
+++ b/lib/romlib/jmptbl.i
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/romlib/romlib.ld.S b/lib/romlib/romlib.ld.S
index d54a684..0d076b4 100644
--- a/lib/romlib/romlib.ld.S
+++ b/lib/romlib/romlib.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/semihosting/aarch32/semihosting_call.S b/lib/semihosting/aarch32/semihosting_call.S
index aced3d1..42d4718 100644
--- a/lib/semihosting/aarch32/semihosting_call.S
+++ b/lib/semihosting/aarch32/semihosting_call.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/semihosting/aarch64/semihosting_call.S b/lib/semihosting/aarch64/semihosting_call.S
index 97d2bca..6f60f3e 100644
--- a/lib/semihosting/aarch64/semihosting_call.S
+++ b/lib/semihosting/aarch64/semihosting_call.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c
index 163a82d..adc6b78 100644
--- a/lib/semihosting/semihosting.c
+++ b/lib/semihosting/semihosting.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/aarch32/asm_stack_protector.S b/lib/stack_protector/aarch32/asm_stack_protector.S
index 19b7525..0ffcf8a 100644
--- a/lib/stack_protector/aarch32/asm_stack_protector.S
+++ b/lib/stack_protector/aarch32/asm_stack_protector.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/aarch64/asm_stack_protector.S b/lib/stack_protector/aarch64/asm_stack_protector.S
index c2245d3..a002617 100644
--- a/lib/stack_protector/aarch64/asm_stack_protector.S
+++ b/lib/stack_protector/aarch64/asm_stack_protector.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/stack_protector.c b/lib/stack_protector/stack_protector.c
index 3ff74fc..d0f2400 100644
--- a/lib/stack_protector/stack_protector.c
+++ b/lib/stack_protector/stack_protector.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk
index b5aba15..4f13bc3 100644
--- a/lib/stack_protector/stack_protector.mk
+++ b/lib/stack_protector/stack_protector.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/utils/mem_region.c b/lib/utils/mem_region.c
index fec086b..e9f0a12 100644
--- a/lib/utils/mem_region.c
+++ b/lib/utils/mem_region.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S
index 3791f2d..0dda979 100644
--- a/lib/xlat_mpu/aarch64/enable_mpu.S
+++ b/lib/xlat_mpu/aarch64/enable_mpu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
index 5068eb8..5a2120b 100644
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/ro_xlat_mpu.mk b/lib/xlat_mpu/ro_xlat_mpu.mk
index 23f1d46..d3af3bd 100644
--- a/lib/xlat_mpu/ro_xlat_mpu.mk
+++ b/lib/xlat_mpu/ro_xlat_mpu.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021, ARM Limited. All rights reserved.
+# Copyright (c) 2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_mpu/xlat_mpu.mk b/lib/xlat_mpu/xlat_mpu.mk
index 041b91c..31bef04 100644
--- a/lib/xlat_mpu/xlat_mpu.mk
+++ b/lib/xlat_mpu/xlat_mpu.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_mpu/xlat_mpu_context.c b/lib/xlat_mpu/xlat_mpu_context.c
index 28c463b..783f21d 100644
--- a/lib/xlat_mpu/xlat_mpu_context.c
+++ b/lib/xlat_mpu/xlat_mpu_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/xlat_mpu_core.c b/lib/xlat_mpu/xlat_mpu_core.c
index 6b4b0c2..33f381d 100644
--- a/lib/xlat_mpu/xlat_mpu_core.c
+++ b/lib/xlat_mpu/xlat_mpu_core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/xlat_mpu_private.h b/lib/xlat_mpu/xlat_mpu_private.h
index e0e479d..14800e9 100644
--- a/lib/xlat_mpu/xlat_mpu_private.h
+++ b/lib/xlat_mpu/xlat_mpu_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c
index 5400875..dc5f956 100644
--- a/lib/xlat_mpu/xlat_mpu_utils.c
+++ b/lib/xlat_mpu/xlat_mpu_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index 4b01b9b..6d098be 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index dc167e3..4dbfc11 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index e2c8370..8b44df2 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h
index 82bc70c..cfecc39 100644
--- a/lib/xlat_tables/xlat_tables_private.h
+++ b/lib/xlat_tables/xlat_tables_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S
index f2fff36..22c2876 100644
--- a/lib/xlat_tables_v2/aarch32/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index a1a44af..920754b 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S
index 9f075e4..247a796 100644
--- a/lib/xlat_tables_v2/aarch64/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/xlat_tables_v2/ro_xlat_tables.mk b/lib/xlat_tables_v2/ro_xlat_tables.mk
index fb8a426..20bb015 100644
--- a/lib/xlat_tables_v2/ro_xlat_tables.mk
+++ b/lib/xlat_tables_v2/ro_xlat_tables.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_tables_v2/xlat_tables.mk b/lib/xlat_tables_v2/xlat_tables.mk
index bcc3e68..b4ad34b 100644
--- a/lib/xlat_tables_v2/xlat_tables.mk
+++ b/lib/xlat_tables_v2/xlat_tables.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index 95dae88..2fbbc78 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/zlib/tf_gunzip.c b/lib/zlib/tf_gunzip.c
index 3ac80bc..8b8d14d 100644
--- a/lib/zlib/tf_gunzip.c
+++ b/lib/zlib/tf_gunzip.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/lib/zlib/zlib.mk b/lib/zlib/zlib.mk
index 98d4efa..a8937a7 100644
--- a/lib/zlib/zlib.mk
+++ b/lib/zlib/zlib.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 3bce3a5..a5c93a6 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -334,10 +334,10 @@
$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES))
-$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS))
-$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
-$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS))
+$(eval BL_DEFINES := IMAGE_$(call uppercase,$(3)) $($(call uppercase,$(3))_DEFINES) $(PLAT_BL_COMMON_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
+$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS) $(PLAT_BL_COMMON_CFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
$$(ECHO) " CC $$<"
@@ -357,10 +357,10 @@
$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES))
-$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS))
-$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
-$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS))
+$(eval BL_DEFINES := IMAGE_$(call uppercase,$(3)) $($(call uppercase,$(3))_DEFINES) $(PLAT_BL_COMMON_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
+$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS) $(PLAT_BL_COMMON_ASFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
$$(ECHO) " AS $$<"
@@ -379,9 +379,9 @@
$(eval DEP := $(1).d)
-$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES))
-$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS))
-$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
+$(eval BL_DEFINES := IMAGE_$(call uppercase,$(3)) $($(call uppercase,$(3))_DEFINES) $(PLAT_BL_COMMON_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
$$(ECHO) " PP $$<"
@@ -504,7 +504,7 @@
define MAKE_BL
$(eval BUILD_DIR := ${BUILD_PLAT}/$(1))
$(eval BL_SOURCES := $($(call uppercase,$(1))_SOURCES))
- $(eval SOURCES := $(BL_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES))
+ $(eval SOURCES := $(sort $(BL_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES)))
$(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
$(eval MAPFILE := $(call IMG_MAPFILE,$(1)))
$(eval ELF := $(call IMG_ELF,$(1)))
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index a065039..964e0f9 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -508,3 +508,6 @@
# Check platform if cache management operations should be performed.
# Disabled by default.
CONDITIONAL_CMO := 0
+
+# By default, disable SPMD Logical partitions
+ENABLE_SPMD_LP := 0
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
index 41dc563..6a0e967 100644
--- a/plat/allwinner/common/sunxi_scpi_pm.c
+++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -125,6 +125,32 @@
psci_power_down_wfi();
}
+static int sunxi_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+ uint32_t ret;
+
+ if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET))
+ return PSCI_E_NOT_SUPPORTED;
+
+ gicv2_cpuif_disable();
+
+ /* Send the system reset request to the SCP. */
+ ret = scpi_sys_power_state(scpi_system_reset);
+ if (ret != SCP_OK) {
+ ERROR("PSCI: SCPI %s failed: %d\n", "reset", ret);
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ psci_power_down_wfi();
+
+ /*
+ * Should not reach here.
+ * However sunxi_system_reset2 has to return some value
+ * according to PSCI v1.1 spec.
+ */
+ return PSCI_E_SUCCESS;
+}
+
static int sunxi_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
@@ -177,6 +203,7 @@
.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish,
.system_off = sunxi_system_off,
.system_reset = sunxi_system_reset,
+ .system_reset2 = sunxi_system_reset2,
.validate_power_state = sunxi_validate_power_state,
.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state,
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 6fcf080..3ed7a63 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -98,6 +98,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
MULTI_CONSOLE_API := 1
ARM_DISABLE_TRUSTED_WDOG := 1
diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk
index 75833f6..d6d3bef 100644
--- a/plat/arm/board/corstone700/platform.mk
+++ b/plat/arm/board/corstone700/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
index b8431c5..dc95ba1 100644
--- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/measured_boot/event_log/event_log.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <plat/arm/common/plat_arm.h>
+#include <tools_share/zero_oid.h>
/* Event Log data */
static uint8_t event_log[PLAT_ARM_EVENT_LOG_MAX_SIZE];
@@ -31,18 +32,21 @@
.slot = U(6),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = TB_FW_CONFIG_ID,
.slot = U(7),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = BL2_IMAGE_ID,
.slot = U(8),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL2_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 564118e..349e064 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -9,7 +9,11 @@
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/measured_boot/event_log/event_log.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#if defined(ARM_COT_cca)
+#include <tools_share/cca_oid.h>
+#else
#include <tools_share/tbbr_oid.h>
+#endif /* ARM_COT_cca */
#include <fvp_critical_data.h>
#include <plat/arm/common/plat_arm.h>
@@ -62,25 +66,31 @@
.slot = U(9),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL31_STRING,
+ .pk_oid = BL31_IMAGE_KEY_OID,
.lock_measurement = true },
{
.id = HW_CONFIG_ID,
.slot = U(10),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_HW_CONFIG_STRING,
+ .pk_oid = HW_CONFIG_KEY_OID,
.lock_measurement = true },
{
.id = SOC_FW_CONFIG_ID,
.slot = U(11),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING,
+ .pk_oid = SOC_FW_CONFIG_KEY_OID,
.lock_measurement = true },
+#if ENABLE_RME
{
.id = RMM_IMAGE_ID,
.slot = U(12),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_RMM_STRING,
+ .pk_oid = RMM_IMAGE_KEY_OID,
.lock_measurement = true },
+#endif /* ENABLE_RME */
{
.id = RSS_MBOOT_INVALID_ID }
};
diff --git a/plat/arm/board/fvp/fvp_common_measured_boot.c b/plat/arm/board/fvp/fvp_common_measured_boot.c
index 7419e5e..0c1d5e7 100644
--- a/plat/arm/board/fvp/fvp_common_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_common_measured_boot.c
@@ -45,3 +45,10 @@
return rc;
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return rss_mboot_set_signer_id(fvp_rss_mboot_metadata, pk_oid, pk_ptr,
+ pk_len);
+}
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk
index 944571d..b8fa4ea 100644
--- a/plat/arm/board/fvp/fvp_cpu_errata.mk
+++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -30,6 +30,7 @@
CORTEX_A77_H_INC := 1
CORTEX_A78_H_INC := 1
NEOVERSE_N1_H_INC := 1
+NEOVERSE_N2_H_INC := 1
NEOVERSE_V1_H_INC := 1
CORTEX_A78_AE_H_INC := 1
CORTEX_A510_H_INC := 1
@@ -41,6 +42,7 @@
$(eval $(call add_define, CORTEX_A77_H_INC))
$(eval $(call add_define, CORTEX_A78_H_INC))
$(eval $(call add_define, NEOVERSE_N1_H_INC))
+$(eval $(call add_define, NEOVERSE_N2_H_INC))
$(eval $(call add_define, NEOVERSE_V1_H_INC))
$(eval $(call add_define, CORTEX_A78_AE_H_INC))
$(eval $(call add_define, CORTEX_A510_H_INC))
diff --git a/plat/arm/board/fvp/fvp_spmd_logical_sp.c b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
new file mode 100644
index 0000000..37b4466
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <services/el3_spmd_logical_sp.h>
+#include <services/ffa_svc.h>
+#include <smccc_helpers.h>
+
+#define SPMD_LP_PARTITION_ID SPMD_LP_ID_START
+#define SPMD_LP_UUID {0xe98e43ad, 0xb7db524f, 0x47a3bf57, 0x1588f4e3}
+
+/* SPMD Logical SP currently only supports sending direct message. */
+#define SPMD_PARTITION_PROPERTIES FFA_PARTITION_DIRECT_REQ_SEND
+
+#define SPMD_LP_MAX_SUPPORTED_SP 10
+static void fvp_get_partition_info(void)
+{
+ struct ffa_value ret = { 0 };
+ uint32_t target_uuid[4] = { 0 };
+ static struct ffa_partition_info_v1_1
+ part_info[SPMD_LP_MAX_SUPPORTED_SP] = { 0 };
+
+ uint16_t num_partitions = 0;
+
+ if (!spmd_el3_invoke_partition_info_get(target_uuid, 0, 0, &ret)) {
+ panic();
+ }
+
+ if (is_ffa_error(&ret)) {
+ panic();
+ }
+
+ num_partitions = ffa_partition_info_regs_get_last_idx(ret) + 1;
+ if (num_partitions > SPMD_LP_MAX_SUPPORTED_SP) {
+ panic();
+ }
+
+ INFO("Number of secure partitions = %d\n", num_partitions);
+
+ for (uint16_t i = 0; i < num_partitions; i++) {
+ INFO("***Start Partition***\n");
+ if (!ffa_partition_info_regs_get_part_info(ret, i, &part_info[i]))
+ panic();
+ INFO("\tPartition ID: 0x%x\n", part_info[i].ep_id);
+ INFO("\tvCPU count:0x%x\n", part_info[i].execution_ctx_count);
+ INFO("\tProperties: 0x%x\n", part_info[i].properties);
+ INFO("\tUUID: 0x%x 0x%x 0x%x 0x%x\n", part_info[i].uuid[0],
+ part_info[i].uuid[1], part_info[i].uuid[2],
+ part_info[i].uuid[3]);
+ INFO("***End Partition***\n");
+ }
+
+}
+
+static int32_t fvp_spmd_logical_partition_init(void)
+{
+ INFO("FVP SPMD LSP: Init function called.\n");
+
+ fvp_get_partition_info();
+ return 0;
+}
+
+/*
+ * Platform specific SMC handler used to translate SIP SMCs or other platform
+ * specific SMCs into FF-A direct messages.
+ */
+uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ struct ffa_value retval = { 0 };
+ uint64_t send_recv_id = SPMD_LP_PARTITION_ID << 16 | 0x8001;
+
+ /*
+ * Forward the SMC as direct request.
+ */
+ if (!spmd_el3_ffa_msg_direct_req(send_recv_id, x2, x3, x4, handle, &retval)) {
+ panic();
+ }
+
+ SMC_RET8(handle, retval.func, retval.arg1, retval.arg2, retval.arg3,
+ retval.arg4, retval.arg5, retval.arg6, retval.arg7);
+}
+
+/* Register SPMD logical partition */
+DECLARE_SPMD_LOGICAL_PARTITION(
+ fvp_spmd_logical_partition,
+ fvp_spmd_logical_partition_init,/* Init Function */
+ SPMD_LP_PARTITION_ID, /* FF-A Partition ID */
+ SPMD_LP_UUID, /* UUID */
+ SPMD_PARTITION_PROPERTIES /* Partition Properties. */
+);
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 7df150e..4803f35 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -213,7 +213,9 @@
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/cortex_x2.S
+ lib/cpus/aarch64/cortex_x2.S \
+ lib/cpus/aarch64/cortex_gelas.S \
+ lib/cpus/aarch64/nevis.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
@@ -222,7 +224,8 @@
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
- lib/cpus/aarch32/cortex_a57.S
+ lib/cpus/aarch32/cortex_a57.S \
+ lib/cpus/aarch32/cortex_a53.S
endif
BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
@@ -405,10 +408,6 @@
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
endif
-ifeq (${ARCH},aarch32)
- NEED_BL32 := yes
-endif
-
# Enable the dynamic translation tables library.
ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
ifeq (${ARCH},aarch32)
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index f7eace8..79cf356 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -96,6 +96,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
# Modification of arm_common.mk
# Process ARM_DISABLE_TRUSTED_WDOG flag
diff --git a/plat/arm/board/juno/cert_create_tbbr.mk b/plat/arm/board/juno/cert_create_tbbr.mk
index c092fe0..4d133b2 100644
--- a/plat/arm/board/juno/cert_create_tbbr.mk
+++ b/plat/arm/board/juno/cert_create_tbbr.mk
@@ -7,7 +7,7 @@
PLAT_DEF_OID := 1
ifeq (${PLAT_DEF_OID},1)
- ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ ifeq (${ETHOSN_NPU_DRIVER},1)
$(eval $(call add_define, PLAT_DEF_OID))
$(eval $(call add_define, PDEF_CERTS))
$(eval $(call add_define, PDEF_EXTS))
diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
index 986299e..ec72160 100644
--- a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
@@ -51,10 +51,10 @@
tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
plat_sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
-#if ARM_ETHOSN_NPU_TZMP1
- arm_ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
- arm_ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
- arm_ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
+#if ETHOSN_NPU_TZMP1
+ ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
+ ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
+ ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
#endif
};
};
diff --git a/plat/arm/board/juno/fip/plat_def_fip_uuid.h b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
index 0f0d11d..46adf24 100644
--- a/plat/arm/board/juno/fip/plat_def_fip_uuid.h
+++ b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
@@ -7,8 +7,8 @@
#ifndef PLAT_DEF_FIP_UUID_H
#define PLAT_DEF_FIP_UUID_H
-#ifdef ARM_ETHOSN_NPU_TZMP1
+#ifdef ETHOSN_NPU_TZMP1
#include <drivers/arm/ethosn_fip.h>
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* PLAT_DEF_FIP_UUID_H */
diff --git a/plat/arm/board/juno/fip/plat_def_uuid_config.c b/plat/arm/board/juno/fip/plat_def_uuid_config.c
index 8133927..705a8ca 100644
--- a/plat/arm/board/juno/fip/plat_def_uuid_config.c
+++ b/plat/arm/board/juno/fip/plat_def_uuid_config.c
@@ -12,11 +12,11 @@
#include "plat_def_fip_uuid.h"
toc_entry_t plat_def_toc_entries[] = {
-#ifdef ARM_ETHOSN_NPU_TZMP1
+#ifdef ETHOSN_NPU_TZMP1
ETHOSN_FW_KEY_CERTIFICATE_DEF,
ETHOSN_FW_CONTENT_CERTIFICATE_DEF,
ETHOSN_FW_DEF,
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
{
.name = NULL,
.uuid = { { 0 } },
diff --git a/plat/arm/board/juno/include/plat_tbbr_img_def.h b/plat/arm/board/juno/include/plat_tbbr_img_def.h
index 3e17ed3..5fbeb4e 100644
--- a/plat/arm/board/juno/include/plat_tbbr_img_def.h
+++ b/plat/arm/board/juno/include/plat_tbbr_img_def.h
@@ -7,12 +7,12 @@
#ifndef JUNO_IMG_DEF_H
#define JUNO_IMG_DEF_H
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
/* Arm(R) Ethos(TM)-N NPU images */
-#define ARM_ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1)
-#define ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2)
-#define ARM_ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3)
+#define ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1)
+#define ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2)
+#define ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3)
#define MAX_NUMBER_IDS U(MAX_IMG_IDS_WITH_SPMDS + 4)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* JUNO_IMG_DEF_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 47258cb..aa96038 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -327,15 +327,15 @@
/* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */
#ifdef JUNO_ETHOSN_TZMP1
-#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
-#define ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
-#define ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
+#define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT
+#define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
+#define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
-#define ARM_ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
-#define ARM_ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
+#define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
+#define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
-#define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
-#define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \
+#define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
+#define ETHOSN_NPU_FW_IMAGE_LIMIT \
(JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE)
#endif
diff --git a/plat/arm/board/juno/juno_tbbr_cot_bl2.c b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
index d48d2e6..8930dbb 100644
--- a/plat/arm/board/juno/juno_tbbr_cot_bl2.c
+++ b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
@@ -32,9 +32,9 @@
#if defined(SPD_spmd)
static unsigned char sp_pkg_hash_buf[MAX_SP_IDS][HASH_DER_LEN];
#endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static unsigned char npu_fw_image_hash_buf[HASH_DER_LEN];
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
@@ -87,12 +87,12 @@
static auth_param_type_desc_t sp_pkg8_hash = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_HASH, SP_PKG8_HASH_OID);
#endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static auth_param_type_desc_t npu_fw_cert_pk = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_PUB_KEY, ETHOSN_NPU_FW_CONTENT_CERT_PK_OID);
static auth_param_type_desc_t npu_fw_image_hash = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_HASH, ETHOSN_NPU_FW_BINARY_OID);
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
/*
* Trusted key certificate
@@ -662,9 +662,9 @@
DEFINE_SIP_SP_PKG(8);
#endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
static const auth_img_desc_t npu_fw_key_cert = {
- .img_id = ARM_ETHOSN_NPU_FW_KEY_CERT_ID,
+ .img_id = ETHOSN_NPU_FW_KEY_CERT_ID,
.img_type = IMG_CERT,
.parent = &trusted_key_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -697,7 +697,7 @@
};
static const auth_img_desc_t npu_fw_content_cert = {
- .img_id = ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID,
+ .img_id = ETHOSN_NPU_FW_CONTENT_CERT_ID,
.img_type = IMG_CERT,
.parent = &npu_fw_key_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -730,7 +730,7 @@
};
static const auth_img_desc_t npu_fw_image = {
- .img_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+ .img_id = ETHOSN_NPU_FW_IMAGE_ID,
.img_type = IMG_RAW,
.parent = &npu_fw_content_cert,
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -743,7 +743,7 @@
}
}
};
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
static const auth_img_desc_t * const cot_desc[] = {
@@ -778,11 +778,11 @@
[SP_PKG7_ID] = &sp_pkg7,
[SP_PKG8_ID] = &sp_pkg8,
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert,
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert,
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image,
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert,
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert,
+ [ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image,
+#endif /* ETHOSN_NPU_TZMP1 */
};
/* Register the CoT in the authentication module */
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index a4e6407..a00bf26 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -43,8 +43,8 @@
JUNO_TZMP1 := 0
$(eval $(call assert_boolean,JUNO_TZMP1))
ifeq (${JUNO_TZMP1}, 1)
- ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
- $(error JUNO_TZMP1 cannot be used together with ARM_ETHOSN_NPU_TZMP1)
+ ifeq (${ETHOSN_NPU_TZMP1},1)
+ $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1)
else
$(eval $(call add_define,JUNO_TZMP1))
endif
@@ -63,6 +63,10 @@
ifneq (${ARCH}, aarch32)
override BL32_SOURCES =
endif
+else
+ ifeq (${ARCH}, aarch32)
+ $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32)
+ endif
endif
ifeq (${ARCH},aarch64)
@@ -207,6 +211,7 @@
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
+include drivers/arm/ethosn/ethosn_npu.mk
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 9ebca23..1506714 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -72,7 +72,8 @@
ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \
${CSS_ENT_BASE}/ras/sgi_ras_common.c \
- ${CSS_ENT_BASE}/ras/sgi_ras_sram.c
+ ${CSS_ENT_BASE}/ras/sgi_ras_sram.c \
+ ${CSS_ENT_BASE}/ras/sgi_ras_cpu.c
endif
# Add the FDT_SOURCES and options for Dynamic Config
diff --git a/plat/arm/board/rdn2/rdn2_ras.c b/plat/arm/board/rdn2/rdn2_ras.c
index c1e5ab6..3aed58e 100644
--- a/plat/arm/board/rdn2/rdn2_ras.c
+++ b/plat/arm/board/rdn2/rdn2_ras.c
@@ -14,6 +14,9 @@
/* Non Secure base RAM ECC UE interrupt */
{SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI},
+
+ /* CPU 1-bit ECC CE error interrupt */
+ {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI}
};
/* RAS error record list definition, used by the common RAS framework. */
@@ -21,11 +24,15 @@
/* Base element RAM Non-secure error record. */
ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL,
&sgi_ras_sram_intr_handler, 0),
+ ERR_RECORD_SYSREG_V1(0, 1, NULL, &sgi_ras_cpu_intr_handler, 0),
};
/* RAS error interrupt list definition, used by the common RAS framework. */
struct ras_interrupt plat_ras_interrupts[] = {
{
+ .intr_number = PLAT_CORE_FAULT_IRQ,
+ .err_record = &plat_err_records[1],
+ }, {
.intr_number = NS_RAM_ECC_CE_INT,
.err_record = &plat_err_records[0],
}, {
diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c
index 6d4bb07..6821a6a 100644
--- a/plat/arm/board/tc/tc_bl1_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl1_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/arm/rss_comms.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <lib/psa/measured_boot.h>
+#include <tools_share/zero_oid.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
@@ -22,18 +23,21 @@
.slot = U(6),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = TB_FW_CONFIG_ID,
.slot = U(7),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
.id = BL2_IMAGE_ID,
.slot = U(8),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL2_STRING,
+ .pk_oid = ZERO_OID,
.lock_measurement = true },
{
diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c
index 9039853..4b79170 100644
--- a/plat/arm/board/tc/tc_bl2_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl2_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/arm/rss_comms.h>
#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <lib/psa/measured_boot.h>
+#include <tools_share/tbbr_oid.h>
#include <plat/common/common_def.h>
#include <platform_def.h>
@@ -22,18 +23,21 @@
.slot = U(9),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_BL31_STRING,
+ .pk_oid = BL31_IMAGE_KEY_OID,
.lock_measurement = true },
{
.id = HW_CONFIG_ID,
.slot = U(10),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_HW_CONFIG_STRING,
+ .pk_oid = HW_CONFIG_KEY_OID,
.lock_measurement = true },
{
.id = SOC_FW_CONFIG_ID,
.slot = U(11),
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING,
+ .pk_oid = SOC_FW_CONFIG_KEY_OID,
.lock_measurement = true },
{
.id = RSS_MBOOT_INVALID_ID }
diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c
index eddcc81..925a411 100644
--- a/plat/arm/board/tc/tc_common_measured_boot.c
+++ b/plat/arm/board/tc/tc_common_measured_boot.c
@@ -28,3 +28,9 @@
return err;
}
+
+int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+{
+ return rss_mboot_set_signer_id(tc_rss_mboot_metadata, pk_oid, pk_ptr,
+ pk_len);
+}
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
index e512192..9a65e7c 100644
--- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -223,17 +223,17 @@
},
#endif /* EL3_PAYLOAD_BASE */
-# if ARM_ETHOSN_NPU_TZMP1
+# if ETHOSN_NPU_TZMP1
{
- .image_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+ .image_id = ETHOSN_NPU_FW_IMAGE_ID,
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
- .image_info.image_base = ARM_ETHOSN_NPU_FW_IMAGE_BASE,
- .image_info.image_max_size = ARM_ETHOSN_NPU_FW_IMAGE_LIMIT -
- ARM_ETHOSN_NPU_FW_IMAGE_BASE,
+ .image_info.image_base = ETHOSN_NPU_FW_IMAGE_BASE,
+ .image_info.image_max_size = ETHOSN_NPU_FW_IMAGE_LIMIT -
+ ETHOSN_NPU_FW_IMAGE_BASE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
-# endif
+#endif /* ETHOSN_NPU_TZMP1 */
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 647a9d9..41d1b66 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -6,6 +6,12 @@
include common/fdt_wrappers.mk
+ifeq (${ARCH},aarch32)
+ ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+ endif
+endif
+
ifeq (${ARCH}, aarch64)
# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
# DRAM (if available) or the TZC secured area of DRAM.
@@ -114,48 +120,6 @@
endif
endif
-# Arm(R) Ethos(TM)-N NPU SiP service
-ARM_ETHOSN_NPU_DRIVER := 0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
-$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
-
-# Arm(R) Ethos(TM)-N NPU TZMP1
-ARM_ETHOSN_NPU_TZMP1 := 0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_TZMP1))
-$(eval $(call add_define,ARM_ETHOSN_NPU_TZMP1))
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
- ifeq (${ARM_ETHOSN_NPU_DRIVER},0)
- $(error ARM_ETHOSN_NPU_TZMP1 is only available if ARM_ETHOSN_NPU_DRIVER=1)
- endif
- ifeq (${PLAT},juno)
- $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
- else
- $(error ARM_ETHOSN_NPU_TZMP1 only supported on Juno platform, not ${PLAT})
- endif
-
- ifeq (${TRUSTED_BOARD_BOOT},0)
- # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
- # tampered with, which is required to protect the confidentiality of protected
- # inference data.
- $(error ARM_ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
- endif
-
- # We need the FW certificate and key certificate
- $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
- $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
- # Needed for our OIDs to be available in tbbr_cot_bl2.c
- $(eval $(call add_define, PLAT_DEF_OID))
- PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
- PLAT_INCLUDES += -Iinclude/drivers/arm/
-
- # We need the firmware to be built into the FIP
- $(eval $(call TOOL_ADD_IMG,ARM_ETHOSN_NPU_FW,--npu-fw))
-
- # Needed so that UUIDs from the FIP are available in BL2
- $(eval $(call add_define,PLAT_DEF_FIP_UUID))
- PLAT_INCLUDES += -I${PLAT_DIR}fip
-endif # ARM_ETHOSN_NPU_TZMP1
-
# Use an implementation of SHA-256 with a smaller memory footprint but reduced
# speed.
$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@@ -348,18 +312,18 @@
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
-ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
+ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
ARM_SVC_HANDLER_SRCS :=
ifeq (${ENABLE_PMF},1)
ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c
endif
-ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ifeq (${ETHOSN_NPU_DRIVER},1)
ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \
drivers/delay_timer/delay_timer.c \
drivers/arm/ethosn/ethosn_smc.c
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
+ifeq (${ETHOSN_NPU_TZMP1},1)
ARM_SVC_HANDLER_SRCS += drivers/arm/ethosn/ethosn_big_fw.c
endif
endif
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 1c95afb..8c16877 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -40,7 +40,11 @@
static const interrupt_prop_t arm_interrupt_props[] = {
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
- PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
+ PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0),
+#if RAS_FFH_SUPPORT
+ INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0,
+ GIC_INTR_CFG_LEVEL)
+#endif
};
/*
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index af8a02f..352d477 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -13,6 +13,9 @@
#include <lib/pmf/pmf.h>
#include <plat/arm/common/arm_sip_svc.h>
#include <plat/arm/common/plat_arm.h>
+#if ENABLE_SPMD_LP
+#include <services/el3_spmd_logical_sp.h>
+#endif
#include <tools_share/uuid.h>
/* ARM SiP Service UUID */
@@ -34,13 +37,13 @@
#endif /* USE_DEBUGFS */
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
if (ethosn_smc_setup() != 0) {
return 1;
}
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
return 0;
}
@@ -81,14 +84,14 @@
#endif /* USE_DEBUGFS */
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
if (is_ethosn_fid(smc_fid)) {
return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
switch (smc_fid) {
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
@@ -114,10 +117,10 @@
/* PMF calls */
call_count += PMF_NUM_SMC_CALLS;
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
/* ETHOSN calls */
call_count += ETHOSN_NUM_SMC_CALLS;
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
/* State switch call */
call_count += 1;
@@ -133,8 +136,13 @@
SMC_RET2(handle, ARM_SIP_SVC_VERSION_MAJOR, ARM_SIP_SVC_VERSION_MINOR);
default:
+#if ENABLE_SPMD_LP
+ return plat_spmd_logical_sp_smc_handler(smc_fid, x1, x2, x3, x4,
+ cookie, handle, flags);
+#else
WARN("Unimplemented ARM SiP Service Call: 0x%x \n", smc_fid);
SMC_RET1(handle, SMC_UNK);
+#endif
}
}
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 743cc90..27acc3a 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -68,9 +68,9 @@
[TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
[NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
[RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE},
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
@@ -91,10 +91,10 @@
[SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
[PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -198,13 +198,13 @@
(uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
open_fip
},
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_IMAGE_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_IMAGE_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID],
open_fip
},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
@@ -285,18 +285,18 @@
open_fip
},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_KEY_CERT_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID],
open_fip
},
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID],
open_fip
},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -305,11 +305,11 @@
#define FCONF_ARM_IO_UUID_NUM_BASE U(10)
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU U(1)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU U(0)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
#define FCONF_ARM_IO_UUID_NUM_TBB U(12)
@@ -323,11 +323,11 @@
#define FCONF_ARM_IO_UUID_NUM_SPD U(0)
#endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */
-#if TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1
+#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0)
-#endif /* TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 */
+#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */
#define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \
FCONF_ARM_IO_UUID_NUM_NPU + \
@@ -355,9 +355,9 @@
{SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
{TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"},
{NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"},
-#if ARM_ETHOSN_NPU_TZMP1
- {ARM_ETHOSN_NPU_FW_IMAGE_ID, "arm_ethosn_npu_fw_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ {ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
{CCA_CONTENT_CERT_ID, "cca_cert_uuid"},
{CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"},
@@ -375,10 +375,10 @@
{SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
{PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- {ARM_ETHOSN_NPU_FW_KEY_CERT_ID, "arm_ethosn_npu_fw_key_cert_uuid"},
- {ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, "arm_ethosn_npu_fw_content_cert_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ {ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"},
+ {ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* TRUSTED_BOARD_BOOT */
};
diff --git a/plat/arm/css/sgi/include/sgi_ras.h b/plat/arm/css/sgi/include/sgi_ras.h
index 24bbfa7..d311807 100644
--- a/plat/arm/css/sgi/include/sgi_ras.h
+++ b/plat/arm/css/sgi/include/sgi_ras.h
@@ -60,4 +60,9 @@
int probe_data,
const struct err_handler_data *const data);
+/* CPU RAS interrupt handler */
+int sgi_ras_cpu_intr_handler(const struct err_record_info *err_rec,
+ int probe_data,
+ const struct err_handler_data *const data);
+
#endif /* SGI_RAS_H */
diff --git a/plat/arm/css/sgi/ras/sgi_ras_cpu.c b/plat/arm/css/sgi/ras/sgi_ras_cpu.c
new file mode 100644
index 0000000..5e77dbb
--- /dev/null
+++ b/plat/arm/css/sgi/ras/sgi_ras_cpu.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <bl31/interrupt_mgmt.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/extensions/ras.h>
+#include <plat/common/platform.h>
+#include <services/sdei.h>
+#include <services/spm_mm_svc.h>
+
+#include <sgi_ras.h>
+
+#define CPU_CONTEXT_REG_GPR_ARR_SIZE 32
+#define CPU_CONTEXT_REG_EL1_ARR_SIZE 17
+#define CPU_CONTEXT_REG_EL2_ARR_SIZE 16
+#define CPU_CONTEXT_REG_EL3_ARR_SIZE 10
+
+/*
+ * MM Communicate message header GUID to indicate the payload is intended for
+ * CPU MM driver.
+ */
+struct efi_guid cpu_ecc_event_guid = {
+ 0x2c1b3bfc, 0x42cd, 0x4a66,
+ {0xac, 0xd1, 0xa4, 0xd1, 0x63, 0xe9, 0x90, 0xf6}
+ };
+
+/*
+ * CPU error information data structure communicated as part of MM
+ * Communication data payload.
+ */
+typedef struct {
+ uint64_t ErrStatus;
+ uint64_t ErrMisc0;
+ uint64_t ErrAddr;
+ uint64_t SecurityState;
+ uint64_t ErrCtxGpr[CPU_CONTEXT_REG_GPR_ARR_SIZE];
+ uint64_t ErrCtxEl1Reg[CPU_CONTEXT_REG_EL1_ARR_SIZE];
+ uint64_t ErrCtxEl2Reg[CPU_CONTEXT_REG_EL2_ARR_SIZE];
+ uint64_t ErrCtxEl3Reg[CPU_CONTEXT_REG_EL3_ARR_SIZE];
+} cpu_err_info;
+
+/*
+ * Reads the CPU context and error information from the relevant registers and
+ * populates the CPU error information data structure.
+ */
+static void populate_cpu_err_data(cpu_err_info *cpu_info,
+ uint64_t security_state)
+{
+ void *ctx;
+
+ ctx = cm_get_context(security_state);
+
+ cpu_info->ErrStatus = read_erxstatus_el1();
+ cpu_info->ErrMisc0 = read_erxmisc0_el1();
+ cpu_info->ErrAddr = read_erxaddr_el1();
+ cpu_info->SecurityState = security_state;
+
+ /* populate CPU EL1 context information. */
+ cpu_info->ErrCtxEl1Reg[0] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_ELR_EL1);
+ cpu_info->ErrCtxEl1Reg[1] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_ESR_EL1);
+ cpu_info->ErrCtxEl1Reg[2] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_FAR_EL1);
+ cpu_info->ErrCtxEl1Reg[3] = read_isr_el1();
+ cpu_info->ErrCtxEl1Reg[4] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_MAIR_EL1);
+ cpu_info->ErrCtxEl1Reg[5] = read_midr_el1();
+ cpu_info->ErrCtxEl1Reg[6] = read_mpidr_el1();
+ cpu_info->ErrCtxEl1Reg[7] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SCTLR_EL1);
+ cpu_info->ErrCtxEl1Reg[8] = read_ctx_reg(get_gpregs_ctx(ctx),
+ CTX_GPREG_SP_EL0);
+ cpu_info->ErrCtxEl1Reg[9] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SP_EL1);
+ cpu_info->ErrCtxEl1Reg[10] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SPSR_EL1);
+ cpu_info->ErrCtxEl1Reg[11] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TCR_EL1);
+ cpu_info->ErrCtxEl1Reg[12] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TPIDR_EL0);
+ cpu_info->ErrCtxEl1Reg[13] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TPIDR_EL1);
+ cpu_info->ErrCtxEl1Reg[14] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TPIDRRO_EL0);
+ cpu_info->ErrCtxEl1Reg[15] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TTBR0_EL1);
+ cpu_info->ErrCtxEl1Reg[16] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TTBR1_EL1);
+
+#if CTX_INCLUDE_EL2_REGS
+ cpu_info->ErrCtxEl2Reg[0] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_ELR_EL2);
+ cpu_info->ErrCtxEl2Reg[1] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_ESR_EL2);
+ cpu_info->ErrCtxEl2Reg[2] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_FAR_EL2);
+ cpu_info->ErrCtxEl2Reg[3] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_HACR_EL2);
+ cpu_info->ErrCtxEl2Reg[4] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_HCR_EL2);
+ cpu_info->ErrCtxEl2Reg[5] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_HPFAR_EL2);
+ cpu_info->ErrCtxEl2Reg[6] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_MAIR_EL2);
+ cpu_info->ErrCtxEl2Reg[7] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_SCTLR_EL2);
+ cpu_info->ErrCtxEl2Reg[8] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_SP_EL2);
+ cpu_info->ErrCtxEl2Reg[9] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_SPSR_EL2);
+ cpu_info->ErrCtxEl2Reg[10] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_TCR_EL2);
+ cpu_info->ErrCtxEl2Reg[11] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_TPIDR_EL2);
+ cpu_info->ErrCtxEl2Reg[12] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_TTBR0_EL2);
+ cpu_info->ErrCtxEl2Reg[13] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_VTCR_EL2);
+ cpu_info->ErrCtxEl2Reg[14] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_VTTBR_EL2);
+ cpu_info->ErrCtxEl2Reg[15] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_ESR_EL2);
+#endif
+
+ cpu_info->ErrCtxEl3Reg[0] = read_ctx_reg(get_el3state_ctx(ctx),
+ CTX_ELR_EL3);
+ cpu_info->ErrCtxEl3Reg[1] = read_ctx_reg(get_el3state_ctx(ctx),
+ CTX_ESR_EL3);
+ cpu_info->ErrCtxEl3Reg[2] = read_far_el3();
+ cpu_info->ErrCtxEl3Reg[4] = read_mair_el3();
+ cpu_info->ErrCtxEl3Reg[5] = read_sctlr_el3();
+ cpu_info->ErrCtxEl3Reg[6] = 0; /* sp_el3 */
+ cpu_info->ErrCtxEl3Reg[7] = read_tcr_el3();
+ cpu_info->ErrCtxEl3Reg[8] = read_tpidr_el3();
+ cpu_info->ErrCtxEl3Reg[9] = read_ttbr0_el3();
+}
+
+/* CPU RAS interrupt handler */
+int sgi_ras_cpu_intr_handler(const struct err_record_info *err_rec,
+ int probe_data,
+ const struct err_handler_data *const data)
+{
+ struct sgi_ras_ev_map *ras_map;
+ mm_communicate_header_t *header;
+ cpu_err_info cpu_info = {0};
+ uint64_t clear_status;
+ uint32_t intr;
+ int ret;
+
+ cm_el1_sysregs_context_save(NON_SECURE);
+ intr = data->interrupt;
+
+ INFO("[CPU RAS] CPU intr received = %d on cpu_id = %d\n",
+ intr, plat_my_core_pos());
+
+ INFO("[CPU RAS] ERXMISC0_EL1 = 0x%lx\n", read_erxmisc0_el1());
+ INFO("[CPU RAS] ERXSTATUS_EL1 = 0x%lx\n", read_erxstatus_el1());
+ INFO("[CPU RAS] ERXADDR_EL1 = 0x%lx\n", read_erxaddr_el1());
+
+ /* Populate CPU Error Source Information. */
+ populate_cpu_err_data(&cpu_info, get_interrupt_src_ss(data->flags));
+
+ /* Clear the interrupt. */
+ clear_status = read_erxstatus_el1();
+ write_erxstatus_el1(clear_status);
+ plat_ic_end_of_interrupt(intr);
+
+ header = (void *) PLAT_SPM_BUF_BASE;
+ memset(header, 0, sizeof(*header));
+ memcpy(&header->data, &cpu_info, sizeof(cpu_info));
+ header->message_len = sizeof(cpu_info);
+ memcpy(&header->header_guid, (void *) &cpu_ecc_event_guid,
+ sizeof(struct efi_guid));
+
+ spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
+ plat_my_core_pos());
+
+ /*
+ * Find if this is a RAS interrupt. There must be an event against
+ * this interrupt
+ */
+ ras_map = sgi_find_ras_event_map_by_intr(intr);
+ if (ras_map == NULL) {
+ ERROR("SGI: RAS error info for interrupt id: %d not found\n",
+ intr);
+ return -1;
+ }
+
+ /* Dispatch the event to the SDEI client */
+ ret = sdei_dispatch_event(ras_map->sdei_ev_num);
+ if (ret != 0) {
+ /*
+ * sdei_dispatch_event() may return failing result in some
+ * cases, for example kernel may not have registered a handler
+ * or RAS event may happen early during boot. We restore the NS
+ * context when sdei_dispatch_event() returns failing result.
+ */
+ ERROR("SDEI dispatch failed: %d", ret);
+ cm_el1_sysregs_context_restore(NON_SECURE);
+ cm_set_next_eret_context(NON_SECURE);
+ }
+
+ return ret;
+}
diff --git a/plat/aspeed/ast2700/include/platform_def.h b/plat/aspeed/ast2700/include/platform_def.h
index 3f2468f..8be26c3 100644
--- a/plat/aspeed/ast2700/include/platform_def.h
+++ b/plat/aspeed/ast2700/include/platform_def.h
@@ -41,13 +41,13 @@
#define MAX_MMAP_REGIONS U(32)
/* BL31 region */
-#define BL31_BASE ULL(0x400000000)
-#define BL31_SIZE ULL(0x400000)
+#define BL31_BASE ULL(0x430000000)
+#define BL31_SIZE SZ_512K
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/* BL32 region */
#define BL32_BASE BL31_LIMIT
-#define BL32_SIZE ULL(0x400000)
+#define BL32_SIZE SZ_16M
#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
/* console */
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index aa2fe86..67413c6 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -210,7 +210,8 @@
BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \
plat/${SOC_DIR}/src/bl2_setup.c \
- plat/${SOC_DIR}/driver/swreg.c
+ plat/${SOC_DIR}/driver/swreg.c \
+ lib/cpus/aarch64/cpu_helpers.S
ifeq (${USE_DDR},yes)
PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index f4f5bfc..156c55d 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -110,3 +110,7 @@
ifeq (${ARCH},aarch64)
$(error Error: AArch64 not supported on i.mx7)
endif
+
+ifeq (${AARCH32_SP}, none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c
index e9ea2d8..bfcd6ce 100644
--- a/plat/imx/imx8m/imx8m_measured_boot.c
+++ b/plat/imx/imx8m/imx8m_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -79,3 +79,9 @@
dump_event_log((uint8_t *)event_log, event_log_cur_size);
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return 0;
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 8e66361..c8a3adf 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -131,7 +131,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
int i;
@@ -146,9 +146,6 @@
imx_csu_init(csu_cfg);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 2462517..6f6daf8 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -159,6 +159,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index aeb1cbf..147249e 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -122,7 +122,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
int i;
@@ -143,9 +143,6 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 4651610..a6b43f2 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -65,6 +65,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index e25668b..b0a41c7 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -118,7 +118,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
unsigned int i;
@@ -139,9 +139,6 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 21836d9..a8400a4 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -156,6 +156,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
index 9c1ebb5..ef7134c 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu.h
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
@@ -57,9 +57,18 @@
unsigned int apc[EMI_MPU_DGROUP_NUM];
};
+enum MPU_REQ_ORIGIN_ZONE_ID {
+ MPU_REQ_ORIGIN_TEE_ZONE_SVP = 0,
+ MPU_REQ_ORIGIN_TEE_ZONE_TUI = 1,
+ MPU_REQ_ORIGIN_TEE_ZONE_WFD = 2,
+ MPU_REQ_ORIGIN_TEE_ZONE_MAX = 3,
+ MPU_REQ_ORIGIN_ZONE_INVALID = 0x7FFFFFFF,
+};
+
int emi_mpu_init(void);
+int emi_mpu_optee_handler(uint64_t encoded_addr, uint64_t zone_size,
+ uint64_t zone_info);
int emi_mpu_set_protection(struct emi_region_info_t *region_info);
void set_emi_mpu_regions(void);
int set_apu_emi_mpu_region(void);
-
#endif
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
index bf77791..7eeadec 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
@@ -7,6 +7,8 @@
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
+#include <smccc_helpers.h>
+
#include <emi_mpu.h>
#include <lib/mtk_init/mtk_init.h>
#include <mtk_sip_svc.h>
@@ -116,7 +118,10 @@
u_register_t x3, u_register_t x4,
void *handle, struct smccc_res *smccc_ret)
{
- /* TODO: implement emi mpu handler */
+ int ret;
+
+ ret = emi_mpu_optee_handler(x1, x2, x3);
+ SMC_RET2(handle, ret, 0U);
return 0;
}
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
index 59ab315..ae1b7ef 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
@@ -6,6 +6,9 @@
#include <common/debug.h>
#include <emi_mpu.h>
+#include <mtk_sip_svc.h>
+
+#define MPU_PHYSICAL_ADDR_SHIFT_BITS (16)
void set_emi_mpu_regions(void)
{
@@ -29,3 +32,43 @@
return emi_mpu_set_protection(®ion_info);
}
+
+static inline uint64_t get_decoded_phys_addr(uint64_t addr)
+{
+ return (addr << MPU_PHYSICAL_ADDR_SHIFT_BITS);
+}
+
+static inline uint32_t get_decoded_zone_id(uint32_t info)
+{
+ return ((info & 0xFFFF0000) >> MPU_PHYSICAL_ADDR_SHIFT_BITS);
+}
+
+int emi_mpu_optee_handler(uint64_t encoded_addr, uint64_t zone_size,
+ uint64_t zone_info)
+{
+ uint64_t phys_addr = get_decoded_phys_addr(encoded_addr);
+ struct emi_region_info_t region_info;
+ enum MPU_REQ_ORIGIN_ZONE_ID zone_id = get_decoded_zone_id(zone_info);
+
+ INFO("encoded_addr = 0x%lx, zone_size = 0x%lx, zone_info = 0x%lx\n",
+ encoded_addr, zone_size, zone_info);
+
+ if (zone_id != MPU_REQ_ORIGIN_TEE_ZONE_SVP) {
+ ERROR("Invalid param %s, %d\n", __func__, __LINE__);
+ return MTK_SIP_E_INVALID_PARAM;
+ }
+
+ /* SVP DRAM */
+ region_info.start = phys_addr;
+ region_info.end = phys_addr + zone_size;
+ region_info.region = 4;
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+
+ emi_mpu_set_protection(®ion_info);
+
+ return 0;
+}
\ No newline at end of file
diff --git a/plat/nuvoton/common/nuvoton_helpers.S b/plat/nuvoton/common/nuvoton_helpers.S
new file mode 100644
index 0000000..09035a1
--- /dev/null
+++ b/plat/nuvoton/common/nuvoton_helpers.S
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NUVOTON_HELPERS_S
+#define NUVOTON_HELPERS_S
+
+#include <asm_macros.S>
+#include <cortex_a35.h>
+#include <platform_def.h>
+
+ .globl plat_is_my_cpu_primary
+ .globl plat_my_core_pos
+ .globl plat_calc_core_pos
+ .globl plat_reset_handler
+ .globl plat_get_my_entrypoint
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+ .globl platform_mem_init
+ .globl npcm845x_mailbox_init
+
+ /* --------------------------------------------------------------------
+ * Helper macro that reads the part number of the current CPU and jumps
+ * to the given label if it matches the CPU MIDR provided.
+ *
+ * Clobbers x0.
+ * --------------------------------------------------------------------
+ */
+ .macro jump_if_cpu_midr _cpu_midr, _label
+
+ mrs x0, midr_el1
+ ubfx x0, x0, MIDR_PN_SHIFT, #12
+ cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+ b.eq \_label
+
+ .endm
+
+ /* ----------------------------------------------
+ * The mailbox_base is used to distinguish warm/cold
+ * reset. The mailbox_base is in the data section, not
+ * in .bss, this allows function to start using this
+ * variable before the runtime memory is initialized.
+ * ----------------------------------------------
+ */
+ .section .data.mailbox_base
+ .align 3
+ mailbox_base: .quad 0x0
+
+ /* ---------------------------------------------
+ * void plat_reset_handler(void);
+ *
+ * To add: Determine the SoC type and call the appropriate
+ * reset handler.
+ *----------------------------------------------- */
+
+func plat_reset_handler
+ ret
+endfunc plat_reset_handler
+
+ /* ----------------------------------------------
+ * unsigned int plat_is_my_cpu_primary(void);
+ * This function checks if this is the primary CPU
+ * ----------------------------------------------
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CPU_MASK)
+ cmp x0, #PLAT_PRIMARY_CPU
+ cset x0, eq
+ ret
+endfunc plat_is_my_cpu_primary
+
+ /* ----------------------------------------------
+ * unsigned int plat_my_core_pos(void)
+ * This Function uses the plat_calc_core_pos()
+ * to get the index of the calling CPU.
+ * ----------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_my_core_pos
+
+ /*
+ * unsigned int plat_calc_core_pos(uint64_t mpidr)
+ * helper function to calculate the core position.
+ * With this function.
+ */
+func plat_calc_core_pos
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_calc_core_pos
+
+ /* ---------------------------------------------
+ * function to get the entrypoint.
+ * ---------------------------------------------
+ */
+ /* ---------------------------------------------------------------------
+ * uintptr_t plat_get_my_entrypoint (void);
+ *
+ * Main job of this routine is to distinguish between a cold and a warm
+ * boot.
+ *
+ * This functions returns:
+ * - 0 for a cold boot.
+ * - Any other value for a warm boot.
+ * ---------------------------------------------------------------------
+ */
+func plat_get_my_entrypoint
+ mov x1, x30
+ bl plat_is_my_cpu_primary
+ /*
+ * Secondaries always cold boot.
+ */
+ cbz w0, 1f
+ /*
+ * Primaries warm boot if they are requested
+ * to power off.
+ */
+ mov_imm x0, PLAT_NPCM_TM_HOLD_BASE
+ ldr x0, [x0]
+ cmp x0, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF
+ adr x0, plat_wait_for_warm_boot
+ csel x0, x0, xzr, eq
+ ret x1
+1: mov x0, #0
+ ret x1
+endfunc plat_get_my_entrypoint
+
+func npcm845x_mailbox_init
+ adrp x1, mailbox_base
+ str x0, [x1, :lo12:mailbox_base]
+ ret
+endfunc npcm845x_mailbox_init
+
+func plat_wait_for_warm_boot
+ /*
+ * Calculate address of our hold entry.
+ * As the function will never return, there is no need to save LR.
+ */
+ bl plat_my_core_pos
+ lsl x0, x0, #3
+ mov x8, x0
+ mov_imm x2, PLAT_NPCM_TM_HOLD_BASE
+ add x0, x0, x2
+ mov_imm x2, PLAT_NPCM_TRUSTED_NOTIFICATION_BASE
+ add x8, x8, x2
+ /*
+ * This code runs way before requesting the warmboot of this core,
+ * so it is possible to clear the mailbox before getting a request
+ * to boot.
+ */
+ mov x1, PLAT_NPCM_TM_HOLD_STATE_WAIT
+ str x1,[x0]
+
+ /* Notify that core is in pending state - do not use x0!, uses x7 and x8! */
+ mov x7, PLAT_NPCM_TM_NOTIFICATION_START
+ str x7,[x8]
+ /*
+ * This code runs way before requesting the warmboot of this core,
+ * so it is possible to clear the mailbox before getting a request
+ * to boot.
+ */
+ mov x1, PLAT_NPCM_TM_HOLD_STATE_WAIT
+ str x1,[x0]
+ /* Wait until we have a go */
+poll_mailbox:
+ wfe
+ ldr x1, [x0]
+ cmp x1, PLAT_NPCM_TM_HOLD_STATE_GO
+ bne poll_mailbox
+
+ mov x7, PLAT_NPCM_TM_NOTIFICATION_BR
+ str x7,[x8]
+ /* Jump to the provided entrypoint */
+ mov_imm x0, PLAT_NPCM_TM_ENTRYPOINT
+ ldr x1, [x0]
+ br x1
+endfunc plat_wait_for_warm_boot
+
+func plat_secondary_cold_boot_setup
+ b plat_wait_for_warm_boot
+endfunc plat_secondary_cold_boot_setup
+
+func plat_crash_console_init
+ mov x0, #1
+ ret
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+ ret
+endfunc plat_crash_console_putc
+
+func plat_crash_console_flush
+ mov x0, #0
+ ret
+endfunc plat_crash_console_flush
+
+func platform_mem_init
+ ret
+endfunc platform_mem_init
+
+#endif /* NUVOTON_HELPERS_S */
diff --git a/plat/nuvoton/common/nuvoton_pm.c b/plat/nuvoton/common/nuvoton_pm.c
new file mode 100644
index 0000000..833ebfb
--- /dev/null
+++ b/plat/nuvoton/common/nuvoton_pm.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+
+/* Allow npcm845x to override these functions */
+#pragma weak plat_arm_program_trusted_mailbox
+#pragma weak plat_setup_psci_ops /* changed to weak */
+
+
+/*******************************************************************************
+ * ARM standard platform handler called to check the validity of the non secure
+ * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise.
+ ******************************************************************************/
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /*
+ * Check if the non secure entrypoint lies within the non
+ * secure DRAM.
+ */
+ if ((entrypoint >= ARM_NS_DRAM1_BASE) &&
+ (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
+ return 0;
+ }
+#ifdef __aarch64__
+ if ((entrypoint >= ARM_DRAM2_BASE) &&
+ (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
+ return 0;
+ }
+#endif
+
+ return -1;
+}
+
+int arm_validate_psci_entrypoint(uintptr_t entrypoint)
+{
+ return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS :
+ PSCI_E_INVALID_ADDRESS;
+}
+
+/******************************************************************************
+ * Helper function to save the platform state before a system suspend. Save the
+ * state of the system components which are not in the Always ON power domain.
+ *****************************************************************************/
+void arm_system_pwr_domain_save(void)
+{
+ /* Assert system power domain is available on the platform */
+ assert(PLAT_MAX_PWR_LVL > ARM_PWR_LVL1);
+
+ plat_arm_gic_save();
+
+ /*
+ * Unregister console now so that it is not registered for a second
+ * time during resume.
+ */
+ arm_console_runtime_end();
+
+ /*
+ * All the other peripheral which are configured by TF-A are
+ * re-initialized on resume from system suspend. Hence we
+ * don't save their state here.
+ */
+}
diff --git a/plat/nuvoton/common/nuvoton_topology.c b/plat/nuvoton/common/nuvoton_topology.c
new file mode 100644
index 0000000..892d9e2
--- /dev/null
+++ b/plat/nuvoton/common/nuvoton_topology.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/psci/psci.h>
+#include <lib/semihosting.h>
+#include <plat/common/platform.h>
+
+/*
+ * Since NPCM845 have only powered/non-powered state,
+ * the tree is structure of level 0
+ * (Single cluster == 0) and 4 representing a "leaf" for every CPU
+ */
+const unsigned char npcm845x_power_domain_tree_desc[] = {
+ PLATFORM_CLUSTER_COUNT,
+ PLATFORM_MAX_CPU_PER_CLUSTER
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ /* A single cluster with 4 CPUs */
+ return npcm845x_power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
+ return -1;
+ }
+
+ cluster_id = (unsigned int)MPIDR_AFFLVL1_VAL(mpidr);
+ cpu_id = (unsigned int)MPIDR_AFFLVL0_VAL(mpidr);
+
+ if (cluster_id > PLATFORM_CLUSTER_COUNT ||
+ cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) {
+ return -1;
+ }
+
+ return (int)(cpu_id + (cluster_id * 4));
+}
diff --git a/plat/nuvoton/common/plat_nuvoton_gic.c b/plat/nuvoton/common/plat_nuvoton_gic.c
new file mode 100644
index 0000000..300670d
--- /dev/null
+++ b/plat/nuvoton/common/plat_nuvoton_gic.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/interrupt_props.h>
+#include <drivers/arm/gicv2.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+};
+
+gicv2_driver_data_t arm_gic_data = {
+ .gicd_base = BASE_GICD_BASE,
+ .gicc_base = BASE_GICC_BASE,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
+};
+
+void plat_gic_driver_init(void)
+{
+ gicv2_driver_init(&arm_gic_data);
+}
+
+void plat_gic_init(void)
+{
+ gicv2_distif_init();
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+void plat_gic_cpuif_enable(void)
+{
+ gicv2_cpuif_enable();
+}
+
+void plat_gic_cpuif_disable(void)
+{
+ gicv2_cpuif_disable();
+}
+
+void plat_gic_pcpu_init(void)
+{
+ gicv2_pcpu_distif_init();
+}
diff --git a/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
new file mode 100644
index 0000000..08448db
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/debugfs.h>
+#include <lib/extensions/ras.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_compat.h>
+#include <npcm845x_clock.h>
+#include <npcm845x_gcr.h>
+#include <npcm845x_lpuart.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <plat_npcm845x.h>
+#include <platform_def.h>
+
+/*
+ * Placeholder variables for copying the arguments that have been passed to
+ * BL31 from BL2.
+ */
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+#if !RESET_TO_BL31
+/*
+ * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
+ * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
+ */
+/* CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); */
+#endif /* !RESET_TO_BL31 */
+
+#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
+ BL31_START, \
+ BL31_END - BL31_START, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#if SEPARATE_NOBITS_REGION
+#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
+ BL31_NOBITS_BASE, \
+ BL31_NOBITS_LIMIT - \
+ BL31_NOBITS_BASE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+#endif /* SEPARATE_NOBITS_REGION */
+
+/******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image
+ * for the security state specified. BL33 corresponds to the non-secure
+ * image type while BL32 corresponds to the secure image type.
+ * A NULL pointer is returned if the image does not exist.
+ *****************************************************************************/
+struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ assert(sec_state_is_valid(type));
+ next_image_info = (type == NON_SECURE)
+ ? &bl33_image_ep_info : &bl32_image_ep_info;
+/*
+ * None of the images on the ARM development platforms can have 0x0
+ * as the entrypoint
+ */
+ if (next_image_info->pc) {
+ return next_image_info;
+ } else {
+ return NULL;
+ }
+}
+
+int board_uart_init(void)
+{
+ unsigned long UART_BASE_ADDR;
+ static console_t console;
+
+#ifdef CONFIG_TARGET_ARBEL_PALLADIUM
+ UART_Init(UART0_DEV, UART_MUX_MODE1,
+ UART_BAUDRATE_115200);
+ UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV);
+#else
+ UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV);
+#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
+
+/*
+ * Register UART w/o initialization -
+ * A clock rate of zero means to skip the initialisation.
+ */
+ console_16550_register((uintptr_t)UART_BASE_ADDR, 0, 0, &console);
+
+ return 0;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return (unsigned int)COUNTER_FREQUENCY;
+}
+
+/******************************************************************************
+ * Perform any BL31 early platform setup common to ARM standard platforms.
+ * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
+ * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
+ * done before the MMU is initialized so that the memory layout can be used
+ * while creating page tables. BL2 has flushed this information to memory,
+ * so we are guaranteed to pick up good data.
+ *****************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+#if RESET_TO_BL31
+ void *from_bl2 = (void *)arg0;
+ void *plat_params_from_bl2 = (void *)arg3;
+
+ if (from_bl2 != NULL) {
+ assert(from_bl2 == NULL);
+ }
+
+ if (plat_params_from_bl2 != NULL) {
+ assert(plat_params_from_bl2 == NULL);
+ }
+#endif /* RESET_TO_BL31 */
+
+/* Initialize Delay timer */
+ generic_delay_timer_init();
+
+/* Do Specific Board/Chip initializations */
+ board_uart_init();
+
+#if RESET_TO_BL31
+ /* There are no parameters from BL2 if BL31 is a reset vector */
+ assert(from_bl2 == NULL);
+ assert(plat_params_from_bl2 == NULL);
+
+#ifdef BL32_BASE
+ /* Populate entry point information for BL32 */
+ SET_PARAM_HEAD(&bl32_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+ SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+ bl32_image_ep_info.pc = BL32_BASE;
+ bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+
+#if defined(SPD_spmd)
+/*
+ * SPM (hafnium in secure world) expects SPM Core manifest base address
+ * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
+ * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
+ * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
+ * keep it in the last page.
+ */
+ bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
+ PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
+#endif /* SPD_spmd */
+#endif /* BL32_BASE */
+
+/* Populate entry point information for BL33 */
+ SET_PARAM_HEAD(&bl33_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+
+/*
+ * Tell BL31 where the non-trusted software image
+ * is located and the entry state information
+ */
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ /* Generic ARM code will switch to EL2, revert to EL1 */
+ bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl33_image_ep_info.spsr &= ~0x8;
+ bl33_image_ep_info.spsr |= 0x4;
+
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, (uint32_t)NON_SECURE);
+
+#if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33)
+/*
+ * Hafnium in normal world expects its manifest address in x0,
+ * which is loaded at base of DRAM.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
+#endif /* SPD_spmd && !ARM_LINUX_KERNEL_AS_BL33 */
+
+#if ARM_LINUX_KERNEL_AS_BL33
+/*
+ * According to the file ``Documentation/arm64/booting.txt`` of the
+ * Linux kernel tree, Linux expects the physical address of the device
+ * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+ * must be 0.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+#endif /* ARM_LINUX_KERNEL_AS_BL33 */
+
+#else /* RESET_TO_BL31 */
+/*
+ * In debug builds, we pass a special value in 'plat_params_from_bl2'
+ * to verify platform parameters from BL2 to BL31.
+ * In release builds, it's not used.
+ */
+ assert(((unsigned long long)plat_params_from_bl2) ==
+ ARM_BL31_PLAT_PARAM_VAL);
+
+/*
+ * Check params passed from BL2 should not be NULL,
+ */
+ bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+
+ assert(params_from_bl2 != NULL);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
+
+/*
+ * Copy BL33 and BL32 (if present), entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
+ while (bl_params != NULL) {
+ if (bl_params->image_id == BL32_IMAGE_ID) {
+ bl32_image_ep_info = *bl_params->ep_info;
+ }
+
+ if (bl_params->image_id == BL33_IMAGE_ID) {
+ bl33_image_ep_info = *bl_params->ep_info;
+ }
+
+ bl_params = bl_params->next_params_info;
+ }
+
+ if (bl33_image_ep_info.pc == 0U) {
+ panic();
+ }
+#endif /* RESET_TO_BL31 */
+}
+
+/*******************************************************************************
+ * Perform any BL31 platform setup common to ARM standard platforms
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+/* Initialize the GIC driver, cpu and distributor interfaces */
+ plat_gic_driver_init();
+ plat_gic_init();
+
+#if RESET_TO_BL31
+#if defined(PLAT_ARM_MEM_PROT_ADDR)
+ arm_nor_psci_do_dyn_mem_protect();
+#endif /* PLAT_ARM_MEM_PROT_ADDR */
+#else
+/*
+ * In this soluction, we also do the security initialzation
+ * even when BL31 is not in the reset vector
+ */
+ npcm845x_security_setup();
+#endif /* RESET_TO_BL31 */
+
+/* Enable and initialize the System level generic timer */
+ mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
+ CNTCR_FCREQ(0U) | CNTCR_EN);
+
+/* Initialize power controller before setting up topology */
+ plat_arm_pwrc_setup();
+
+#if RAS_EXTENSION
+ ras_init();
+#endif
+
+#if USE_DEBUGFS
+ debugfs_init();
+#endif /* USE_DEBUGFS */
+}
+
+void arm_console_runtime_init(void)
+{
+/* Added in order to ignore the original weak function */
+}
+
+void plat_arm_program_trusted_mailbox(uintptr_t address)
+{
+/*
+ * now we don't use ARM mailbox,
+ * so that function added to ignore the weak one
+ */
+}
+
+void __init bl31_plat_arch_setup(void)
+{
+ npcm845x_bl31_plat_arch_setup();
+}
+
+void __init plat_arm_pwrc_setup(void)
+{
+/* NPCM850 is always powered so no need for power control */
+}
+
+void __init npcm845x_bl31_plat_arch_setup(void)
+{
+ const mmap_region_t bl_regions[] = {
+ MAP_BL31_TOTAL,
+#if SEPARATE_NOBITS_REGION
+ MAP_BL31_NOBITS,
+#endif /* SEPARATE_NOBITS_REGION */
+ ARM_MAP_BL_RO,
+#if USE_ROMLIB
+ ARM_MAP_ROMLIB_CODE,
+ ARM_MAP_ROMLIB_DATA,
+#endif /* USE_ROMLIB */
+#if USE_COHERENT_MEM
+ ARM_MAP_BL_COHERENT_RAM,
+#endif /* USE_COHERENT_MEM */
+ ARM_MAP_SHARED_RAM,
+#ifdef SECONDARY_BRINGUP
+ ARM_MAP_NS_DRAM1,
+ #ifdef BL32_BASE
+ ARM_MAP_BL32_CORE_MEM
+ #endif /* BL32_BASE */
+#endif /* SECONDARY_BRINGUP */
+ {0}
+ };
+ setup_page_tables(bl_regions, plat_arm_get_mmap());
+ enable_mmu_el3(0U);
+}
diff --git a/plat/nuvoton/npcm845x/npcm845x_common.c b/plat/nuvoton/npcm845x/npcm845x_common.c
new file mode 100644
index 0000000..fc393fd
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_common.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <lib/xlat_tables/xlat_tables_compat.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+const mmap_region_t plat_arm_mmap[] = {
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
diff --git a/plat/nuvoton/npcm845x/npcm845x_psci.c b/plat/nuvoton/npcm845x/npcm845x_psci.c
new file mode 100644
index 0000000..a954265
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_psci.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <lib/semihosting.h>
+#include <npcm845x_clock.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <plat_npcm845x.h>
+
+#define ADP_STOPPED_APPLICATION_EXIT 0x20026
+
+/* Make composite power state parameter till power level 0 */
+#if PSCI_EXTENDED_STATE_ID
+/* Not Extended */
+#define npcm845x_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | \
+ ((type) << PSTATE_TYPE_SHIFT))
+#else
+#define npcm845x_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | \
+ ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
+ ((type) << PSTATE_TYPE_SHIFT))
+#endif /* PSCI_EXTENDED_STATE_ID */
+
+#define npcm845x_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
+ (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \
+ npcm845x_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
+
+/*
+ * The table storing the valid idle power states. Ensure that the
+ * array entries are populated in ascending order of state-id to
+ * enable us to use binary search during power state validation.
+ * The table must be terminated by a NULL entry.
+ */
+static const unsigned int npcm845x_pm_idle_states[] = {
+/*
+ * Cluster = 0 (RUN) CPU=1 (RET, higest in idle) -
+ * Retention. The Power state is Stand-by
+ */
+
+/* State-id - 0x01 */
+ npcm845x_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET,
+ MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
+
+/*
+ * For testing purposes.
+ * Only CPU suspend to standby is supported by NPCM845x
+ */
+ /* State-id - 0x02 */
+ npcm845x_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF,
+ MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
+ 0,
+};
+
+/*******************************************************************************
+ * Platform handler called to check the validity of the non secure
+ * entrypoint.
+ ******************************************************************************/
+int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /*
+ * Check if the non secure entrypoint lies within the non
+ * secure DRAM.
+ */
+ NOTICE("%s() nuvoton_psci\n", __func__);
+#ifdef PLAT_ARM_TRUSTED_DRAM_BASE
+ if ((entrypoint >= PLAT_ARM_TRUSTED_DRAM_BASE) &&
+ (entrypoint < (PLAT_ARM_TRUSTED_DRAM_BASE +
+ PLAT_ARM_TRUSTED_DRAM_SIZE))) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+#endif /* PLAT_ARM_TRUSTED_DRAM_BASE */
+ /* For TFTS purposes, '0' is also illegal */
+ #ifdef SPD_tspd
+ if (entrypoint == 0) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+ #endif /* SPD_tspd */
+ return PSCI_E_SUCCESS;
+}
+
+/*******************************************************************************
+ * Platform handler called when a CPU is about to enter standby.
+ ******************************************************************************/
+void npcm845x_cpu_standby(plat_local_state_t cpu_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ uint64_t scr;
+
+ scr = read_scr_el3();
+ write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+ /*
+ * Enter standby state
+ * dsb is good practice before using wfi to enter low power states
+ */
+ isb();
+ dsb();
+ wfi();
+
+ /* Once awake */
+ write_scr_el3(scr);
+}
+
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be turned on. The
+ * mpidr determines the CPU to be turned on.
+ ******************************************************************************/
+int npcm845x_pwr_domain_on(u_register_t mpidr)
+{
+ int rc = PSCI_E_SUCCESS;
+ int cpu_id = plat_core_pos_by_mpidr(mpidr);
+
+ if ((unsigned int)cpu_id >= PLATFORM_CORE_COUNT) {
+ ERROR("%s() CPU 0x%X\n", __func__, cpu_id);
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ if (cpu_id == -1) {
+ /* domain on was not called by a CPU */
+ ERROR("%s() was not per CPU 0x%X\n", __func__, cpu_id);
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ unsigned int pos = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+ uintptr_t hold_base = PLAT_NPCM_TM_HOLD_BASE;
+
+ assert(pos < PLATFORM_CORE_COUNT);
+
+ hold_base += pos * PLAT_NPCM_TM_HOLD_ENTRY_SIZE;
+
+ mmio_write_64(hold_base, PLAT_NPCM_TM_HOLD_STATE_GO);
+ /* No cache maintenance here, hold_base is mapped as device memory. */
+
+ /* Make sure that the write has completed */
+ dsb();
+ isb();
+
+ sev();
+
+ return rc;
+}
+
+
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be suspended. The
+ * target_state encodes the power state that each level should transition to.
+ ******************************************************************************/
+void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ gicv2_cpuif_disable();
+
+ NOTICE("%s() Out of suspend\n", __func__);
+}
+
+
+/*******************************************************************************
+ * Platform handler called when a power domain has just been powered on after
+ * being turned off earlier. The target_state encodes the low power state that
+ * each level has woken up from.
+ ******************************************************************************/
+void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
+ PLAT_LOCAL_STATE_OFF);
+
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+
+/*******************************************************************************
+ * Platform handler called when a power domain has just been powered on after
+ * having been suspended earlier. The target_state encodes the low power state
+ * that each level has woken up from.
+ ******************************************************************************/
+void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
+ PLAT_LOCAL_STATE_OFF);
+
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+
+void __dead2 npcm845x_system_reset(void)
+{
+ uintptr_t RESET_BASE_ADDR;
+ uint32_t val;
+
+ NOTICE("%s() nuvoton_psci\n", __func__);
+ console_flush();
+
+ dsbsy();
+ isb();
+
+ /*
+ * In future - support all reset types. For now, SW1 reset
+ * Enable software reset 1 to reboot the BMC
+ */
+ RESET_BASE_ADDR = (uintptr_t)0xF0801000;
+
+ /* Read SW1 control register */
+ val = mmio_read_32(RESET_BASE_ADDR + 0x44);
+ /* Keep SPI BMC & MC persist*/
+ val &= 0xFBFFFFDF;
+ /* Setting SW1 control register */
+ mmio_write_32(RESET_BASE_ADDR + 0x44, val);
+ /* Set SW1 reset */
+ mmio_write_32(RESET_BASE_ADDR + 0x14, 0x8);
+ dsb();
+
+ while (1) {
+ ;
+ }
+}
+
+int npcm845x_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int state_id;
+ int i;
+
+ NOTICE("%s() nuvoton_psci\n", __func__);
+ assert(req_state);
+
+ /*
+ * Currently we are using a linear search for finding the matching
+ * entry in the idle power state array. This can be made a binary
+ * search if the number of entries justify the additional complexity.
+ */
+ for (i = 0; !!npcm845x_pm_idle_states[i]; i++) {
+ if (power_state == npcm845x_pm_idle_states[i]) {
+ break;
+ }
+ }
+
+ /* Return error if entry not found in the idle state array */
+ if (!npcm845x_pm_idle_states[i]) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ i = 0;
+ state_id = psci_get_pstate_id(power_state);
+
+ /* Parse the State ID and populate the state info parameter */
+ while (state_id) {
+ req_state->pwr_domain_state[i++] = (uint8_t)state_id &
+ PLAT_LOCAL_PSTATE_MASK;
+ state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+/*
+ * The NPCM845 doesn't truly support power management at SYSTEM power domain.
+ * The SYSTEM_SUSPEND will be down-graded to the cluster level within
+ * the platform layer. The `fake` SYSTEM_SUSPEND allows us to validate
+ * some of the driver save and restore sequences on FVP.
+ */
+#if !ARM_BL31_IN_DRAM
+void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+ unsigned int i;
+
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (i = ARM_PWR_LVL0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ req_state->pwr_domain_state[i] = (uint8_t)PLAT_LOCAL_STATE_OFF;
+ }
+}
+#endif /* !ARM_BL31_IN_DRAM */
+
+/*
+ * The rest of the PSCI implementation are for testing purposes only.
+ * Not supported in Arbel
+ */
+void __dead2 npcm845x_system_off(void)
+{
+ console_flush();
+
+ dsbsy();
+ isb();
+
+ /* NPCM845 doesn't allow real system off, Do reaset instead */
+ /* Do reset here TBD which, in the meanwhile SW1 reset */
+ for (;;) {
+ wfi();
+ }
+}
+
+void __dead2 plat_secondary_cold_boot_setup(void);
+
+void __dead2 npcm845x_pwr_down_wfi(
+ const psci_power_state_t *target_state)
+{
+ uintptr_t hold_base = PLAT_NPCM_TM_HOLD_BASE;
+ unsigned int pos = plat_my_core_pos();
+
+ if (pos == 0) {
+ /*
+ * The secondaries will always be in a wait
+ * for warm boot on reset, but the BSP needs
+ * to be able to distinguish between waiting
+ * for warm boot (e.g. after psci_off, waiting
+ * for psci_on) and a cold boot.
+ */
+ mmio_write_64(hold_base, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF);
+ /* No cache maintenance here, we run with caches off already. */
+ dsb();
+ isb();
+ }
+
+ wfe();
+
+ while (1) {
+ ;
+ }
+}
+
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be turned off. The
+ * target_state encodes the power state that each level should transition to.
+ ******************************************************************************/
+void npcm845x_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ plat_secondary_cold_boot_setup();
+}
+
+static const plat_psci_ops_t npcm845x_plat_psci_ops = {
+ .cpu_standby = npcm845x_cpu_standby,
+ .pwr_domain_on = npcm845x_pwr_domain_on,
+ .pwr_domain_suspend = npcm845x_pwr_domain_suspend,
+ .pwr_domain_on_finish = npcm845x_pwr_domain_on_finish,
+ .pwr_domain_suspend_finish = npcm845x_pwr_domain_suspend_finish,
+ .system_reset = npcm845x_system_reset,
+ .validate_power_state = npcm845x_validate_power_state,
+ .validate_ns_entrypoint = npcm845x_validate_ns_entrypoint,
+
+ /* For testing purposes only This PSCI states are not supported */
+ .pwr_domain_off = npcm845x_pwr_domain_off,
+ .pwr_domain_pwr_down_wfi = npcm845x_pwr_down_wfi,
+};
+
+/* For reference only
+ * typedef struct plat_psci_ops {
+ * void (*cpu_standby)(plat_local_state_t cpu_state);
+ * int (*pwr_domain_on)(u_register_t mpidr);
+ * void (*pwr_domain_off)(const psci_power_state_t *target_state);
+ * void (*pwr_domain_suspend_pwrdown_early)(
+ * const psci_power_state_t *target_state);
+ * void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
+ * void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
+ * void (*pwr_domain_on_finish_late)(
+ * const psci_power_state_t *target_state);
+ * void (*pwr_domain_suspend_finish)(
+ * const psci_power_state_t *target_state);
+ * void __dead2 (*pwr_domain_pwr_down_wfi)(
+ * const psci_power_state_t *target_state);
+ * void __dead2 (*system_off)(void);
+ * void __dead2 (*system_reset)(void);
+ * int (*validate_power_state)(unsigned int power_state,
+ * psci_power_state_t *req_state);
+ * int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
+ * void (*get_sys_suspend_power_state)(
+ * psci_power_state_t *req_state);
+ * int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
+ * int pwrlvl);
+ * int (*translate_power_state_by_mpidr)(u_register_t mpidr,
+ * unsigned int power_state,
+ * psci_power_state_t *output_state);
+ * int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
+ * int (*mem_protect_chk)(uintptr_t base, u_register_t length);
+ * int (*read_mem_protect)(int *val);
+ * int (*write_mem_protect)(int val);
+ * int (*system_reset2)(int is_vendor,
+ * int reset_type, u_register_t cookie);
+ * } plat_psci_ops_t;
+ */
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ uintptr_t *entrypoint = (void *)PLAT_NPCM_TM_ENTRYPOINT;
+
+ *entrypoint = sec_entrypoint;
+
+ *psci_ops = &npcm845x_plat_psci_ops;
+
+ return 0;
+}
diff --git a/plat/nuvoton/npcm845x/npcm845x_serial_port.c b/plat/nuvoton/npcm845x/npcm845x_serial_port.c
new file mode 100644
index 0000000..946e9d0
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_serial_port.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/delay_timer.h>
+#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <npcm845x_clock.h>
+#include <npcm845x_gcr.h>
+#include <npcm845x_lpuart.h>
+#include <plat_npcm845x.h>
+
+
+uintptr_t npcm845x_get_base_uart(UART_DEV_T devNum)
+{
+ return 0xF0000000 + devNum * 0x1000;
+}
+
+uintptr_t npcm845x_get_base_clk(void)
+{
+ return 0xF0801000;
+}
+
+uintptr_t npcm845x_get_base_gcr(void)
+{
+ return 0xF0800000;
+}
+
+void npcm845x_wait_for_empty(int uart_n)
+{
+ volatile struct npcmX50_uart *uart = (struct npcmX50_uart *)npcm845x_get_base_uart(uart_n);
+
+ while ((*(uint8_t *)(uintptr_t)(&uart->lsr) & 0x40) == 0x00) {
+/*
+ * wait for THRE (Transmitter Holding Register Empty)
+ * and TSR (Transmitter Shift Register) to be empty.
+ * Some delay. notice needed some delay so UartUpdateTool
+ * will pass w/o error log
+ */
+ }
+
+ volatile int delay;
+
+ for (delay = 0; delay < 10000; delay++) {
+ ;
+ }
+}
+
+int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate)
+{
+ uint32_t val = 0;
+ uintptr_t clk_base = npcm845x_get_base_clk();
+ uintptr_t gcr_base = npcm845x_get_base_gcr();
+ uintptr_t uart_base = npcm845x_get_base_uart(devNum);
+ volatile struct npcmX50_uart *uart = (struct npcmX50_uart *)uart_base;
+
+/* Use CLKREF to be independent of CPU frequency */
+ volatile struct clk_ctl *clk_ctl_obj = (struct clk_ctl *)clk_base;
+ volatile struct npcm845x_gcr *gcr_ctl_obj =
+ (struct npcm845x_gcr *)gcr_base;
+
+ clk_ctl_obj->clksel = clk_ctl_obj->clksel & ~(0x3 << 8);
+ clk_ctl_obj->clksel = clk_ctl_obj->clksel | (0x2 << 8);
+
+ /* Set devider according to baudrate */
+ clk_ctl_obj->clkdiv1 =
+ (unsigned int)(clk_ctl_obj->clkdiv1 & ~(0x1F << 16));
+
+ /* clear bits 11-15 - set value 0 */
+ if (devNum == UART3_DEV) {
+ clk_ctl_obj->clkdiv2 =
+ (unsigned int)(clk_ctl_obj->clkdiv2 & ~(0x1F << 11));
+ }
+
+ npcm845x_wait_for_empty(devNum);
+
+ val = (uint32_t)LCR_WLS_8bit;
+ mmio_write_8((uintptr_t)&uart->lcr, (uint8_t)val);
+
+ /* disable all interrupts */
+ mmio_write_8((uintptr_t)&uart->ier, 0);
+
+ /*
+ * Set the RX FIFO trigger level, reset RX, TX FIFO
+ */
+ val = (uint32_t)(FCR_FME | FCR_RFR | FCR_TFR | FCR_RFITL_4B);
+
+ /* reset TX and RX FIFO */
+ mmio_write_8((uintptr_t)(&uart->fcr), (uint8_t)val);
+
+ /* Set port for 8 bit, 1 stop, no parity */
+ val = (uint32_t)LCR_WLS_8bit;
+
+ /* Set DLAB bit; Accesses the Divisor Latch Registers (DLL, DLM). */
+ val |= 0x80;
+ mmio_write_8((uintptr_t)(&uart->lcr), (uint8_t)val);
+
+ /* Baud Rate = UART Clock 24MHz / (16 * (11+2)) = 115384 */
+ mmio_write_8((uintptr_t)(&uart->dll), 11);
+ mmio_write_8((uintptr_t)(&uart->dlm), 0x00);
+
+ val = mmio_read_8((uintptr_t)&uart->lcr);
+
+ /* Clear DLAB bit; Accesses RBR, THR or IER registers. */
+ val &= 0x7F;
+ mmio_write_8((uintptr_t)(&uart->lcr), (uint8_t)val);
+
+ if (devNum == UART0_DEV) {
+ gcr_ctl_obj->mfsel4 &= ~(1 << 1);
+ gcr_ctl_obj->mfsel1 |= 1 << 9;
+ } else if (devNum == UART3_DEV) {
+ /* Pin Mux */
+ gcr_ctl_obj->mfsel4 &= ~(1 << 1);
+ gcr_ctl_obj->mfsel1 |= 1 << 11;
+ gcr_ctl_obj->spswc &= (7 << 0);
+ gcr_ctl_obj->spswc |= (2 << 0);
+ } else {
+ /* halt */
+ while (1) {
+ ;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/nuvoton/npcm845x/platform.mk b/plat/nuvoton/npcm845x/platform.mk
new file mode 100644
index 0000000..5120cc6
--- /dev/null
+++ b/plat/nuvoton/npcm845x/platform.mk
@@ -0,0 +1,370 @@
+#
+# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+#
+# Copyright (c) 2017-2023 Nuvoton Ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# This is a debug flag for bring-up. It allows reducing CPU numbers
+# SECONDARY_BRINGUP := 1
+RESET_TO_BL31 := 1
+SPMD_SPM_AT_SEL2 := 0
+#temporary until the RAM size is reduced
+USE_COHERENT_MEM := 1
+
+
+$(eval $(call add_define,RESET_TO_BL31))
+
+ifeq (${ARCH}, aarch64)
+# On ARM standard platorms, the TSP can execute from Trusted SRAM,
+# Trusted DRAM (if available) or the TZC secured area of DRAM.
+# TZC secured DRAM is the default.
+
+# Process ARM_BL31_IN_DRAM flag
+ARM_BL31_IN_DRAM := 0
+$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
+$(eval $(call add_define,ARM_BL31_IN_DRAM))
+endif
+
+# For the original power-state parameter format, the State-ID can be encoded
+# according to the recommended encoding or zero. This flag determines which
+# State-ID encoding to be parsed.
+ARM_RECOM_STATE_ID_ENC := 0
+
+# If the PSCI_EXTENDED_STATE_ID is set, then ARM_RECOM_STATE_ID_ENC
+# need to be set. Else throw a build error.
+ifeq (${PSCI_EXTENDED_STATE_ID}, 1)
+ifeq (${ARM_RECOM_STATE_ID_ENC}, 0)
+$(error Build option ARM_RECOM_STATE_ID_ENC needs to be set if \
+ PSCI_EXTENDED_STATE_ID is set for ARM platforms)
+endif
+endif
+
+# Process ARM_RECOM_STATE_ID_ENC flag
+$(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC))
+$(eval $(call add_define,ARM_RECOM_STATE_ID_ENC))
+
+# Process ARM_DISABLE_TRUSTED_WDOG flag
+# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set
+ARM_DISABLE_TRUSTED_WDOG := 0
+ifeq (${SPIN_ON_BL1_EXIT}, 1)
+ARM_DISABLE_TRUSTED_WDOG := 1
+endif
+$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG))
+$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG))
+
+# Process ARM_CONFIG_CNTACR
+ARM_CONFIG_CNTACR := 1
+$(eval $(call assert_boolean,ARM_CONFIG_CNTACR))
+$(eval $(call add_define,ARM_CONFIG_CNTACR))
+
+# Process ARM_BL31_IN_DRAM flag
+ARM_BL31_IN_DRAM := 0
+$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
+$(eval $(call add_define,ARM_BL31_IN_DRAM))
+
+# Process ARM_PLAT_MT flag
+ARM_PLAT_MT := 0
+$(eval $(call assert_boolean,ARM_PLAT_MT))
+$(eval $(call add_define,ARM_PLAT_MT))
+
+# Use translation tables library v2 by default
+ARM_XLAT_TABLES_LIB_V1 := 0
+$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
+$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
+
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33 := 0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+
+ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
+ifeq (${ARCH},aarch64)
+ifneq (${RESET_TO_BL31},1)
+$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_BL31=1.")
+endif
+else
+ifneq (${RESET_TO_SP_MIN},1)
+$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.")
+endif
+endif
+
+ifndef PRELOADED_BL33_BASE
+$(error "PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+endif
+
+ifndef ARM_PRELOADED_DTB_BASE
+$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+endif
+
+$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+endif
+
+# Use an implementation of SHA-256 with a smaller memory footprint
+# but reduced speed.
+$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
+
+# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
+# in the FIP if the platform requires.
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
+endif
+
+# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms
+ENABLE_PSCI_STAT := 1
+ENABLE_PMF := 1
+
+# On ARM platforms, separate the code and read-only data sections to allow
+# mapping the former as executable and the latter as execute-never.
+SEPARATE_CODE_AND_RODATA := 1
+
+# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS
+# and NOBITS sections of BL31 image are adjacent to each other and loaded
+# into Trusted SRAM.
+SEPARATE_NOBITS_REGION := 0
+
+# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
+# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
+# the build to require that ARM_BL31_IN_DRAM is enabled as well.
+ifeq ($(SEPARATE_NOBITS_REGION),1)
+ifneq ($(ARM_BL31_IN_DRAM),1)
+$(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled)
+endif
+
+ifneq ($(RECLAIM_INIT_CODE),0)
+$(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported)
+endif
+endif
+
+# Disable ARM Cryptocell by default
+ARM_CRYPTOCELL_INTEG := 0
+$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
+$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
+
+# Enable PIE support for RESET_TO_BL31 case
+ifeq (${RESET_TO_BL31},1)
+ENABLE_PIE := 1
+endif
+
+# CryptoCell integration relies on coherent buffers for passing data from
+# the AP CPU to the CryptoCell
+
+ifeq (${ARM_CRYPTOCELL_INTEG},1)
+ifeq (${USE_COHERENT_MEM},0)
+$(error "ARM_CRYPTOCELL_INTEG needs USE_COHERENT_MEM to be set.")
+endif
+endif
+
+PLAT_INCLUDES := -Iinclude/plat/nuvoton/npcm845x \
+ -Iinclude/plat/nuvoton/common \
+ -Iinclude/drivers/nuvoton/npcm845x \
+
+ifeq (${ARCH}, aarch64)
+PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
+endif
+
+# Include GICv3 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
+NPCM850_GIC_SOURCES := ${GICV2_SOURCES}
+
+BL31_SOURCES +=lib/cpus/aarch64/cortex_a35.S \
+ plat/common/plat_psci_common.c \
+ drivers/ti/uart/aarch64/16550_console.S \
+ plat/nuvoton/npcm845x/npcm845x_psci.c \
+ plat/nuvoton/npcm845x/npcm845x_serial_port.c \
+ plat/nuvoton/common/nuvoton_topology.c \
+ plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
+
+PLAT_BL_COMMON_SOURCES := drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ plat/common/plat_gicv2.c \
+ plat/arm/common/arm_gicv2.c \
+ plat/nuvoton/common/plat_nuvoton_gic.c \
+ ${NPCM850_GIC_SOURCES} \
+ plat/nuvoton/npcm845x/npcm845x_common.c \
+ plat/nuvoton/common/nuvoton_helpers.S \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ plat/arm/common/arm_common.c \
+ plat/arm/common/arm_console.c
+
+ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
+PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/${ARCH}/xlat_tables.c
+else
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+endif
+
+ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c
+
+ifeq (${SPD},spmd)
+ifeq (${SPMD_SPM_AT_SEL2},1)
+ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
+endif
+endif
+
+BL1_SOURCES += drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/common/arm_bl1_setup.c \
+ plat/arm/common/arm_err.c \
+ ${ARM_IO_SOURCES}
+
+ifdef EL3_PAYLOAD_BASE
+# Need the plat_arm_program_trusted_mailbox() function to release secondary CPUs
+# from their holding pen
+BL1_SOURCES += plat/arm/common/arm_pm.c
+endif
+
+BL2_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/common/arm_bl2_setup.c \
+ plat/arm/common/arm_err.c \
+ ${ARM_IO_SOURCES}
+
+# Firmware Configuration Framework sources
+include lib/fconf/fconf.mk
+
+# Add `libfdt` and Arm common helpers required for Dynamic Config
+include lib/libfdt/libfdt.mk
+
+DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
+ plat/arm/common/arm_dyn_cfg_helpers.c \
+ common/fdt_wrappers.c
+
+BL1_SOURCES += ${DYN_CFG_SOURCES}
+BL2_SOURCES += ${DYN_CFG_SOURCES}
+
+ifeq (${BL2_AT_EL3},1)
+BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c
+endif
+
+# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
+# the AArch32 descriptors.
+BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
+BL2_SOURCES += plat/arm/common/arm_image_load.c \
+ common/desc_image_load.c
+
+ifeq (${SPD},opteed)
+BL2_SOURCES += lib/optee/optee_utils.c
+endif
+
+BL2U_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ plat/arm/common/arm_bl2u_setup.c
+
+BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
+ plat/nuvoton/common/nuvoton_pm.c \
+ plat/nuvoton/common/nuvoton_topology.c \
+ plat/common/plat_psci_common.c
+
+ifeq (${ENABLE_PMF}, 1)
+ifeq (${ARCH}, aarch64)
+BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c \
+ plat/arm/common/arm_sip_svc.c \
+ lib/pmf/pmf_smc.c
+else
+BL32_SOURCES += plat/arm/common/arm_sip_svc.c \
+ lib/pmf/pmf_smc.c
+endif
+endif
+
+ifeq (${EL3_EXCEPTION_HANDLING},1)
+BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c
+endif
+
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES += plat/arm/common/aarch64/arm_sdei.c
+ifeq (${SDEI_IN_FCONF},1)
+BL31_SOURCES += plat/arm/common/fconf/fconf_sdei_getter.c
+endif
+endif
+
+# RAS sources
+ifeq (${RAS_EXTENSION},1)
+BL31_SOURCES += lib/extensions/ras/std_err_record.c \
+ lib/extensions/ras/ras_common.c
+endif
+
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
+endif
+
+ifeq (${SPD},spmd)
+BL31_SOURCES += plat/common/plat_spmd_manifest.c \
+ common/fdt_wrappers.c \
+ ${LIBFDT_SRCS}
+endif
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+# Include common TBB sources
+AUTH_SOURCES := drivers/auth/auth_mod.c \
+ drivers/auth/crypto_mod.c \
+ drivers/auth/img_parser_mod.c \
+ lib/fconf/fconf_tbbr_getter.c
+
+# Include the selected chain of trust sources.
+ifeq (${COT},tbbr)
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
+BL1_SOURCES += drivers/auth/tbbr/tbbr_cot_bl1.c
+BL2_SOURCES += drivers/auth/tbbr/tbbr_cot_bl2.c
+else ifeq (${COT},dualroot)
+AUTH_SOURCES += drivers/auth/dualroot/cot.c
+else
+$(error Unknown chain of trust ${COT})
+endif
+
+BL1_SOURCES += ${AUTH_SOURCES} \
+ bl1/tbbr/tbbr_img_desc.c \
+ plat/arm/common/arm_bl1_fwu.c \
+ plat/common/tbbr/plat_tbbr.c
+
+BL2_SOURCES += ${AUTH_SOURCES} \
+ plat/common/tbbr/plat_tbbr.c
+
+$(eval $(call TOOL_ADD_IMG,ns_bl2u,--fwu,FWU_))
+
+# We expect to locate the *.mk files under the directories specified below
+ifeq (${ARM_CRYPTOCELL_INTEG},0)
+CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
+else
+CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
+endif
+
+IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
+
+$(info Including ${CRYPTO_LIB_MK})
+include ${CRYPTO_LIB_MK}
+
+$(info Including ${IMG_PARSER_LIB_MK})
+include ${IMG_PARSER_LIB_MK}
+endif
+
+ifeq (${MEASURED_BOOT},1)
+MEASURED_BOOT_MK := drivers/measured_boot/measured_boot.mk
+$(info Including ${MEASURED_BOOT_MK})
+include ${MEASURED_BOOT_MK}
+endif
+
+ifeq (${EL3_EXCEPTION_HANDLING},1)
+BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c
+endif
+
+BL1_SOURCES :=
+BL2_SOURCES :=
+BL2U_SOURCES :=
+
+DEBUG_CONSOLE ?= 0
+$(eval $(call add_define,DEBUG_CONSOLE))
diff --git a/plat/nvidia/tegra/include/lib/profiler.h b/plat/nvidia/tegra/include/lib/profiler.h
index 684c872..a7d5e7b 100644
--- a/plat/nvidia/tegra/include/lib/profiler.h
+++ b/plat/nvidia/tegra/include/lib/profiler.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nvidia/tegra/lib/debug/profiler.c b/plat/nvidia/tegra/lib/debug/profiler.c
index dd76a4e..b5baf42 100644
--- a/plat/nvidia/tegra/lib/debug/profiler.c
+++ b/plat/nvidia/tegra/lib/debug/profiler.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
new file mode 100644
index 0000000..b8b57d2
--- /dev/null
+++ b/plat/qemu/common/common.mk
@@ -0,0 +1,112 @@
+#
+# Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/libfdt/libfdt.mk
+include common/fdt_wrappers.mk
+
+PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
+ -I${PLAT_QEMU_COMMON_PATH}/include \
+ -I${PLAT_QEMU_PATH}/include \
+ -Iinclude/common/tbbr
+
+ifeq (${ARCH},aarch32)
+QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
+else
+QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/qemu_max.S
+
+PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
+endif
+
+PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S
+
+include lib/xlat_tables_v2/xlat_tables.mk
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+
+ifneq ($(ENABLE_STACK_PROTECTOR), 0)
+ PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
+endif
+
+BL1_SOURCES += drivers/io/io_semihosting.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
+ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
+ ${QEMU_CPU_LIBS}
+
+BL2_SOURCES += drivers/io/io_semihosting.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
+ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
+ common/desc_image_load.c \
+ common/fdt_fixup.c
+
+BL31_SOURCES += ${QEMU_CPU_LIBS} \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ plat/common/plat_psci_common.c \
+ ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
+ common/fdt_fixup.c \
+ ${QEMU_GIC_SOURCES}
+
+# CPU flag enablement
+ifeq (${ARCH},aarch64)
+
+# Later QEMU versions support SME and SVE.
+# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
+ifeq (${SPM_MM},1)
+ ENABLE_SVE_FOR_NS := 0
+ ENABLE_SME_FOR_NS := 0
+else
+ ENABLE_SVE_FOR_NS := 2
+ ENABLE_SME_FOR_NS := 2
+endif
+
+# QEMU will use the RNDR instruction for the stack protector canary.
+ENABLE_FEAT_RNG := 2
+
+# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
+ENABLE_FEAT_FGT := 2
+
+# Treating this as a memory-constrained port for now
+USE_COHERENT_MEM := 0
+
+# This can be overridden depending on CPU(s) used in the QEMU image
+HW_ASSISTED_COHERENCY := 1
+
+CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
+$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
+endif
+
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
+CTX_INCLUDE_PAUTH_REGS := 1
+endif
+
+endif
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index a10ab65..16e89c1 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -4,6 +4,14 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+PLAT_QEMU_PATH := plat/qemu/qemu
+PLAT_QEMU_COMMON_PATH := plat/qemu/common
+
+SEPARATE_CODE_AND_RODATA := 1
+ENABLE_STACK_PROTECTOR := 0
+
+include plat/qemu/common/common.mk
+
# Use the GICv2 driver on QEMU by default
QEMU_USE_GIC_DRIVER := QEMU_GICV2
@@ -18,17 +26,6 @@
$(eval $(call add_define,ARMV7_SUPPORTS_VFP))
# Qemu expects a BL32 boot stage.
NEED_BL32 := yes
-else
-CTX_INCLUDE_AARCH32_REGS := 0
-ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
-$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
-endif
-
-# Treating this as a memory-constrained port for now
-USE_COHERENT_MEM := 0
-
-# This can be overridden depending on CPU(s) used in the QEMU image
-HW_ASSISTED_COHERENCY := 1
endif # ARMv7
ifeq (${SPD},opteed)
@@ -42,42 +39,10 @@
add-lib-optee := yes
endif
-include lib/libfdt/libfdt.mk
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
-PLAT_QEMU_PATH := plat/qemu/qemu
-PLAT_QEMU_COMMON_PATH := plat/qemu/common
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -I${PLAT_QEMU_COMMON_PATH}/include \
- -I${PLAT_QEMU_PATH}/include \
- -Iinclude/common/tbbr
-
-ifeq (${ARM_ARCH_MAJOR},8)
-PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
-
-QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S \
- lib/cpus/aarch64/cortex_a76.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/qemu_max.S
-else
-QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
-endif
-
-PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
-
-include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
ifneq (${TRUSTED_BOARD_BOOT},0)
AUTH_SOURCES := drivers/auth/auth_mod.c \
@@ -150,42 +115,7 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
endif
-BL1_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
- ${QEMU_CPU_LIBS}
-
-ifeq (${ARM_ARCH_MAJOR},8)
-BL1_SOURCES += lib/cpus/${ARCH}/aem_generic.S \
- lib/cpus/${ARCH}/cortex_a53.S \
- lib/cpus/${ARCH}/cortex_a57.S \
- lib/cpus/${ARCH}/cortex_a72.S \
- lib/cpus/${ARCH}/qemu_max.S \
-
-else
-BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S
-endif
-
-BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
- common/fdt_fixup.c \
- common/fdt_wrappers.c \
- common/desc_image_load.c \
+BL2_SOURCES += ${FDT_WRAPPERS_SOURCES} \
common/uuid.c
ifeq ($(add-lib-optee),yes)
@@ -218,29 +148,16 @@
$(error "Incorrect GIC driver chosen for QEMU platform")
endif
-ifeq (${ARM_ARCH_MAJOR},8)
-BL31_SOURCES += ${QEMU_CPU_LIBS} \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- plat/common/plat_psci_common.c \
- drivers/arm/pl061/pl061_gpio.c \
+ifeq (${ARCH},aarch64)
+BL31_SOURCES += drivers/arm/pl061/pl061_gpio.c \
drivers/gpio/gpio.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
- ${PLAT_QEMU_COMMON_PATH}/topology.c \
- ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
- ${QEMU_GIC_SOURCES}
+ ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
+ ${PLAT_QEMU_COMMON_PATH}/topology.c
ifeq (${SDEI_SUPPORT}, 1)
BL31_SOURCES += plat/qemu/common/qemu_sdei.c
endif
-# Pointer Authentication sources
-ifeq (${ENABLE_PAUTH}, 1)
-PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
- lib/extensions/pauth/pauth_helpers.S
-endif
-
ifeq (${SPD},spmd)
BL31_SOURCES += plat/common/plat_spmd_manifest.c \
common/uuid.c \
@@ -280,12 +197,6 @@
$(eval $(call TOOL_ADD_PAYLOAD,${QEMU_TOS_FW_CONFIG},--tos-fw-config,${QEMU_TOS_FW_CONFIG}))
endif
-SEPARATE_CODE_AND_RODATA := 1
-ENABLE_STACK_PROTECTOR := 0
-ifneq ($(ENABLE_STACK_PROTECTOR), 0)
- PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
-endif
-
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
@@ -306,15 +217,6 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-# QEMU will use the RNDR instruction for the stack protector canary.
-ENABLE_FEAT_RNG := 2
-
-# Later QEMU versions support SME and SVE.
-ifneq (${ARCH},aarch32)
- ENABLE_SVE_FOR_NS := 2
- ENABLE_SME_FOR_NS := 2
-endif
-
qemu_fw.bios: bl1 fip
$(ECHO) " DD $@"
$(Q)cp ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/$@
diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
index 122bb23..077f7a4 100644
--- a/plat/qemu/qemu/qemu_measured_boot.c
+++ b/plat/qemu/qemu/qemu_measured_boot.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
- * Copyright (c) 2022, Linaro.
+ * Copyright (c) 2022-2023, Linaro.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,3 +118,9 @@
return 0;
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return 0;
+}
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 3dfefd0..4a8df46 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -4,11 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-include common/fdt_wrappers.mk
+PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
+PLAT_QEMU_COMMON_PATH := plat/qemu/common
+
+MULTI_CONSOLE_API := 1
+CRASH_REPORTING := 1
-CRASH_REPORTING := 1
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT := 0
-include lib/libfdt/libfdt.mk
+SEPARATE_CODE_AND_RODATA := 1
+ENABLE_STACK_PROTECTOR := 0
ifeq (${SPM_MM},1)
NEED_BL32 := yes
@@ -16,75 +22,16 @@
GICV2_G0_FOR_EL3 := 1
endif
+include plat/qemu/common/common.mk
+
# Enable new version of image loading on QEMU platforms
LOAD_IMAGE_V2 := 1
-CTX_INCLUDE_AARCH32_REGS := 0
-ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
-$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
-endif
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
-PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
-PLAT_QEMU_COMMON_PATH := plat/qemu/common
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -I${PLAT_QEMU_COMMON_PATH}/include \
- -I${PLAT_QEMU_PATH}/include \
- -Iinclude/common/tbbr
-
-PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
-
-PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
-
-# Treating this as a memory-constrained port for now
-USE_COHERENT_MEM := 0
-
-# This can be overridden depending on CPU(s) used in the QEMU image
-HW_ASSISTED_COHERENCY := 1
-
-QEMU_CPU_LIBS := lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/qemu_max.S
-
-include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
-BL1_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
-
-BL1_SOURCES += ${QEMU_CPU_LIBS}
-
-BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
- common/fdt_fixup.c \
- $(LIBFDT_SRCS)
-ifeq (${LOAD_IMAGE_V2},1)
-BL2_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
- common/desc_image_load.c
-endif
+BL2_SOURCES += $(LIBFDT_SRCS)
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -92,18 +39,10 @@
QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c
-BL31_SOURCES += ${QEMU_CPU_LIBS} \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- plat/common/plat_psci_common.c \
- ${PLAT_QEMU_PATH}/sbsa_gic.c \
+BL31_SOURCES += ${PLAT_QEMU_PATH}/sbsa_gic.c \
${PLAT_QEMU_PATH}/sbsa_pm.c \
${PLAT_QEMU_PATH}/sbsa_sip_svc.c \
- ${PLAT_QEMU_PATH}/sbsa_topology.c \
- ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
- common/fdt_fixup.c \
- ${QEMU_GIC_SOURCES}
+ ${PLAT_QEMU_PATH}/sbsa_topology.c
BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
@@ -111,17 +50,6 @@
BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c
endif
-SEPARATE_CODE_AND_RODATA := 1
-ENABLE_STACK_PROTECTOR := 0
-ifneq ($(ENABLE_STACK_PROTECTOR), 0)
- PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
-endif
-
-MULTI_CONSOLE_API := 1
-
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
# Use known base for UEFI if not given from command line
# By default BL33 is at FLASH1 base
PRELOADED_BL33_BASE ?= 0x10000000
@@ -137,10 +65,3 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-
-# Later QEMU versions support SME and SVE.
-ENABLE_SVE_FOR_NS := 2
-ENABLE_SME_FOR_NS := 2
-
-# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
-ENABLE_FEAT_FGT := 2
diff --git a/plat/qti/msm8916/platform.mk b/plat/qti/msm8916/platform.mk
index 4f4dcb4..c71ad94 100644
--- a/plat/qti/msm8916/platform.mk
+++ b/plat/qti/msm8916/platform.mk
@@ -75,11 +75,14 @@
PRELOADED_BL33_BASE ?= 0x8f600000
ifeq (${ARCH},aarch64)
-BL32_BASE ?= BL31_LIMIT
-$(eval $(call add_define,BL31_BASE))
+ BL32_BASE ?= BL31_LIMIT
+ $(eval $(call add_define,BL31_BASE))
else
-# There is no BL31 on aarch32, so reuse its location for BL32
-BL32_BASE ?= $(BL31_BASE)
+ ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+ endif
+ # There is no BL31 on aarch32, so reuse its location for BL32
+ BL32_BASE ?= $(BL31_BASE)
endif
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk
index b8dd195..e6f78cf 100644
--- a/plat/rockchip/rk3288/platform.mk
+++ b/plat/rockchip/rk3288/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -67,3 +67,7 @@
ENABLE_SVE_FOR_NS := 0
WORKAROUND_CVE_2017_5715 := 0
+
+ifeq (${AARCH32_SP}, none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index c935b7d..5b0a171 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -222,7 +222,7 @@
static void boot_mmc(enum mmc_device_type mmc_dev_type,
uint16_t boot_interface_instance)
{
- int io_result __unused;
+ int io_result __maybe_unused;
struct stm32_sdmmc2_params params;
zeromem(¶ms, sizeof(struct stm32_sdmmc2_params));
@@ -294,7 +294,7 @@
#if STM32MP_SPI_NOR
static void boot_spi_nor(boot_api_context_t *boot_context)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = stm32_qspi_init();
assert(io_result == 0);
@@ -313,7 +313,7 @@
#if STM32MP_RAW_NAND
static void boot_fmc2_nand(boot_api_context_t *boot_context)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = stm32_fmc2_init();
assert(io_result == 0);
@@ -332,7 +332,7 @@
#if STM32MP_SPI_NAND
static void boot_spi_nand(boot_api_context_t *boot_context)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = stm32_qspi_init();
assert(io_result == 0);
@@ -351,7 +351,7 @@
#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
static void mmap_io_setup(void)
{
- int io_result __unused;
+ int io_result __maybe_unused;
io_result = register_io_dev_memmap(&memmap_dev_con);
assert(io_result == 0);
@@ -364,7 +364,7 @@
#if STM32MP_UART_PROGRAMMER
static void stm32cubeprogrammer_uart(void)
{
- int ret __unused;
+ int ret __maybe_unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
uintptr_t uart_base;
@@ -378,7 +378,7 @@
#if STM32MP_USB_PROGRAMMER
static void stm32cubeprogrammer_usb(void)
{
- int ret __unused;
+ int ret __maybe_unused;
struct usb_handle *pdev;
/* Init USB on platform */
@@ -390,10 +390,9 @@
#endif
#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
-
void stm32mp_io_setup(void)
{
- int io_result __unused;
+ int io_result __maybe_unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
@@ -473,7 +472,7 @@
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
- static bool gpt_init_done __unused;
+ static bool gpt_init_done __maybe_unused;
uint16_t boot_itf = stm32mp_get_boot_itf_selected();
switch (boot_itf) {
@@ -516,6 +515,7 @@
gpt_init_done = true;
} else {
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+
assert(bl_mem_params != NULL);
mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
@@ -538,7 +538,14 @@
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+/*
+ * With FWU Multi Bank feature enabled, the selection of
+ * the image to boot will be done by fwu_init calling the
+ * platform hook, plat_fwu_set_images_source.
+ */
+#if !PSA_FWU_SUPPORT
image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
+#endif
break;
#endif
@@ -591,7 +598,7 @@
return rc;
}
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
/*
* In each boot in non-trial mode, we set the BKP register to
* FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
@@ -652,54 +659,108 @@
{
unsigned int i;
uint32_t boot_idx;
- const partition_entry_t *entry;
- const uuid_t *img_type_uuid, *img_uuid;
+ const partition_entry_t *entry __maybe_unused;
+ const uuid_t *img_type_uuid;
+ const uuid_t *img_uuid __maybe_unused;
io_block_spec_t *image_spec;
+ const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
boot_idx = plat_fwu_get_boot_idx();
assert(boot_idx < NR_OF_FW_BANKS);
for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
img_type_uuid = &metadata->img_entry[i].img_type_uuid;
+
+ img_uuid = &metadata->img_entry[i].img_props[boot_idx].img_uuid;
+
image_spec = stm32_get_image_spec(img_type_uuid);
if (image_spec == NULL) {
ERROR("Unable to get image spec for the image in the metadata\n");
panic();
}
- img_uuid =
- &metadata->img_entry[i].img_props[boot_idx].img_uuid;
+ switch (boot_itf) {
+#if (STM32MP_SDMMC || STM32MP_EMMC)
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+ entry = get_partition_entry_by_uuid(img_uuid);
+ if (entry == NULL) {
+ ERROR("No partition with the uuid mentioned in metadata\n");
+ panic();
+ }
- entry = get_partition_entry_by_uuid(img_uuid);
- if (entry == NULL) {
- ERROR("Unable to find the partition with the uuid mentioned in metadata\n");
+ image_spec->offset = entry->start;
+ image_spec->length = entry->length;
+ break;
+#endif
+#if STM32MP_SPI_NOR
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ if (guidcmp(img_uuid, &STM32MP_NOR_FIP_A_GUID) == 0) {
+ image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
+ } else if (guidcmp(img_uuid, &STM32MP_NOR_FIP_B_GUID) == 0) {
+ image_spec->offset = STM32MP_NOR_FIP_B_OFFSET;
+ } else {
+ ERROR("Invalid uuid mentioned in metadata\n");
+ panic();
+ }
+ break;
+#endif
+ default:
panic();
+ break;
}
-
- image_spec->offset = entry->start;
- image_spec->length = entry->length;
}
}
static int plat_set_image_source(unsigned int image_id,
uintptr_t *handle,
- uintptr_t *image_spec,
- const char *part_name)
+ uintptr_t *image_spec)
{
struct plat_io_policy *policy;
- io_block_spec_t *spec;
- const partition_entry_t *entry = get_partition_entry(part_name);
-
- if (entry == NULL) {
- ERROR("Unable to find the %s partition\n", part_name);
- return -ENOENT;
- }
+ io_block_spec_t *spec __maybe_unused;
+ const partition_entry_t *entry __maybe_unused;
+ const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
policy = &policies[image_id];
-
spec = (io_block_spec_t *)policy->image_spec;
- spec->offset = entry->start;
- spec->length = entry->length;
+
+ switch (boot_itf) {
+#if (STM32MP_SDMMC || STM32MP_EMMC)
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+ partition_init(GPT_IMAGE_ID);
+
+ if (image_id == FWU_METADATA_IMAGE_ID) {
+ entry = get_partition_entry(METADATA_PART_1);
+ } else {
+ entry = get_partition_entry(METADATA_PART_2);
+ }
+
+ if (entry == NULL) {
+ ERROR("Unable to find a metadata partition\n");
+ return -ENOENT;
+ }
+
+ spec->offset = entry->start;
+ spec->length = entry->length;
+ break;
+#endif
+
+#if STM32MP_SPI_NOR
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+ if (image_id == FWU_METADATA_IMAGE_ID) {
+ spec->offset = STM32MP_NOR_METADATA1_OFFSET;
+ } else {
+ spec->offset = STM32MP_NOR_METADATA2_OFFSET;
+ }
+
+ spec->length = sizeof(struct fwu_metadata);
+ break;
+#endif
+ default:
+ panic();
+ break;
+ }
*image_spec = policy->image_spec;
*handle = *policy->dev_handle;
@@ -711,20 +772,9 @@
uintptr_t *handle,
uintptr_t *image_spec)
{
- char *part_name;
-
assert((image_id == FWU_METADATA_IMAGE_ID) ||
(image_id == BKUP_FWU_METADATA_IMAGE_ID));
- partition_init(GPT_IMAGE_ID);
-
- if (image_id == FWU_METADATA_IMAGE_ID) {
- part_name = METADATA_PART_1;
- } else {
- part_name = METADATA_PART_2;
- }
-
- return plat_set_image_source(image_id, handle, image_spec,
- part_name);
+ return plat_set_image_source(image_id, handle, image_spec);
}
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 1a59f0b..5514c09 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,12 +27,12 @@
};
#endif
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
static io_block_spec_t metadata_block_spec = {
.offset = 0, /* To be filled at runtime */
.length = 0, /* To be filled at runtime */
};
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
/* By default, STM32 platforms load images from the FIP */
struct plat_io_policy policies[MAX_NUMBER_IDS] = {
@@ -58,7 +58,7 @@
.check = open_storage
},
#endif
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
[FWU_METADATA_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&metadata_block_spec,
@@ -71,7 +71,7 @@
.img_type_guid = NULL_GUID,
.check = open_storage
},
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
};
#define DEFAULT_UUID_NUMBER U(7)
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index f5184e7..9695c9b 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -48,6 +48,3 @@
BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
plat/st/stm32mp1/stm32mp1_scmi.c
-
-# Arm Archtecture services
-BL32_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index 4098386..fa2d20e 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -128,11 +128,26 @@
* STM32MP1 RAW partition offset for devices without GPT
******************************************************************************/
#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
+#if PSA_FWU_SUPPORT
+#define STM32MP_NOR_METADATA1_OFFSET U(0x00080000)
+#define STM32MP_NOR_METADATA2_OFFSET U(0x000C0000)
+#define STM32MP_NOR_FIP_A_OFFSET U(0x00100000)
+#define STM32MP_NOR_FIP_A_GUID (const struct efi_guid)EFI_GUID(0x4fd84c93, \
+ 0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
+ 0x88, 0x70, 0x87)
+
+#define STM32MP_NOR_FIP_B_OFFSET U(0x00500000)
+#define STM32MP_NOR_FIP_B_GUID (const struct efi_guid)EFI_GUID(0x09c54952, \
+ 0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
+ 0x76, 0x6f, 0xb3)
+
+#else /* PSA_FWU_SUPPORT */
#ifndef STM32MP_NOR_FIP_OFFSET
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
#endif
#ifndef STM32MP_NAND_FIP_OFFSET
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
#endif
+#endif /* PSA_FWU_SUPPORT */
#endif /* STM32MP1_FIP_DEF_H */
diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index b80cf45..72ba107 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -174,9 +174,7 @@
PM_CLOCK_GETSTATE,
PM_CLOCK_SETDIVIDER,
PM_CLOCK_GETDIVIDER,
- PM_CLOCK_SETRATE,
- PM_CLOCK_GETRATE,
- PM_CLOCK_SETPARENT,
+ PM_CLOCK_SETPARENT = 43,
PM_CLOCK_GETPARENT,
PM_SECURE_IMAGE,
/* FPGA PL Readback */
diff --git a/plat/xilinx/common/include/pm_svc_main.h b/plat/xilinx/common/include/pm_svc_main.h
index 1a27bdf..4cf7727 100644
--- a/plat/xilinx/common/include/pm_svc_main.h
+++ b/plat/xilinx/common/include/pm_svc_main.h
@@ -10,6 +10,26 @@
#include <pm_common.h>
+/******************************************************************************/
+/**
+ * SECURE_REDUNDANT_CALL() - Adds redundancy to the function call. This is to
+ * avoid glitches which can skip a function call
+ * and cause altering of the code flow in security
+ * critical functions.
+ * @status: Variable which holds the return value of function executed
+ * @status_tmp: Variable which holds the return value of redundant function
+ * call executed
+ * @function: Function to be executed
+ *
+ * Return: None
+ *
+ ******************************************************************************/
+#define SECURE_REDUNDANT_CALL(status, status_tmp, function, ...) \
+ { \
+ status = function(__VA_ARGS__); \
+ status_tmp = function(__VA_ARGS__); \
+ }
+
int32_t pm_setup(void);
uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, const void *cookie, void *handle,
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 3d12d51..dc3e893 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -4,8 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*
*/
+#include <common/debug.h>
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
+#include <libfdt.h>
#include <plat_fdt.h>
#include <platform_def.h>
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index f45c9f0..5beb765 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -157,10 +157,10 @@
#endif /* PLAT_versal_net */
/**
- * xbl_tfa_handover() - Populates the bl32 and bl33 image info structures.
+ * xbl_handover() - Populates the bl32 and bl33 image info structures.
* @bl32: BL32 image info structure.
* @bl33: BL33 image info structure.
- * @tfa_handoff_addr: TF-A handoff address.
+ * @handoff_addr: TF-A handoff address.
*
* Process the handoff parameters from the XBL and populate the BL32 and BL33
* image info structures accordingly.
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index fb32f2a..1e5808c 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -23,6 +23,7 @@
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_ipi.h"
+#include "pm_svc_main.h"
#define MODE 0x80000000U
@@ -399,8 +400,9 @@
{
uintptr_t ret;
uint32_t pm_arg[PAYLOAD_ARG_CNT] = {0};
- uint32_t security_flag = SECURE_FLAG;
+ uint32_t security_flag = NON_SECURE_FLAG;
uint32_t api_id;
+ bool status = false, status_tmp = false;
/* Handle case where PM wasn't initialized properly */
if (pm_up == false) {
@@ -408,11 +410,14 @@
}
/*
- * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as non-secure (1)
- * if smc called is non secure
+ * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as secure (0)
+ * if smc called is secure
+ *
+ * Add redundant macro call to immune the code from glitches
*/
- if (is_caller_non_secure(flags) != 0) {
- security_flag = NON_SECURE_FLAG;
+ SECURE_REDUNDANT_CALL(status, status_tmp, is_caller_secure, flags);
+ if ((status != false) && (status_tmp != false)) {
+ security_flag = SECURE_FLAG;
}
pm_arg[0] = (uint32_t)x1;
diff --git a/plat/xilinx/versal/aarch64/versal_helpers.S b/plat/xilinx/versal/aarch64/versal_helpers.S
index f868b18..350ddc4 100644
--- a/plat/xilinx/versal/aarch64/versal_helpers.S
+++ b/plat/xilinx/versal/aarch64/versal_helpers.S
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <asm_macros.S>
#include <arch.h>
+#include <asm_macros.S>
#include <drivers/arm/gicv3.h>
#include <platform_def.h>
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index cdee6b5..74b082d 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -20,7 +20,7 @@
[IPI_ID_PMC] = {
.ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = PMC_REG_BASE,
- .secure_only = 0U,
+ .secure_only = IPI_SECURE_MASK,
},
/* A72 IPI */
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
index bc62efc..ccebff2 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
+++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
@@ -6,9 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <asm_macros.S>
-
#include <arch.h>
+#include <asm_macros.S>
#include <drivers/arm/gicv3.h>
#include <platform_def.h>
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index 626611c..cff400c 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -321,15 +321,9 @@
isb();
- /* Clear power down interrupt status before enabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id),
- APU_PCIL_CORE_X_ISR_POWER_MASK);
/* Enable power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id),
APU_PCIL_CORE_X_IEN_POWER_MASK);
- /* Clear wakeup interrupt status before enabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id),
- APU_PCIL_CORE_X_ISR_WAKE_MASK);
/* Enable wake interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id),
APU_PCIL_CORE_X_IEN_WAKE_MASK);
@@ -383,9 +377,6 @@
/* Disabled power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
APU_PCIL_CORE_X_IDS_POWER_MASK);
- /* Clear wakeup interrupt status before disabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpuid),
- APU_PCIL_CORE_X_ISR_WAKE_MASK);
/* Disable wake interrupt */
mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
APU_PCIL_CORE_X_IDS_WAKE_MASK);
diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c
index 0943c62..e8d8fb7 100644
--- a/plat/xilinx/versal_net/versal_net_ipi.c
+++ b/plat/xilinx/versal_net/versal_net_ipi.c
@@ -26,7 +26,7 @@
[IPI_ID_PMC] = {
.ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE,
- .secure_only = 0,
+ .secure_only = IPI_SECURE_MASK,
},
/* RPU0 IPI */
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index a96c378..b584031 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -229,20 +229,9 @@
size_t i, j, len;
const char *name = "EG/EV";
-#ifdef IMAGE_BL32
- /*
- * For BL32, get the chip id info directly by reading corresponding
- * registers instead of making pm call. This has limitation
- * that these registers should be configured to have access
- * from APU which is default case.
- */
- chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
- chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
-#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
return "XCZUUNKN";
}
-#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
ZYNQMP_CSU_IDCODE_SVD_MASK);
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 36fa0f8..9c79855 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -20,7 +20,7 @@
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
# pncd SPD requires secure SGI to be handled at EL1
-ifeq (${SPD},pncd)
+ifeq (${SPD}, $(filter ${SPD},pncd tspd))
ifeq (${ZYNQMP_WDT_RESTART},1)
$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
endif
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 2041541..9682e59 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2458,7 +2458,7 @@
if (clock_id == CLK_MAX) {
memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ?
CLK_NAME_LEN : sizeof(END_OF_CLK));
- } else if (!pm_clock_valid(clock_id)) {
+ } else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index ece5954..0199597 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -1321,39 +1321,6 @@
}
/**
- * pm_clock_setrate - Set the clock rate for given id.
- * @clock_id: Id of the clock.
- * @rate: rate value in hz.
- *
- * This function is used by master to set rate for any clock.
- *
- * Return: Returns status, either success or error+reason.
- *
- */
-enum pm_ret_status pm_clock_setrate(uint32_t clock_id,
- uint64_t rate)
-{
- return PM_RET_ERROR_NOTSUPPORTED;
-}
-
-/**
- * pm_clock_getrate - Get the clock rate for given id.
- * @clock_id: Id of the clock.
- * @rate: rate value in hz.
- *
- * This function is used by master to get rate
- * for any clock.
- *
- * Return: Returns status, either success or error+reason.
- *
- */
-enum pm_ret_status pm_clock_getrate(uint32_t clock_id,
- uint64_t *rate)
-{
- return PM_RET_ERROR_NOTSUPPORTED;
-}
-
-/**
* pm_clock_setparent - Set the clock parent for given id.
* @clock_id: Id of the clock.
* @parent_index: Index of the parent clock into clock's parents array.
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
index a2597bc..f69a3e7 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
@@ -143,10 +143,6 @@
uint32_t divider);
enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
uint32_t *divider);
-enum pm_ret_status pm_clock_setrate(uint32_t clock_id,
- uint64_t rate);
-enum pm_ret_status pm_clock_getrate(uint32_t clock_id,
- uint64_t *rate);
enum pm_ret_status pm_clock_setparent(uint32_t clock_id,
uint32_t parent_index);
enum pm_ret_status pm_clock_getparent(uint32_t clock_id,
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index e297ecb..5a6a9f8 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -435,23 +435,6 @@
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
- case PM_CLOCK_SETRATE:
- ret = pm_clock_setrate(pm_arg[0],
- ((uint64_t)pm_arg[2]) << 32 | pm_arg[1]);
-
- SMC_RET1(handle, (uint64_t)ret);
-
- case PM_CLOCK_GETRATE:
- {
- uint64_t value = 0;
-
- ret = pm_clock_getrate(pm_arg[0], &value);
- SMC_RET2(handle, (uint64_t)ret |
- (((uint64_t)value & 0xFFFFFFFFU) << 32U),
- (value >> 32U) & 0xFFFFFFFFU);
-
- }
-
case PM_CLOCK_SETPARENT:
ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index ed3300b..02d0b23 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -28,9 +28,6 @@
&tsp_boot_console);
console_set_scope(&tsp_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
-
- /* Initialize the platform config for future decision making */
- zynqmp_config_setup();
}
/*******************************************************************************
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index bb042c7..57d211e 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,8 @@
return SMC_ARCH_CALL_SUCCESS;
case SMCCC_ARCH_SOC_ID:
return plat_is_smccc_feature_available(arg1);
+#ifdef __aarch64__
+ /* Workaround checks are currently only implemented for aarch64 */
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
@@ -88,6 +90,7 @@
}
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
+#endif /* __aarch64__ */
/* Fallthrough */
@@ -128,6 +131,7 @@
SMC_RET1(handle, smccc_arch_features(x1));
case SMCCC_ARCH_SOC_ID:
SMC_RET1(handle, smccc_arch_id(x1));
+#ifdef __aarch64__
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
/*
@@ -156,6 +160,7 @@
*/
SMC_RET0(handle);
#endif
+#endif /* __aarch64__ */
default:
WARN("Unimplemented Arm Architecture Service Call: 0x%x \n",
smc_fid);
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 00a3b73..9906fac 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -39,7 +39,7 @@
#include <cortex_a9.h>
#endif
-#define MAX_ERRATA_ENTRIES 16
+#define MAX_ERRATA_ENTRIES 32
#define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1)
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index d7f501b..71a907b 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -346,8 +346,10 @@
[12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
[13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
- [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [14] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
+ [15] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [16] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
+ [17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */
diff --git a/services/std_svc/spm/el3_spmc/spmc.h b/services/std_svc/spm/el3_spmc/spmc.h
index 13875b9..48644ac 100644
--- a/services/std_svc/spm/el3_spmc/spmc.h
+++ b/services/std_svc/spm/el3_spmc/spmc.h
@@ -213,30 +213,6 @@
uint32_t ffa_version;
};
-/**
- * Holds information returned for each partition by the FFA_PARTITION_INFO_GET
- * interface.
- */
-struct ffa_partition_info_v1_0 {
- uint16_t ep_id;
- uint16_t execution_ctx_count;
- uint32_t properties;
-};
-
-/* Extended structure for v1.1. */
-struct ffa_partition_info_v1_1 {
- uint16_t ep_id;
- uint16_t execution_ctx_count;
- uint32_t properties;
- uint32_t uuid[4];
-};
-
-/* FF-A Partition Info Get related macros. */
-#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7)
-#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8)
-#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0)
-#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1)
-
/* Reference to power management hooks */
extern const spd_pm_ops_t spmc_pm;
diff --git a/services/std_svc/spmd/spmd.mk b/services/std_svc/spmd/spmd.mk
index 6f451c8..72376f7 100644
--- a/services/std_svc/spmd/spmd.mk
+++ b/services/std_svc/spmd/spmd.mk
@@ -15,7 +15,18 @@
SPMD_SOURCES += $(addprefix services/std_svc/spmd/, \
${ARCH}/spmd_helpers.S \
spmd_pm.c \
- spmd_main.c)
+ spmd_main.c \
+ spmd_logical_sp.c)
+
+# Specify platform specific SPMD logical partition implementation.
+SPMD_LP_SOURCES := $(wildcard $(addprefix ${PLAT_DIR}/, \
+ ${PLAT}_spmd_logical_sp*.c))
+
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq ($(wildcard $(SPMD_LP_SOURCES)),)
+SPMD_SOURCES += $(SPMD_LP_SOURCES)
+endif
+endif
# Let the top-level Makefile know that we intend to include a BL32 image
NEED_BL32 := yes
diff --git a/services/std_svc/spmd/spmd_logical_sp.c b/services/std_svc/spmd/spmd_logical_sp.c
new file mode 100644
index 0000000..964b36b
--- /dev/null
+++ b/services/std_svc/spmd/spmd_logical_sp.c
@@ -0,0 +1,742 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+#include "spmd_private.h"
+
+#include <common/debug.h>
+#include <common/uuid.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <services/el3_spmd_logical_sp.h>
+#include <services/spmc_svc.h>
+#include <smccc_helpers.h>
+
+
+/*
+ * Maximum ffa_partition_info entries that can be returned by an invocation
+ * of FFA_PARTITION_INFO_GET_REGS_64 is size in bytes, of available
+ * registers/args in struct ffa_value divided by size of struct
+ * ffa_partition_info. For this ABI, arg3-arg17 in ffa_value can be used, i.e.
+ * 15 uint64_t fields. For FF-A v1.1, this value should be 5.
+ */
+#define MAX_INFO_REGS_ENTRIES_PER_CALL \
+ (uint8_t)((15 * sizeof(uint64_t)) / \
+ sizeof(struct ffa_partition_info_v1_1))
+CASSERT(MAX_INFO_REGS_ENTRIES_PER_CALL == 5, assert_too_many_info_reg_entries);
+
+#if ENABLE_SPMD_LP
+static bool is_spmd_lp_inited;
+static bool is_spmc_inited;
+
+/*
+ * Helper function to obtain the array storing the EL3
+ * SPMD Logical Partition descriptors.
+ */
+static struct spmd_lp_desc *get_spmd_el3_lp_array(void)
+{
+ return (struct spmd_lp_desc *) SPMD_LP_DESCS_START;
+}
+
+/*******************************************************************************
+ * Validate any logical partition descriptors before we initialize.
+ * Initialization of said partitions will be taken care of during SPMD boot.
+ ******************************************************************************/
+static int el3_spmd_sp_desc_validate(struct spmd_lp_desc *lp_array)
+{
+ /* Check the array bounds are valid. */
+ assert(SPMD_LP_DESCS_END > SPMD_LP_DESCS_START);
+
+ /*
+ * No support for SPMD logical partitions when SPMC is at EL3.
+ */
+ assert(!is_spmc_at_el3());
+
+ /* If no SPMD logical partitions are implemented then simply bail out. */
+ if (SPMD_LP_DESCS_COUNT == 0U) {
+ return -1;
+ }
+
+ for (uint32_t index = 0U; index < SPMD_LP_DESCS_COUNT; index++) {
+ struct spmd_lp_desc *lp_desc = &lp_array[index];
+
+ /* Validate our logical partition descriptors. */
+ if (lp_desc == NULL) {
+ ERROR("Invalid SPMD Logical SP Descriptor\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Ensure the ID follows the convention to indicate it resides
+ * in the secure world.
+ */
+ if (!ffa_is_secure_world_id(lp_desc->sp_id)) {
+ ERROR("Invalid SPMD Logical SP ID (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure SPMD logical partition is in valid range. */
+ if (!is_spmd_lp_id(lp_desc->sp_id)) {
+ ERROR("Invalid SPMD Logical Partition ID (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure the UUID is not the NULL UUID. */
+ if (lp_desc->uuid[0] == 0 && lp_desc->uuid[1] == 0 &&
+ lp_desc->uuid[2] == 0 && lp_desc->uuid[3] == 0) {
+ ERROR("Invalid UUID for SPMD Logical SP (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure init function callback is registered. */
+ if (lp_desc->init == NULL) {
+ ERROR("Missing init function for Logical SP(0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure that SPMD LP only supports sending direct requests. */
+ if (lp_desc->properties != FFA_PARTITION_DIRECT_REQ_SEND) {
+ ERROR("Invalid SPMD logical partition properties (0x%x)\n",
+ lp_desc->properties);
+ return -EINVAL;
+ }
+
+ /* Ensure that all partition IDs are unique. */
+ for (uint32_t inner_idx = index + 1;
+ inner_idx < SPMD_LP_DESCS_COUNT; inner_idx++) {
+ if (lp_desc->sp_id == lp_array[inner_idx].sp_id) {
+ ERROR("Duplicate SPMD logical SP ID Detected (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+ }
+ }
+ return 0;
+}
+
+static void spmd_encode_ffa_error(struct ffa_value *retval, int32_t error_code)
+{
+ retval->func = FFA_ERROR;
+ retval->arg1 = FFA_TARGET_INFO_MBZ;
+ retval->arg2 = (uint32_t)error_code;
+ retval->arg3 = FFA_TARGET_INFO_MBZ;
+ retval->arg4 = FFA_TARGET_INFO_MBZ;
+ retval->arg5 = FFA_TARGET_INFO_MBZ;
+ retval->arg6 = FFA_TARGET_INFO_MBZ;
+ retval->arg7 = FFA_TARGET_INFO_MBZ;
+}
+
+static void spmd_build_direct_message_req(spmd_spm_core_context_t *ctx,
+ uint64_t x1, uint64_t x2,
+ uint64_t x3, uint64_t x4)
+{
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+
+ write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32);
+ write_ctx_reg(gpregs, CTX_GPREG_X1, x1);
+ write_ctx_reg(gpregs, CTX_GPREG_X2, x2);
+ write_ctx_reg(gpregs, CTX_GPREG_X3, x3);
+ write_ctx_reg(gpregs, CTX_GPREG_X4, x4);
+ write_ctx_reg(gpregs, CTX_GPREG_X5, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X6, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X7, 0U);
+}
+
+static void spmd_encode_ctx_to_ffa_value(spmd_spm_core_context_t *ctx,
+ struct ffa_value *retval)
+{
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+
+ retval->func = read_ctx_reg(gpregs, CTX_GPREG_X0);
+ retval->arg1 = read_ctx_reg(gpregs, CTX_GPREG_X1);
+ retval->arg2 = read_ctx_reg(gpregs, CTX_GPREG_X2);
+ retval->arg3 = read_ctx_reg(gpregs, CTX_GPREG_X3);
+ retval->arg4 = read_ctx_reg(gpregs, CTX_GPREG_X4);
+ retval->arg5 = read_ctx_reg(gpregs, CTX_GPREG_X5);
+ retval->arg6 = read_ctx_reg(gpregs, CTX_GPREG_X6);
+ retval->arg7 = read_ctx_reg(gpregs, CTX_GPREG_X7);
+ retval->arg8 = read_ctx_reg(gpregs, CTX_GPREG_X8);
+ retval->arg9 = read_ctx_reg(gpregs, CTX_GPREG_X9);
+ retval->arg10 = read_ctx_reg(gpregs, CTX_GPREG_X10);
+ retval->arg11 = read_ctx_reg(gpregs, CTX_GPREG_X11);
+ retval->arg12 = read_ctx_reg(gpregs, CTX_GPREG_X12);
+ retval->arg13 = read_ctx_reg(gpregs, CTX_GPREG_X13);
+ retval->arg14 = read_ctx_reg(gpregs, CTX_GPREG_X14);
+ retval->arg15 = read_ctx_reg(gpregs, CTX_GPREG_X15);
+ retval->arg16 = read_ctx_reg(gpregs, CTX_GPREG_X16);
+ retval->arg17 = read_ctx_reg(gpregs, CTX_GPREG_X17);
+}
+
+static void spmd_logical_sp_set_dir_req_ongoing(spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing |= SPMD_LP_FFA_DIR_REQ_ONGOING;
+}
+
+static void spmd_logical_sp_reset_dir_req_ongoing(spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing &= ~SPMD_LP_FFA_DIR_REQ_ONGOING;
+}
+
+static void spmd_build_ffa_info_get_regs(spmd_spm_core_context_t *ctx,
+ const uint32_t uuid[4],
+ const uint16_t start_index,
+ const uint16_t tag)
+{
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+
+ uint64_t arg1 = (uint64_t)uuid[1] << 32 | uuid[0];
+ uint64_t arg2 = (uint64_t)uuid[3] << 32 | uuid[2];
+ uint64_t arg3 = start_index | (uint64_t)tag << 16;
+
+ write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_PARTITION_INFO_GET_REGS_SMC64);
+ write_ctx_reg(gpregs, CTX_GPREG_X1, arg1);
+ write_ctx_reg(gpregs, CTX_GPREG_X2, arg2);
+ write_ctx_reg(gpregs, CTX_GPREG_X3, arg3);
+ write_ctx_reg(gpregs, CTX_GPREG_X4, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X5, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X6, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X7, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X8, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X9, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X10, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X11, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X12, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X13, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X14, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X15, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X16, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X17, 0U);
+}
+
+static void spmd_logical_sp_set_info_regs_ongoing(spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing |= SPMD_LP_FFA_INFO_GET_REG_ONGOING;
+}
+
+static void spmd_logical_sp_reset_info_regs_ongoing(
+ spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing &= ~SPMD_LP_FFA_INFO_GET_REG_ONGOING;
+}
+
+static void spmd_fill_lp_info_array(
+ struct ffa_partition_info_v1_1 (*partitions)[EL3_SPMD_MAX_NUM_LP],
+ uint32_t uuid[4], uint16_t *lp_count_out)
+{
+ uint16_t lp_count = 0;
+ struct spmd_lp_desc *lp_array;
+ bool uuid_is_null = is_null_uuid(uuid);
+
+ if (SPMD_LP_DESCS_COUNT == 0U) {
+ *lp_count_out = 0;
+ return;
+ }
+
+ lp_array = get_spmd_el3_lp_array();
+ for (uint16_t index = 0; index < SPMD_LP_DESCS_COUNT; ++index) {
+ struct spmd_lp_desc *lp = &lp_array[index];
+
+ if (uuid_is_null || uuid_match(uuid, lp->uuid)) {
+ uint16_t array_index = lp_count;
+
+ ++lp_count;
+
+ (*partitions)[array_index].ep_id = lp->sp_id;
+ (*partitions)[array_index].execution_ctx_count = 1;
+ (*partitions)[array_index].properties = lp->properties;
+ (*partitions)[array_index].properties |=
+ (FFA_PARTITION_INFO_GET_AARCH64_STATE <<
+ FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT);
+ if (uuid_is_null) {
+ memcpy(&((*partitions)[array_index].uuid),
+ &lp->uuid, sizeof(lp->uuid));
+ }
+ }
+ }
+
+ *lp_count_out = lp_count;
+}
+
+static inline void spmd_pack_lp_count_props(
+ uint64_t *xn, uint16_t ep_id, uint16_t vcpu_count,
+ uint32_t properties)
+{
+ *xn = (uint64_t)ep_id;
+ *xn |= (uint64_t)vcpu_count << 16;
+ *xn |= (uint64_t)properties << 32;
+}
+
+static inline void spmd_pack_lp_uuid(uint64_t *xn_1, uint64_t *xn_2,
+ uint32_t uuid[4])
+{
+ *xn_1 = (uint64_t)uuid[0];
+ *xn_1 |= (uint64_t)uuid[1] << 32;
+ *xn_2 = (uint64_t)uuid[2];
+ *xn_2 |= (uint64_t)uuid[3] << 32;
+}
+#endif
+
+/*
+ * Initialize SPMD logical partitions. This function assumes that it is called
+ * only after the SPMC has successfully initialized.
+ */
+int32_t spmd_logical_sp_init(void)
+{
+#if ENABLE_SPMD_LP
+ int32_t rc = 0;
+ struct spmd_lp_desc *spmd_lp_descs;
+
+ assert(SPMD_LP_DESCS_COUNT <= EL3_SPMD_MAX_NUM_LP);
+
+ if (is_spmd_lp_inited == true) {
+ return 0;
+ }
+
+ if (is_spmc_inited == false) {
+ return -1;
+ }
+
+ spmd_lp_descs = get_spmd_el3_lp_array();
+
+ /* Perform initial validation of the SPMD Logical Partitions. */
+ rc = el3_spmd_sp_desc_validate(spmd_lp_descs);
+ if (rc != 0) {
+ ERROR("Logical SPMD Partition validation failed!\n");
+ return rc;
+ }
+
+ VERBOSE("SPMD Logical Secure Partition init start.\n");
+ for (unsigned int i = 0U; i < SPMD_LP_DESCS_COUNT; i++) {
+ rc = spmd_lp_descs[i].init();
+ if (rc != 0) {
+ ERROR("SPMD Logical SP (0x%x) failed to initialize\n",
+ spmd_lp_descs[i].sp_id);
+ return rc;
+ }
+ VERBOSE("SPMD Logical SP (0x%x) Initialized\n",
+ spmd_lp_descs[i].sp_id);
+ }
+
+ INFO("SPMD Logical Secure Partition init completed.\n");
+ if (rc == 0) {
+ is_spmd_lp_inited = true;
+ }
+ return rc;
+#else
+ return 0;
+#endif
+}
+
+void spmd_logical_sp_set_spmc_initialized(void)
+{
+#if ENABLE_SPMD_LP
+ is_spmc_inited = true;
+#endif
+}
+
+void spmd_logical_sp_set_spmc_failure(void)
+{
+#if ENABLE_SPMD_LP
+ is_spmc_inited = false;
+#endif
+}
+
+/*
+ * This function takes an ffa_value structure populated with partition
+ * information from an FFA_PARTITION_INFO_GET_REGS ABI call, extracts
+ * the values and writes it into a ffa_partition_info_v1_1 structure for
+ * other code to consume.
+ */
+bool ffa_partition_info_regs_get_part_info(
+ struct ffa_value args, uint8_t idx,
+ struct ffa_partition_info_v1_1 *partition_info)
+{
+ uint64_t *arg_ptrs;
+ uint64_t info, uuid_lo, uuid_high;
+
+ /*
+ * Each partition information is encoded in 3 registers, so there can be
+ * a maximum of 5 entries.
+ */
+ if (idx >= 5 || partition_info == NULL) {
+ return false;
+ }
+
+ /*
+ * List of pointers to args in return value. arg0/func encodes ff-a
+ * function, arg1 is reserved, arg2 encodes indices. arg3 and greater
+ * values reflect partition properties.
+ */
+ arg_ptrs = (uint64_t *)&args + ((idx * 3) + 3);
+ info = *arg_ptrs;
+
+ arg_ptrs++;
+ uuid_lo = *arg_ptrs;
+
+ arg_ptrs++;
+ uuid_high = *arg_ptrs;
+
+ partition_info->ep_id = (uint16_t)(info & 0xFFFFU);
+ partition_info->execution_ctx_count = (uint16_t)((info >> 16) & 0xFFFFU);
+ partition_info->properties = (uint32_t)(info >> 32);
+ partition_info->uuid[0] = (uint32_t)(uuid_lo & 0xFFFFFFFFU);
+ partition_info->uuid[1] = (uint32_t)((uuid_lo >> 32) & 0xFFFFFFFFU);
+ partition_info->uuid[2] = (uint32_t)(uuid_high & 0xFFFFFFFFU);
+ partition_info->uuid[3] = (uint32_t)((uuid_high >> 32) & 0xFFFFFFFFU);
+
+ return true;
+}
+
+/*
+ * This function is called by the SPMD in response to
+ * an FFA_PARTITION_INFO_GET_REG ABI invocation by the SPMC. Secure partitions
+ * are allowed to discover the presence of EL3 SPMD logical partitions by
+ * invoking the aforementioned ABI and this function populates the required
+ * information about EL3 SPMD logical partitions.
+ */
+uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1,
+ uint64_t x2, uint64_t x3)
+{
+#if ENABLE_SPMD_LP
+ uint32_t target_uuid[4] = { 0 };
+ uint32_t w0;
+ uint32_t w1;
+ uint32_t w2;
+ uint32_t w3;
+ uint16_t start_index;
+ uint16_t tag;
+ static struct ffa_partition_info_v1_1 partitions[EL3_SPMD_MAX_NUM_LP];
+ uint16_t lp_count = 0;
+ uint16_t max_idx = 0;
+ uint16_t curr_idx = 0;
+ uint8_t num_entries_to_ret = 0;
+ struct ffa_value ret = { 0 };
+ uint64_t *arg_ptrs = (uint64_t *)&ret + 3;
+
+ w0 = (uint32_t)(x1 & 0xFFFFFFFFU);
+ w1 = (uint32_t)(x1 >> 32);
+ w2 = (uint32_t)(x2 & 0xFFFFFFFFU);
+ w3 = (uint32_t)(x2 >> 32);
+
+ target_uuid[0] = w0;
+ target_uuid[1] = w1;
+ target_uuid[2] = w2;
+ target_uuid[3] = w3;
+
+ start_index = (uint16_t)(x3 & 0xFFFFU);
+ tag = (uint16_t)((x3 >> 16) & 0xFFFFU);
+
+ assert(handle == cm_get_context(SECURE));
+
+ if (tag != 0) {
+ VERBOSE("Tag is not 0. Cannot return partition info.\n");
+ return spmd_ffa_error_return(handle, FFA_ERROR_RETRY);
+ }
+
+ memset(&partitions, 0, sizeof(partitions));
+
+ spmd_fill_lp_info_array(&partitions, target_uuid, &lp_count);
+
+ if (lp_count == 0) {
+ VERBOSE("No SPDM EL3 logical partitions exist.\n");
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ }
+
+ if (start_index >= lp_count) {
+ VERBOSE("start_index = %d, lp_count = %d (start index must be"
+ " less than partition count.\n",
+ start_index, lp_count);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_INVALID_PARAMETER);
+ }
+
+ max_idx = lp_count - 1;
+ num_entries_to_ret = (max_idx - start_index) + 1;
+ num_entries_to_ret =
+ MIN(num_entries_to_ret, MAX_INFO_REGS_ENTRIES_PER_CALL);
+ curr_idx = start_index + num_entries_to_ret - 1;
+ assert(curr_idx <= max_idx);
+
+ ret.func = FFA_SUCCESS_SMC64;
+ ret.arg2 = (uint64_t)((sizeof(struct ffa_partition_info_v1_1) & 0xFFFFU) << 48);
+ ret.arg2 |= (uint64_t)(curr_idx << 16);
+ ret.arg2 |= (uint64_t)max_idx;
+
+ for (uint16_t idx = start_index; idx <= curr_idx; ++idx) {
+ spmd_pack_lp_count_props(arg_ptrs, partitions[idx].ep_id,
+ partitions[idx].execution_ctx_count,
+ partitions[idx].properties);
+ arg_ptrs++;
+ if (is_null_uuid(target_uuid)) {
+ spmd_pack_lp_uuid(arg_ptrs, (arg_ptrs + 1),
+ partitions[idx].uuid);
+ }
+ arg_ptrs += 2;
+ }
+
+ SMC_RET18(handle, ret.func, ret.arg1, ret.arg2, ret.arg3, ret.arg4,
+ ret.arg5, ret.arg6, ret.arg7, ret.arg8, ret.arg9, ret.arg10,
+ ret.arg11, ret.arg12, ret.arg13, ret.arg14, ret.arg15,
+ ret.arg16, ret.arg17);
+#else
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+#endif
+}
+
+/* This function can be used by an SPMD logical partition to invoke the
+ * FFA_PARTITION_INFO_GET_REGS ABI to the SPMC, to discover the secure
+ * partitions in the system. The function takes a UUID, start index and
+ * tag and the partition information are returned in an ffa_value structure
+ * and can be consumed by using appropriate helper functions.
+ */
+bool spmd_el3_invoke_partition_info_get(
+ const uint32_t target_uuid[4],
+ const uint16_t start_index,
+ const uint16_t tag,
+ struct ffa_value *retval)
+{
+#if ENABLE_SPMD_LP
+ uint64_t rc = UINT64_MAX;
+ spmd_spm_core_context_t *ctx = spmd_get_context();
+
+ if (retval == NULL) {
+ return false;
+ }
+
+ memset(retval, 0, sizeof(*retval));
+
+ if (!is_spmc_inited) {
+ VERBOSE("Cannot discover partition before,"
+ " SPMC is initialized.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ if (tag != 0) {
+ VERBOSE("Tag must be zero. other tags unsupported\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ /* Save the non-secure context before entering SPMC */
+ cm_el1_sysregs_context_save(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_save(NON_SECURE);
+#endif
+
+ spmd_build_ffa_info_get_regs(ctx, target_uuid, start_index, tag);
+ spmd_logical_sp_set_info_regs_ongoing(ctx);
+
+ rc = spmd_spm_core_sync_entry(ctx);
+ if (rc != 0ULL) {
+ ERROR("%s failed (%lx) on CPU%u\n", __func__, rc,
+ plat_my_core_pos());
+ panic();
+ }
+
+ spmd_logical_sp_reset_info_regs_ongoing(ctx);
+ spmd_encode_ctx_to_ffa_value(ctx, retval);
+
+ assert(is_ffa_error(retval) || is_ffa_success(retval));
+
+ cm_el1_sysregs_context_restore(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_restore(NON_SECURE);
+#endif
+ cm_set_next_eret_context(NON_SECURE);
+ return true;
+#else
+ return false;
+#endif
+}
+
+/*******************************************************************************
+ * This function sends an FF-A Direct Request from a partition in EL3 to a
+ * partition that may reside under an SPMC (only lower ELs supported). The main
+ * use of this API is for SPMD logical partitions.
+ * The API is expected to be used when there are platform specific SMCs that
+ * need to be routed to a secure partition that is FF-A compliant or when
+ * there are group 0 interrupts that need to be handled first in EL3 and then
+ * forwarded to an FF-A compliant secure partition. Therefore, it is expected
+ * that the handle to the context provided belongs to the non-secure context.
+ * This also means that interrupts/SMCs that trap to EL3 during secure execution
+ * cannot use this API.
+ * x1, x2, x3 and x4 are encoded as specified in the FF-A specification.
+ * retval is used to pass the direct response values to the caller.
+ * The function returns true if retval has valid values, and false otherwise.
+ ******************************************************************************/
+bool spmd_el3_ffa_msg_direct_req(uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *handle,
+ struct ffa_value *retval)
+{
+#if ENABLE_SPMD_LP
+
+ uint64_t rc = UINT64_MAX;
+ spmd_spm_core_context_t *ctx = spmd_get_context();
+
+ if (retval == NULL) {
+ return false;
+ }
+
+ memset(retval, 0, sizeof(*retval));
+
+ if (!is_spmd_lp_inited || !is_spmc_inited) {
+ VERBOSE("Cannot send SPMD logical partition direct message,"
+ " Partitions not initialized or SPMC not initialized.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ /*
+ * x2 must be zero, since there is no support for framework message via
+ * an SPMD logical partition. This is sort of a useless check and it is
+ * possible to not take parameter. However, as the framework extends it
+ * may be useful to have x2 and extend this function later with
+ * functionality based on x2.
+ */
+ if (x2 != 0) {
+ VERBOSE("x2 must be zero. Cannot send framework message.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ /*
+ * Current context must be non-secure. API is expected to be used
+ * when entry into EL3 and the SPMD logical partition is via an
+ * interrupt that occurs when execution is in normal world and
+ * SMCs from normal world. FF-A compliant SPMCs are expected to
+ * trap interrupts during secure execution in lower ELs since they
+ * are usually not re-entrant and SMCs from secure world can be
+ * handled synchronously. There is no known use case for an SPMD
+ * logical partition to send a direct message to another partition
+ * in response to a secure interrupt or SMCs from secure world.
+ */
+ if (handle != cm_get_context(NON_SECURE)) {
+ VERBOSE("Handle must be for the non-secure context.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ if (!is_spmd_lp_id(ffa_endpoint_source(x1))) {
+ VERBOSE("Source ID must be valid SPMD logical partition"
+ " ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (is_spmd_lp_id(ffa_endpoint_destination(x1))) {
+ VERBOSE("Destination ID must not be SPMD logical partition"
+ " ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (!ffa_is_secure_world_id(ffa_endpoint_destination(x1))) {
+ VERBOSE("Destination ID must be secure world ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (ffa_endpoint_destination(x1) == SPMD_DIRECT_MSG_ENDPOINT_ID) {
+ VERBOSE("Destination ID must not be SPMD ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (ffa_endpoint_destination(x1) == spmd_spmc_id_get()) {
+ VERBOSE("Destination ID must not be SPMC ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ /* Save the non-secure context before entering SPMC */
+ cm_el1_sysregs_context_save(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_save(NON_SECURE);
+#endif
+
+ /*
+ * Perform synchronous entry into the SPMC. Synchronous entry is
+ * required because the spec requires that a direct message request
+ * from an SPMD LP look like a function call from it's perspective.
+ */
+ spmd_build_direct_message_req(ctx, x1, x2, x3, x4);
+ spmd_logical_sp_set_dir_req_ongoing(ctx);
+
+ rc = spmd_spm_core_sync_entry(ctx);
+
+ spmd_logical_sp_reset_dir_req_ongoing(ctx);
+
+ if (rc != 0ULL) {
+ ERROR("%s failed (%lx) on CPU%u\n", __func__, rc,
+ plat_my_core_pos());
+ panic();
+ } else {
+ spmd_encode_ctx_to_ffa_value(ctx, retval);
+
+ /*
+ * Only expect error or direct response,
+ * spmd_spm_core_sync_exit should not be called on other paths.
+ * Checks are asserts since the LSP can fail gracefully if the
+ * source or destination ids are not the same. Panic'ing would
+ * not provide any benefit.
+ */
+ assert(is_ffa_error(retval) || is_ffa_direct_msg_resp(retval));
+ assert(is_ffa_error(retval) ||
+ (ffa_endpoint_destination(retval->arg1) ==
+ ffa_endpoint_source(x1)));
+ assert(is_ffa_error(retval) ||
+ (ffa_endpoint_source(retval->arg1) ==
+ ffa_endpoint_destination(x1)));
+ }
+
+ cm_el1_sysregs_context_restore(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_restore(NON_SECURE);
+#endif
+ cm_set_next_eret_context(NON_SECURE);
+
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool is_spmd_logical_sp_info_regs_req_in_progress(
+ spmd_spm_core_context_t *ctx)
+{
+#if ENABLE_SPMD_LP
+ return ((ctx->spmd_lp_sync_req_ongoing & SPMD_LP_FFA_INFO_GET_REG_ONGOING)
+ == SPMD_LP_FFA_INFO_GET_REG_ONGOING);
+#else
+ return false;
+#endif
+}
+
+bool is_spmd_logical_sp_dir_req_in_progress(
+ spmd_spm_core_context_t *ctx)
+{
+#if ENABLE_SPMD_LP
+ return ((ctx->spmd_lp_sync_req_ongoing & SPMD_LP_FFA_DIR_REQ_ONGOING)
+ == SPMD_LP_FFA_DIR_REQ_ONGOING);
+#else
+ return false;
+#endif
+}
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 587e60f..d830403 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -27,6 +27,7 @@
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
#include <platform_def.h>
+#include <services/el3_spmd_logical_sp.h>
#include <services/ffa_svc.h>
#include <services/spmc_svc.h>
#include <services/spmd_svc.h>
@@ -86,8 +87,7 @@
******************************************************************************/
static int32_t spmd_init(void);
static int spmd_spmc_init(void *pm_addr);
-static uint64_t spmd_ffa_error_return(void *handle,
- int error_code);
+
static uint64_t spmd_smc_forward(uint32_t smc_fid,
bool secure_origin,
uint64_t x1,
@@ -190,6 +190,12 @@
VERBOSE("SPM Core init end.\n");
+ spmd_logical_sp_set_spmc_initialized();
+ rc = spmd_logical_sp_init();
+ if (rc != 0) {
+ WARN("SPMD Logical partitions failed init.\n");
+ }
+
return 1;
}
@@ -742,7 +748,7 @@
/*******************************************************************************
* Return FFA_ERROR with specified error code
******************************************************************************/
-static uint64_t spmd_ffa_error_return(void *handle, int error_code)
+uint64_t spmd_ffa_error_return(void *handle, int error_code)
{
SMC_RET8(handle, (uint32_t) FFA_ERROR,
FFA_TARGET_INFO_MBZ, (uint32_t)error_code,
@@ -845,6 +851,16 @@
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
+ /*
+ * If there is an on-going info regs from EL3 SPMD LP, unconditionally
+ * return, we don't expect any other FF-A ABIs to be called between
+ * calls to FFA_PARTITION_INFO_GET_REGS.
+ */
+ if (is_spmd_logical_sp_info_regs_req_in_progress(ctx)) {
+ assert(secure_origin);
+ spmd_spm_core_sync_exit(0ULL);
+ }
+
switch (smc_fid) {
case FFA_ERROR:
/*
@@ -856,6 +872,16 @@
spmd_spm_core_sync_exit(x2);
}
+ /*
+ * If there was an SPMD logical partition direct request on-going,
+ * return back to the SPMD logical partition so the error can be
+ * consumed.
+ */
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ spmd_spm_core_sync_exit(0ULL);
+ }
+
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
handle, flags);
@@ -1045,6 +1071,31 @@
case FFA_MSG_SEND_DIRECT_REQ_SMC32:
case FFA_MSG_SEND_DIRECT_REQ_SMC64:
+ /*
+ * Regardless of secure_origin, SPMD logical partitions cannot
+ * handle direct messages. They can only initiate direct
+ * messages and consume direct responses or errors.
+ */
+ if (is_spmd_lp_id(ffa_endpoint_source(x1)) ||
+ is_spmd_lp_id(ffa_endpoint_destination(x1))) {
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_INVALID_PARAMETER
+ );
+ }
+
+ /*
+ * When there is an ongoing SPMD logical partition direct
+ * request, there cannot be another direct request. Return
+ * error in this case. Panic'ing is an option but that does
+ * not provide the opportunity for caller to abort based on
+ * error codes.
+ */
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_DENIED);
+ }
+
if (!secure_origin) {
/* Validate source endpoint is non-secure for non-secure caller. */
if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) {
@@ -1072,7 +1123,9 @@
break; /* Not reached */
case FFA_MSG_SEND_DIRECT_RESP_SMC32:
- if (secure_origin && spmd_is_spmc_message(x1)) {
+ case FFA_MSG_SEND_DIRECT_RESP_SMC64:
+ if (secure_origin && (spmd_is_spmc_message(x1) ||
+ is_spmd_logical_sp_dir_req_in_progress(ctx))) {
spmd_spm_core_sync_exit(0ULL);
} else {
/* Forward direct message to the other world */
@@ -1112,7 +1165,6 @@
/* Forward the call to the other world */
/* fallthrough */
case FFA_MSG_SEND:
- case FFA_MSG_SEND_DIRECT_RESP_SMC64:
case FFA_MEM_DONATE_SMC32:
case FFA_MEM_DONATE_SMC64:
case FFA_MEM_LEND_SMC32:
@@ -1129,11 +1181,14 @@
case FFA_SUCCESS_SMC32:
case FFA_SUCCESS_SMC64:
/*
- * TODO: Assume that no requests originate from EL3 at the
- * moment. This will change if a SP service is required in
- * response to secure interrupts targeted to EL3. Until then
- * simply forward the call to the Normal world.
+ * If there is an ongoing direct request from an SPMD logical
+ * partition, return an error.
*/
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_DENIED);
+ }
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
@@ -1160,6 +1215,12 @@
FFA_ERROR_NOT_SUPPORTED);
}
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_DENIED);
+ }
+
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
handle, flags);
@@ -1175,8 +1236,8 @@
#if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED
case FFA_PARTITION_INFO_GET_REGS_SMC64:
if (secure_origin) {
- /* TODO: Future patches to enable support for this */
- return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ return spmd_el3_populate_logical_partition_info(handle, x1,
+ x2, x3);
}
/* Call only supported with SMCCC 1.2+ */
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index ff6942e..fef7ef6 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -52,8 +52,15 @@
cpu_context_t cpu_ctx;
spmc_state_t state;
bool secure_interrupt_ongoing;
+#if ENABLE_SPMD_LP
+ uint8_t spmd_lp_sync_req_ongoing;
+#endif
} spmd_spm_core_context_t;
+/* Flags to indicate ongoing requests for SPMD EL3 logical partitions */
+#define SPMD_LP_FFA_DIR_REQ_ONGOING U(0x1)
+#define SPMD_LP_FFA_INFO_GET_REG_ONGOING U(0x2)
+
/*
* Reserve ID for NS physical FFA Endpoint.
*/
@@ -100,6 +107,9 @@
* otherwise it returns a negative value
*/
int plat_spmd_handle_group0_interrupt(uint32_t id);
+
+uint64_t spmd_ffa_error_return(void *handle, int error_code);
+
#endif /* __ASSEMBLER__ */
#endif /* SPMD_PRIVATE_H */
diff --git a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
index 46b5179..fef2116 100644
--- a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
@@ -8,8 +8,8 @@
ifeq (${PLAT_DEF_UUID}, yes)
HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
-HOSTCCFLAGS += -DARM_ETHOSN_NPU_TZMP1
+ifeq (${ETHOSN_NPU_TZMP1},1)
+HOSTCCFLAGS += -DETHOSN_NPU_TZMP1
endif
INCLUDE_PATHS += -I./ -I${PLAT_DIR}fip -I../../include/
OBJECTS += ${PLAT_DIR}fip/plat_def_uuid_config.o
diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py
index 4067331..c69e0a7 100644
--- a/tools/sptool/sp_mk_generator.py
+++ b/tools/sptool/sp_mk_generator.py
@@ -1,5 +1,5 @@
#!/usr/bin/python3
-# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -21,6 +21,7 @@
param2: "SP_LAYOUT_FILE", json file containing platform provided information
param3: plat out directory
param4: CoT parameter
+param5: Generated dts file "sp_list_fragment.dts"
Generated "sp_gen.mk" file contains triplet of following information for each
Secure Partition entry
@@ -112,6 +113,34 @@
''' Helper to fetch pm offset from sp_layout.json '''
return get_offset_from_layout(node["pm"])
+def get_uuid(sp_layout, sp, args :dict):
+ ''' Helper to fetch uuid from pm file listed in sp_layout.json'''
+ if "uuid" in sp_layout[sp]:
+ # Extract the UUID from the JSON file if the SP entry has a 'uuid' field
+ uuid_std = uuid.UUID(sp_layout[sp]['uuid'])
+ else:
+ with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
+ uuid_lines = [l for l in pm_f if 'uuid' in l]
+ assert(len(uuid_lines) == 1)
+ # The uuid field in SP manifest is the little endian representation
+ # mapped to arguments as described in SMCCC section 5.3.
+ # Convert each unsigned integer value to a big endian representation
+ # required by fiptool.
+ uuid_parsed = re.findall("0x([0-9a-f]+)", uuid_lines[0])
+ y = list(map(bytearray.fromhex, uuid_parsed))
+ z = [int.from_bytes(i, byteorder='little', signed=False) for i in y]
+ uuid_std = uuid.UUID(f'{z[0]:08x}{z[1]:08x}{z[2]:08x}{z[3]:08x}')
+ return uuid_std
+
+def get_load_address(sp_layout, sp, args :dict):
+ ''' Helper to fetch load-address from pm file listed in sp_layout.json'''
+ with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
+ load_address_lines = [l for l in pm_f if 'load-address' in l]
+ assert(len(load_address_lines) == 1)
+ load_address_parsed = re.search("(0x[0-9a-f]+)", load_address_lines[0])
+ return load_address_parsed.group(0)
+
+
@SpSetupActions.sp_action(global_action=True)
def check_max_sps(sp_layout, _, args :dict):
''' Check validate the maximum number of SPs is respected. '''
@@ -195,37 +224,53 @@
@SpSetupActions.sp_action
def gen_fiptool_args(sp_layout, sp, args :dict):
''' Generate arguments for the FIP Tool. '''
- if "uuid" in sp_layout[sp]:
- # Extract the UUID from the JSON file if the SP entry has a 'uuid' field
- uuid_std = uuid.UUID(sp_layout[sp]['uuid'])
- else:
- with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f:
- uuid_lines = [l for l in pm_f if 'uuid' in l]
- assert(len(uuid_lines) == 1)
- # The uuid field in SP manifest is the little endian representation
- # mapped to arguments as described in SMCCC section 5.3.
- # Convert each unsigned integer value to a big endian representation
- # required by fiptool.
- uuid_parsed = re.findall("0x([0-9a-f]+)", uuid_lines[0])
- y = list(map(bytearray.fromhex, uuid_parsed))
- z = [int.from_bytes(i, byteorder='little', signed=False) for i in y]
- uuid_std = uuid.UUID(f'{z[0]:08x}{z[1]:08x}{z[2]:08x}{z[3]:08x}')
+ uuid_std = get_uuid(sp_layout, sp, args)
write_to_sp_mk_gen(f"FIP_ARGS += --blob uuid={str(uuid_std)},file={get_sp_pkg(sp, args)}\n", args)
return args
+@SpSetupActions.sp_action
+def gen_fconf_fragment(sp_layout, sp, args: dict):
+ ''' Generate the fconf fragment file'''
+ with open(args["fconf_fragment"], "a") as f:
+ uuid = get_uuid(sp_layout, sp, args)
+ owner = "Plat" if sp_layout[sp].get("owner") == "Plat" else "SiP"
+
+ if "physical-load-address" in sp_layout[sp].keys():
+ load_address = sp_layout[sp]["physical-load-address"]
+ else:
+ load_address = get_load_address(sp_layout, sp, args)
+
+ f.write(
+f'''\
+{sp} {{
+ uuid = "{uuid}";
+ load-address = <{load_address}>;
+ owner = "{owner}";
+}};
+
+''')
+ return args
+
def init_sp_actions(sys):
- sp_layout_file = os.path.abspath(sys.argv[2])
- with open(sp_layout_file) as json_file:
- sp_layout = json.load(json_file)
# Initialize arguments for the SP actions framework
args = {}
args["sp_gen_mk"] = os.path.abspath(sys.argv[1])
+ sp_layout_file = os.path.abspath(sys.argv[2])
args["sp_layout_dir"] = os.path.dirname(sp_layout_file)
args["out_dir"] = os.path.abspath(sys.argv[3])
args["dualroot"] = sys.argv[4] == "dualroot"
+ args["fconf_fragment"] = os.path.abspath(sys.argv[5])
+
+
+ with open(sp_layout_file) as json_file:
+ sp_layout = json.load(json_file)
#Clear content of file "sp_gen.mk".
with open(args["sp_gen_mk"], "w"):
None
+ #Clear content of file "fconf_fragment".
+ with open(args["fconf_fragment"], "w"):
+ None
+
return args, sp_layout
if __name__ == "__main__":