feat(ti): set L2 cache ECC and and parity on A72 cores
The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index cc9934c..6742e74 100644
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -114,6 +114,9 @@
orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
#endif
+ /* Enable L2 ECC and parity with inline data */
+ orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
+ orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
msr CORTEX_A72_L2CTLR_EL1, x0
isb
ret