drivers: marvell: comphy: add rx training on 10G port
This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.
Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index 48172b2..4e17390 100644
--- a/plat/marvell/armada/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c
@@ -50,6 +50,9 @@
#define MVEBU_COMPHY_OFFSET 0x441000
#define MVEBU_CP_BASE_MASK (~0xffffff)
+/* Common PHY register */
+#define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS 0x120a2c
+
/* This macro is used to identify COMPHY related calls from SMC function ID */
#define is_comphy_fid(fid) \
((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
@@ -76,7 +79,7 @@
void *handle,
u_register_t flags)
{
- u_register_t ret, read;
+ u_register_t ret, read, x5 = x1;
uint32_t w2[2] = {0, 0};
int i;
@@ -91,6 +94,7 @@
SMC_RET1(handle, SMC_UNK);
}
+ x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS;
x1 += MVEBU_COMPHY_OFFSET;
if (x2 >= MAX_LANE_NR) {
@@ -105,7 +109,7 @@
/* Comphy related FID's */
case MV_SIP_COMPHY_POWER_ON:
/* x1: comphy_base, x2: comphy_index, x3: comphy_mode */
- ret = mvebu_cp110_comphy_power_on(x1, x2, x3);
+ ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5);
SMC_RET1(handle, ret);
case MV_SIP_COMPHY_POWER_OFF:
/* x1: comphy_base, x2: comphy_index */