refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
As of now, several internal macros utilize "CSS_SGI" as their prefix.
Given the change to neoverse_rd, and the subsequent migration out of the
css directory, the prefix "CSS_SGI" is no longer appropriate.
Therefore, update the macro prefixes to "NRD" for consistency and
clarity.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3d1a9dba3e83f6e107379fc5bcf8256cc93d8c3d
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
index aa8702f..83590eb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
@@ -13,8 +13,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(4)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
@@ -31,15 +31,15 @@
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* Maximum number of address bits used per chip */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
+#define NRD_ADDR_BITS_PER_CHIP U(42)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
index 918728a..0c6756c 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
@@ -15,7 +15,7 @@
#if defined(IMAGE_BL31)
static const mmap_region_t rdn1edge_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
};
@@ -25,7 +25,7 @@
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
},
.spi_ids = {
{PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START,
@@ -37,7 +37,7 @@
static uintptr_t rdn1e1_multichip_gicr_frames[] = {
PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
+ NRD_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
UL(0) /* Zero Termination */
};
#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
index 959daea..f3f6238 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
@@ -20,7 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
- CSS_SGI_DMC620_TZC_REGIONS_DEF
+ NRD_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
index 2e81536..133eb16 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
@@ -12,11 +12,11 @@
******************************************************************************/
static const unsigned char rdn1edge_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#if (NRD_CHIP_COUNT > 1)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
index 3892c66..840ea4a 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
@@ -19,8 +19,8 @@
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x2A920000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
@@ -69,14 +69,14 @@
*/
#ifdef __aarch64__
#if (NRD_PLATFORM_VARIANT == 2)
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */
+#define NRD_ADDR_BITS_PER_CHIP U(46) /* 64TB */
#else
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */
+#define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */
#endif
-#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
index 24072ca..0051049 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
@@ -19,15 +19,15 @@
static const mmap_region_t rdn2mc_dynamic_mmap[] = {
#if NRD_CHIP_COUNT > 1
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if NRD_CHIP_COUNT > 2
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if NRD_CHIP_COUNT > 3
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+ NRD_MAP_DEVICE_REMOTE_CHIP(3),
#endif
};
#endif
@@ -40,13 +40,13 @@
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
#if NRD_CHIP_COUNT > 1
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#endif
#if NRD_CHIP_COUNT > 2
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if NRD_CHIP_COUNT > 3
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
.spi_ids = {
@@ -70,15 +70,15 @@
PLAT_ARM_GICR_BASE,
#if NRD_CHIP_COUNT > 1
/* Chip 1's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
#endif
#if NRD_CHIP_COUNT > 2
/* Chip 2's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if NRD_CHIP_COUNT > 3
/* Chip 3's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
#endif
UL(0) /* Zero Termination */
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
index 3cdc0d3..8ec8345 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
@@ -8,9 +8,9 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
-#define RDN2_TZC_CPER_REGION \
- {CSS_SGI_SP_CPER_BUF_BASE, (CSS_SGI_SP_CPER_BUF_BASE + \
- CSS_SGI_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
+#define RDN2_TZC_CPER_REGION \
+ {NRD_SP_CPER_BUF_BASE, (NRD_SP_CPER_BUF_BASE + \
+ NRD_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
static const arm_tzc_regions_info_t tzc_regions[] = {
@@ -63,7 +63,7 @@
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {
- arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
+ TZC400_BASE(j), tzc_regions_mc[i-1]);
}
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
index 1dea43e..b8b6b7a 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
@@ -12,30 +12,30 @@
******************************************************************************/
const unsigned char rd_n2_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1))
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 2))
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 3))
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
index 7eca2bd..f889561 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
@@ -12,8 +12,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
@@ -47,14 +47,14 @@
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/* Maximum number of address bits used per chip */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
+#define NRD_ADDR_BITS_PER_CHIP U(42)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
index 5ae20dd..20e4266 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
@@ -12,22 +12,22 @@
******************************************************************************/
const unsigned char rd_v1_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
index c0f8ebd..3e7c9b5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
@@ -11,8 +11,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(4)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
@@ -47,12 +47,12 @@
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
/* Remote chip address offset (4TB per chip) */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
+#define NRD_ADDR_BITS_PER_CHIP U(42)
/* Physical and virtual address space limits for MMU in AARCH64 mode */
-#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
/* GIC related constants */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
index 820c7e5..4455ec4 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
@@ -15,16 +15,16 @@
#if defined(IMAGE_BL31)
static const mmap_region_t rdv1mc_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
#if (NRD_CHIP_COUNT > 2)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_MAP_DEVICE_REMOTE_CHIP(2),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if (NRD_CHIP_COUNT > 3)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+ NRD_MAP_DEVICE_REMOTE_CHIP(3),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
#endif
};
@@ -35,12 +35,12 @@
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#if (NRD_CHIP_COUNT > 2)
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if (NRD_CHIP_COUNT > 3)
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
.spi_ids = {
@@ -60,14 +60,14 @@
/* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE,
/* Chip 1's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
#if (NRD_CHIP_COUNT > 2)
/* Chip 2's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if (NRD_CHIP_COUNT > 3)
/* Chip 3's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
#endif
UL(0) /* Zero Termination */
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
index 8f371c5..d437def 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
@@ -56,7 +56,7 @@
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {
- arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
+ TZC400_BASE(j), tzc_regions_mc[i-1]);
}
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
index d0eeb1d..52514ca 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
@@ -15,27 +15,27 @@
******************************************************************************/
const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
((PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT)),
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#if (NRD_CHIP_COUNT > 1)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (NRD_CHIP_COUNT > 2)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (NRD_CHIP_COUNT > 3)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
index 7cc5366..9658ee1 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
@@ -13,8 +13,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(4)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45000000)
@@ -28,14 +28,14 @@
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* Maximum number of address bits used per chip */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
+#define NRD_ADDR_BITS_PER_CHIP U(36)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
index 00b49e2..8b8a382 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
@@ -20,7 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
- CSS_SGI_DMC620_TZC_REGIONS_DEF
+ NRD_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
index 9f5e18a..15ffc65 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
@@ -11,8 +11,8 @@
******************************************************************************/
static const unsigned char sgi575_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************