refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
As of now, several internal macros utilize "CSS_SGI" as their prefix.
Given the change to neoverse_rd, and the subsequent migration out of the
css directory, the prefix "CSS_SGI" is no longer appropriate.
Therefore, update the macro prefixes to "NRD" for consistency and
clarity.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3d1a9dba3e83f6e107379fc5bcf8256cc93d8c3d
diff --git a/plat/arm/board/neoverse_rd/common/arch/aarch64/nrd_helper.S b/plat/arm/board/neoverse_rd/common/arch/aarch64/nrd_helper.S
index 14c3a7c..d250f3b 100644
--- a/plat/arm/board/neoverse_rd/common/arch/aarch64/nrd_helper.S
+++ b/plat/arm/board/neoverse_rd/common/arch/aarch64/nrd_helper.S
@@ -21,15 +21,15 @@
*
* Helper function to calculate the core position.
* (ChipId * PLAT_ARM_CLUSTER_COUNT *
- * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
- * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
- * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
+ * NRD_MAX_CPUS_PER_CLUSTER * NRD_MAX_PE_PER_CPU) +
+ * (ClusterId * NRD_MAX_CPUS_PER_CLUSTER * NRD_MAX_PE_PER_CPU) +
+ * (CPUId * NRD_MAX_PE_PER_CPU) +
* ThreadId
*
* which can be simplified as:
*
* ((((ChipId * PLAT_ARM_CLUSTER_COUNT) + ClusterId) *
- * CSS_SGI_MAX_CPUS_PER_CLUSTER) + CPUId) * CSS_SGI_MAX_PE_PER_CPU +
+ * NRD_MAX_CPUS_PER_CLUSTER) + CPUId) * NRD_MAX_PE_PER_CPU +
* ThreadId
* ------------------------------------------------------
*/
@@ -51,9 +51,9 @@
/* Compute linear position */
mov x4, #PLAT_ARM_CLUSTER_COUNT
madd x2, x3, x4, x2
- mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
+ mov x4, #NRD_MAX_CPUS_PER_CLUSTER
madd x1, x2, x4, x1
- mov x4, #CSS_SGI_MAX_PE_PER_CPU
+ mov x4, #NRD_MAX_PE_PER_CPU
madd x0, x1, x4, x0
ret
endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h b/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h
index b303757..5a68960 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h
@@ -16,14 +16,14 @@
#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
PLAT_ARM_CLUSTER_COUNT * \
- CSS_SGI_MAX_CPUS_PER_CLUSTER * \
- CSS_SGI_MAX_PE_PER_CPU)
+ NRD_MAX_CPUS_PER_CLUSTER * \
+ NRD_MAX_PE_PER_CPU)
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
/* Remote chip address offset */
-#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n))
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
@@ -100,13 +100,13 @@
/*
* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
* calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
- * and BL1-RW. CSS_SGI_BL31_SIZE - is tuned with respect to the actual BL31
+ * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31
* PROGBITS size which is around 64-68KB at the time this change is being made.
* A buffer of ~35KB is added to account for future expansion of the image,
* making it a total of 100KB.
*/
-#define CSS_SGI_BL31_SIZE (116 * 1024) /* 116 KB */
-#define PLAT_ARM_MAX_BL31_SIZE (CSS_SGI_BL31_SIZE + \
+#define NRD_BL31_SIZE (116 * 1024) /* 116 KB */
+#define PLAT_ARM_MAX_BL31_SIZE (NRD_BL31_SIZE + \
PLAT_ARM_MAX_BL2_SIZE + \
PLAT_ARM_MAX_BL1_RW_SIZE)
@@ -167,32 +167,32 @@
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
-#define CSS_SGI_DEVICE_BASE (0x20000000)
-#define CSS_SGI_DEVICE_SIZE (0x20000000)
-#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \
- CSS_SGI_DEVICE_BASE, \
- CSS_SGI_DEVICE_SIZE, \
+#define NRD_DEVICE_BASE (0x20000000)
+#define NRD_DEVICE_SIZE (0x20000000)
+#define NRD_MAP_DEVICE MAP_REGION_FLAT( \
+ NRD_DEVICE_BASE, \
+ NRD_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \
MAP_REGION_FLAT( \
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
MT_NON_CACHEABLE | MT_RW | MT_SECURE \
)
-#define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \
+#define NRD_MAP_DEVICE_REMOTE_CHIP(n) \
MAP_REGION_FLAT( \
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
- CSS_SGI_DEVICE_BASE, \
- CSS_SGI_DEVICE_SIZE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_DEVICE_BASE, \
+ NRD_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE \
)
#define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \
MAP_REGION_FLAT( \
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
SOC_CSS_DEVICE_BASE, \
SOC_CSS_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE \
@@ -215,13 +215,13 @@
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
*/
-#define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+#define NRD_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
-#define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x10000)
-#define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \
- CSS_SGI_SP_CPER_BUF_BASE, \
- CSS_SGI_SP_CPER_BUF_BASE, \
- CSS_SGI_SP_CPER_BUF_SIZE, \
+#define NRD_SP_CPER_BUF_SIZE ULL(0x10000)
+#define NRD_SP_CPER_BUF_MMAP MAP_REGION2( \
+ NRD_SP_CPER_BUF_BASE, \
+ NRD_SP_CPER_BUF_BASE, \
+ NRD_SP_CPER_BUF_SIZE, \
MT_RW_DATA | MT_NS | MT_USER, \
PAGE_SIZE)
@@ -231,7 +231,7 @@
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE + \
- CSS_SGI_SP_CPER_BUF_SIZE)
+ NRD_SP_CPER_BUF_SIZE)
#elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
/*
* Secure partition stack follows right after the memory region that is shared
@@ -277,11 +277,11 @@
* to multi-chip platforms.
*/
#define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \
- {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
+ {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
+ {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
#if SPM_MM
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_dmc620_tzc_regions.h b/plat/arm/board/neoverse_rd/common/include/nrd_dmc620_tzc_regions.h
index a38c759..c63d750 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_dmc620_tzc_regions.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_dmc620_tzc_regions.h
@@ -10,7 +10,7 @@
#include <drivers/arm/tzc_dmc620.h>
#if SPM_MM
-#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
+#define NRD_DMC620_TZC_REGIONS_DEF \
{ \
.region_base = ARM_AP_TZC_DRAM1_BASE, \
.region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \
@@ -25,7 +25,7 @@
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}
#else
-#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
+#define NRD_DMC620_TZC_REGIONS_DEF \
{ \
.region_base = ARM_AP_TZC_DRAM1_BASE, \
.region_top = ARM_AP_TZC_DRAM1_END, \
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h
index 81cbdf4..c4e377b 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h
@@ -92,7 +92,7 @@
#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \
MAP_REGION_FLAT( \
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \
SOC_MEMCNTRL_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 0c6a162..a22c799 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -41,9 +41,9 @@
#if (NRD_CHIP_COUNT > 1)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ NRD_REMOTE_CHIP_MEM_OFFSET(1),
.db_reg_addr = PLAT_CSS_MHU_BASE
- + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
+ + NRD_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
@@ -52,9 +52,9 @@
#if (NRD_CHIP_COUNT > 2)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ NRD_REMOTE_CHIP_MEM_OFFSET(2),
.db_reg_addr = PLAT_CSS_MHU_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
+ NRD_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
@@ -63,9 +63,9 @@
#if (NRD_CHIP_COUNT > 3)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ NRD_REMOTE_CHIP_MEM_OFFSET(3),
.db_reg_addr = PLAT_CSS_MHU_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
+ NRD_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat.c b/plat/arm/board/neoverse_rd/common/nrd_plat.c
index 692139c..f2fd215 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat.c
@@ -37,7 +37,7 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
SGI_MAP_FLASH0_RO,
- CSS_SGI_MAP_DEVICE,
+ NRD_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
{0}
};
@@ -49,17 +49,17 @@
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- CSS_SGI_MAP_DEVICE,
+ NRD_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
#if NRD_CHIP_COUNT > 1
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if NRD_CHIP_COUNT > 2
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if NRD_CHIP_COUNT > 3
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+ NRD_MAP_DEVICE_REMOTE_CHIP(3),
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
@@ -77,7 +77,7 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
- CSS_SGI_MAP_DEVICE,
+ NRD_MAP_DEVICE,
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
@@ -97,7 +97,7 @@
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
#if ENABLE_FEAT_RAS && FFH_SUPPORT
- CSS_SGI_SP_CPER_BUF_MMAP,
+ NRD_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat_v2.c b/plat/arm/board/neoverse_rd/common/nrd_plat_v2.c
index c07117e..b39c8f0 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat_v2.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat_v2.c
@@ -25,7 +25,7 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
SGI_MAP_FLASH0_RO,
- CSS_SGI_MAP_DEVICE,
+ NRD_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
{0}
@@ -39,7 +39,7 @@
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- CSS_SGI_MAP_DEVICE,
+ NRD_MAP_DEVICE,
SOC_MEMCNTRL_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
@@ -72,7 +72,7 @@
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- CSS_SGI_MAP_DEVICE,
+ NRD_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
@@ -90,7 +90,7 @@
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
#if ENABLE_FEAT_RAS && FFH_SUPPORT
- CSS_SGI_SP_CPER_BUF_MMAP,
+ NRD_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,
diff --git a/plat/arm/board/neoverse_rd/common/nrd_topology.c b/plat/arm/board/neoverse_rd/common/nrd_topology.c
index 40be049..9113bd8 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_topology.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_topology.c
@@ -15,7 +15,7 @@
******************************************************************************/
unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
{
- return CSS_SGI_MAX_CPUS_PER_CLUSTER;
+ return NRD_MAX_CPUS_PER_CLUSTER;
}
#if ARM_PLAT_MT
@@ -24,6 +24,6 @@
*****************************************************************************/
unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
{
- return CSS_SGI_MAX_PE_PER_CPU;
+ return NRD_MAX_PE_PER_CPU;
}
#endif
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
index aa8702f..83590eb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
@@ -13,8 +13,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(4)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
@@ -31,15 +31,15 @@
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* Maximum number of address bits used per chip */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
+#define NRD_ADDR_BITS_PER_CHIP U(42)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
index 918728a..0c6756c 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
@@ -15,7 +15,7 @@
#if defined(IMAGE_BL31)
static const mmap_region_t rdn1edge_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
};
@@ -25,7 +25,7 @@
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
},
.spi_ids = {
{PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START,
@@ -37,7 +37,7 @@
static uintptr_t rdn1e1_multichip_gicr_frames[] = {
PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE +
- CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
+ NRD_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
UL(0) /* Zero Termination */
};
#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
index 959daea..f3f6238 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
@@ -20,7 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
- CSS_SGI_DMC620_TZC_REGIONS_DEF
+ NRD_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
index 2e81536..133eb16 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
@@ -12,11 +12,11 @@
******************************************************************************/
static const unsigned char rdn1edge_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#if (NRD_CHIP_COUNT > 1)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
index 3892c66..840ea4a 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
@@ -19,8 +19,8 @@
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x2A920000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
@@ -69,14 +69,14 @@
*/
#ifdef __aarch64__
#if (NRD_PLATFORM_VARIANT == 2)
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */
+#define NRD_ADDR_BITS_PER_CHIP U(46) /* 64TB */
#else
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */
+#define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */
#endif
-#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
index 24072ca..0051049 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
@@ -19,15 +19,15 @@
static const mmap_region_t rdn2mc_dynamic_mmap[] = {
#if NRD_CHIP_COUNT > 1
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if NRD_CHIP_COUNT > 2
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if NRD_CHIP_COUNT > 3
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+ NRD_MAP_DEVICE_REMOTE_CHIP(3),
#endif
};
#endif
@@ -40,13 +40,13 @@
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
#if NRD_CHIP_COUNT > 1
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#endif
#if NRD_CHIP_COUNT > 2
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if NRD_CHIP_COUNT > 3
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
.spi_ids = {
@@ -70,15 +70,15 @@
PLAT_ARM_GICR_BASE,
#if NRD_CHIP_COUNT > 1
/* Chip 1's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
#endif
#if NRD_CHIP_COUNT > 2
/* Chip 2's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if NRD_CHIP_COUNT > 3
/* Chip 3's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
#endif
UL(0) /* Zero Termination */
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
index 3cdc0d3..8ec8345 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
@@ -8,9 +8,9 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
-#define RDN2_TZC_CPER_REGION \
- {CSS_SGI_SP_CPER_BUF_BASE, (CSS_SGI_SP_CPER_BUF_BASE + \
- CSS_SGI_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
+#define RDN2_TZC_CPER_REGION \
+ {NRD_SP_CPER_BUF_BASE, (NRD_SP_CPER_BUF_BASE + \
+ NRD_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
static const arm_tzc_regions_info_t tzc_regions[] = {
@@ -63,7 +63,7 @@
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {
- arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
+ TZC400_BASE(j), tzc_regions_mc[i-1]);
}
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
index 1dea43e..b8b6b7a 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
@@ -12,30 +12,30 @@
******************************************************************************/
const unsigned char rd_n2_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1))
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 2))
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 3))
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
index 7eca2bd..f889561 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
@@ -12,8 +12,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
@@ -47,14 +47,14 @@
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/* Maximum number of address bits used per chip */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
+#define NRD_ADDR_BITS_PER_CHIP U(42)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
index 5ae20dd..20e4266 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
@@ -12,22 +12,22 @@
******************************************************************************/
const unsigned char rd_v1_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
index c0f8ebd..3e7c9b5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
@@ -11,8 +11,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(4)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
@@ -47,12 +47,12 @@
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
/* Remote chip address offset (4TB per chip) */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
+#define NRD_ADDR_BITS_PER_CHIP U(42)
/* Physical and virtual address space limits for MMU in AARCH64 mode */
-#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
/* GIC related constants */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
index 820c7e5..4455ec4 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
@@ -15,16 +15,16 @@
#if defined(IMAGE_BL31)
static const mmap_region_t rdv1mc_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
#if (NRD_CHIP_COUNT > 2)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_MAP_DEVICE_REMOTE_CHIP(2),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if (NRD_CHIP_COUNT > 3)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
- CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+ NRD_MAP_DEVICE_REMOTE_CHIP(3),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
#endif
};
@@ -35,12 +35,12 @@
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#if (NRD_CHIP_COUNT > 2)
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if (NRD_CHIP_COUNT > 3)
- (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
.spi_ids = {
@@ -60,14 +60,14 @@
/* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE,
/* Chip 1's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
#if (NRD_CHIP_COUNT > 2)
/* Chip 2's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if (NRD_CHIP_COUNT > 3)
/* Chip 3's GICR BASE */
- PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
#endif
UL(0) /* Zero Termination */
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
index 8f371c5..d437def 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
@@ -56,7 +56,7 @@
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {
- arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
+ TZC400_BASE(j), tzc_regions_mc[i-1]);
}
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
index d0eeb1d..52514ca 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
@@ -15,27 +15,27 @@
******************************************************************************/
const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
((PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT)),
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#if (NRD_CHIP_COUNT > 1)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (NRD_CHIP_COUNT > 2)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
#endif
#if (NRD_CHIP_COUNT > 3)
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
index 7cc5366..9658ee1 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
@@ -13,8 +13,8 @@
#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(4)
+#define NRD_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45000000)
@@ -28,14 +28,14 @@
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* Maximum number of address bits used per chip */
-#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
+#define NRD_ADDR_BITS_PER_CHIP U(36)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
index 00b49e2..8b8a382 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
@@ -20,7 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
- CSS_SGI_DMC620_TZC_REGIONS_DEF
+ NRD_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
index 9f5e18a..15ffc65 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
@@ -11,8 +11,8 @@
******************************************************************************/
static const unsigned char sgi575_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************