| commit | a8e530a246754ff3d4d97d52ea6bc925b2992339 | [log] [tgz] |
|---|---|---|
| author | Karl Li <karl.li@mediatek.corp-partner.google.com> | Thu Aug 24 14:14:45 2023 +0800 |
| committer | developer <developer@mediatek.com> | Tue Oct 03 13:27:18 2023 +0800 |
| tree | a03917079a8db018beca519cec4d41b6d6245711 | |
| parent | e581ac479ba258fdd1bbc01b6b1e8cbc7f0ed875 [diff] [blame] |
feat(mt8188): add DSB before udelay To ensure that all explicit memory accesses are complete before udelay, insert dsb before udelay. Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c index c1b3de0..86c4b81 100644 --- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c +++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -88,6 +88,7 @@ mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST); + dsb(); udelay(RESET_DEALY_US); mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN |