commit a8e530a246754ff3d4d97d52ea6bc925b2992339
author Karl Li <karl.li@mediatek.corp-partner.google.com> Thu Aug 24 14:14:45 2023 +0800
committer developer <developer@mediatek.com> Tue Oct 03 13:27:18 2023 +0800
tree a03917079a8db018beca519cec4d41b6d6245711
parent e581ac479ba258fdd1bbc01b6b1e8cbc7f0ed875

feat(mt8188): add DSB before udelay

To ensure that all explicit memory accesses are complete before udelay,
insert dsb before udelay.

Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a

plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c

diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
index c1b3de0..86c4b81 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -88,6 +88,7 @@
 
 	mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
 
+	dsb();
 	udelay(RESET_DEALY_US);
 
 	mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN |

plat/mediatek/drivers/apusys/mt8188/apusys_power.c

diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
index cdfc133..0a2781b 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
@@ -37,7 +37,6 @@
 		if ((reg_val & mask) == value) {
 			return 0;
 		}
-
 		udelay(APU_POLL_STEP_US);
 	} while (--count);
 
@@ -169,15 +168,19 @@
 static void apu_sleep_rpc_rcx(void)
 {
 	mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR);
+	dsb();
 	udelay(10);
 
 	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10));
+	dsb();
 	udelay(10);
 
 	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ);
+	dsb();
 	udelay(10);
 
 	mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ);
+	dsb();
 	udelay(100);
 }
 
@@ -313,12 +316,15 @@
 static void apu_buck_off_cfg(void)
 {
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET);
+	dsb();
 	udelay(10);
 
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_SET);
+	dsb();
 	udelay(10);
 
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_CLR);
+	dsb();
 	udelay(10);
 }
 
@@ -425,15 +431,19 @@
 {
 	mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO);
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_CLR);
+	dsb();
 	udelay(10);
 
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_SET);
+	dsb();
 	udelay(10);
 
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_CLR);
+	dsb();
 	udelay(10);
 
 	mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, SRAM_AOC_ISO_CLR);
+	dsb();
 	udelay(10);
 }