refactor(ast2700): adopt RESET_TO_BL31 boot flow
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initialization are moved to a preceding MCU.
This patch updates the build configuration and also adds
the SMP mailbox setup code to hold secondary cores until
they are being waken up.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
diff --git a/docs/plat/ast2700.rst b/docs/plat/ast2700.rst
index 0352aea..6deade3 100644
--- a/docs/plat/ast2700.rst
+++ b/docs/plat/ast2700.rst
@@ -7,11 +7,11 @@
Boot Flow
---------
- BootRom --> BL1/BL2 --> TF-A BL31 --> BL32 (optional) --> BL33 --> Linux Kernel
+ BootRom --> TF-A BL31 --> BL32 --> BL33 --> Linux Kernel
How to build
------------
.. code:: shell
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700 SPD=opteed
diff --git a/plat/aspeed/ast2700/include/platform_reg.h b/plat/aspeed/ast2700/include/platform_reg.h
index 20ae32a..7f26865 100644
--- a/plat/aspeed/ast2700/include/platform_reg.h
+++ b/plat/aspeed/ast2700/include/platform_reg.h
@@ -18,11 +18,10 @@
#define UART12_BASE (UART_BASE + 0xb00)
/* CPU-die SCU */
-#define SCU_CPU_BASE U(0x12c02000)
-#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780)
-#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
-#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
-#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798)
-#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0)
+#define SCU_CPU_BASE U(0x12c02000)
+#define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780)
+#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
+#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
+#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798)
#endif /* PLATFORM_REG_H */
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c
index 36e7338..fde5dbb 100644
--- a/plat/aspeed/ast2700/plat_bl31_setup.c
+++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -10,6 +10,7 @@
#include <drivers/arm/gicv3.h>
#include <drivers/console.h>
#include <drivers/ti/uart/uart_16550.h>
+#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -55,7 +56,14 @@
console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
- bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
+ SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_2, 0);
+ bl32_ep_info.pc = BL32_BASE;
+ SET_SECURITY_STATE(bl32_ep_info.h.attr, SECURE);
+
+ SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_2, 0);
+ bl33_ep_info.pc = mmio_read_64(SCU_CPU_SMP_EP0);
+ bl33_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE);
}
void bl31_plat_arch_setup(void)
diff --git a/plat/aspeed/ast2700/plat_helpers.S b/plat/aspeed/ast2700/plat_helpers.S
index 1457692..c6d987e 100644
--- a/plat/aspeed/ast2700/plat_helpers.S
+++ b/plat/aspeed/ast2700/plat_helpers.S
@@ -10,6 +10,7 @@
#include <cortex_a35.h>
#include <platform_def.h>
+ .globl platform_mem_init
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl plat_secondary_cold_boot_setup
@@ -18,6 +19,12 @@
.globl plat_crash_console_putc
.globl plat_crash_console_flush
+/* void platform_mem_init(void); */
+func platform_mem_init
+ /* DRAM init. is done by preceding MCU */
+ ret
+endfunc platform_mem_init
+
/* unsigned int plat_is_my_cpu_primary(void); */
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
@@ -37,6 +44,21 @@
ret
endfunc plat_my_core_pos
+/* void plat_secondary_cold_boot_setup (void); */
+func plat_secondary_cold_boot_setup
+ mov x0, xzr
+ bl plat_my_core_pos
+ mov_imm x1, SCU_CPU_SMP_EP0
+ add x1, x1, x0, lsl #3
+
+poll_smp_mbox_go:
+ wfe
+ ldr x0, [x1]
+ cmp x0, xzr
+ beq poll_smp_mbox_go
+ br x0
+endfunc plat_secondary_cold_boot_setup
+
/* unsigned int plat_get_syscnt_freq2(void); */
func plat_get_syscnt_freq2
mov_imm w0, PLAT_SYSCNT_CLKIN_HZ
diff --git a/plat/aspeed/ast2700/platform.mk b/plat/aspeed/ast2700/platform.mk
index 16ecf0a..873c60e 100644
--- a/plat/aspeed/ast2700/platform.mk
+++ b/plat/aspeed/ast2700/platform.mk
@@ -25,8 +25,10 @@
${GICV3_SOURCES} \
${XLAT_TABLES_LIB_SRCS}
+RESET_TO_BL31 := 1
+
PROGRAMMABLE_RESET_ADDRESS := 1
-COLD_BOOT_SINGLE_CPU := 1
+COLD_BOOT_SINGLE_CPU := 0
ENABLE_SVE_FOR_NS := 0