fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 34fa2e9..5b439c9 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -986,6 +986,12 @@
Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1
and r0p2. It is still open.
+For Cortex-A720_AE, the following errata build flags are defined :
+
+- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround
+ to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0.
+ It is still open.
+
DSU Errata Workarounds
----------------------