Merge pull request #233 from jcastillo-arm/jc/tf-issues/254
Juno: Add support for image overlaying in Trusted SRAM
diff --git a/Makefile b/Makefile
index 8979f7f..c82c7a2 100644
--- a/Makefile
+++ b/Makefile
@@ -63,6 +63,8 @@
# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
# This defaults to being present in DEBUG builds only.
ASM_ASSERTION := ${DEBUG}
+# Default FIP file name
+FIP_NAME := fip.bin
# Checkpatch ignores
CHECK_IGNORE = --ignore COMPLEX_MACRO
@@ -256,7 +258,7 @@
FIPTOOLPATH ?= tools/fip_create
FIPTOOL ?= ${FIPTOOLPATH}/fip_create
fiptool: ${FIPTOOL}
-fip: ${BUILD_PLAT}/fip.bin
+fip: ${BUILD_PLAT}/${FIP_NAME}
locate-checkpatch:
ifndef CHECKPATCH
@@ -485,7 +487,7 @@
endif
-${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${FIPTOOL} check_bl30 check_bl33
+${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} check_bl30 check_bl33
${Q}${FIPTOOL} --dump \
${FIP_ARGS} \
$@
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index a73946e..b7e2cff 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -61,6 +61,7 @@
*/
INFO("BL2: Loading BL3-0\n");
bl2_plat_get_bl30_meminfo(&bl30_mem_info);
+ bl30_image_info.h.version = VERSION_1;
e = load_image(&bl30_mem_info,
BL30_IMAGE_NAME,
BL30_BASE,
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index 246381a..b913f5f 100644
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -4,9 +4,10 @@
Contents
--------
-1. Introduction
-2. CPU Errata Workarounds
-3. CPU Specific optimizations
+1. [Introduction](#1--introduction)
+2. [CPU Errata Workarounds](#2--cpu-errata-workarounds)
+3. [CPU Specific optimizations](#3--cpu-specific-optimizations)
+
1. Introduction
----------------
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index e40ca96..41aaf7f 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -3,17 +3,17 @@
Contents :
-1. Introduction
-2. Cold boot
-3. EL3 runtime services framework
-4. Power State Coordination Interface
-5. Secure-EL1 Payloads and Dispatchers
-6. Crash Reporting in BL3-1
-7. CPU specific operations framework
-8. Memory layout of BL images
-9. Firmware Image Package (FIP)
-10. Code Structure
-11. References
+1. [Introduction](#1--introduction)
+2. [Cold boot](#2--cold-boot)
+3. [EL3 runtime services framework](#3--el3-runtime-services-framework)
+4. [Power State Coordination Interface](#4--power-state-coordination-interface)
+5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers)
+6. [Crash Reporting in BL3-1](#6--crash-reporting-in-bl3-1)
+7. [CPU specific operations framework](#7--cpu-specific-operations-framework)
+8. [Memory layout of BL images](#8-memory-layout-of-bl-images)
+9. [Firmware Image Package (FIP)](#9--firmware-image-package-fip)
+10. [Code Structure](#10--code-structure)
+11. [References](#11--references)
1. Introduction
diff --git a/docs/interrupt-framework-design.md b/docs/interrupt-framework-design.md
index d620f3b..ff001b1 100644
--- a/docs/interrupt-framework-design.md
+++ b/docs/interrupt-framework-design.md
@@ -3,37 +3,37 @@
Contents :
-1. Introduction
- * Assumptions
- * Concepts
- - Interrupt Types
- - Routing Model
- - Valid Routing Models
- + Secure-EL1 Interrupts
- + Non-secure Interrupts
- - Mapping of Interrupt Type to Signal
+1. [Introduction](#1-introduction)
+ * [Assumptions](#11-assumptions)
+ * [Concepts](#12-concepts)
+ - [Interrupt Types](#121-interrupt-types)
+ - [Routing Model](#122-routing-model)
+ - [Valid Routing Models](#123-valid-routing-models)
+ + [Secure-EL1 Interrupts](#1231-secure-el1-interrupts)
+ + [Non-secure Interrupts](#1232-non-secure-interrupts)
+ - [Mapping of Interrupt Type to Signal](#124-mapping-of-interrupt-type-to-signal)
-2. Interrupt Management
- * Software Components
- * Interrupt Registration
- - EL3 Runtime Firmware
- - Secure Payload Dispatcher
- + Test Secure Payload Dispatcher behavior
- - Secure Payload
- + Secure Payload IHF design w.r.t Secure-EL1 interrupts
- + Secure Payload IHF design w.r.t Non-secure interrupts
- + Test Secure Payload behavior
- * Interrupt Handling
- - EL3 Runtime Firmware
- - Secure Payload Dispatcher
- + Interrupt Entry
- + Interrupt Exit
- + Test Secure Payload Dispatcher behavior
- - Secure Payload
- + Test Secure Payload behavior
+2. [Interrupt Management](#2-interrupt-management)
+ * [Software Components](#21-software-components)
+ * [Interrupt Registration](#22-interrupt-registration)
+ - [EL3 Runtime Firmware](#221-el3-runtime-firmware)
+ - [Secure Payload Dispatcher](#222-secure-payload-dispatcher)
+ + [Test Secure Payload Dispatcher behavior](#2221-test-secure-payload-dispatcher-behavior)
+ - [Secure Payload](#223-secure-payload)
+ + [Secure Payload IHF design w.r.t Secure-EL1 interrupts](#2231-secure-payload-ihf-design-wrt-secure-el1-interrupts)
+ + [Secure Payload IHF design w.r.t Non-secure interrupts](#2232-secure-payload-ihf-design-wrt-non-secure-interrupts)
+ + [Test Secure Payload behavior](#2233-test-secure-payload-behavior)
+ * [Interrupt Handling](#23-interrupt-handling)
+ - [EL3 Runtime Firmware](#231-el3-runtime-firmware)
+ - [Secure Payload Dispatcher](#232-secure-payload-dispatcher)
+ + [Interrupt Entry](#2321-interrupt-entry)
+ + [Interrupt Exit](#2322-interrupt-exit)
+ + [Test Secure Payload Dispatcher behavior](#2323-test-secure-payload-dispatcher-behavior)
+ - [Secure Payload](#233-secure-payload)
+ + [Test Secure Payload behavior](#2331-test-secure-payload-behavior)
-1. Introduction
+1. Introduction
----------------
This document describes the design of the Interrupt management framework in ARM
Trusted Firmware. This section briefly describes the requirements from this
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 7831a27..3855ca7 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -4,21 +4,21 @@
Contents
--------
-1. Introduction
-2. Common Modifications
- * Common mandatory modifications
- * Handling reset
- * Common optional modifications
-3. Boot Loader stage specific modifications
- * Boot Loader stage 1 (BL1)
- * Boot Loader stage 2 (BL2)
- * Boot Loader stage 3-1 (BL3-1)
- * PSCI implementation (in BL3-1)
- * Interrupt Management framework (in BL3-1)
- * Crash Reporting mechanism (in BL3-1)
-4. Build flags
-5. C Library
-6. Storage abstraction layer
+1. [Introduction](#1--introduction)
+2. [Common Modifications](#2--common-modifications)
+ * [Common mandatory modifications](#21-common-mandatory-modifications)
+ * [Handling reset](#22-handling-reset)
+ * [Common optional modifications](#23-common-optional-modifications)
+3. [Boot Loader stage specific modifications](#3--modifications-specific-to-a-boot-loader-stage)
+ * [Boot Loader stage 1 (BL1)](#31-boot-loader-stage-1-bl1)
+ * [Boot Loader stage 2 (BL2)](#32-boot-loader-stage-2-bl2)
+ * [Boot Loader stage 3-1 (BL3-1)](#32-boot-loader-stage-3-1-bl3-1)
+ * [PSCI implementation (in BL3-1)](#33-power-state-coordination-interface-in-bl3-1)
+ * [Interrupt Management framework (in BL3-1)](#34--interrupt-management-framework-in-bl3-1)
+ * [Crash Reporting mechanism (in BL3-1)](#35--crash-reporting-mechanism-in-bl3-1)
+4. [Build flags](#4--build-flags)
+5. [C Library](#5--c-library)
+6. [Storage abstraction layer](#6--storage-abstraction-layer)
- - - - - - - - - - - - - - - - - -
diff --git a/docs/rt-svc-writers-guide.md b/docs/rt-svc-writers-guide.md
index 2d13f74..c39a495 100644
--- a/docs/rt-svc-writers-guide.md
+++ b/docs/rt-svc-writers-guide.md
@@ -4,14 +4,14 @@
Contents
--------
-1. Introduction
-2. Owning Entities, Call Types and Function IDs
-3. Getting started
-4. Registering a runtime service
-5. Initializing a runtime service
-6. Handling runtime service requests
-7. Services that contain multiple sub-services
-8. Secure-EL1 Payload Dispatcher service (SPD)
+1. [Introduction](#1--introduction)
+2. [Owning Entities, Call Types and Function IDs](#2--owning-entities-call-types-and-function-ids)
+3. [Getting started](#3--getting-started)
+4. [Registering a runtime service](#4--registering-a-runtime-service)
+5. [Initializing a runtime service](#5-initializing-a-runtime-service)
+6. [Handling runtime service requests](#6--handling-runtime-service-requests)
+7. [Services that contain multiple sub-services](#7--services-that-contain-multiple-sub-services)
+8. [Secure-EL1 Payload Dispatcher service (SPD)](#8--secure-el1-payload-dispatcher-service-spd)
- - - - - - - - - - - - - - - - - -
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 0b95a1b..b33c4c0 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -3,15 +3,15 @@
Contents :
-1. Introduction
-2. Host machine requirements
-3. Tools
-4. Building the Trusted Firmware
-5. Obtaining the normal world software
-6. Preparing the images to run on FVP
-7. Running the software on FVP
-8. Preparing the images to run on Juno
-9. Running the software on Juno
+1. [Introduction](#1--introduction)
+2. [Host machine requirements](#2--host-machine-requirements)
+3. [Tools](#3--tools)
+4. [Building the Trusted Firmware](#4--building-the-trusted-firmware)
+5. [Obtaining the normal world software](#5--obtaining-the-normal-world-software)
+6. [Preparing the images to run on FVP](#6--preparing-the-images-to-run-on-fvp)
+7. [Running the software on FVP](#7--running-the-software-on-fvp)
+8. [Preparing the images to run on Juno](#8--preparing-the-images-to-run-on-juno)
+9. [Running the software on Juno](#9--running-the-software-on-juno)
1. Introduction
@@ -176,6 +176,9 @@
BL3-2 image for the `fip` target. In this case, the BL3-2 in the ARM
Trusted Firmware will not be built.
+* `FIP_NAME`: This is an optional build option which specifies the FIP
+ filename for the `fip` target. Default is `fip.bin`.
+
* `CROSS_COMPILE`: Prefix to toolchain binaries. Please refer to examples in
this document for usage.
@@ -697,7 +700,7 @@
<path-to>/Foundation_v8 \
--cores=4 \
- --no-secure-memory \
+ --secure-memory \
--visualization \
--gicv3 \
--data="<path-to>/<bl1-binary>"@0x0 \
@@ -814,16 +817,16 @@
-C cluster1.NUM_CORES=4 \
-C cache_state_modelled=1 \
-C bp.pl011_uart0.untimed_fifos=1 \
- -C cluster0.cpu0.RVBAR=0x04022000 \
- -C cluster0.cpu1.RVBAR=0x04022000 \
- -C cluster0.cpu2.RVBAR=0x04022000 \
- -C cluster0.cpu3.RVBAR=0x04022000 \
- -C cluster1.cpu0.RVBAR=0x04022000 \
- -C cluster1.cpu1.RVBAR=0x04022000 \
- -C cluster1.cpu2.RVBAR=0x04022000 \
- -C cluster1.cpu3.RVBAR=0x04022000 \
- --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04022000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04000000 \
+ -C cluster0.cpu0.RVBAR=0x04023000 \
+ -C cluster0.cpu1.RVBAR=0x04023000 \
+ -C cluster0.cpu2.RVBAR=0x04023000 \
+ -C cluster0.cpu3.RVBAR=0x04023000 \
+ -C cluster1.cpu0.RVBAR=0x04023000 \
+ -C cluster1.cpu1.RVBAR=0x04023000 \
+ -C cluster1.cpu2.RVBAR=0x04023000 \
+ -C cluster1.cpu3.RVBAR=0x04023000 \
+ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
@@ -841,16 +844,16 @@
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
-C bp.pl011_uart0.untimed_fifos=1 \
- -C cluster0.cpu0.RVBARADDR=0x04022000 \
- -C cluster0.cpu1.RVBARADDR=0x04022000 \
- -C cluster0.cpu2.RVBARADDR=0x04022000 \
- -C cluster0.cpu3.RVBARADDR=0x04022000 \
- -C cluster1.cpu0.RVBARADDR=0x04022000 \
- -C cluster1.cpu1.RVBARADDR=0x04022000 \
- -C cluster1.cpu2.RVBARADDR=0x04022000 \
- -C cluster1.cpu3.RVBARADDR=0x04022000 \
- --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04022000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04000000 \
+ -C cluster0.cpu0.RVBARADDR=0x04023000 \
+ -C cluster0.cpu1.RVBARADDR=0x04023000 \
+ -C cluster0.cpu2.RVBARADDR=0x04023000 \
+ -C cluster0.cpu3.RVBARADDR=0x04023000 \
+ -C cluster1.cpu0.RVBARADDR=0x04023000 \
+ -C cluster1.cpu1.RVBARADDR=0x04023000 \
+ -C cluster1.cpu2.RVBARADDR=0x04023000 \
+ -C cluster1.cpu3.RVBARADDR=0x04023000 \
+ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
@@ -900,7 +903,7 @@
<path-to>/Foundation_v8 \
--cores=4 \
- --no-secure-memory \
+ --secure-memory \
--visualization \
--no-gicv3 \
--data="<path-to>/<bl1-binary>"@0x0 \
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index d431baa..7320a0a 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -40,24 +40,24 @@
* registers
*********************************************************************/
-#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
-static inline uint64_t read_ ## _name(void) \
-{ \
- uint64_t v; \
- __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
- return v; \
+#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
+static inline uint64_t read_ ## _name(void) \
+{ \
+ uint64_t v; \
+ __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
+ return v; \
}
-#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
-static inline void write_ ## _name(uint64_t v) \
-{ \
- __asm__ ("msr " #_reg_name ", %0" : : "r" (v)); \
+#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
+static inline void write_ ## _name(uint64_t v) \
+{ \
+ __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
}
#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
-static inline void write_ ## _name(const uint64_t v) \
-{ \
- __asm__ ("msr " #_reg_name ", %0" : : "i" (v)); \
+static inline void write_ ## _name(const uint64_t v) \
+{ \
+ __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
}
/* Define read function for system register */
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index 99c23d8..06f2a64 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -209,7 +209,6 @@
#define IRQ_SEC_SGI_5 13
#define IRQ_SEC_SGI_6 14
#define IRQ_SEC_SGI_7 15
-#define IRQ_SEC_SGI_8 16
/*******************************************************************************
* PL011 related constants
diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h
index cfcbe0b..8e1a83d 100644
--- a/plat/juno/juno_def.h
+++ b/plat/juno/juno_def.h
@@ -158,7 +158,6 @@
#define IRQ_SEC_SGI_5 13
#define IRQ_SEC_SGI_6 14
#define IRQ_SEC_SGI_7 15
-#define IRQ_SEC_SGI_8 16
/*******************************************************************************
* PL011 related constants
diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c
index 2267ad0..155f842 100644
--- a/services/std_svc/psci/psci_common.c
+++ b/services/std_svc/psci/psci_common.c
@@ -201,7 +201,7 @@
int psci_check_afflvl_range(int start_afflvl, int end_afflvl)
{
/* Sanity check the parameters passed */
- if (end_afflvl > MPIDR_MAX_AFFLVL)
+ if (end_afflvl > get_max_afflvl())
return PSCI_E_INVALID_PARAMS;
if (start_afflvl < MPIDR_AFFLVL0)
diff --git a/services/std_svc/psci/psci_main.c b/services/std_svc/psci/psci_main.c
index 0ffa5d7..2e700e8 100644
--- a/services/std_svc/psci/psci_main.c
+++ b/services/std_svc/psci/psci_main.c
@@ -86,7 +86,7 @@
/* Sanity check the requested state */
target_afflvl = psci_get_pstate_afflvl(power_state);
- if (target_afflvl > MPIDR_MAX_AFFLVL)
+ if (target_afflvl > get_max_afflvl())
return PSCI_E_INVALID_PARAMS;
/* Determine the 'state type' in the 'power_state' parameter */
diff --git a/services/std_svc/psci/psci_setup.c b/services/std_svc/psci/psci_setup.c
index a5ae4ef..8e9d15d 100644
--- a/services/std_svc/psci/psci_setup.c
+++ b/services/std_svc/psci/psci_setup.c
@@ -77,12 +77,18 @@
return PSCI_E_INVALID_PARAMS;
/*
+ * Make sure we are within array limits.
+ */
+ assert(min_idx >= 0 && max_idx < PSCI_NUM_AFFS);
+
+ /*
* Bisect the array around 'mid' and then recurse into the array chunk
* where the key is likely to be found. The mpidrs in each node in the
* 'psci_aff_map' for a given affinity level are stored in an ascending
* order which makes the binary search possible.
*/
mid = min_idx + ((max_idx - min_idx) >> 1); /* Divide by 2 */
+
if (psci_aff_map[mid].mpidr > key)
return psci_aff_map_get_idx(key, min_idx, mid - 1);
else if (psci_aff_map[mid].mpidr < key)
@@ -95,6 +101,9 @@
{
int rc;
+ if (aff_lvl > get_max_afflvl())
+ return NULL;
+
/* Right shift the mpidr to the required affinity level */
mpidr = mpidr_mask_lower_afflvls(mpidr, aff_lvl);
diff --git a/tools/fip_create/fip_create.c b/tools/fip_create/fip_create.c
index d1802b7..c940c5b 100644
--- a/tools/fip_create/fip_create.c
+++ b/tools/fip_create/fip_create.c
@@ -543,7 +543,7 @@
if (status != 0) {
printf("Failed to process %s\n",
options[option_index].name);
- break;
+ return status;
} else {
/* Update package */
*do_pack = 1;