Merge "refactor(cm): minor update on conditions used in prepare_el3_exit" into integration
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 5c8f03c..8775ab4 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -959,8 +959,8 @@
scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
CTX_SCR_EL3);
- if (((scr_el3 & SCR_HCE_BIT) != 0U)
- || (el2_implemented != EL_IMPL_NONE)) {
+ if (el2_implemented != EL_IMPL_NONE) {
+
/*
* If context is not being used for EL2, initialize
* HCRX_EL2 with its init value here.
@@ -986,28 +986,32 @@
write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
}
- }
- if ((scr_el3 & SCR_HCE_BIT) != 0U) {
- /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
- sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_SCTLR_EL1);
- sctlr_elx &= SCTLR_EE_BIT;
- sctlr_elx |= SCTLR_EL2_RES1;
+ /* Condition to ensure EL2 is being used. */
+ if ((scr_el3 & SCR_HCE_BIT) != 0U) {
+ /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
+ sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SCTLR_EL1);
+ sctlr_elx &= SCTLR_EE_BIT;
+ sctlr_elx |= SCTLR_EL2_RES1;
#if ERRATA_A75_764081
- /*
- * If workaround of errata 764081 for Cortex-A75 is used
- * then set SCTLR_EL2.IESB to enable Implicit Error
- * Synchronization Barrier.
- */
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
- write_sctlr_el2(sctlr_elx);
- } else if (el2_implemented != EL_IMPL_NONE) {
- init_nonsecure_el2_unused(ctx);
+ /*
+ * If workaround of errata 764081 for Cortex-A75
+ * is used then set SCTLR_EL2.IESB to enable
+ * Implicit Error Synchronization Barrier.
+ */
+ sctlr_elx |= SCTLR_IESB_BIT;
+#endif /* ERRATA_A75_764081 */
+ write_sctlr_el2(sctlr_elx);
+ } else {
+ /*
+ * (scr_el3 & SCR_HCE_BIT==0)
+ * EL2 implemented but unused.
+ */
+ init_nonsecure_el2_unused(ctx);
+ }
}
}
-
cm_el1_sysregs_context_restore(security_state);
cm_set_next_eret_context(security_state);
}