rockchip: add support for rk3288
The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features
with later SoCs.
Working features are general non-secure mode (the gic needs special
love for that), psci-based smp bringing cpu cores online and also
taking them offline again, psci-based suspend (the simpler variant
also included in the linux kernel, deeper suspend following later)
and I was also already able to test HYP-mode and was able to boot
a virtual kernel using kvm.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibaaa583b2e78197591a91d254339706fe732476a
diff --git a/plat/rockchip/rk3288/include/shared/bl32_param.h b/plat/rockchip/rk3288/include/shared/bl32_param.h
new file mode 100644
index 0000000..743dad4
--- /dev/null
+++ b/plat/rockchip/rk3288/include/shared/bl32_param.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BL32_PARAM_H
+#define BL32_PARAM_H
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+/* TF txet, ro, rw, Size: 2MB */
+#define TZRAM_BASE (0x0)
+#define TZRAM_SIZE (0x200000)
+
+/*******************************************************************************
+ * BL32 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL32 at the top of the Trusted RAM
+ */
+#define BL32_BASE (TZRAM_BASE + 0x100000)
+#define BL32_LIMIT (TZRAM_BASE + TZRAM_SIZE)
+
+#endif /* BL32_PARAM_H */