| commit | 8666b3c4c7dfe499ff00ae6203acd47d914ebf98 | [log] [tgz] |
|---|---|---|
| author | Maninder Singh <maninder.singh_1@nxp.com> | Mon Jan 31 02:16:10 2022 -0700 |
| committer | Jiafei Pan <Jiafei.Pan@nxp.com> | Tue Nov 22 16:35:19 2022 +0800 |
| tree | 09e149b897602df6ee7764f4ad7dfcec0e84a9bf | |
| parent | 2174f321f6b48ab1fe60b6d63c622595a57979bc [diff] |
fix(nxp-ddr): apply Max CDD values for warm boot Timing CFG 0 and Timing CFG 4 are ddr controller registers that have been affected by 1d phy training during cold boot. They are needed to be stored and restored along with phy training values. Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466