tree 09e149b897602df6ee7764f4ad7dfcec0e84a9bf
parent 2174f321f6b48ab1fe60b6d63c622595a57979bc
author Maninder Singh <maninder.singh_1@nxp.com> 1643620570 -0700
committer Jiafei Pan <Jiafei.Pan@nxp.com> 1669106119 +0800

fix(nxp-ddr): apply Max CDD values for warm boot

Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466