| /* |
| * Copyright (c) 2023-2024, Arm Limited. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| /* If SCMI power domain control is enabled */ |
| #if TC_SCMI_PD_CTRL_EN |
| #define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) |
| #define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) |
| #endif /* TC_SCMI_PD_CTRL_EN */ |
| |
| /* Use SCMI controlled clocks */ |
| #if TC_DPU_USE_SCMI_CLK |
| #define DPU_CLK_ATTR1 \ |
| clocks = <&scmi_clk 0>; \ |
| clock-names = "aclk" |
| |
| #define DPU_CLK_ATTR2 \ |
| clocks = <&scmi_clk 1>; \ |
| clock-names = "pxclk" |
| |
| #define DPU_CLK_ATTR3 \ |
| clocks = <&scmi_clk 2>; \ |
| clock-names = "pxclk" \ |
| /* Use fixed clocks */ |
| #else /* !TC_DPU_USE_SCMI_CLK */ |
| #define DPU_CLK_ATTR1 \ |
| clocks = <&dpu_aclk>; \ |
| clock-names = "aclk" |
| |
| #define DPU_CLK_ATTR2 \ |
| clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ |
| clock-names = "pxclk", "aclk" |
| |
| #define DPU_CLK_ATTR3 DPU_CLK_ATTR2 |
| #endif /* !TC_DPU_USE_SCMI_CLK */ |
| |
| / { |
| #if !TC_DPU_USE_SCMI_CLK |
| dpu_aclk: dpu_aclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <VENCODER_TIMING_CLK>; |
| clock-output-names = "fpga:dpu_aclk"; |
| }; |
| |
| dpu_pixel_clk: dpu-pixel-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <VENCODER_TIMING_CLK>; |
| clock-output-names = "pxclk"; |
| }; |
| #endif /* !TC_DPU_USE_SCMI_CLK */ |
| }; |