| /* |
| * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #include <arch.h> |
| #include <asm_macros.S> |
| #include <assert_macros.S> |
| #include <cortex_a57.h> |
| #include <cpu_macros.S> |
| #include <plat_macros.S> |
| |
| /* --------------------------------------------- |
| * Disable L1 data cache and unified L2 cache |
| * --------------------------------------------- |
| */ |
| func cortex_a57_disable_dcache |
| mrs x1, sctlr_el3 |
| bic x1, x1, #SCTLR_C_BIT |
| msr sctlr_el3, x1 |
| isb |
| ret |
| |
| /* --------------------------------------------- |
| * Disable all types of L2 prefetches. |
| * --------------------------------------------- |
| */ |
| func cortex_a57_disable_l2_prefetch |
| mrs x0, CPUECTLR_EL1 |
| orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT |
| mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK |
| orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK |
| bic x0, x0, x1 |
| msr CPUECTLR_EL1, x0 |
| isb |
| dsb sy |
| ret |
| |
| /* --------------------------------------------- |
| * Disable intra-cluster coherency |
| * --------------------------------------------- |
| */ |
| func cortex_a57_disable_smp |
| mrs x0, CPUECTLR_EL1 |
| bic x0, x0, #CPUECTLR_SMP_BIT |
| msr CPUECTLR_EL1, x0 |
| ret |
| |
| /* --------------------------------------------- |
| * Disable debug interfaces |
| * --------------------------------------------- |
| */ |
| func cortex_a57_disable_ext_debug |
| mov x0, #1 |
| msr osdlr_el1, x0 |
| isb |
| dsb sy |
| ret |
| |
| func cortex_a57_reset_func |
| #if ERRATA_A57_806969 || ERRATA_A57_813420 |
| /* --------------------------------------------- |
| * Ensure that the following errata is only |
| * applied on r0p0 parts. |
| * --------------------------------------------- |
| */ |
| #if ASM_ASSERTION |
| mrs x0, midr_el1 |
| ubfx x1, x0, #MIDR_VAR_SHIFT, #4 |
| ubfx x2, x0, #MIDR_REV_SHIFT, #4 |
| orr x0, x1, x2 |
| cmp x0, #0 |
| ASM_ASSERT(eq) |
| #endif |
| mov x1, xzr |
| #if ERRATA_A57_806969 |
| orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
| #endif |
| #if ERRATA_A57_813420 |
| orr x1, x1, #CPUACTLR_DCC_AS_DCCI |
| #endif |
| mrs x0, CPUACTLR_EL1 |
| orr x0, x0, x1 |
| msr CPUACTLR_EL1, x0 |
| #endif |
| |
| /* --------------------------------------------- |
| * As a bare minimum enable the SMP bit. |
| * --------------------------------------------- |
| */ |
| mrs x0, CPUECTLR_EL1 |
| orr x0, x0, #CPUECTLR_SMP_BIT |
| msr CPUECTLR_EL1, x0 |
| isb |
| ret |
| |
| func cortex_a57_core_pwr_dwn |
| mov x18, x30 |
| |
| /* --------------------------------------------- |
| * Turn off caches. |
| * --------------------------------------------- |
| */ |
| bl cortex_a57_disable_dcache |
| |
| /* --------------------------------------------- |
| * Disable the L2 prefetches. |
| * --------------------------------------------- |
| */ |
| bl cortex_a57_disable_l2_prefetch |
| |
| /* --------------------------------------------- |
| * Flush L1 cache to PoU. |
| * --------------------------------------------- |
| */ |
| mov x0, #DCCISW |
| bl dcsw_op_louis |
| |
| /* --------------------------------------------- |
| * Come out of intra cluster coherency |
| * --------------------------------------------- |
| */ |
| bl cortex_a57_disable_smp |
| |
| /* --------------------------------------------- |
| * Force the debug interfaces to be quiescent |
| * --------------------------------------------- |
| */ |
| mov x30, x18 |
| b cortex_a57_disable_ext_debug |
| |
| func cortex_a57_cluster_pwr_dwn |
| mov x18, x30 |
| |
| /* --------------------------------------------- |
| * Turn off caches. |
| * --------------------------------------------- |
| */ |
| bl cortex_a57_disable_dcache |
| |
| /* --------------------------------------------- |
| * Disable the L2 prefetches. |
| * --------------------------------------------- |
| */ |
| bl cortex_a57_disable_l2_prefetch |
| |
| /* --------------------------------------------- |
| * Disable the optional ACP. |
| * --------------------------------------------- |
| */ |
| bl plat_disable_acp |
| |
| /* --------------------------------------------- |
| * Flush L1 and L2 caches to PoC. |
| * --------------------------------------------- |
| */ |
| mov x0, #DCCISW |
| bl dcsw_op_all |
| |
| /* --------------------------------------------- |
| * Come out of intra cluster coherency |
| * --------------------------------------------- |
| */ |
| bl cortex_a57_disable_smp |
| |
| /* --------------------------------------------- |
| * Force the debug interfaces to be quiescent |
| * --------------------------------------------- |
| */ |
| mov x30, x18 |
| b cortex_a57_disable_ext_debug |
| |
| /* --------------------------------------------- |
| * This function provides cortex_a57 specific |
| * register information for crash reporting. |
| * It needs to return with x6 pointing to |
| * a list of register names in ascii and |
| * x8 - x15 having values of registers to be |
| * reported. |
| * --------------------------------------------- |
| */ |
| .section .rodata.cortex_a57_regs, "aS" |
| cortex_a57_regs: /* The ascii list of register names to be reported */ |
| .asciz "cpuectlr_el1", "" |
| |
| func cortex_a57_cpu_reg_dump |
| adr x6, cortex_a57_regs |
| mrs x8, CPUECTLR_EL1 |
| ret |
| |
| |
| declare_cpu_ops cortex_a57, CORTEX_A57_MIDR |