feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
diff --git a/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h
index 2659daf..639abd3 100644
--- a/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h
+++ b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h
@@ -10,8 +10,12 @@
#include <stdint.h>
/* setup the SMC command ops */
-#define MTK_SIP_APU_START_MCU 0x00U
-#define MTK_SIP_APU_STOP_MCU 0x01U
+#define MTK_SIP_APU_START_MCU (0x00U)
+#define MTK_SIP_APU_STOP_MCU (0x01U)
+#define MTK_SIP_APUPWR_BUS_PROT_CG_ON (0x02U)
+#define MTK_SIP_APUPWR_BULK_PLL (0x03U)
+#define MTK_SIP_APUPWR_ACC_INIT_ALL (0x04U)
+#define MTK_SIP_APUPWR_ACC_TOP (0x05U)
/* AO Register */
#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
@@ -20,28 +24,28 @@
#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
#define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14)
-#define PRE_DEFINE_CACHE_TCM 0x3U
-#define PRE_DEFINE_CACHE 0x2U
-#define PRE_DEFINE_SHIFT_0G 0U
-#define PRE_DEFINE_SHIFT_1G 2U
-#define PRE_DEFINE_SHIFT_2G 4U
-#define PRE_DEFINE_SHIFT_3G 6U
+#define PRE_DEFINE_CACHE_TCM (0x3U)
+#define PRE_DEFINE_CACHE (0x2U)
+#define PRE_DEFINE_SHIFT_0G (0U)
+#define PRE_DEFINE_SHIFT_1G (2U)
+#define PRE_DEFINE_SHIFT_2G (4U)
+#define PRE_DEFINE_SHIFT_3G (6U)
-#define SEC_FW_NON_SECURE 1U
-#define SEC_FW_SHIFT_NS 4U
-#define SEC_FW_DOMAIN_SHIFT 0U
+#define SEC_FW_NON_SECURE (1U)
+#define SEC_FW_SHIFT_NS (4U)
+#define SEC_FW_DOMAIN_SHIFT (0U)
-#define SEC_USR_FW_NON_SECURE 1U
-#define SEC_USR_FW_SHIFT_NS 4U
-#define SEC_USR_FW_DOMAIN_SHIFT 0U
+#define SEC_USR_FW_NON_SECURE (1U)
+#define SEC_USR_FW_SHIFT_NS (4U)
+#define SEC_USR_FW_DOMAIN_SHIFT (0U)
-#define SYS_CTRL_RUN 0U
-#define SYS_CTRL_STALL 1U
+#define SYS_CTRL_RUN (0U)
+#define SYS_CTRL_STALL (1U)
/* Reviser Register */
#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100)
#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104)
int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
- uint32_t *ret1);
+ uint32_t *ret1);
#endif /* MTK_APUSYS_H */