| developer | 4791789 | 2021-11-01 16:43:47 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2021, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MTK_APUSYS_H |
| 8 | #define MTK_APUSYS_H |
| 9 | |
| 10 | #include <stdint.h> |
| 11 | |
| 12 | /* setup the SMC command ops */ |
| 13 | #define MTK_SIP_APU_START_MCU 0x00U |
| 14 | #define MTK_SIP_APU_STOP_MCU 0x01U |
| 15 | |
| 16 | /* AO Register */ |
| 17 | #define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) |
| 18 | #define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) |
| 19 | #define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) |
| 20 | #define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) |
| 21 | #define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14) |
| 22 | |
| 23 | #define PRE_DEFINE_CACHE_TCM 0x3U |
| 24 | #define PRE_DEFINE_CACHE 0x2U |
| 25 | #define PRE_DEFINE_SHIFT_0G 0U |
| 26 | #define PRE_DEFINE_SHIFT_1G 2U |
| 27 | #define PRE_DEFINE_SHIFT_2G 4U |
| 28 | #define PRE_DEFINE_SHIFT_3G 6U |
| 29 | |
| 30 | #define SEC_FW_NON_SECURE 1U |
| 31 | #define SEC_FW_SHIFT_NS 4U |
| 32 | #define SEC_FW_DOMAIN_SHIFT 0U |
| 33 | |
| 34 | #define SEC_USR_FW_NON_SECURE 1U |
| 35 | #define SEC_USR_FW_SHIFT_NS 4U |
| 36 | #define SEC_USR_FW_DOMAIN_SHIFT 0U |
| 37 | |
| 38 | #define SYS_CTRL_RUN 0U |
| 39 | #define SYS_CTRL_STALL 1U |
| 40 | |
| 41 | /* Reviser Register */ |
| 42 | #define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100) |
| 43 | #define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104) |
| 44 | |
| 45 | int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, |
| 46 | uint32_t *ret1); |
| 47 | #endif /* MTK_APUSYS_H */ |