| /* |
| * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <plat/arm/common/plat_arm.h> |
| #include <plat/arm/css/common/css_pm.h> |
| #include <platform_def.h> |
| |
| /****************************************************************************** |
| * The power domain tree descriptor. |
| ******************************************************************************/ |
| const unsigned char tc_pd_tree_desc[] = { |
| PLAT_ARM_CLUSTER_COUNT, |
| PLAT_MAX_CPUS_PER_CLUSTER, |
| }; |
| |
| /******************************************************************************* |
| * This function returns the topology tree information. |
| ******************************************************************************/ |
| const unsigned char *plat_get_power_domain_tree_desc(void) |
| { |
| return tc_pd_tree_desc; |
| } |
| |
| /******************************************************************************* |
| * The array mapping platform core position (implemented by plat_my_core_pos()) |
| * to the SCMI power domain ID implemented by SCP. |
| ******************************************************************************/ |
| const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)), |
| #if PLATFORM_CORE_COUNT == 14 |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)), |
| (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)), |
| #endif /* PLATFORM_CORE_COUNT == 14 */ |
| }; |
| |
| /******************************************************************************* |
| * This function returns the core count within the cluster corresponding to |
| * `mpidr`. |
| ******************************************************************************/ |
| unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) |
| { |
| return PLAT_MAX_CPUS_PER_CLUSTER; |
| } |
| |
| #if ARM_PLAT_MT |
| /****************************************************************************** |
| * Return the number of PE's supported by the CPU. |
| *****************************************************************************/ |
| unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr) |
| { |
| return PLAT_MAX_PE_PER_CPU; |
| } |
| #endif |