Merge changes from topic "imx8ulp_support" into integration
* changes:
docs(maintainers): add the maintainers for imx8ulp
docs(imx8ulp): add imx8ulp platform
fix(imx8ulp): increase the mmap region num
feat(imx8ulp): adjust the dram mapped region
feat(imx8ulp): ddrc switch auto low power and software interface
feat(imx8ulp): add some delay before cmc1 access
feat(imx8ulp): add a flag check for the ddr status
fix(imx8ulp): add sw workaround for csi/hotplug test hang
feat(imx8ulp): adjust the voltage when sys dvfs enabled
feat(imx8ulp): enable the DDR frequency scaling support
fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only
feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID
feat(imx8ulp): add memory region policy
feat(imx8ulp): protect TEE region for secure access only
feat(imx8ulp): add trusty support
feat(imx8ulp): add OPTEE support
feat(imx8ulp): update the upower config for power optimization
feat(imx8ulp): allow RTD to reset APD through MU
feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD
feat(imx8ulp): add system power off support
feat(imx8ulp): add APD power down mode(PD) support in system suspend
feat(imx8ulp): add the basic support for idle & system suspned
feat(imx8ulp): enable 512KB cache after resume on imx8ulp
feat(imx8ulp): add the initial XRDC support
feat(imx8ulp): allocated caam did for the non secure world
feat(imx8ulp): add i.MX8ULP basic support
build(changelog): add new scopes for nxp imx8ulp platform
feat(scmi): add scmi sensor support
diff --git a/.commitlintrc.js b/.commitlintrc.js
index cfafbed..53e3a63 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,10 +8,9 @@
"use strict";
-const fs = require("fs");
-const yaml = require("js-yaml");
-
-const { "trailer-exists": trailerExists } = require("@commitlint/rules").default;
+import fs from "fs";
+import rules from "@commitlint/rules";
+import yaml from "js-yaml";
/*
* The types and scopes accepted by both Commitlint and Commitizen are defined by the changelog
@@ -37,7 +36,7 @@
function getScopes(subsections) {
return subsections.flatMap(subsection => {
- const scope = subsection.scope ? [ subsection.scope ] : [];
+ const scope = subsection.scope ? [subsection.scope] : [];
const subscopes = getScopes(subsection.subsections || []);
return scope.concat(subscopes);
@@ -47,13 +46,13 @@
const types = getTypes(changelog.sections).sort(); /* Sort alphabetically */
const scopes = getScopes(changelog.subsections).sort(); /* Sort alphabetically */
-module.exports = {
+export default {
extends: ["@commitlint/config-conventional"],
plugins: [
{
rules: {
- "signed-off-by-exists": trailerExists,
- "change-id-exists": trailerExists,
+ "signed-off-by-exists": rules["trailer-exists"],
+ "change-id-exists": rules["trailer-exists"],
},
},
],
@@ -64,7 +63,7 @@
"change-id-exists": [1, "always", "Change-Id:"], /* Warning */
"signed-off-by-exists": [1, "always", "Signed-off-by:"], /* Warning */
- "type-case": [2, "always", "lower-case" ], /* Error */
+ "type-case": [2, "always", "lower-case"], /* Error */
"type-enum": [2, "always", types], /* Error */
"scope-case": [2, "always", "lower-case"], /* Error */
diff --git a/.nvmrc b/.nvmrc
index e0325e5..ee09fac 100644
--- a/.nvmrc
+++ b/.nvmrc
@@ -1 +1 @@
-v16.17.1
+v20.11.1
diff --git a/.versionrc.js b/.versionrc.cjs
similarity index 100%
rename from .versionrc.js
rename to .versionrc.cjs
diff --git a/Makefile b/Makefile
index 2892f21..6a1ea99 100644
--- a/Makefile
+++ b/Makefile
@@ -452,8 +452,12 @@
DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
endif
+ ifeq ($(findstring trusty_sp,$(ARM_SPMC_MANIFEST_DTS)),trusty_sp)
+ DTC_CPPFLAGS += -DTRUSTY_SP_FW_CONFIG
+ endif
+
ifeq ($(TS_SP_FW_CONFIG),1)
- DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
+ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
endif
ifneq ($(ARM_BL2_SP_LIST_DTS),)
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index ed48311..962c362 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -476,21 +476,33 @@
bl handle_sysreg_trap
/*
* returns:
- * -1: unhandled trap, panic
+ * -1: unhandled trap, UNDEF injection into lower EL
* 0: handled trap, return to the trapping instruction (repeating it)
* 1: handled trap, return to the next instruction
*/
tst w0, w0
- b.mi elx_panic /* negative return value: panic */
- b.eq 1f /* zero: do not change ELR_EL3 */
+ b.mi 2f /* negative: undefined exception injection */
- /* advance the PC to continue after the instruction */
+ b.eq 1f /* zero: do not change ELR_EL3 */
+ /* positive: advance the PC to continue after the instruction */
ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
add x1, x1, #4
str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
1:
b el3_exit
+2:
+ /*
+ * UNDEF injection to lower EL, the support is only provided for lower
+ * EL in AArch64 mode, for AArch32 mode it will do elx_panic as before.
+ */
+ mrs x0, spsr_el3
+ tst x0, #(SPSR_M_MASK << SPSR_M_SHIFT)
+ b.ne elx_panic
+ /* Pass context pointer as an argument to inject_undef64 */
+ mov x0, x19
+ bl inject_undef64
+ b el3_exit
smc_unknown:
/*
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index 2cfe14a..d14a91e 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,8 +7,11 @@
* Dispatch synchronous system register traps from lower ELs.
*/
+#include <arch_features.h>
+#include <arch_helpers.h>
#include <bl31/sync_handle.h>
#include <context.h>
+#include <lib/el3_runtime/context_mgmt.h>
int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx)
{
@@ -28,3 +31,205 @@
return TRAP_RET_UNHANDLED;
}
+
+static bool is_tge_enabled(void)
+{
+ u_register_t hcr_el2 = read_hcr_el2();
+
+ return ((read_feat_vhe_id_field() != 0U) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
+}
+
+/*
+ * This function is to ensure that undef injection does not happen into
+ * non-existent S-EL2. This could happen when trap happens from S-EL{1,0}
+ * and non-secure world is running with TGE bit set, considering EL3 does
+ * not save/restore EL2 registers if only one world has EL2 enabled.
+ * So reading hcr_el2.TGE would give NS world value.
+ */
+static bool is_secure_trap_without_sel2(u_register_t scr)
+{
+ return ((scr & (SCR_NS_BIT | SCR_EEL2_BIT)) == 0);
+}
+
+static unsigned int target_el(unsigned int from_el, u_register_t scr)
+{
+ if (from_el > MODE_EL1) {
+ return from_el;
+ } else if (is_tge_enabled() && !is_secure_trap_without_sel2(scr)) {
+ return MODE_EL2;
+ } else {
+ return MODE_EL1;
+ }
+}
+
+static u_register_t get_elr_el3(u_register_t spsr_el3, u_register_t vbar, unsigned int target_el)
+{
+ unsigned int outgoing_el = GET_EL(spsr_el3);
+ u_register_t elr_el3 = 0;
+
+ if (outgoing_el == target_el) {
+ /*
+ * Target EL is either EL1 or EL2, lsb can tell us the SPsel
+ * Thread mode : 0
+ * Handler mode : 1
+ */
+ if ((spsr_el3 & (MODE_SP_MASK << MODE_SP_SHIFT)) == MODE_SP_ELX) {
+ elr_el3 = vbar + CURRENT_EL_SPX;
+ } else {
+ elr_el3 = vbar + CURRENT_EL_SP0;
+ }
+ } else {
+ /* Vector address for Lower EL using Aarch64 */
+ elr_el3 = vbar + LOWER_EL_AARCH64;
+ }
+
+ return elr_el3;
+}
+
+/*
+ * Explicitly create all bits of SPSR to get PSTATE at exception return.
+ *
+ * The code is based on "Aarch64.exceptions.takeexception" described in
+ * DDI0602 revision 2023-06.
+ * "https://developer.arm.com/documentation/ddi0602/2023-06/Shared-Pseudocode/
+ * aarch64-exceptions-takeexception"
+ *
+ * NOTE: This piece of code must be reviewed every release to ensure that
+ * we keep up with new ARCH features which introduces a new SPSR bit.
+ */
+static u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el)
+{
+ u_register_t new_spsr = 0;
+ u_register_t sctlr;
+
+ /* Set M bits for target EL in AArch64 mode, also get sctlr */
+ if (target_el == MODE_EL2) {
+ sctlr = read_sctlr_el2();
+ new_spsr |= (SPSR_M_AARCH64 << SPSR_M_SHIFT) | SPSR_M_EL2H;
+ } else {
+ sctlr = read_sctlr_el1();
+ new_spsr |= (SPSR_M_AARCH64 << SPSR_M_SHIFT) | SPSR_M_EL1H;
+ }
+
+ /* Mask all exceptions, update DAIF bits */
+ new_spsr |= SPSR_DAIF_MASK << SPSR_DAIF_SHIFT;
+
+ /* If FEAT_BTI is present, clear BTYPE bits */
+ new_spsr |= old_spsr & (SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
+ if (is_armv8_5_bti_present()) {
+ new_spsr &= ~(SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
+ }
+
+ /* If SSBS is implemented, take the value from SCTLR.DSSBS */
+ new_spsr |= old_spsr & SPSR_SSBS_BIT_AARCH64;
+ if (is_feat_ssbs_present()) {
+ if ((sctlr & SCTLR_DSSBS_BIT) != 0U) {
+ new_spsr |= SPSR_SSBS_BIT_AARCH64;
+ } else {
+ new_spsr &= ~SPSR_SSBS_BIT_AARCH64;
+ }
+ }
+
+ /* If FEAT_NMI is implemented, ALLINT = !(SCTLR.SPINTMASK) */
+ new_spsr |= old_spsr & SPSR_ALLINT_BIT_AARCH64;
+ if (is_feat_nmi_present()) {
+ if ((sctlr & SCTLR_SPINTMASK_BIT) != 0U) {
+ new_spsr &= ~SPSR_ALLINT_BIT_AARCH64;
+ } else {
+ new_spsr |= SPSR_ALLINT_BIT_AARCH64;
+ }
+ }
+
+ /* Clear PSTATE.IL bit explicitly */
+ new_spsr &= ~SPSR_IL_BIT;
+
+ /* Clear PSTATE.SS bit explicitly */
+ new_spsr &= ~SPSR_SS_BIT;
+
+ /* Update PSTATE.PAN bit */
+ new_spsr |= old_spsr & SPSR_PAN_BIT;
+ if (is_feat_pan_present() &&
+ ((target_el == MODE_EL1) || ((target_el == MODE_EL2) && is_tge_enabled())) &&
+ ((sctlr & SCTLR_SPAN_BIT) == 0U)) {
+ new_spsr |= SPSR_PAN_BIT;
+ }
+
+ /* Clear UAO bit if FEAT_UAO is present */
+ new_spsr |= old_spsr & SPSR_UAO_BIT_AARCH64;
+ if (is_feat_uao_present()) {
+ new_spsr &= ~SPSR_UAO_BIT_AARCH64;
+ }
+
+ /* DIT bits are unchanged */
+ new_spsr |= old_spsr & SPSR_DIT_BIT;
+
+ /* If FEAT_MTE2 is implemented mask tag faults by setting TCO bit */
+ new_spsr |= old_spsr & SPSR_TCO_BIT_AARCH64;
+ if (read_feat_mte_id_field() >= MTE_IMPLEMENTED_ELX) {
+ new_spsr |= SPSR_TCO_BIT_AARCH64;
+ }
+
+ /* NZCV bits are unchanged */
+ new_spsr |= old_spsr & SPSR_NZCV;
+
+ /* If FEAT_EBEP is present set PM bit */
+ new_spsr |= old_spsr & SPSR_PM_BIT_AARCH64;
+ if (is_feat_ebep_present()) {
+ new_spsr |= SPSR_PM_BIT_AARCH64;
+ }
+
+ /* If FEAT_SEBEP is present clear PPEND bit */
+ new_spsr |= old_spsr & SPSR_PPEND_BIT;
+ if (is_feat_sebep_present()) {
+ new_spsr &= ~SPSR_PPEND_BIT;
+ }
+
+ /* If FEAT_GCS is present, update EXLOCK bit */
+ new_spsr |= old_spsr & SPSR_EXLOCK_BIT_AARCH64;
+ if (is_feat_gcs_present()) {
+ u_register_t gcscr;
+ if (target_el == MODE_EL2) {
+ gcscr = read_gcscr_el2();
+ } else {
+ gcscr = read_gcscr_el1();
+ }
+ new_spsr |= (gcscr & GCSCR_EXLOCK_EN_BIT) ? SPSR_EXLOCK_BIT_AARCH64 : 0;
+ }
+
+ return new_spsr;
+}
+
+/*
+ * Handler for injecting Undefined exception to lower EL which is caused by
+ * lower EL accessing system registers of which (old)EL3 firmware is unaware.
+ *
+ * This is a safety net to avoid EL3 panics caused by system register access
+ * that triggers an exception syndrome EC=0x18.
+ */
+void inject_undef64(cpu_context_t *ctx)
+{
+ u_register_t esr = (EC_UNKNOWN << ESR_EC_SHIFT) | ESR_IL_BIT;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t elr_el3 = read_ctx_reg(state, CTX_ELR_EL3);
+ u_register_t old_spsr = read_ctx_reg(state, CTX_SPSR_EL3);
+ u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
+ u_register_t new_spsr = 0;
+ unsigned int to_el = target_el(GET_EL(old_spsr), scr_el3);
+
+ if (to_el == MODE_EL2) {
+ write_elr_el2(elr_el3);
+ elr_el3 = get_elr_el3(old_spsr, read_vbar_el2(), to_el);
+ write_esr_el2(esr);
+ write_spsr_el2(old_spsr);
+ } else {
+ write_elr_el1(elr_el3);
+ elr_el3 = get_elr_el3(old_spsr, read_vbar_el1(), to_el);
+ write_esr_el1(esr);
+ write_spsr_el1(old_spsr);
+ }
+
+ new_spsr = create_spsr(old_spsr, to_el);
+
+ write_ctx_reg(state, CTX_SPSR_EL3, new_spsr);
+ write_ctx_reg(state, CTX_ELR_EL3, elr_el3);
+}
diff --git a/docs/getting_started/build-internals.rst b/docs/getting_started/build-internals.rst
index 390c367..c43f4e9 100644
--- a/docs/getting_started/build-internals.rst
+++ b/docs/getting_started/build-internals.rst
@@ -19,3 +19,11 @@
``HANDLE_EA_EL3_FIRST_NS`` is set. Currently only NS world routes EA to EL3 but
in future when Secure/Realm wants to use FFH then they can introduce new macros
which will enable this option implicitly.
+
+- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
+ tb_fw_config device tree. This flag is defined only when
+ ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
+
+- ``TRUSTY_SP_FW_CONFIG``: DTC build flag to include Trusty as SP in
+ tb_fw_config device tree. This flag is defined only when
+ ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern trusty_sp.
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 16522bd..37545ce 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -740,10 +740,6 @@
1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
wants the timer registers to be saved and restored.
-- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
- tb_fw_config device tree. This flag is defined only when
- ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
-
- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
for the BL image. It can be either 0 (include) or 1 (remove). The default
value is 0.
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index c60820d..555fe7f 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -94,9 +94,8 @@
* If partition numbers could be found, check & update it.
*/
static int load_gpt_header(uintptr_t image_handle, size_t header_offset,
- unsigned long long *part_lba)
+ gpt_header_t *header)
{
- gpt_header_t header;
size_t bytes_read;
int result;
uint32_t header_crc, calc_crc;
@@ -107,7 +106,7 @@
header_offset);
return result;
}
- result = io_read(image_handle, (uintptr_t)&header,
+ result = io_read(image_handle, (uintptr_t)header,
sizeof(gpt_header_t), &bytes_read);
if ((result != 0) || (sizeof(gpt_header_t) != bytes_read)) {
VERBOSE("GPT header read error(%i) or read mismatch occurred,"
@@ -115,8 +114,8 @@
sizeof(gpt_header_t), bytes_read);
return result;
}
- if (memcmp(header.signature, GPT_SIGNATURE,
- sizeof(header.signature)) != 0) {
+ if (memcmp(header->signature, GPT_SIGNATURE,
+ sizeof(header->signature)) != 0) {
VERBOSE("GPT header signature failure\n");
return -EINVAL;
}
@@ -126,25 +125,24 @@
* computed by setting this field to 0, and computing the
* 32-bit CRC for HeaderSize bytes.
*/
- header_crc = header.header_crc;
- header.header_crc = 0U;
+ header_crc = header->header_crc;
+ header->header_crc = 0U;
- calc_crc = tf_crc32(0U, (uint8_t *)&header, sizeof(gpt_header_t));
+ calc_crc = tf_crc32(0U, (uint8_t *)header, sizeof(gpt_header_t));
if (header_crc != calc_crc) {
ERROR("Invalid GPT Header CRC: Expected 0x%x but got 0x%x.\n",
header_crc, calc_crc);
return -EINVAL;
}
- header.header_crc = header_crc;
+ header->header_crc = header_crc;
/* partition numbers can't exceed PLAT_PARTITION_MAX_ENTRIES */
- list.entry_count = header.list_num;
+ list.entry_count = header->list_num;
if (list.entry_count > PLAT_PARTITION_MAX_ENTRIES) {
list.entry_count = PLAT_PARTITION_MAX_ENTRIES;
}
- *part_lba = header.part_lba;
return 0;
}
@@ -231,12 +229,13 @@
* Retrieve each entry in the partition table, parse the data from each
* entry and store them in the list of partition table entries.
*/
-static int load_partition_gpt(uintptr_t image_handle,
- unsigned long long part_lba)
+static int load_partition_gpt(uintptr_t image_handle, gpt_header_t header)
{
- const signed long long gpt_entry_offset = LBA(part_lba);
+ const signed long long gpt_entry_offset = LBA(header.part_lba);
gpt_entry_t entry;
- int result, i;
+ int result;
+ unsigned int i;
+ uint32_t calc_crc = 0U;
result = io_seek(image_handle, IO_SEEK_SET, gpt_entry_offset);
if (result != 0) {
@@ -245,23 +244,36 @@
return result;
}
- for (i = 0; i < list.entry_count; i++) {
+ for (i = 0; i < (unsigned int)list.entry_count; i++) {
result = load_gpt_entry(image_handle, &entry);
if (result != 0) {
- VERBOSE("Failed to load gpt entry data(%i) error is (%i)\n",
+ VERBOSE("Failed to load gpt entry data(%u) error is (%i)\n",
i, result);
return result;
}
result = parse_gpt_entry(&entry, &list.list[i]);
if (result != 0) {
+ result = io_seek(image_handle, IO_SEEK_SET,
+ (gpt_entry_offset + (i * sizeof(gpt_entry_t))));
+ if (result != 0) {
+ VERBOSE("Failed to seek (%i)\n", result);
+ return result;
+ }
break;
}
+
+ /*
+ * Calculate CRC of Partition entry array to compare with CRC
+ * value in header
+ */
+ calc_crc = tf_crc32(calc_crc, (uint8_t *)&entry, sizeof(gpt_entry_t));
}
if (i == 0) {
VERBOSE("No Valid GPT Entries found\n");
return -EINVAL;
}
+
/*
* Only records the valid partition number that is loaded from
* partition table.
@@ -269,6 +281,29 @@
list.entry_count = i;
dump_entries(list.entry_count);
+ /*
+ * If there are less valid entries than the possible number of entries
+ * from the header, continue to load the partition entry table to
+ * calculate the full CRC in order to check against the partition CRC
+ * from the header for validation.
+ */
+ for (; i < header.list_num; i++) {
+ result = load_gpt_entry(image_handle, &entry);
+ if (result != 0) {
+ VERBOSE("Failed to load gpt entry data(%u) error is (%i)\n",
+ i, result);
+ return result;
+ }
+
+ calc_crc = tf_crc32(calc_crc, (uint8_t *)&entry, sizeof(gpt_entry_t));
+ }
+
+ if (header.part_crc != calc_crc) {
+ ERROR("Invalid GPT Partition Array Entry CRC: Expected 0x%x"
+ " but got 0x%x.\n", header.part_crc, calc_crc);
+ return -EINVAL;
+ }
+
return 0;
}
@@ -279,7 +314,7 @@
static int load_backup_gpt(unsigned int image_id, unsigned int sector_nums)
{
int result;
- unsigned long long part_lba = 0;
+ gpt_header_t header;
size_t gpt_header_offset;
uintptr_t dev_handle, image_spec, image_handle;
io_block_spec_t *block_spec;
@@ -316,8 +351,8 @@
INFO("Trying to retrieve back-up GPT header\n");
/* Last block is backup-GPT header, after the end of GPT entries */
gpt_header_offset = LBA(part_num_entries);
- result = load_gpt_header(image_handle, gpt_header_offset, &part_lba);
- if ((result != 0) || (part_lba == 0)) {
+ result = load_gpt_header(image_handle, gpt_header_offset, &header);
+ if ((result != 0) || (header.part_lba == 0)) {
ERROR("Failed to retrieve Backup GPT header,"
"Partition maybe corrupted\n");
goto out;
@@ -327,7 +362,8 @@
* Note we mapped last 33 blocks(LBA-33), first block here starts with
* entries while last block was header.
*/
- result = load_partition_gpt(image_handle, 0);
+ header.part_lba = 0;
+ result = load_partition_gpt(image_handle, header);
out:
io_close(image_handle);
@@ -342,19 +378,19 @@
static int load_primary_gpt(uintptr_t image_handle, unsigned int first_lba)
{
int result;
- unsigned long long part_lba;
size_t gpt_header_offset;
+ gpt_header_t header;
/* Try to load Primary GPT header from LBA1 */
gpt_header_offset = LBA(first_lba);
- result = load_gpt_header(image_handle, gpt_header_offset, &part_lba);
- if ((result != 0) || (part_lba == 0)) {
+ result = load_gpt_header(image_handle, gpt_header_offset, &header);
+ if ((result != 0) || (header.part_lba == 0)) {
VERBOSE("Failed to retrieve Primary GPT header,"
"trying to retrieve back-up GPT header\n");
return result;
}
- return load_partition_gpt(image_handle, part_lba);
+ return load_partition_gpt(image_handle, header);
}
/*
diff --git a/fdts/tc.dts b/fdts/tc.dts
index b7acb8d..63f6c3d 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -6,6 +6,14 @@
/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "platform_def.h"
+#include "tc_vers.dtsi"
+#if TARGET_FLAVOUR_FVP
+#include "tc_fvp.dtsi"
+#endif /* TARGET_FLAVOUR_FVP */
+
/ {
compatible = "arm,tc";
interrupt-parent = <&gic>;
@@ -13,11 +21,23 @@
#size-cells = <2>;
aliases {
- serial0 = &ap_ns_uart;
+ serial0 = &os_uart;
};
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = STDOUT_PATH;
+ /*
+ * Add some dummy entropy for Linux so it
+ * doesn't delay the boot waiting for it.
+ */
+ rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
+ 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >;
};
cpus {
@@ -50,6 +70,26 @@
core7 {
cpu = <&CPU7>;
};
+#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
+ core8 {
+ cpu = <&CPU8>;
+ };
+ core9 {
+ cpu = <&CPU9>;
+ };
+ core10 {
+ cpu = <&CPU10>;
+ };
+ core11 {
+ cpu = <&CPU11>;
+ };
+ core12 {
+ cpu = <&CPU12>;
+ };
+ core13 {
+ cpu = <&CPU13>;
+ };
+#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
};
@@ -58,7 +98,7 @@
* These values may be inaccurate.
*/
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
@@ -85,19 +125,16 @@
mpmm_gear0: counter@0 {
reg = <0>;
-
enable-at-el3;
};
mpmm_gear1: counter@1 {
reg = <1>;
-
enable-at-el3;
};
mpmm_gear2: counter@2 {
reg = <2>;
-
enable-at-el3;
};
};
@@ -110,7 +147,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <406>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@@ -122,7 +159,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <406>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@@ -132,9 +169,14 @@
compatible = "arm,armv8";
reg = <0x200>;
enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <406>;
+#if TARGET_PLATFORM <= 2
+ clocks = <&scmi_dvfs 0>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
+#elif TARGET_PLATFORM == 3
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -144,9 +186,14 @@
compatible = "arm,armv8";
reg = <0x300>;
enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <406>;
+#if TARGET_PLATFORM <= 2
+ clocks = <&scmi_dvfs 0>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
+#elif TARGET_PLATFORM == 3
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -158,7 +205,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <912>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@@ -170,7 +217,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <912>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@@ -180,9 +227,14 @@
compatible = "arm,armv8";
reg = <0x600>;
enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <912>;
+#if TARGET_PLATFORM <= 2
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+#elif TARGET_PLATFORM == 3
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -192,13 +244,85 @@
compatible = "arm,armv8";
reg = <0x700>;
enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
+#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+#else
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
amu = <&amu>;
supports-mpmm;
};
+#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
+ CPU8:cpu@800 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x800>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU9:cpu@900 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x900>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU10:cpu@A00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xA00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU11:cpu@B00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xB00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU12:cpu@C00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xC00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 3>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU13:cpu@D00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xD00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 3>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
reserved-memory {
@@ -213,24 +337,48 @@
linux,cma-default;
};
- optee@0xf8e00000 {
+ optee {
compatible = "restricted-dma-pool";
- reg = <0x00000000 0xf8e00000 0 0x00200000>;
+ reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
+ };
+
+ fwu_mm {
+ reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>;
+ no-map;
};
};
+ memory {
+ device_type = "memory";
+ reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
+ <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
+ HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
+ cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
+#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
+ ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
+ <&CPU12>, <&CPU13>
+#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
+ ;
+ };
+
sram: sram@6000000 {
compatible = "mmio-sram";
- reg = <0x0 0x06000000 0x0 0x8000>;
+ reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x0 0x06000000 0x8000>;
+ ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>;
cpu_scp_scmi_mem: scp-shmem@0 {
compatible = "arm,scmi-shmem";
@@ -238,22 +386,22 @@
};
};
- mbox_db_rx: mhu@45010000 {
+ mbox_db_rx: mhu@MHU_RX_ADDR() {
compatible = "arm,mhuv2-rx","arm,primecell";
- reg = <0x0 0x45010000 0x0 0x1000>;
- clocks = <&soc_refclk100mhz>;
+ reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
+ clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
- interrupts = <0 317 4>;
+ interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_rx";
mhu-protocol = "doorbell";
arm,mhuv2-protocols = <0 1>;
};
- mbox_db_tx: mhu@45000000 {
+ mbox_db_tx: mhu@MHU_TX_ADDR() {
compatible = "arm,mhuv2-tx","arm,primecell";
- reg = <0x0 0x45000000 0x0 0x1000>;
- clocks = <&soc_refclk100mhz>;
+ reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
+ clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
@@ -261,12 +409,6 @@
arm,mhuv2-protocols = <0 1>;
};
- cmn-pmu {
- compatible = "arm,ci-700";
- reg = <0x0 0x50000000 0x0 0x10000000>;
- interrupts = <0x0 460 0x4>;
- };
-
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
@@ -275,6 +417,13 @@
#address-cells = <1>;
#size-cells = <0>;
+#if TC_SCMI_PD_CTRL_EN
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+#endif /* TC_SCMI_PD_CTRL_EN */
+
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
@@ -286,30 +435,30 @@
};
};
- gic: interrupt-controller@2c010000 {
- compatible = "arm,gic-600", "arm,gic-v3";
+ gic: interrupt-controller@GIC_CTRL_ADDR {
+ compatible = "arm,gic-v3";
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
- <0x0 0x30080000 0 0x200000>; /* GICR */
- interrupts = <0x1 0x9 0x4>;
+ <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
+ interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <0x1 13 0x8>,
- <0x1 14 0x8>,
- <0x1 11 0x8>,
- <0x1 10 0x8>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
- soc_refclk100mhz: refclk100mhz {
+ soc_refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <100000000>;
+ clock-frequency = <1000000000>;
clock-output-names = "apb_pclk";
};
@@ -320,34 +469,25 @@
clock-output-names = "iofpga_clk";
};
- soc_uartclk: uartclk {
+ soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <50000000>;
+ clock-frequency = <UARTCLK_FREQ>;
clock-output-names = "uartclk";
};
- ap_ns_uart: uart@2A400000 {
+ /* soc_uart0 on FPGA, ap_ns_uart on FVP */
+ os_uart: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0x2A400000 0x0 0x1000>;
- interrupts = <0x0 63 0x4>;
- clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
+ reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_uartclk>, <&soc_refclk>;
clock-names = "uartclk", "apb_pclk";
status = "okay";
};
- rtc0: rtc@1C170000 {
- compatible = "arm,pl031", "arm,primecell";
- reg = <0x0 0x1C170000 0x0 0x1000>;
- interrupts = <0x0 100 0x4>;
- clocks = <&soc_refclk100mhz>;
- clock-names = "apb_pclk";
- wakeup-source;
- };
-
vencoder {
compatible = "drm,virtual-encoder";
-
port {
vencoder_in: endpoint {
remote-endpoint = <&dp_pl0_out0>;
@@ -355,63 +495,22 @@
};
display-timings {
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- vactive = <480>;
- hfront-porch = <16>;
- hback-porch = <48>;
- hsync-len = <96>;
- vfront-porch = <10>;
- vback-porch = <33>;
- vsync-len = <2>;
+ timing-panel {
+ VENCODER_TIMING;
};
};
};
- hdlcd: hdlcd@7ff60000 {
- compatible = "arm,hdlcd";
- reg = <0x0 0x7ff60000 0x0 0x1000>;
- interrupts = <0x0 117 0x4>;
- clocks = <&fake_hdlcd_clk>;
- clock-names = "pxlclk";
- status = "disabled";
-
- port {
- hdlcd_out: endpoint {
- remote-endpoint = <&vencoder_in>;
- };
- };
- };
-
- fake_hdlcd_clk: fake-hdlcd-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25175000>;
- clock-output-names = "pxlclk";
- };
-
ethernet@18000000 {
- compatible = "smsc,lan91c111";
+ compatible = ETH_COMPATIBLE;
reg = <0x0 0x18000000 0x0 0x10000>;
- interrupts = <0 109 4>;
- };
-
- kmi@1c060000 {
- compatible = "arm,pl050", "arm,primecell";
- reg = <0x0 0x001c060000 0x0 0x1000>;
- interrupts = <0 197 4>;
- clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- kmi@1c070000 {
- compatible = "arm,pl050", "arm,primecell";
- reg = <0x0 0x001c070000 0x0 0x1000>;
- interrupts = <0 103 4>;
- clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
- clock-names = "KMIREFCLK", "apb_pclk";
+ /* FPGA only but will work on FVP. Keep for simplicity */
+ phy-mode = "mii";
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
};
bp_clock24mhz: clock24mhz {
@@ -421,11 +520,6 @@
clock-output-names = "bp:clock24mhz";
};
- virtio_block@1c130000 {
- compatible = "virtio,mmio";
- reg = <0x0 0x1c130000 0x0 0x200>;
- interrupts = <0 204 4>;
- };
sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";
@@ -445,12 +539,12 @@
mmci@1c050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
- interrupts = <0 107 0x4>,
- <0 108 0x4>;
- cd-gpios = <&sysreg 0 0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ MMC_REMOVABLE;
wp-gpios = <&sysreg 1 0>;
- bus-width = <8>;
- max-frequency = <12000000>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
vmmc-supply = <&fixed_3v3>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "mclk", "apb_pclk";
@@ -471,18 +565,23 @@
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
- interrupts = <0 66 4>, <0 67 4>, <0 65 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "JOB", "MMU", "GPU";
- clocks = <&gpu_clk>, <&gpu_core_clk>;
- clock-names = "clk_mali", "shadercores";
+ clocks = <&gpu_core_clk>;
+ clock-names = "shadercores";
+#if TC_SCMI_PD_CTRL_EN
+ power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
+ scmi-perf-domain = <3>;
+#endif /* TC_SCMI_PD_CTRL_EN */
+
+#if TC_IOMMU_EN
iommus = <&smmu_700 0x200>;
- operating-points = <
- /* KHz uV */
- 50000 820000
- >;
+#endif /* TC_IOMMU_EN */
};
- power_model@simple {
+ power_model_simple {
/*
* Numbers used are irrelevant to Titan,
* it helps suppressing the kernel warnings.
@@ -494,27 +593,37 @@
thermal-zone = "";
};
- smmu_700: smmu_700@3f000000 {
+#if TC_IOMMU_EN
+ smmu_700: iommu@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <0x0 0x3f000000 0x0 0x5000000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
};
+#endif /* TC_IOMMU_EN */
- dp0: display@2cc00000 {
+ dp0: display@DPU_ADDR() {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
- reg = <0 0x2cc00000 0 0x20000>;
- interrupts = <0 69 4>;
+ reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>;
+ interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DPU";
- clocks = <&scmi_clk 0>;
- clock-names = "aclk";
+ DPU_CLK_ATTR1;
+#if TC_IOMMU_EN
iommus = <&smmu_700 0x100>;
+#endif /* TC_IOMMU_EN */
+#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
+ power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
+#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
+
pl0: pipeline@0 {
reg = <0>;
- clocks = <&scmi_clk 1>;
- clock-names = "pxclk";
+ DPU_CLK_ATTR2;
pl_id = <0>;
ports {
#address-cells = <1>;
@@ -530,8 +639,7 @@
pl1: pipeline@1 {
reg = <1>;
- clocks = <&scmi_clk 2>;
- clock-names = "pxclk";
+ DPU_CLK_ATTR3;
pl_id = <1>;
ports {
#address-cells = <1>;
@@ -549,7 +657,7 @@
*/
msc0 {
compatible = "arm,mpam-msc";
- reg = <0x1 0x00010000 0x0 0x2000>;
+ reg = <MPAM_ADDR 0x0 0x2000>;
};
ete0 {
@@ -592,8 +700,72 @@
cpu = <&CPU7>;
};
+#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
+ ete8 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU8>;
+ };
+
+ ete9 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU9>;
+ };
+
+ ete10 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU10>;
+ };
+
+ ete11 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU11>;
+ };
+
+ ete12 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU12>;
+ };
+
- trbe0 {
+ ete13 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU13>;
+ };
+#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
+
+ trbe {
compatible = "arm,trace-buffer-extension";
- interrupts = <1 2 4>;
+ interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ trusty {
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ ranges = <0x00>;
+ compatible = "android,trusty-v1";
+
+ virtio {
+ compatible = "android,trusty-virtio-v1";
+ };
+
+ test {
+ compatible = "android,trusty-test-v1";
+ };
+
+ log {
+ compatible = "android,trusty-log-v1";
+ };
+
+ irq {
+ ipi-range = <0x08 0x0f 0x08>;
+ interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>;
+ interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>;
+ compatible = "android,trusty-irq-v1";
+ };
+ };
+
+ /* used in U-boot, Linux doesn't care */
+ arm_ffa {
+ compatible = "arm,ffa";
+ method = "smc";
};
};
diff --git a/fdts/tc_fvp.dtsi b/fdts/tc_fvp.dtsi
new file mode 100644
index 0000000..42f3818
--- /dev/null
+++ b/fdts/tc_fvp.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/ {
+ rtc@1c170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0x1C170000 0x0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_refclk>;
+ clock-names = "apb_pclk";
+ };
+
+ kmi@1c060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x001c060000 0x0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ kmi@1c070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x001c070000 0x0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ virtio_block@1c130000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c130000 0x0 0x200>;
+ /* spec lists this wrong */
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi
new file mode 100644
index 0000000..43fafd5
--- /dev/null
+++ b/fdts/tc_vers.dtsi
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* If SCMI power domain control is enabled */
+#if TC_SCMI_PD_CTRL_EN
+#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
+#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
+#endif /* TC_SCMI_PD_CTRL_EN */
+
+/* All perf is normalized against the big core */
+#define BIG_CAPACITY 1024
+
+#if TARGET_PLATFORM <= 2
+#if TARGET_FLAVOUR_FVP
+#define LIT_CAPACITY 406
+#define MID_CAPACITY 912
+#else /* TARGET_FLAVOUR_FPGA */
+#define LIT_CAPACITY 280
+#define MID_CAPACITY 775
+/* this is an area optimized configuration of the big core */
+#define BIG2_CAPACITY 930
+#endif /* TARGET_FLAVOUR_FPGA */
+
+#define INT_MBOX_RX 317
+#define MHU_TX_ADDR(pref) pref##45000000 /* hex */
+#define MHU_RX_ADDR(pref) pref##45010000 /* hex */
+#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
+#define UARTCLK_FREQ 5000000
+#elif TARGET_PLATFORM == 3
+
+#define LIT_CAPACITY 239
+#define MID_CAPACITY 686
+
+#define INT_MBOX_RX 300
+#define MHU_TX_ADDR(pref) pref##46040000 /* hex */
+#define MHU_RX_ADDR(pref) pref##46140000 /* hex */
+#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
+#define UARTCLK_FREQ 3750000
+#endif /* TARGET_PLATFORM == 3 */
+
+#if TARGET_FLAVOUR_FVP
+#define STDOUT_PATH "serial0:115200n8"
+#define GIC_CTRL_ADDR 2c010000
+#define GIC_GICR_OFFSET 0x200000
+#define UART_OFFSET 0x1000
+#define VENCODER_TIMING_CLK 25175000
+#define VENCODER_TIMING \
+ clock-frequency = <VENCODER_TIMING_CLK>; \
+ hactive = <640>; \
+ vactive = <480>; \
+ hfront-porch = <16>; \
+ hback-porch = <48>; \
+ hsync-len = <96>; \
+ vfront-porch = <10>; \
+ vback-porch = <33>; \
+ vsync-len = <2>
+#define ETH_COMPATIBLE "smsc,lan91c111"
+#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0>
+#if TARGET_PLATFORM <= 2
+#define DPU_ADDR(pref) pref##2cc00000
+#define DPU_IRQ 69
+#else /* TARGET_PLATFORM >= 3 */
+#define DPU_ADDR(pref) pref##4000000000
+#define DPU_IRQ 579
+#endif /* TARGET_PLATFORM >= 3 */
+
+#else /* TARGET_FLAVOUR_FPGA */
+
+#define STDOUT_PATH "serial0:38400n8"
+#define GIC_CTRL_ADDR 30000000
+#define GIC_GICR_OFFSET 0x1000000
+#define UART_OFFSET 0x10000
+/* 1440x3200@120 framebuffer */
+#define VENCODER_TIMING_CLK 836000000
+#define VENCODER_TIMING \
+ clock-frequency = <VENCODER_TIMING_CLK>; \
+ hactive = <1440>; \
+ vactive = <3200>; \
+ hfront-porch = <136>; \
+ hback-porch = <296>; \
+ hsync-len = <160>; \
+ vfront-porch = <3>; \
+ vback-porch = <217>; \
+ vsync-len = <10>
+#define ETH_COMPATIBLE "smsc,lan9115"
+#define MMC_REMOVABLE non-removable
+#define DPU_ADDR(pref) pref##2cc00000
+#define DPU_IRQ 69
+#endif /* TARGET_FLAVOUR_FPGA */
+
+/* Use SCMI controlled clocks */
+#if TC_DPU_USE_SCMI_CLK
+#define DPU_CLK_ATTR1 \
+ clocks = <&scmi_clk 0>; \
+ clock-names = "aclk"
+
+#define DPU_CLK_ATTR2 \
+ clocks = <&scmi_clk 1>; \
+ clock-names = "pxclk"
+
+#define DPU_CLK_ATTR3 \
+ clocks = <&scmi_clk 2>; \
+ clock-names = "pxclk" \
+/* Use fixed clocks */
+#else /* !TC_DPU_USE_SCMI_CLK */
+#define DPU_CLK_ATTR1 \
+ clocks = <&dpu_aclk>; \
+ clock-names = "aclk"
+
+#define DPU_CLK_ATTR2 \
+ clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
+ clock-names = "pxclk", "aclk"
+
+#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
+#endif /* !TC_DPU_USE_SCMI_CLK */
+
+/ {
+#if TARGET_PLATFORM <= 2
+ cmn-pmu {
+ compatible = "arm,ci-700";
+ reg = <0x0 0x50000000 0x0 0x10000000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
+ };
+#endif /* TARGET_PLATFORM <= 2 */
+
+#if !TC_DPU_USE_SCMI_CLK
+ dpu_aclk: dpu_aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <VENCODER_TIMING_CLK>;
+ clock-output-names = "fpga:dpu_aclk";
+ };
+
+ dpu_pixel_clk: dpu-pixel-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <VENCODER_TIMING_CLK>;
+ clock-output-names = "pxclk";
+ };
+#endif /* !TC_DPU_USE_SCMI_CLK */
+};
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index a711753..7e759d81 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -163,6 +163,11 @@
#define ID_PFR1_SEC_MASK U(0xf)
#define ID_PFR1_ELx_ENABLED U(1)
+/* ID_PFR2 definitions */
+#define ID_PFR2_SSBS_SHIFT U(4)
+#define ID_PFR2_SSBS_MASK U(0xf)
+#define SSBS_UNAVAILABLE U(0)
+
/* SCTLR definitions */
#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
(U(1) << 3))
@@ -552,6 +557,7 @@
#define ID_DFR1 p15, 0, c0, c3, 5
#define ID_PFR0 p15, 0, c0, c1, 0
#define ID_PFR1 p15, 0, c0, c1, 1
+#define ID_PFR2 p15, 0, c0, c3, 4
#define MAIR0 p15, 0, c10, c2, 0
#define MAIR1 p15, 0, c10, c2, 1
#define TTBCR p15, 0, c2, c0, 2
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index dd9b7ad..734a6b5 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -128,6 +128,17 @@
return read_feat_pan_id_field() != 0U;
}
+static inline bool is_feat_pan_present(void)
+{
+ return read_feat_pan_id_field() != 0U;
+}
+
+static inline unsigned int is_feat_ssbs_present(void)
+{
+ return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) &
+ ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE;
+}
+
/*
* TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch
* code. In fact, EL2 context switching is only needed for AArch64 (since
@@ -164,6 +175,10 @@
static inline bool is_feat_s2pie_supported(void) { return false; }
static inline bool is_feat_s1pie_supported(void) { return false; }
static inline bool is_feat_sxpie_supported(void) { return false; }
+static inline bool is_feat_uao_present(void) { return false; }
+static inline bool is_feat_nmi_present(void) { return false; }
+static inline bool is_feat_ebep_present(void) { return false; }
+static inline bool is_feat_sebep_present(void) { return false; }
static inline unsigned int read_feat_pmuv3_id_field(void)
{
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index 3a7c768..3244d3b 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -224,6 +224,7 @@
DEFINE_COPROCR_READ_FUNC(id_dfr1, ID_DFR1)
DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
+DEFINE_COPROCR_READ_FUNC(id_pfr2, ID_PFR2)
DEFINE_COPROCR_READ_FUNC(isr, ISR)
DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index b88d6c6..8a4c071 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -75,6 +75,19 @@
#define INVALID_MPID U(0xFFFFFFFF)
/*******************************************************************************
+ * Definitions for Exception vector offsets
+ ******************************************************************************/
+#define CURRENT_EL_SP0 0x0
+#define CURRENT_EL_SPX 0x200
+#define LOWER_EL_AARCH64 0x400
+#define LOWER_EL_AARCH32 0x600
+
+#define SYNC_EXCEPTION 0x0
+#define IRQ_EXCEPTION 0x80
+#define FIQ_EXCEPTION 0x100
+#define SERROR_EXCEPTION 0x180
+
+/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
@@ -231,6 +244,11 @@
#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
+/* ID_AA64DFR0_EL1.SEBEP definitions */
+#define ID_AA64DFR0_SEBEP_SHIFT U(24)
+#define ID_AA64DFR0_SEBEP_MASK ULL(0xf)
+#define SEBEP_IMPLEMENTED ULL(1)
+
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
@@ -253,6 +271,11 @@
#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
+/* ID_AA64DFR1_EL1 definitions */
+#define ID_AA64DFR1_EBEP_SHIFT U(48)
+#define ID_AA64DFR1_EBEP_MASK ULL(0xf)
+#define EBEP_IMPLEMENTED ULL(1)
+
/* ID_AA64ISAR0_EL1 definitions */
#define ID_AA64ISAR0_RNDR_SHIFT U(60)
#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
@@ -358,6 +381,9 @@
#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
+#define ID_AA64MMFR2_EL1_UAO_SHIFT U(4)
+#define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf)
+
#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
@@ -386,25 +412,29 @@
#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
/* ID_AA64PFR1_EL1 definitions */
-#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
-#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
-
-#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
-#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
-
-#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
-
#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
+#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
+#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
+#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
+
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
+#define ID_AA64PFR1_EL1_NMI_SHIFT U(36)
+#define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf)
+#define NMI_IMPLEMENTED ULL(1)
+
+#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
+#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
+#define GCS_IMPLEMENTED ULL(1)
+
#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
@@ -503,6 +533,7 @@
#define SCTLR_TCF0_SHIFT U(38)
#define SCTLR_TCF0_MASK ULL(3)
#define SCTLR_ENTP2_BIT (ULL(1) << 60)
+#define SCTLR_SPINTMASK_BIT (ULL(1) << 62)
/* Tag Check Faults in EL0 have no effect on the PE */
#define SCTLR_TCF0_NO_EFFECT U(0)
@@ -730,6 +761,10 @@
#define DAIF_IRQ_BIT (U(1) << 1)
#define DAIF_ABT_BIT (U(1) << 2)
#define DAIF_DBG_BIT (U(1) << 3)
+#define SPSR_V_BIT (U(1) << 28)
+#define SPSR_C_BIT (U(1) << 29)
+#define SPSR_Z_BIT (U(1) << 30)
+#define SPSR_N_BIT (U(1) << 31)
#define SPSR_DAIF_SHIFT U(6)
#define SPSR_DAIF_MASK U(0xf)
@@ -750,25 +785,32 @@
#define SPSR_M_MASK U(0x1)
#define SPSR_M_AARCH64 U(0x0)
#define SPSR_M_AARCH32 U(0x1)
+#define SPSR_M_EL1H U(0x5)
#define SPSR_M_EL2H U(0x9)
#define SPSR_EL_SHIFT U(2)
#define SPSR_EL_WIDTH U(2)
-#define SPSR_SSBS_SHIFT_AARCH64 U(12)
+#define SPSR_BTYPE_SHIFT_AARCH64 U(10)
+#define SPSR_BTYPE_MASK_AARCH64 U(0x3)
+#define SPSR_SSBS_SHIFT_AARCH64 U(12)
#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
#define SPSR_SSBS_SHIFT_AARCH32 U(23)
#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
-
+#define SPSR_ALLINT_BIT_AARCH64 BIT_64(13)
+#define SPSR_IL_BIT BIT_64(20)
+#define SPSR_SS_BIT BIT_64(21)
#define SPSR_PAN_BIT BIT_64(22)
-
+#define SPSR_UAO_BIT_AARCH64 BIT_64(23)
#define SPSR_DIT_BIT BIT(24)
-
#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
+#define SPSR_PM_BIT_AARCH64 BIT_64(32)
+#define SPSR_PPEND_BIT BIT(33)
+#define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34)
+#define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT)
#define DISABLE_ALL_EXCEPTIONS \
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
-
#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
/*
@@ -946,6 +988,7 @@
#define ESR_EC_LENGTH U(6)
#define ESR_ISS_SHIFT U(0)
#define ESR_ISS_LENGTH U(25)
+#define ESR_IL_BIT (U(1) << 25)
#define EC_UNKNOWN U(0x0)
#define EC_WFE_WFI U(0x1)
#define EC_AARCH32_CP15_MRC_MCR U(0x3)
@@ -1408,6 +1451,9 @@
******************************************************************************/
#define GCSCR_EL2 S3_4_C2_C5_0
#define GCSPR_EL2 S3_4_C2_C5_1
+#define GCSCR_EL1 S3_0_C2_C5_0
+
+#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6)
/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 60fb522..de59d45 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -42,6 +42,11 @@
CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
ENABLE_FEAT_PAN)
+static inline bool is_feat_pan_present(void)
+{
+ return read_feat_pan_id_field() != 0U;
+}
+
CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
ENABLE_FEAT_VHE)
@@ -51,6 +56,12 @@
ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
}
+static inline bool is_feat_uao_present(void)
+{
+ return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
+ ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
+}
+
static inline bool is_feat_pacqarma3_present(void)
{
uint64_t mask_id_aa64isar2 =
@@ -89,6 +100,42 @@
ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
}
+static inline unsigned int get_armv8_5_mte_support(void)
+{
+ return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
+ ID_AA64PFR1_EL1_MTE_MASK);
+}
+
+static inline bool is_feat_ssbs_present(void)
+{
+ return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
+ ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE;
+}
+
+static inline bool is_feat_nmi_present(void)
+{
+ return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
+ ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
+}
+
+static inline bool is_feat_gcs_present(void)
+{
+ return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
+ ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
+}
+
+static inline bool is_feat_ebep_present(void)
+{
+ return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
+ ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
+}
+
+static inline bool is_feat_sebep_present(void)
+{
+ return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
+ ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
+}
+
CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
ENABLE_FEAT_MTE)
CREATE_FEATURE_FUNCS_VER(feat_mte2, read_feat_mte_id_field, MTE_IMPLEMENTED_ELX,
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 2d97018..6356cab 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -241,6 +241,7 @@
void flush_dcache_range(uintptr_t addr, size_t size);
void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
+void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
bool is_dcache_enabled(void);
@@ -271,6 +272,7 @@
DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1)
DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1)
DEFINE_IDREG_READ_FUNC(id_afr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)
DEFINE_SYSREG_READ_FUNC(ctr_el0)
@@ -645,6 +647,7 @@
/* FEAT_GCS Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h
index 1ac4f98..ae61f31 100644
--- a/include/bl31/sync_handle.h
+++ b/include/bl31/sync_handle.h
@@ -55,6 +55,9 @@
*/
int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx);
+/* Handler for injecting UNDEF exception to lower EL */
+void inject_undef64(cpu_context_t *ctx);
+
/* Prototypes for system register emulation handlers provided by platforms. */
int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx);
int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx);
diff --git a/include/lib/psa/rss_crypto_defs.h b/include/lib/psa/rss_crypto_defs.h
index 40d217a..301dc05 100644
--- a/include/lib/psa/rss_crypto_defs.h
+++ b/include/lib/psa/rss_crypto_defs.h
@@ -41,25 +41,39 @@
* Structure used to pack non-pointer types in a call to PSA Crypto APIs
*/
struct rss_crypto_pack_iovec {
- psa_key_id_t key_id; /*!< Key id */
- psa_algorithm_t alg; /*!< Algorithm */
- uint32_t op_handle; /*!< Frontend context handle associated to a
- * multipart operation
- */
- uint32_t ad_length; /*!< Additional Data length for multipart AEAD */
- uint32_t plaintext_length; /*!< Plaintext length for multipart AEAD */
+ psa_key_id_t key_id; /* !< Key id */
+ psa_algorithm_t alg; /* !< Algorithm */
+ uint32_t op_handle; /*
+ * !< Frontend context handle
+ * associated to a multipart operation
+ */
+ uint32_t ad_length; /*
+ * !< Additional Data length for
+ * multipart AEAD
+ */
+ uint32_t plaintext_length; /*
+ * !< Plaintext length for multipart
+ * AEAD
+ */
- struct rss_crypto_aead_pack_input aead_in; /*!< Packs AEAD-related inputs */
+ struct rss_crypto_aead_pack_input aead_in; /*
+ * !< Packs AEAD-related
+ * inputs
+ */
- uint16_t function_id; /*!< Used to identify the function in the
- * API dispatcher to the service backend
- * See rss_crypto_func_sid for detail
- */
- uint16_t step; /*!< Key derivation step */
- union {
- size_t capacity; /*!< Key derivation capacity */
- uint64_t value; /*!< Key derivation integer for update*/
- };
+ uint16_t function_id; /*
+ * !< Used to identify the function in the
+ * API dispatcher to the service backend
+ * See rss_crypto_func_sid for detail
+ */
+ uint16_t step; /* !< Key derivation step */
+ union {
+ size_t capacity; /* !< Key derivation capacity */
+ uint64_t value; /*
+ * !< Key derivation integer for
+ * update
+ */
+ };
};
#endif /* RSS_CRYPTO_DEFS_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index a170a09..8a03c7d 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -53,6 +53,9 @@
#define GENMASK GENMASK_32
#endif
+#define HI(addr) (addr >> 32)
+#define LO(addr) (addr & 0xffffffff)
+
/*
* This variant of div_round_up can be used in macro definition but should not
* be used in C code as the `div` parameter is evaluated twice.
diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h
index 96ed963..d8a332e 100644
--- a/include/plat/arm/common/fconf_arm_sp_getter.h
+++ b/include/plat/arm/common/fconf_arm_sp_getter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,12 +9,17 @@
#include <common/tbbr/tbbr_img_def.h>
#include <lib/fconf/fconf.h>
+#include <platform_def.h>
#include <tools_share/uuid.h>
/* arm_sp getter */
#define arm__sp_getter(prop) arm_sp.prop
+#ifdef PLAT_ARM_SP_MAX_SIZE
+#define ARM_SP_MAX_SIZE PLAT_ARM_SP_MAX_SIZE
+#else
#define ARM_SP_MAX_SIZE U(0xb0000)
+#endif /* PLAT_ARM_SP_MAX_SIZE */
#define ARM_SP_OWNER_NAME_LEN U(8)
struct arm_sp_t {
diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S
index 314ed6e..ff9a4e6 100644
--- a/lib/aarch64/cache_helpers.S
+++ b/lib/aarch64/cache_helpers.S
@@ -9,6 +9,7 @@
.globl flush_dcache_range
.globl flush_dcache_to_popa_range
+ .globl flush_dcache_to_popa_range_mte2
.globl clean_dcache_range
.globl inv_dcache_range
.globl dcsw_op_louis
@@ -17,6 +18,20 @@
.globl dcsw_op_level2
.globl dcsw_op_level3
+/* Opcodes for data cache maintenance by PA instructions. */
+
+/*
+ * sys #6, c7, c14, #1, x0
+ * DC CIPAPA, X0
+ */
+#define dc_cipapa_x0 0xd50e7e20
+
+/*
+ * sys #6, c7, c14, #3, x0
+ * DC CIDGPAPA, X0
+ */
+#define dc_cigdpapa_x0 0xd50e7ea0
+
/*
* This macro can be used for implementing various data cache operations `op`
*/
@@ -37,6 +52,24 @@
ret
.endm
+/* op: the hexadecimal instruction opcode for the cache operation */
+.macro do_dcache_maintenance_instr op
+ /* Exit early if size is zero */
+ cbz x1, exit_loop_\op
+ dcache_line_size x2, x3
+ sub x3, x2, #1
+ bic x0, x0, x3
+ add x1, x1, x0
+loop_\op:
+ .inst \op
+ add x0, x0, x2
+ cmp x0, x1
+ b.lo loop_\op
+ dsb osh
+exit_loop_\op:
+ ret
+.endm
+
.macro check_plat_can_cmo
#if CONDITIONAL_CMO
mov x3, x30
@@ -49,10 +82,11 @@
mov x0, x2
#endif
.endm
- /* ------------------------------------------
- * Clean+Invalidate from base address till
- * size. 'x0' = addr, 'x1' = size
- * ------------------------------------------
+
+ /* -------------------------------------------
+ * DCache Clean+Invalidate by MVA from base
+ * address till size. 'x0' = addr, 'x1' = size
+ * -------------------------------------------
*/
func flush_dcache_range
check_plat_can_cmo
@@ -60,8 +94,8 @@
endfunc flush_dcache_range
/* ------------------------------------------
- * Clean from base address till size.
- * 'x0' = addr, 'x1' = size
+ * DCache Clean by MVA from base address till
+ * size. 'x0' = addr, 'x1' = size
* ------------------------------------------
*/
func clean_dcache_range
@@ -70,8 +104,8 @@
endfunc clean_dcache_range
/* ------------------------------------------
- * Invalidate from base address till
- * size. 'x0' = addr, 'x1' = size
+ * DCache Invalidate by MVA from base address
+ * till size. 'x0' = addr, 'x1' = size
* ------------------------------------------
*/
func inv_dcache_range
@@ -79,37 +113,36 @@
do_dcache_maintenance_by_mva ivac
endfunc inv_dcache_range
-
/*
- * On implementations with FEAT_MTE2,
- * Root firmware must issue DC_CIGDPAPA instead of DC_CIPAPA ,
- * in order to additionally clean and invalidate Allocation Tags
- * associated with the affected locations.
- *
* ------------------------------------------
- * Clean+Invalidate by PA to POPA
- * from base address till size.
+ * DCache Clean+Invalidate by PA to POPA from
+ * base address till size.
* 'x0' = addr, 'x1' = size
* ------------------------------------------
*/
func flush_dcache_to_popa_range
- /* Exit early if size is zero */
- cbz x1, exit_loop_dc_cipapa
check_plat_can_cmo
- dcache_line_size x2, x3
- sub x3, x2, #1
- bic x0, x0, x3
- add x1, x1, x0
-loop_dc_cipapa:
- sys #6, c7, c14, #1, x0 /* DC CIPAPA,<Xt> */
- add x0, x0, x2
- cmp x0, x1
- b.lo loop_dc_cipapa
- dsb osh
-exit_loop_dc_cipapa:
- ret
+ /* dc cipapa, x0 */
+ do_dcache_maintenance_instr dc_cipapa_x0
endfunc flush_dcache_to_popa_range
+ /*
+ * ------------------------------------------
+ * Clean+Invalidate by PA to POPA (MTE2)
+ * from base address till size.
+ * 'x0' = addr, 'x1' = size
+ * ------------------------------------------
+ * On implementations with FEAT_MTE2, Root firmware must issue
+ * DC_CIGDPAPA instead of DC_CIPAPA, in order to additionally
+ * clean and invalidate Allocation Tags associated with the
+ * affected locations.
+ */
+func flush_dcache_to_popa_range_mte2
+ check_plat_can_cmo
+ /* dc cigdpapa, x0 */
+ do_dcache_maintenance_instr dc_cigdpapa_x0
+endfunc flush_dcache_to_popa_range_mte2
+
/* ---------------------------------------------------------------
* Data cache operations by set/way to the level specified
*
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index f5353cb..36f7a51 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -11,6 +11,7 @@
#include <stdint.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include "gpt_rme_private.h"
@@ -1095,8 +1096,13 @@
* states, remove any data speculatively fetched into the target
* physical address space. Issue DC CIPAPA over address range
*/
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ if (is_feat_mte2_supported()) {
+ flush_dcache_to_popa_range_mte2(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ } else {
+ flush_dcache_to_popa_range(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ }
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, target_pas);
@@ -1107,8 +1113,13 @@
nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ if (is_feat_mte2_supported()) {
+ flush_dcache_to_popa_range_mte2(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ } else {
+ flush_dcache_to_popa_range(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ }
/* Unlock access to the L1 tables. */
spin_unlock(&gpt_lock);
@@ -1225,8 +1236,13 @@
}
/* Ensure that the scrubbed data has made it past the PoPA */
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ if (is_feat_mte2_supported()) {
+ flush_dcache_to_popa_range_mte2(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ } else {
+ flush_dcache_to_popa_range(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ }
/*
* Remove any data loaded speculatively
@@ -1234,8 +1250,13 @@
*/
nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ if (is_feat_mte2_supported()) {
+ flush_dcache_to_popa_range_mte2(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ } else {
+ flush_dcache_to_popa_range(nse | base,
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ }
/* Clear existing GPI encoding and transition granule. */
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
diff --git a/package-lock.json b/package-lock.json
index e43fa65..7753a38 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,7 +1,7 @@
{
"name": "trusted-firmware-a",
"version": "2.10.0",
- "lockfileVersion": 2,
+ "lockfileVersion": 3,
"requires": true,
"packages": {
"": {
@@ -10,48 +10,111 @@
"hasInstallScript": true,
"license": "BSD-3-Clause",
"devDependencies": {
- "@commitlint/cli": "^16.1.0",
- "@commitlint/config-conventional": "^16.0.0",
- "@commitlint/cz-commitlint": "^16.1.0",
- "commitizen": "^4.2.4",
+ "@commitlint/cli": "^19.0.0",
+ "@commitlint/config-conventional": "^19.0.0",
+ "@commitlint/cz-commitlint": "^19.0.0",
+ "commitizen": "^4.3.0",
"conventional-changelog-tf-a": "file:tools/conventional-changelog-tf-a",
- "husky": "^7.0.4",
+ "husky": "^9.0.11",
"js-yaml": "^4.1.0",
- "standard-version": "^9.3.2"
+ "standard-version": "^9.5.0"
},
"engines": {
- "node": ">=16.0.0"
+ "node": ">=20"
}
},
"node_modules/@babel/code-frame": {
- "version": "7.18.6",
- "resolved": "https://registry.npmjs.org/@babel/code-frame/-/code-frame-7.18.6.tgz",
- "integrity": "sha512-TDCmlK5eOvH+eH7cdAFlNXeVJqWIQ7gW9tY1GJIpUtFb6CmjVyq2VM3u71bOyR8CRihcCgMUYoDNyLXao3+70Q==",
+ "version": "7.23.5",
+ "resolved": "https://registry.npmjs.org/@babel/code-frame/-/code-frame-7.23.5.tgz",
+ "integrity": "sha512-CgH3s1a96LipHCmSUmYFPwY7MNx8C3avkq7i4Wl3cfa662ldtUe4VM1TPXX70pfmrlWTb6jLqTYrZyT2ZTJBgA==",
"dev": true,
"dependencies": {
- "@babel/highlight": "^7.18.6"
+ "@babel/highlight": "^7.23.4",
+ "chalk": "^2.4.2"
},
"engines": {
"node": ">=6.9.0"
}
},
+ "node_modules/@babel/code-frame/node_modules/ansi-styles": {
+ "version": "3.2.1",
+ "resolved": "https://registry.npmjs.org/ansi-styles/-/ansi-styles-3.2.1.tgz",
+ "integrity": "sha512-VT0ZI6kZRdTh8YyJw3SMbYm/u+NqfsAxEpWO0Pf9sq8/e94WxxOpPKx9FR1FlyCtOVDNOQ+8ntlqFxiRc+r5qA==",
+ "dev": true,
+ "dependencies": {
+ "color-convert": "^1.9.0"
+ },
+ "engines": {
+ "node": ">=4"
+ }
+ },
+ "node_modules/@babel/code-frame/node_modules/chalk": {
+ "version": "2.4.2",
+ "resolved": "https://registry.npmjs.org/chalk/-/chalk-2.4.2.tgz",
+ "integrity": "sha512-Mti+f9lpJNcwF4tWV8/OrTTtF1gZi+f8FqlyAdouralcFWFQWF2+NgCHShjkCb+IFBLq9buZwE1xckQU4peSuQ==",
+ "dev": true,
+ "dependencies": {
+ "ansi-styles": "^3.2.1",
+ "escape-string-regexp": "^1.0.5",
+ "supports-color": "^5.3.0"
+ },
+ "engines": {
+ "node": ">=4"
+ }
+ },
+ "node_modules/@babel/code-frame/node_modules/color-convert": {
+ "version": "1.9.3",
+ "resolved": "https://registry.npmjs.org/color-convert/-/color-convert-1.9.3.tgz",
+ "integrity": "sha512-QfAUtd+vFdAtFQcC8CCyYt1fYWxSqAiK2cSD6zDB8N3cpsEBAvRxp9zOGg6G/SHHJYAT88/az/IuDGALsNVbGg==",
+ "dev": true,
+ "dependencies": {
+ "color-name": "1.1.3"
+ }
+ },
+ "node_modules/@babel/code-frame/node_modules/color-name": {
+ "version": "1.1.3",
+ "resolved": "https://registry.npmjs.org/color-name/-/color-name-1.1.3.tgz",
+ "integrity": "sha512-72fSenhMw2HZMTVHeCA9KCmpEIbzWiQsjN+BHcBbS9vr1mtt+vJjPdksIBNUmKAW8TFUDPJK5SUU3QhE9NEXDw==",
+ "dev": true
+ },
+ "node_modules/@babel/code-frame/node_modules/has-flag": {
+ "version": "3.0.0",
+ "resolved": "https://registry.npmjs.org/has-flag/-/has-flag-3.0.0.tgz",
+ "integrity": "sha512-sKJf1+ceQBr4SMkvQnBDNDtf4TXpVhVGateu0t918bl30FnbE2m4vNLX+VWe/dpjlb+HugGYzW7uQXH98HPEYw==",
+ "dev": true,
+ "engines": {
+ "node": ">=4"
+ }
+ },
+ "node_modules/@babel/code-frame/node_modules/supports-color": {
+ "version": "5.5.0",
+ "resolved": "https://registry.npmjs.org/supports-color/-/supports-color-5.5.0.tgz",
+ "integrity": "sha512-QjVjwdXIt408MIiAqCX4oUKsgU2EqAGzs2Ppkm4aQYbjm+ZEWEcW4SfFNTr4uMNZma0ey4f5lgLrkB0aX0QMow==",
+ "dev": true,
+ "dependencies": {
+ "has-flag": "^3.0.0"
+ },
+ "engines": {
+ "node": ">=4"
+ }
+ },
"node_modules/@babel/helper-validator-identifier": {
- "version": "7.19.1",
- "resolved": "https://registry.npmjs.org/@babel/helper-validator-identifier/-/helper-validator-identifier-7.19.1.tgz",
- "integrity": "sha512-awrNfaMtnHUr653GgGEs++LlAvW6w+DcPrOliSMXWCKo597CwL5Acf/wWdNkf/tfEQE3mjkeD1YOVZOUV/od1w==",
+ "version": "7.22.20",
+ "resolved": "https://registry.npmjs.org/@babel/helper-validator-identifier/-/helper-validator-identifier-7.22.20.tgz",
+ "integrity": "sha512-Y4OZ+ytlatR8AI+8KZfKuL5urKp7qey08ha31L8b3BwewJAoJamTzyvxPR/5D+KkdJCGPq/+8TukHBlY10FX9A==",
"dev": true,
"engines": {
"node": ">=6.9.0"
}
},
"node_modules/@babel/highlight": {
- "version": "7.18.6",
- "resolved": "https://registry.npmjs.org/@babel/highlight/-/highlight-7.18.6.tgz",
- "integrity": "sha512-u7stbOuYjaPezCuLj29hNW1v64M2Md2qupEKP1fHc7WdOA3DgLh37suiSrZYY7haUB7iBeQZ9P1uiRF359do3g==",
+ "version": "7.23.4",
+ "resolved": "https://registry.npmjs.org/@babel/highlight/-/highlight-7.23.4.tgz",
+ "integrity": "sha512-acGdbYSfp2WheJoJm/EBBBLh/ID8KDc64ISZ9DYtBmC8/Q204PZJLHyzeB5qMzJ5trcOkybd78M4x2KWsUq++A==",
"dev": true,
"dependencies": {
- "@babel/helper-validator-identifier": "^7.18.6",
- "chalk": "^2.0.0",
+ "@babel/helper-validator-identifier": "^7.22.20",
+ "chalk": "^2.4.2",
"js-tokens": "^4.0.0"
},
"engines": {
@@ -121,4525 +184,1219 @@
}
},
"node_modules/@commitlint/cli": {
- "version": "16.3.0",
- "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-16.3.0.tgz",
- "integrity": "sha512-P+kvONlfsuTMnxSwWE1H+ZcPMY3STFaHb2kAacsqoIkNx66O0T7sTpBxpxkMrFPyhkJiLJnJWMhk4bbvYD3BMA==",
+ "version": "19.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-19.0.0.tgz",
+ "integrity": "sha512-SVBQG6k+eOOmlejYTtxnqJGmhrzy/m0qH3bVeoHY3gtlJBK3Kb32RjJioteBYk8Vuo58x5ehAjXwsQFX58X+xw==",
"dev": true,
"dependencies": {
- "@commitlint/format": "^16.2.1",
- "@commitlint/lint": "^16.2.4",
- "@commitlint/load": "^16.3.0",
- "@commitlint/read": "^16.2.1",
- "@commitlint/types": "^16.2.1",
- "lodash": "^4.17.19",
- "resolve-from": "5.0.0",
- "resolve-global": "1.0.0",
+ "@commitlint/format": "^19.0.0",
+ "@commitlint/lint": "^19.0.0",
+ "@commitlint/load": "^19.0.0",
+ "@commitlint/read": "^19.0.0",
+ "@commitlint/types": "^19.0.0",
+ "execa": "^8.0.1",
+ "resolve-from": "^5.0.0",
+ "resolve-global": "^2.0.0",
"yargs": "^17.0.0"
},
"bin": {
"commitlint": "cli.js"
},
"engines": {
- "node": ">=v12"
+ "node": ">=v18"
}
},
- "node_modules/@commitlint/config-conventional": {
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}
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"dev": true
},
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"resolved": "https://registry.npmjs.org/type-fest/-/type-fest-0.21.3.tgz",
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+ "dev": true,
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+ },
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+ }
},
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"resolved": "https://registry.npmjs.org/typedarray/-/typedarray-0.0.6.tgz",
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+ "resolved": "https://registry.npmjs.org/typescript/-/typescript-5.3.3.tgz",
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+ }
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+ }
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+ "node_modules/undici-types": {
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"dev": true,
- "optional": true
+ "peer": true
},
- "universalify": {
- "version": "2.0.0",
- "resolved": "https://registry.npmjs.org/universalify/-/universalify-2.0.0.tgz",
- "integrity": "sha512-hAZsKq7Yy11Zu1DE0OzWjw7nnLZmJZYTDZZyEFHZdUhV8FkH5MCfoU1XMaxXovpyW5nq5scPqq0ZDP9Zyl04oQ==",
- "dev": true
+ "node_modules/unicorn-magic": {
+ "version": "0.1.0",
+ "resolved": "https://registry.npmjs.org/unicorn-magic/-/unicorn-magic-0.1.0.tgz",
+ "integrity": "sha512-lRfVq8fE8gz6QMBuDM6a+LO3IAzTi05H6gCVaUpir2E1Rwpo4ZUog45KpNXKC/Mn3Yb9UDuHumeFTo9iV/D9FQ==",
+ "dev": true,
+ "engines": {
+ "node": ">=18"
+ },
+ "funding": {
+ "url": "https://github.com/sponsors/sindresorhus"
+ }
+ },
+ "node_modules/universalify": {
+ "version": "2.0.1",
+ "resolved": "https://registry.npmjs.org/universalify/-/universalify-2.0.1.tgz",
+ "integrity": "sha512-gptHNQghINnc/vTGIk0SOFGFNXw7JVrlRUtConJRlvaw6DuX0wO5Jeko9sWrMBhh+PsYAZ7oXAiOnf/UKogyiw==",
+ "dev": true,
+ "engines": {
+ "node": ">= 10.0.0"
+ }
},
- "uri-js": {
+ "node_modules/uri-js": {
"version": "4.4.1",
"resolved": "https://registry.npmjs.org/uri-js/-/uri-js-4.4.1.tgz",
"integrity": "sha512-7rKUyy33Q1yc98pQ1DAmLtwX109F7TIfWlW1Ydo8Wl1ii1SeHieeh0HHfPeL2fMXK6z0s8ecKs9frCuLJvndBg==",
"dev": true,
- "requires": {
+ "dependencies": {
"punycode": "^2.1.0"
}
},
- "util-deprecate": {
+ "node_modules/util-deprecate": {
"version": "1.0.2",
"resolved": "https://registry.npmjs.org/util-deprecate/-/util-deprecate-1.0.2.tgz",
"integrity": "sha512-EPD5q1uXyFxJpCrLnCc1nHnq3gOa6DZBocAIiI2TaSCA7VCJ1UJDMagCzIkXNsUYfD1daK//LTEQ8xiIbrHtcw==",
"dev": true
},
- "v8-compile-cache-lib": {
- "version": "3.0.1",
- "resolved": "https://registry.npmjs.org/v8-compile-cache-lib/-/v8-compile-cache-lib-3.0.1.tgz",
- "integrity": "sha512-wa7YjyUGfNZngI/vtK0UHAN+lgDCxBPCylVXGp0zu59Fz5aiGtNXaq3DhIov063MorB+VfufLh3JlF2KdTK3xg==",
- "dev": true
- },
- "validate-npm-package-license": {
+ "node_modules/validate-npm-package-license": {
"version": "3.0.4",
"resolved": "https://registry.npmjs.org/validate-npm-package-license/-/validate-npm-package-license-3.0.4.tgz",
"integrity": "sha512-DpKm2Ui/xN7/HQKCtpZxoRWBhZ9Z0kqtygG8XCgNQ8ZlDnxuQmWhj566j8fN4Cu3/JmbhsDo7fcAJq4s9h27Ew==",
"dev": true,
- "requires": {
+ "dependencies": {
"spdx-correct": "^3.0.0",
"spdx-expression-parse": "^3.0.0"
}
},
- "wcwidth": {
+ "node_modules/wcwidth": {
"version": "1.0.1",
"resolved": "https://registry.npmjs.org/wcwidth/-/wcwidth-1.0.1.tgz",
"integrity": "sha512-XHPEwS0q6TaxcvG85+8EYkbiCux2XtWG2mkc47Ng2A77BQu9+DqIOJldST4HgPkuea7dvKSj5VgX3P1d4rW8Tg==",
"dev": true,
- "requires": {
+ "dependencies": {
"defaults": "^1.0.3"
}
},
- "which": {
+ "node_modules/which": {
"version": "2.0.2",
"resolved": "https://registry.npmjs.org/which/-/which-2.0.2.tgz",
"integrity": "sha512-BLI3Tl1TW3Pvl70l3yq3Y64i+awpwXqsGBYWkkqMtnbXgrMD+yj7rhW0kuEDxzJaYXGjEW5ogapKNMEKNMjibA==",
"dev": true,
- "requires": {
+ "dependencies": {
"isexe": "^2.0.0"
+ },
+ "bin": {
+ "node-which": "bin/node-which"
+ },
+ "engines": {
+ "node": ">= 8"
}
},
- "word-wrap": {
- "version": "1.2.4",
- "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz",
- "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==",
- "dev": true
+ "node_modules/word-wrap": {
+ "version": "1.2.5",
+ "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.5.tgz",
+ "integrity": "sha512-BN22B5eaMMI9UMtjrGd5g5eCYPpCPDUy0FJXbYsaT5zYxjFOckS53SQDE3pWkVoWpHXVb3BrYcEN4Twa55B5cA==",
+ "dev": true,
+ "engines": {
+ "node": ">=0.10.0"
+ }
},
- "wordwrap": {
+ "node_modules/wordwrap": {
"version": "1.0.0",
"resolved": "https://registry.npmjs.org/wordwrap/-/wordwrap-1.0.0.tgz",
"integrity": "sha512-gvVzJFlPycKc5dZN4yPkP8w7Dc37BtP1yczEneOb4uq34pXZcvrtRTmWV8W+Ume+XCxKgbjM+nevkyFPMybd4Q==",
"dev": true
},
- "wrap-ansi": {
- "version": "7.0.0",
- "resolved": "https://registry.npmjs.org/wrap-ansi/-/wrap-ansi-7.0.0.tgz",
- "integrity": "sha512-YVGIj2kamLSTxw6NsZjoBxfSwsn0ycdesmc4p+Q21c5zPuZ1pl+NfxVdxPtdHvmNVOQ6XSYG4AUtyt/Fi7D16Q==",
+ "node_modules/wrap-ansi": {
+ "version": "6.2.0",
+ "resolved": "https://registry.npmjs.org/wrap-ansi/-/wrap-ansi-6.2.0.tgz",
+ "integrity": "sha512-r6lPcBGxZXlIcymEu7InxDMhdW0KDxpLgoFLcguasxCaJ/SOIZwINatK9KY/tf+ZrlywOKU0UDj3ATXUBfxJXA==",
"dev": true,
- "requires": {
+ "peer": true,
+ "dependencies": {
"ansi-styles": "^4.0.0",
"string-width": "^4.1.0",
"strip-ansi": "^6.0.0"
+ },
+ "engines": {
+ "node": ">=8"
}
},
- "wrappy": {
+ "node_modules/wrappy": {
"version": "1.0.2",
"resolved": "https://registry.npmjs.org/wrappy/-/wrappy-1.0.2.tgz",
"integrity": "sha512-l4Sp/DRseor9wL6EvV2+TuQn63dMkPjZ/sp9XkghTEbV9KlPS1xUsZ3u7/IQO4wxtcFB4bgpQPRcR3QCvezPcQ==",
"dev": true
},
- "xtend": {
+ "node_modules/xtend": {
"version": "4.0.2",
"resolved": "https://registry.npmjs.org/xtend/-/xtend-4.0.2.tgz",
"integrity": "sha512-LKYU1iAXJXUgAXn9URjiu+MWhyUXHsvfp7mcuYm9dSUKK0/CjtrUwFAxD82/mCWbtLsGjFIad0wIsod4zrTAEQ==",
- "dev": true
+ "dev": true,
+ "engines": {
+ "node": ">=0.4"
+ }
},
- "y18n": {
+ "node_modules/y18n": {
"version": "5.0.8",
"resolved": "https://registry.npmjs.org/y18n/-/y18n-5.0.8.tgz",
"integrity": "sha512-0pfFzegeDWJHJIAmTLRP2DwHjdF5s7jo9tuztdQxAhINCdvS+3nGINqPd00AphqJR/0LhANUS6/+7SCb98YOfA==",
- "dev": true
+ "dev": true,
+ "engines": {
+ "node": ">=10"
+ }
},
- "yallist": {
+ "node_modules/yallist": {
"version": "4.0.0",
"resolved": "https://registry.npmjs.org/yallist/-/yallist-4.0.0.tgz",
"integrity": "sha512-3wdGidZyq5PB084XLES5TpOSRA3wjXAlIWMhum2kRcv/41Sn2emQ0dycQW4uZXLejwKvg6EsvbdlVL+FYEct7A==",
"dev": true
},
- "yaml": {
- "version": "1.10.2",
- "resolved": "https://registry.npmjs.org/yaml/-/yaml-1.10.2.tgz",
- "integrity": "sha512-r3vXyErRCYJ7wg28yvBY5VSoAF8ZvlcW9/BwUzEtUsjvX/DKs24dIkuwjtuprwJJHsbyUbLApepYTR1BN4uHrg==",
- "dev": true
- },
- "yargs": {
- "version": "17.6.0",
- "resolved": "https://registry.npmjs.org/yargs/-/yargs-17.6.0.tgz",
- "integrity": "sha512-8H/wTDqlSwoSnScvV2N/JHfLWOKuh5MVla9hqLjK3nsfyy6Y4kDSYSvkU5YCUEPOSnRXfIyx3Sq+B/IWudTo4g==",
+ "node_modules/yargs": {
+ "version": "17.7.2",
+ "resolved": "https://registry.npmjs.org/yargs/-/yargs-17.7.2.tgz",
+ "integrity": "sha512-7dSzzRQ++CKnNI/krKnYRV7JKKPUXMEh61soaHKg9mrWEhzFWhFnxPxGl+69cD1Ou63C13NUPCnmIcrvqCuM6w==",
"dev": true,
- "requires": {
+ "dependencies": {
"cliui": "^8.0.1",
"escalade": "^3.1.1",
"get-caller-file": "^2.0.5",
"require-directory": "^2.1.1",
"string-width": "^4.2.3",
"y18n": "^5.0.5",
- "yargs-parser": "^21.0.0"
+ "yargs-parser": "^21.1.1"
},
- "dependencies": {
- "yargs-parser": {
- "version": "21.1.1",
- "resolved": "https://registry.npmjs.org/yargs-parser/-/yargs-parser-21.1.1.tgz",
- "integrity": "sha512-tVpsJW7DdjecAiFpbIB1e3qxIQsE6NoPc5/eTdrbbIC4h0LVsWhnoa3g+m2HclBIujHzsxZ4VJVA+GUuc2/LBw==",
- "dev": true
- }
+ "engines": {
+ "node": ">=12"
}
},
- "yargs-parser": {
+ "node_modules/yargs-parser": {
"version": "20.2.9",
"resolved": "https://registry.npmjs.org/yargs-parser/-/yargs-parser-20.2.9.tgz",
"integrity": "sha512-y11nGElTIV+CT3Zv9t7VKl+Q3hTQoT9a1Qzezhhl6Rp21gJ/IVTW7Z3y9EWXhuUBC2Shnf+DX0antecpAwSP8w==",
- "dev": true
+ "dev": true,
+ "engines": {
+ "node": ">=10"
+ }
},
- "yn": {
- "version": "3.1.1",
- "resolved": "https://registry.npmjs.org/yn/-/yn-3.1.1.tgz",
- "integrity": "sha512-Ux4ygGWsu2c7isFWe8Yu1YluJmqVhxqK2cLXNQA5AcC3QfbGNpM7fu0Y8b/z16pXLnFxZYvWhd3fhBY9DLmC6Q==",
- "dev": true
+ "node_modules/yargs/node_modules/yargs-parser": {
+ "version": "21.1.1",
+ "resolved": "https://registry.npmjs.org/yargs-parser/-/yargs-parser-21.1.1.tgz",
+ "integrity": "sha512-tVpsJW7DdjecAiFpbIB1e3qxIQsE6NoPc5/eTdrbbIC4h0LVsWhnoa3g+m2HclBIujHzsxZ4VJVA+GUuc2/LBw==",
+ "dev": true,
+ "engines": {
+ "node": ">=12"
+ }
},
- "yocto-queue": {
+ "node_modules/yocto-queue": {
"version": "0.1.0",
"resolved": "https://registry.npmjs.org/yocto-queue/-/yocto-queue-0.1.0.tgz",
"integrity": "sha512-rVksvsnNCdJ/ohGc6xgPwyN8eheCxsiLM8mxuE/t/mOVqJewPuO1miLpTHQiRgTKCLexL4MeAFVagts7HmNZ2Q==",
- "dev": true
+ "dev": true,
+ "engines": {
+ "node": ">=10"
+ },
+ "funding": {
+ "url": "https://github.com/sponsors/sindresorhus"
+ }
+ },
+ "tools/conventional-changelog-tf-a": {
+ "version": "2.10.0",
+ "dev": true,
+ "license": "BSD-3-Clause",
+ "dependencies": {
+ "conventional-changelog-conventionalcommits": "^4.6.1",
+ "execa": "^5.1.1",
+ "lodash": "^4.17.21",
+ "q": "^1.5.1"
+ }
}
}
}
diff --git a/package.json b/package.json
index 1c557fd..43c897e 100644
--- a/package.json
+++ b/package.json
@@ -2,22 +2,23 @@
"name": "trusted-firmware-a",
"version": "2.10.0",
"license": "BSD-3-Clause",
+ "type": "module",
"private": true,
"scripts": {
"postinstall": "husky install",
"release": "standard-version"
},
"engines": {
- "node": ">=16.0.0"
+ "node": ">=20"
},
"devDependencies": {
- "@commitlint/cli": "^16.1.0",
- "@commitlint/config-conventional": "^16.0.0",
- "@commitlint/cz-commitlint": "^16.1.0",
- "commitizen": "^4.2.4",
+ "@commitlint/cli": "^19.0.0",
+ "@commitlint/config-conventional": "^19.0.0",
+ "@commitlint/cz-commitlint": "^19.0.0",
+ "commitizen": "^4.3.0",
"conventional-changelog-tf-a": "file:tools/conventional-changelog-tf-a",
- "husky": "^7.0.4",
+ "husky": "^9.0.11",
"js-yaml": "^4.1.0",
- "standard-version": "^9.3.2"
+ "standard-version": "^9.5.0"
}
}
diff --git a/plat/arm/board/tc/fdts/tc_fw_config.dts b/plat/arm/board/tc/fdts/tc_fw_config.dts
index a84c7f8..982da5b 100644
--- a/plat/arm/board/tc/fdts/tc_fw_config.dts
+++ b/plat/arm/board/tc/fdts/tc_fw_config.dts
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
+#include <platform_def.h>
/dts-v1/;
@@ -25,8 +26,8 @@
};
hw-config {
- load-address = <0x0 0x83000000>;
- max-size = <0x8000>;
+ load-address = <0x0 PLAT_HW_CONFIG_DTB_BASE>;
+ max-size = <PLAT_HW_CONFIG_DTB_SIZE>;
id = <HW_CONFIG_ID>;
};
};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_common_sp_manifest.dtsi b/plat/arm/board/tc/fdts/tc_spmc_common_sp_manifest.dtsi
new file mode 100644
index 0000000..06c2937
--- /dev/null
+++ b/plat/arm/board/tc/fdts/tc_spmc_common_sp_manifest.dtsi
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Secure world memory map. For a full view of the DRAM map, see platform_def.h
+ *
+ * 0xf900_c000 ------------------
+ * | ... |
+ * 0xf901_c000 ------------------
+ * | (63MB) | Trusty (=/=> OP-TEE)
+ * 0xfcf1_c000 ------------------
+ * | ... |
+ * 0xfd00_0000 ------------------
+ * | (512K) | Hafnium
+ * 0xfd08_0000 ------------------
+ * | ... | Hafnium stack
+ * 0xfd28_0000 ------------------
+ * | (11MB) | OP-TEE (=/=> Trusty)
+ * 0xfdd8_0000 ------------------
+ * | ... |
+ * 0xfde0_0000 ------------------
+ * | (2MB) | Firmware Upgrade
+ * 0xfec0_0000 ------------------
+ * | (2MB) | Crypto
+ * 0xfee0_0000 ------------------
+ * | (2MB) | Internal Truested Storage
+ * 0xff00_0000 ------------------
+ */
+&hafnium {
+ vm1 {
+ is_ffa_partition;
+ vcpu_count = <8>;
+ /* partition information filled in separately */
+ };
+#ifdef TS_SP_FW_CONFIG
+ vm2 {
+ is_ffa_partition;
+ debug_name = "internal-trusted-storage";
+ load_address = <0xfee00000>;
+ vcpu_count = <1>;
+ mem_size = <0x200000>; /* 2MB TZC DRAM */
+ };
+ vm3 {
+ is_ffa_partition;
+ debug_name = "crypto";
+ load_address = <0xfec00000>;
+ vcpu_count = <1>;
+ mem_size = <0x200000>; /* 2MB TZC DRAM */
+ };
+ vm4 {
+ is_ffa_partition;
+ debug_name = "firmware-update";
+ load_address = <0xfde00000>;
+ vcpu_count = <1>;
+ mem_size = <0xe00000>; /* 14MB TZC DRAM */
+ };
+#endif
+};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
similarity index 66%
rename from plat/arm/board/tc/fdts/tc_spmc_manifest.dts
rename to plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
index 8ef6330..3bc0cbb 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
@@ -1,9 +1,9 @@
/*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-/dts-v1/;
+#include <platform_def.h>
/ {
compatible = "arm,ffa-core-manifest-1.0";
@@ -20,36 +20,9 @@
binary_size = <0x80000>;
};
- hypervisor {
+ hafnium:hypervisor {
compatible = "hafnium,hafnium";
- vm1 {
- is_ffa_partition;
- debug_name = "cactus-primary";
- load_address = <0xfe000000>;
- vcpu_count = <8>;
- mem_size = <1048576>;
- };
- vm2 {
- is_ffa_partition;
- debug_name = "cactus-secondary";
- load_address = <0xfe100000>;
- vcpu_count = <8>;
- mem_size = <1048576>;
- };
- vm3 {
- is_ffa_partition;
- debug_name = "cactus-tertiary";
- load_address = <0xfe200000>;
- vcpu_count = <1>;
- mem_size = <1048576>;
- };
- vm4 {
- is_ffa_partition;
- debug_name = "ivy";
- load_address = <0xfe600000>;
- vcpu_count = <1>;
- mem_size = <1048576>;
- };
+ /* filled in in top level .dts */
};
cpus {
@@ -117,16 +90,21 @@
};
};
+ /* the full secure world range */
memory@0 {
device_type = "memory";
- reg = <0x0 0xfd000000 0x0 0x2000000>,
- <0x0 0x7000000 0x0 0x1000000>,
+ reg = <0x0 TC_TZC_DRAM1_BASE 0x0 TC_TZC_DRAM1_SIZE>,
<0x0 0xff000000 0x0 0x1000000>;
};
memory@1 {
device_type = "ns-memory";
- reg = <0x00008800 0x80000000 0x0 0x7f000000>,
- <0x0 0x88000000 0x1 0x00000000>;
+ reg =
+#ifdef TS_SP_FW_CONFIG
+ <0x0 0x08000000 0x0 0x4000000>,
+#endif /* TS_SP_FW_CONFIG */
+ <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
+ <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
+ HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
index 73314ee..840b80f 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
@@ -1,129 +1,17 @@
/*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
-/ {
- compatible = "arm,ffa-core-manifest-1.0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- attribute {
- spmc_id = <0x8000>;
- maj_ver = <0x1>;
- min_ver = <0x2>;
- exec_state = <0x0>;
- load_address = <0x0 0xfd000000>;
- entrypoint = <0x0 0xfd000000>;
- binary_size = <0x80000>;
- };
-
- hypervisor {
- compatible = "hafnium,hafnium";
- vm1 {
- is_ffa_partition;
- debug_name = "op-tee";
- load_address = <0xfd280000>;
- vcpu_count = <8>;
-#ifdef TS_SP_FW_CONFIG
- mem_size = <26738688>; /* 25MB TZC DRAM */
-#else
- mem_size = <30928896>; /* 29MB TZC DRAM */
-#endif
- };
-#ifdef TS_SP_FW_CONFIG
- vm2 {
- is_ffa_partition;
- debug_name = "internal-trusted-storage";
- load_address = <0xfee00000>;
- vcpu_count = <1>;
- mem_size = <2097152>; /* 2MB TZC DRAM */
- };
- vm3 {
- is_ffa_partition;
- debug_name = "crypto";
- load_address = <0xfec00000>;
- vcpu_count = <1>;
- mem_size = <2097152>; /* 2MB TZC DRAM */
- };
-#endif
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- };
-
- /*
- * SPMC (Hafnium) requires secondary cpu nodes are declared in
- * descending order
- */
- CPU7:cpu@700 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x700>;
- enable-method = "psci";
- };
-
- CPU6:cpu@600 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x600>;
- enable-method = "psci";
- };
-
- CPU5:cpu@500 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x500>;
- enable-method = "psci";
- };
-
- CPU4:cpu@400 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x400>;
- enable-method = "psci";
- };
-
- CPU3:cpu@300 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x300>;
- enable-method = "psci";
- };
-
- CPU2:cpu@200 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x200>;
- enable-method = "psci";
- };
-
- CPU1:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0xfd000000 0x0 0x2000000>;
- };
+#include <tc_spmc_manifest.dtsi>
+#include <tc_spmc_common_sp_manifest.dtsi>
- memory@1 {
- device_type = "ns-memory";
- reg = <0x0 0x80000000 0x0 0x79000000>,
- <0x80 0x80000000 0x1 0x80000000>;
+&hafnium {
+ vm1 {
+ debug_name = "op-tee";
+ load_address = <0xfd280000>;
+ mem_size = <0xb00000>; /* 11MB TZC DRAM */
};
};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_test_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_test_manifest.dts
new file mode 100644
index 0000000..2e35f82
--- /dev/null
+++ b/plat/arm/board/tc/fdts/tc_spmc_test_manifest.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+#include <tc_spmc_manifest.dtsi>
+
+/ {
+ hypervisor {
+ vm1 {
+ is_ffa_partition;
+ debug_name = "cactus-primary";
+ load_address = <0xfe000000>;
+ vcpu_count = <8>;
+ mem_size = <1048576>;
+ };
+ vm2 {
+ is_ffa_partition;
+ debug_name = "cactus-secondary";
+ load_address = <0xfe100000>;
+ vcpu_count = <8>;
+ mem_size = <1048576>;
+ };
+ vm3 {
+ is_ffa_partition;
+ debug_name = "cactus-tertiary";
+ load_address = <0xfe200000>;
+ vcpu_count = <1>;
+ mem_size = <1048576>;
+ };
+ vm4 {
+ is_ffa_partition;
+ debug_name = "ivy";
+ load_address = <0xfe600000>;
+ vcpu_count = <1>;
+ mem_size = <1048576>;
+ };
+ };
+};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_trusty_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_trusty_sp_manifest.dts
new file mode 100644
index 0000000..8233eda
--- /dev/null
+++ b/plat/arm/board/tc/fdts/tc_spmc_trusty_sp_manifest.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+#include <tc_spmc_manifest.dtsi>
+#include <tc_spmc_common_sp_manifest.dtsi>
+
+&hafnium {
+ vm1 {
+ debug_name = "trusty";
+ load_address = <0xf901c000>;
+ mem_size = <0x3f00000>; /* 64MB TZC DRAM - 1MB align */
+ };
+};
diff --git a/plat/arm/board/tc/fdts/tc_tb_fw_config.dts b/plat/arm/board/tc/fdts/tc_tb_fw_config.dts
index 4c6ccef..c58f17b 100644
--- a/plat/arm/board/tc/fdts/tc_tb_fw_config.dts
+++ b/plat/arm/board/tc/fdts/tc_tb_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,12 +41,21 @@
uuid = "d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0";
load-address = <0xfec00000>;
};
+ firmware-update {
+ uuid = "6823a838-1b06-470e-9774-0cce8bfb53fd";
+ load-address = <0xfde00000>;
+ };
#endif
#if OPTEE_SP_FW_CONFIG
op-tee {
uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
load-address = <0xfd280000>;
};
+#elif TRUSTY_SP_FW_CONFIG
+ trusty {
+ uuid = "40ee25f0-a2bc-304c-8c4c-a173c57d8af1";
+ load-address = <0xf901c000>;
+ };
#else
cactus-primary {
uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index e8f97e1..a42e39d 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -17,8 +17,6 @@
#include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h>
-#define PLATFORM_CORE_COUNT 8
-
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
/*
@@ -30,6 +28,17 @@
* - Region to load secure partitions
*
*
+ * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE
+ * | DTB |
+ * | (32K) |
+ * 0x8000_8000 ------------------
+ * | ... |
+ * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE
+ * | FWU shmem |
+ * | (4MB) |
+ * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE
+ * | OP-TEE shmem |
+ * | (2MB) |
* 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE
* | |
* | SPMC |
@@ -46,7 +55,7 @@
*/
#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
TC_TZC_DRAM1_SIZE)
-#define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */
+#define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */
#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
TC_TZC_DRAM1_SIZE - 1)
@@ -54,8 +63,12 @@
#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
ARM_TZC_DRAM1_SIZE - \
TC_TZC_DRAM1_SIZE)
-#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \
- TC_NS_DRAM1_SIZE - 1)
+#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1)
+
+#define TC_NS_OPTEE_SIZE (2 * SZ_1M)
+#define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE)
+#define TC_NS_FWU_SIZE (4 * SZ_1M)
+#define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE)
/*
* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
@@ -71,7 +84,7 @@
TC_TZC_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
-#define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000)
+#define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE
#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
#define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \
@@ -186,6 +199,13 @@
#define TC_DEVICE_BASE 0x21000000
#define TC_DEVICE_SIZE 0x5f000000
+#if defined(TARGET_FLAVOUR_FPGA)
+#undef V2M_FLASH0_BASE
+#undef V2M_FLASH0_SIZE
+#define V2M_FLASH0_BASE UL(0x0C000000)
+#define V2M_FLASH0_SIZE UL(0x02000000)
+#endif
+
// TC_MAP_DEVICE covers different peripherals
// available to the platform
#define TC_MAP_DEVICE MAP_REGION_FLAT( \
@@ -206,12 +226,24 @@
#define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE)
#define PLAT_ARM_NSRAM_BASE 0x06000000
+#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
+#else /* TARGET_FLAVOUR_FPGA */
+#define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */
+#endif /* TARGET_FLAVOUR_FPGA */
+#if TARGET_PLATFORM <= 2
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#elif TARGET_PLATFORM == 3
+#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
+#endif /* TARGET_PLATFORM == 3 */
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
+#define TC_NS_MTE_SIZE (256 * SZ_1M)
+/* the SCP puts the carveout at the end of DRAM2 */
+#define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE)
+
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \
INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \
@@ -221,6 +253,8 @@
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
+#define PLAT_ARM_SP_MAX_SIZE U(0x2000000)
+
/*******************************************************************************
* Memprotect definitions
******************************************************************************/
@@ -252,11 +286,21 @@
CSS_SCMI_PAYLOAD_SIZE_MAX)
#define PLAT_ARM_CLUSTER_COUNT U(1)
+#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2
+#define PLAT_MAX_CPUS_PER_CLUSTER U(14)
+#else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
+#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_PE_PER_CPU U(1)
+#define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT)
+
/* Message Handling Unit (MHU) base addresses */
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
+#if TARGET_PLATFORM <= 2
+ #define PLAT_CSS_MHU_BASE UL(0x45400000)
+#elif TARGET_PLATFORM == 3
+ #define PLAT_CSS_MHU_BASE UL(0x46000000)
+#endif /* TARGET_PLATFORM == 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* TC2: AP<->RSS MHUs */
@@ -335,16 +379,41 @@
/* UART related constants */
-#undef PLAT_ARM_BOOT_UART_BASE
-#define PLAT_ARM_BOOT_UART_BASE 0x2A410000
+#define TC_UART0 0x2a400000
+#define TC_UART1 0x2a410000
+/*
+ * TODO: if any more undefs are needed, it's better to consider dropping the
+ * board_css_def.h include above
+ */
+#undef PLAT_ARM_BOOT_UART_BASE
#undef PLAT_ARM_RUN_UART_BASE
-#define PLAT_ARM_RUN_UART_BASE 0x2A400000
-
#undef PLAT_ARM_SP_MIN_RUN_UART_BASE
#define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE
#undef PLAT_ARM_CRASH_UART_BASE
+#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
+#undef PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+#if TARGET_FLAVOUR_FVP
+#define PLAT_ARM_BOOT_UART_BASE TC_UART1
+#define TC_UARTCLK 7372800
+#else /* TARGET_FLAVOUR_FPGA */
+#define PLAT_ARM_BOOT_UART_BASE TC_UART0
+#if TARGET_PLATFORM <= 2
+#define TC_UARTCLK 5000000
+#elif TARGET_PLATFORM >= 3
+#define TC_UARTCLK 3750000
+#endif /* TARGET_PLATFORM >= 3 */
+#undef ARM_CONSOLE_BAUDRATE
+#define ARM_CONSOLE_BAUDRATE 38400
+#endif /* TARGET_FLAVOUR_FPGA */
+
+#define PLAT_ARM_RUN_UART_BASE TC_UART0
+#define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 6874cfa..652a17e 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -1,61 +1,72 @@
-# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include common/fdt_wrappers.mk
-ifeq ($(TARGET_PLATFORM), 0)
- $(error Platform ${PLAT}$(TARGET_PLATFORM) is deprecated.)
-endif
-
-ifeq ($(TARGET_PLATFORM), 1)
- $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
- Some of the features might not work as expected)
-endif
-
-ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
- $(error TARGET_PLATFORM must be less than or equal to 2)
-endif
-
-$(eval $(call add_define,TARGET_PLATFORM))
+TARGET_FLAVOUR := fvp
+# DPU with SCMI may not necessarily work, so allow its independence
+TC_DPU_USE_SCMI_CLK := 1
+# SCMI power domain control enable
+TC_SCMI_PD_CTRL_EN := 1
+# IOMMU: Enable the use of system or individual MMUs
+TC_IOMMU_EN := 1
-CSS_LOAD_SCP_IMAGES := 1
-
-CSS_USE_SCMI_SDS_DRIVER := 1
-
-ENABLE_FEAT_RAS := 1
-
-SDEI_SUPPORT := 0
+# System setup
+CSS_USE_SCMI_SDS_DRIVER := 1
+HW_ASSISTED_COHERENCY := 1
+USE_COHERENT_MEM := 0
+GIC_ENABLE_V4_EXTN := 1
+GICV3_SUPPORT_GIC600 := 1
+override NEED_BL2U := no
+override ARM_PLAT_MT := 1
-EL3_EXCEPTION_HANDLING := 0
+# CPU setup
+ARM_ARCH_MINOR := 7
+BRANCH_PROTECTION := 1
+ENABLE_FEAT_MPAM := 1 # default is 2, optimise
+ENABLE_SVE_FOR_NS := 2 # to show we use it
+ENABLE_SVE_FOR_SWD := 1
+ENABLE_TRBE_FOR_NS := 1
+ENABLE_SYS_REG_TRACE_FOR_NS := 1
+ENABLE_FEAT_AMU := 1
+ENABLE_AMU_FCONF := 1
+ENABLE_AMU_AUXILIARY_COUNTERS := 1
+ENABLE_MPMM := 1
+ENABLE_MPMM_FCONF := 1
-HANDLE_EA_EL3_FIRST_NS := 0
+CTX_INCLUDE_AARCH32_REGS := 0
-# System coherency is managed in hardware
-HW_ASSISTED_COHERENCY := 1
-
-# When building for systems with hardware-assisted coherency, there's no need to
-# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
-USE_COHERENT_MEM := 0
+ifeq (${SPD},spmd)
+ SPMD_SPM_AT_SEL2 := 1
+ ENABLE_FEAT_MTE := 1
+ CTX_INCLUDE_PAUTH_REGS := 1
+endif
-GIC_ENABLE_V4_EXTN := 1
-# GIC-600 configuration
-GICV3_SUPPORT_GIC600 := 1
+ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
+ $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
+ Some of the features might not work as expected)
+endif
-# Enable SVE
-ENABLE_SVE_FOR_NS := 2
-ENABLE_SVE_FOR_SWD := 1
+ifeq ($(shell expr $(TARGET_PLATFORM) \<= 3), 0)
+ $(error TARGET_PLATFORM must be less than or equal to 3)
+endif
-# enable trace buffer control registers access to NS by default
-ENABLE_TRBE_FOR_NS := 1
+ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),)
+ $(error TARGET_FLAVOUR must be fvp or fpga)
+endif
-# enable trace system registers access to NS by default
-ENABLE_SYS_REG_TRACE_FOR_NS := 1
+$(eval $(call add_defines, \
+ TARGET_PLATFORM \
+ TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
+ TC_DPU_USE_SCMI_CLK \
+ TC_SCMI_PD_CTRL_EN \
+ TC_IOMMU_EN \
+))
-# enable trace filter control registers access to NS by default
-ENABLE_TRF_FOR_NS := 1
+CSS_LOAD_SCP_IMAGES := 1
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -64,13 +75,10 @@
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
-override NEED_BL2U := no
-
-override ARM_PLAT_MT := 1
-
TC_BASE = plat/arm/board/tc
-PLAT_INCLUDES += -I${TC_BASE}/include/
+PLAT_INCLUDES += -I${TC_BASE}/include/ \
+ -I${TC_BASE}/fdts/
# CPU libraries for TARGET_PLATFORM=1
ifeq (${TARGET_PLATFORM}, 1)
@@ -86,6 +94,13 @@
lib/cpus/aarch64/cortex_x4.S
endif
+# CPU libraries for TARGET_PLATFORM=3
+ifeq (${TARGET_PLATFORM}, 3)
+TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
+ lib/cpus/aarch64/cortex_chaberton.S \
+ lib/cpus/aarch64/cortex_blackhawk.S
+endif
+
INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c
PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \
@@ -133,7 +148,7 @@
ifeq (${SPD},spmd)
ifeq ($(ARM_SPMC_MANIFEST_DTS),)
-ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts
+ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_test_manifest.dts
endif
FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
@@ -152,19 +167,6 @@
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG}))
-override CTX_INCLUDE_AARCH32_REGS := 0
-
-override CTX_INCLUDE_PAUTH_REGS := 1
-
-override ENABLE_SPE_FOR_NS := 0
-
-override ENABLE_FEAT_AMU := 1
-override ENABLE_AMU_AUXILIARY_COUNTERS := 1
-override ENABLE_AMU_FCONF := 1
-
-override ENABLE_MPMM := 1
-override ENABLE_MPMM_FCONF := 1
-
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build
# flags present in Measured Boot makefile.
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index aac7ece..d884366 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -75,6 +75,25 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ /*
+ * Pass the hw_config to BL33 in R0. You'll notice that
+ * arm_bl31_early_platform_setup does something similar but only behind
+ * ARM_LINUX_KERNEL_AS_BL33 and we want to pass the DTB even to a
+ * bootloader. Lucky for us, it copies the ep_info BL2 gave us to BL33
+ * unconditionally in the generic case so hijack that.
+ * TODO: this goes away with firmware handoff when it will be proper
+ */
+
+ bl_params_node_t *bl_params = ((bl_params_t *)arg0)->head;
+
+ while (bl_params != NULL) {
+ if (bl_params->image_id == BL33_IMAGE_ID) {
+ bl_params->ep_info->args.arg0 = arg2;
+ break;
+ }
+ bl_params = bl_params->next_params_info;
+ }
+
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
/* Fill the properties struct with the info from the config dtb */
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index 27d4b11..e5d05c4 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c
@@ -30,6 +30,7 @@
#if IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
+ TC_MAP_NS_DRAM1,
TC_FLASH0_RO,
TC_MAP_DEVICE,
{0}
diff --git a/plat/arm/board/tc/tc_topology.c b/plat/arm/board/tc/tc_topology.c
index 9e18da6..cc0dcc2 100644
--- a/plat/arm/board/tc/tc_topology.c
+++ b/plat/arm/board/tc/tc_topology.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
+#include <platform_def.h>
/******************************************************************************
* The power domain tree descriptor.
@@ -36,6 +37,14 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+#if PLATFORM_CORE_COUNT == 14
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
+#endif /* PLATFORM_CORE_COUNT == 14 */
};
/*******************************************************************************