Merge "fix(nuvoton): prevent changing clock frequency" into integration
diff --git a/Makefile b/Makefile
index 800346a..7058d57 100644
--- a/Makefile
+++ b/Makefile
@@ -1221,7 +1221,6 @@
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
ENABLE_FEAT_HCX \
- ENABLE_FEAT_MTE \
ENABLE_FEAT_MTE2 \
ENABLE_FEAT_PAN \
ENABLE_FEAT_RNG \
@@ -1235,7 +1234,6 @@
ENABLE_FEAT_S1POE \
ENABLE_FEAT_GCS \
ENABLE_FEAT_VHE \
- ENABLE_FEAT_MTE_PERM \
ENABLE_FEAT_MPAM \
ENABLE_RME \
ENABLE_SPE_FOR_NS \
@@ -1384,9 +1382,7 @@
ENABLE_FEAT_S2POE \
ENABLE_FEAT_S1POE \
ENABLE_FEAT_GCS \
- ENABLE_FEAT_MTE \
ENABLE_FEAT_MTE2 \
- ENABLE_FEAT_MTE_PERM \
FEATURE_DETECTION \
TWED_DELAY \
ENABLE_FEAT_TWED \
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index f1b1fa6..474b4d5 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -165,7 +165,7 @@
/* If FEAT_MTE2 is implemented mask tag faults by setting TCO bit */
new_spsr |= old_spsr & SPSR_TCO_BIT_AARCH64;
- if (read_feat_mte_id_field() >= MTE_IMPLEMENTED_ELX) {
+ if (is_feat_mte2_present()) {
new_spsr |= SPSR_TCO_BIT_AARCH64;
}
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index d8031f9..805575a 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -239,10 +239,10 @@
service_arg1 = (uint64_t)(service_args >> 64U);
/*
- * Write a dummy value to an MTE register, to simulate usage in the
+ * Write a dummy value to an MTE2 register, to simulate usage in the
* secure world
*/
- if (is_feat_mte_supported()) {
+ if (is_feat_mte2_supported()) {
write_gcr_el1(0x99);
}
diff --git a/changelog.yaml b/changelog.yaml
index 3875a48..b7f281c 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -116,8 +116,11 @@
- title: Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM)
scope: mpam
- - title: Memory Tagging Extension
- scope: mte
+ - title: Memory Tagging Extension2
+ scope: mte2
+
+ deprecated:
+ - mte
- title: Pointer Authentication Extension
scope: pauth
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 7a2f0d7..7f01037 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -167,9 +167,7 @@
"TRF", 1, 1);
/* v8.5 features */
- check_feature(ENABLE_FEAT_MTE, read_feat_mte_id_field(), "MTE",
- MTE_IMPLEMENTED_EL0, MTE_IMPLEMENTED_ASY);
- check_feature(ENABLE_FEAT_MTE2, read_feat_mte_id_field(), "MTE2",
+ check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
read_feat_bti();
@@ -204,8 +202,6 @@
"S2POE", 1, 1);
check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
"S1POE", 1, 1);
- check_feature(ENABLE_FEAT_MTE_PERM, read_feat_mte_perm_id_field(),
- "MTE_PERM", 1, 1);
check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
"CSV2_3", 3, 3);
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst
index 4834d3a..b6f4219 100644
--- a/docs/components/secure-partition-manager.rst
+++ b/docs/components/secure-partition-manager.rst
@@ -215,7 +215,7 @@
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
- ENABLE_FEAT_MTE=1 \
+ ENABLE_FEAT_MTE2=1 \
BL32=<path-to-hafnium-binary> \
BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \
@@ -233,7 +233,7 @@
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
- ENABLE_FEAT_MTE=1 \
+ ENABLE_FEAT_MTE2=1 \
BL32=<path-to-hafnium-binary> \
BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 4ee184c..5733214 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -918,6 +918,10 @@
For Cortex-A720, the following errata build flags are defined :
+- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to
+ Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+ It is fixed in r0p2.
+
- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to
Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
It is fixed in r0p2.
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index fa06c8e..2ba54ea 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2800,9 +2800,11 @@
- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
option set to 1. This option defaults to 0.
-- Memory Tagging Extension feature is unconditionally enabled for both worlds.
- To enable MTE at EL0 use ``ENABLE_FEAT_MTE`` is required and to enable MTE at
- ELX ``ENABLE_FEAT_MTE2`` is required.
+- Memory Tagging Extension feature has few variants but not all of them require
+ enablement from EL3 to be used at lower EL. e.g. Memory tagging only at
+ EL0(MTE) does not require EL3 configuration however memory tagging at
+ EL2/EL1 (MTE2) does require EL3 enablement and we need to set this option
+ ``ENABLE_FEAT_MTE2`` to 1. This option defaults to 0.
Armv7-A
~~~~~~~
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index f817da0..c18c155 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -340,23 +340,11 @@
flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
-- ``ENABLE_FEAT_MTE``: Numeric value to enable Memory Tagging Extension
- if the platform wants to use this feature at EL0 ``ENABLE_FEAT_MTE`` is
- required. This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
- feature detection mechanism. Default value is ``0``.
-
- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2
if the platform wants to use this feature and MTE2 is enabled at ELX.
This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
-- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for
- ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to
- memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural
- feature available from v8.9 and upwards. This flag can take the values 0 to
- 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is
- ``0``.
-
- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
permission fault for any privileged data access from EL1/EL2 to virtual
diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst
index 762801d..014221e 100644
--- a/docs/security_advisories/security-advisory-tfv-9.rst
+++ b/docs/security_advisories/security-advisory-tfv-9.rst
@@ -87,7 +87,7 @@
+----------------------+
| Neoverse-V2 |
+----------------------+
-| Neoverse-Poseidon |
+| Neoverse-V3 |
+----------------------+
For all other cores impacted by Spectre-BHB, some of which that do not implement
diff --git a/drivers/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/renesas/rcar/qos/D3/qos_init_d3.c
index b96e822..8e1ebcb 100644
--- a/drivers/renesas/rcar/qos/D3/qos_init_d3.c
+++ b/drivers/renesas/rcar/qos/D3/qos_init_d3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,7 @@
struct rcar_gen3_dbsc_qos_settings d3_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
{ DBSC_DBSCHSZ0, 0x00000001 },
diff --git a/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
index 6f4c66c..1931dd1 100644
--- a/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
+++ b/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,7 +28,7 @@
struct rcar_gen3_dbsc_qos_settings e3_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
{ DBSC_DBSCHSZ0, 0x00000001 },
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
index 329bcb8..6d93313 100644
--- a/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,7 @@
struct rcar_gen3_dbsc_qos_settings h3_v11_qos[] = {
/* BUFCAM settings */
/* DBSC_DBCAM0CNF0 not set */
- { DBSC_DBCAM0CNF1, 0x00044218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
/* DBSC_DBCAM0CNF3 not set */
{ DBSC_DBSCHCNT0, 0x080F0037 },
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
index c20ab08..f44da87 100644
--- a/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,7 +63,7 @@
struct rcar_gen3_dbsc_qos_settings h3_v20_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4U },
{ DBSC_DBCAM0CNF3, 0x00000000U },
{ DBSC_DBSCHCNT0, 0x000F0037U },
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
index 1fe6182..867d9e0 100644
--- a/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,7 +62,7 @@
struct rcar_gen3_dbsc_qos_settings h3_v30_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4U },
{ DBSC_DBCAM0CNF3, 0x00000000U },
{ DBSC_DBSCHCNT0, 0x000F0037U },
diff --git a/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
index f1ee41b..d758dbf 100644
--- a/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ b/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,7 +62,7 @@
struct rcar_gen3_dbsc_qos_settings h3n_v30_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4U },
{ DBSC_DBCAM0CNF3, 0x00000000U },
{ DBSC_DBSCHCNT0, 0x000F0037U },
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
index a8264cb..d096d01 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,7 +19,7 @@
struct rcar_gen3_dbsc_qos_settings m3_v10_qos[] = {
/* BUFCAM settings */
/* DBSC_DBCAM0CNF0 not set */
- { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBCAM0CNF3, 0x00000000 },
{ DBSC_DBSCHCNT0, 0x080F0037 },
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
index 22fd83a..640fe80 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2017-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,7 +62,7 @@
struct rcar_gen3_dbsc_qos_settings m3_v11_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBCAM0CNF3, 0x00000000 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
index 43d21d7..f5ca4b6 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2019-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,7 +62,7 @@
struct rcar_gen3_dbsc_qos_settings m3_v30_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBCAM0CNF3, 0x00000000 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
diff --git a/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
index 446340b..95c6ac9 100644
--- a/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+++ b/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2017-2024, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -60,7 +60,7 @@
struct rcar_gen3_dbsc_qos_settings m3n_v10_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00043218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
{ DBSC_DBSCHSZ0, 0x00000001 },
diff --git a/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c b/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
index 076876c..4e1734c 100644
--- a/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
+++ b/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * Copyright (c) 2015-2024, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -19,7 +19,7 @@
struct rcar_gen3_dbsc_qos_settings v3m_qos[] = {
/* BUFCAM settings */
- { DBSC_DBCAM0CNF1, 0x00044218 },
+ { DBSC_DBCAM0CNF1, 0x00048218U },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBSCHCNT0, 0x080F003F },
{ DBSC_DBSCHCNT1, 0x00001010 },
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index 734a6b5..b52e4d0 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -159,7 +159,6 @@
static inline bool is_feat_spe_supported(void) { return false; }
static inline bool is_feat_rng_supported(void) { return false; }
static inline bool is_feat_gcs_supported(void) { return false; }
-static inline bool is_feat_mte_supported(void) { return false; }
static inline bool is_feat_mte2_supported(void) { return false; }
static inline bool is_feat_mpam_supported(void) { return false; }
static inline bool is_feat_hcx_supported(void) { return false; }
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index de59d45..7582fc6 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -105,6 +105,10 @@
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
ID_AA64PFR1_EL1_MTE_MASK);
}
+static inline unsigned int is_feat_mte2_present(void)
+{
+ return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX;
+}
static inline bool is_feat_ssbs_present(void)
{
@@ -136,18 +140,14 @@
ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
}
-CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
- ENABLE_FEAT_MTE)
-CREATE_FEATURE_FUNCS_VER(feat_mte2, read_feat_mte_id_field, MTE_IMPLEMENTED_ELX,
- ENABLE_FEAT_MTE2)
+CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX,
+ ENABLE_FEAT_MTE2)
CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
ENABLE_FEAT_SEL2)
CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
ENABLE_FEAT_TWED)
CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
ENABLE_FEAT_FGT)
-CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
- ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
ENABLE_FEAT_ECV)
CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h
index e542d4e..fb27f79 100644
--- a/include/lib/cpus/aarch64/cortex_a720.h
+++ b/include/lib/cpus/aarch64/cortex_a720.h
@@ -13,6 +13,11 @@
#define CORTEX_A720_BHB_LOOP_COUNT U(132)
/*******************************************************************************
+ * CPU Auxiliary Control register 1 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0
+
+/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
deleted file mode 100644
index 117826d..0000000
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NEOVERSE_POSEIDON_H
-#define NEOVERSE_POSEIDON_H
-
-
-#define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830)
-#define NEOVERSE_POSEIDON_V_MIDR U(0x410FD840)
-
-/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
-#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions.
- ******************************************************************************/
-#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* NEOVERSE_POSEIDON_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v3.h b/include/lib/cpus/aarch64/neoverse_v3.h
new file mode 100644
index 0000000..e5f75ba
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_v3.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_V3_H
+#define NEOVERSE_V3_H
+
+
+#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830)
+#define NEOVERSE_V3_MIDR U(0x410FD840)
+
+/* Neoverse V3 loop count for CVE-2022-23960 mitigation */
+#define NEOVERSE_V3_BHB_LOOP_COUNT U(132)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_V3_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 44efee5..fbaa008 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -141,7 +141,7 @@
#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
#endif /* NS_TIMER_SWITCH */
-#if ENABLE_FEAT_MTE
+#if ENABLE_FEAT_MTE2
#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
@@ -151,7 +151,7 @@
#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
#else
#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
-#endif /* ENABLE_FEAT_MTE */
+#endif /* ENABLE_FEAT_MTE2 */
/*
* End of system registers.
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index abd649c..a5be22d 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -60,15 +60,18 @@
check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0)
-/* Errata applies only when Static profiling extension is enabled. */
workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290
- /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
+/* Erratum 2413290 workaround is required only if SPE is enabled */
+#if ENABLE_SPE_FOR_NS != 0
+ /* Check if Static profiling extension is implemented or present. */
mrs x1, id_aa64dfr0_el1
ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
cbz x0, 1f
+ /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57)
sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58)
1:
+#endif
workaround_reset_end cortex_a715, ERRATUM(2413290)
check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0)
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index 2075acd..53a1b78 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -26,6 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
+/* Erratum 2926083 workaround is required only if SPE is enabled */
+#if ENABLE_SPE_FOR_NS != 0
+ /* Check if Static profiling extension is implemented or present. */
+ mrs x1, id_aa64dfr0_el1
+ ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
+ cbz x0, 1f
+ /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
+ sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57)
+ sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58)
+1:
+#endif
+workaround_reset_end cortex_a720, ERRATUM(2926083)
+
+check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1)
+
workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794
sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37)
workaround_reset_end cortex_a720, ERRATUM(2940794)
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
deleted file mode 100644
index 54c2ff9..0000000
--- a/lib/cpus/aarch64/neoverse_poseidon.S
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <neoverse_poseidon.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-#include "wa_cve_2022_23960_bhb_vector.S"
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
-#endif /* WORKAROUND_CVE_2022_23960 */
-
-workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
-#if IMAGE_BL31
- /*
- * The Neoverse-poseidon generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- override_vector_table wa_cve_vbar_neoverse_poseidon
-
-#endif /* IMAGE_BL31 */
-workaround_reset_end neoverse_poseidon, CVE(2022,23960)
-
-check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-
- /* ---------------------------------------------
- * HW will do the cache maintenance while powering down
- * ---------------------------------------------
- */
-func neoverse_poseidon_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
- NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-
- isb
- ret
-endfunc neoverse_poseidon_core_pwr_dwn
-
-cpu_reset_func_start neoverse_poseidon
- /* Disable speculative loads */
- msr SSBS, xzr
-cpu_reset_func_end neoverse_poseidon
-
-errata_report_shim neoverse_poseidon
-
- /* ---------------------------------------------
- * This function provides Neoverse-Poseidon specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.neoverse_poseidon_regs, "aS"
-neoverse_poseidon_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func neoverse_poseidon_cpu_reg_dump
- adr x6, neoverse_poseidon_regs
- mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
- ret
-endfunc neoverse_poseidon_cpu_reg_dump
-
-declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
- neoverse_poseidon_reset_func, \
- neoverse_poseidon_core_pwr_dwn
-
-declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_V_MIDR, \
- neoverse_poseidon_reset_func, \
- neoverse_poseidon_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
new file mode 100644
index 0000000..67258c8
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_v3.S
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_v3.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+#include "wa_cve_2022_23960_bhb_vector.S"
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
+#endif /* WORKAROUND_CVE_2022_23960 */
+
+workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse V3 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_v3
+
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v3, CVE(2022,23960)
+
+check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+ /* ---------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ---------------------------------------------
+ */
+func neoverse_v3_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------
+ */
+ sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
+ NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
+ isb
+ ret
+endfunc neoverse_v3_core_pwr_dwn
+
+cpu_reset_func_start neoverse_v3
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end neoverse_v3
+
+errata_report_shim neoverse_v3
+
+ /* ---------------------------------------------
+ * This function provides Neoverse V3 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_v3_regs, "aS"
+neoverse_v3_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_v3_cpu_reg_dump
+ adr x6, neoverse_v3_regs
+ mrs x8, NEOVERSE_V3_CPUECTLR_EL1
+ ret
+endfunc neoverse_v3_cpu_reg_dump
+
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
+ neoverse_v3_reset_func, \
+ neoverse_v3_core_pwr_dwn
+
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
+ neoverse_v3_reset_func, \
+ neoverse_v3_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index a7a8c8a..872f6c7 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -940,6 +940,10 @@
# only to revision r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2561034
+# Flag to apply erratum 2926083 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_A720_2926083
+
# Flag to apply erratum 2940794 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2940794
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index ee94dfd..7a00e47 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1277,7 +1277,7 @@
el2_sysregs_context_save_common(el2_sysregs_ctx);
el2_sysregs_context_save_gic(el2_sysregs_ctx);
- if (is_feat_mte_supported()) {
+ if (is_feat_mte2_supported()) {
write_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
}
@@ -1363,7 +1363,7 @@
el2_sysregs_context_restore_common(el2_sysregs_ctx);
el2_sysregs_context_restore_gic(el2_sysregs_ctx);
- if (is_feat_mte_supported()) {
+ if (is_feat_mte2_supported()) {
write_tfsr_el2(read_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2));
}
@@ -1508,12 +1508,12 @@
write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1());
#endif /* NS_TIMER_SWITCH */
-#if ENABLE_FEAT_MTE
+#if ENABLE_FEAT_MTE2
write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1());
write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1());
write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1());
write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1());
-#endif /* ENABLE_FEAT_MTE */
+#endif /* ENABLE_FEAT_MTE2 */
}
@@ -1563,12 +1563,12 @@
write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1));
#endif /* NS_TIMER_SWITCH */
-#if ENABLE_FEAT_MTE
+#if ENABLE_FEAT_MTE2
write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1));
write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1));
write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1));
write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1));
-#endif /* ENABLE_FEAT_MTE */
+#endif /* ENABLE_FEAT_MTE2 */
}
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 643d550..ac47960 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -307,27 +307,16 @@
# registers, by setting SCR_EL3.TRNDR.
ENABLE_FEAT_RNG_TRAP ?= 0
-# Enable Memory Tagging Extension. This must be set to 1 if the platform wants
-# to use this feature in the Secure world and MTE is enabled at ELX.
ifeq ($(CTX_INCLUDE_MTE_REGS),1)
- $(warning CTX_INCLUDE_MTE_REGS option is deprecated use ENABLE_FEAT_MTE, Enabling ENABLE_FEAT_MTE)
- ENABLE_FEAT_MTE ?= 1
+ $(warning CTX_INCLUDE_MTE_REGS option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
-ifeq (${ARCH},aarch32)
- ifneq ($(or $(ENABLE_FEAT_MTE),0),0)
- $(error ENABLE_FEAT_MTE is not supported for AArch32)
- endif
+ifeq ($(ENABLE_FEAT_MTE),1)
+ $(warning ENABLE_FEAT_MTE option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
-ENABLE_FEAT_MTE ?= 0
-ENABLE_FEAT_MTE2 ?= 0
-
-# Add a error message to indicate incorrect MTE2 selection without MTE enabled.
-ifneq ($(ENABLE_FEAT_MTE2),0)
- ifeq ($(ENABLE_FEAT_MTE),0)
- $(error ENABLE_FEAT_MTE2 is not supported without enabling ENABLE_FEAT_MTE)
- endif
-endif
+# Enable FEAT_MTE2. This must be set to 1 if the platform wants
+# to use this feature and is enabled at ELX.
+ENABLE_FEAT_MTE2 ?= 0
#----
# 8.6
@@ -352,9 +341,6 @@
# 8.9
#----
-# Flag to enable NoTagAccess memory region attribute for stage 2 of translation.
-ENABLE_FEAT_MTE_PERM ?= 0
-
# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE).
ENABLE_FEAT_S2PIE ?= 0
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 569ac3f..6b995af 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -76,7 +76,6 @@
ENABLE_FEAT_CSV2_3 := 2
ENABLE_FEAT_DIT := 2
ENABLE_FEAT_PAN := 2
-ENABLE_FEAT_MTE_PERM := 2
ENABLE_FEAT_VHE := 2
CTX_INCLUDE_NEVE_REGS := 2
ENABLE_FEAT_SEL2 := 2
@@ -205,6 +204,7 @@
lib/cpus/aarch64/cortex_a78c.S \
lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_a715.S \
+ lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 2f23d80..b30e40c 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -40,7 +40,6 @@
ifeq (${SPD},spmd)
SPMD_SPM_AT_SEL2 := 1
- ENABLE_FEAT_MTE := 1
CTX_INCLUDE_PAUTH_REGS := 1
endif
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index dc9dd59..bff8fb4 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -77,11 +77,31 @@
static const struct imx_csu_cfg csu_cfg[] = {
/* peripherals csl setting */
- CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED),
+ CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
+ CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED),
+ CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED),
/* master HP0~1 */
/* SA setting */
+ CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED),
/* HP control setting */
diff --git a/plat/imx/imx8m/imx8mm/include/imx_sec_def.h b/plat/imx/imx8m/imx8mm/include/imx_sec_def.h
index 6215983..d53c922 100644
--- a/plat/imx/imx8m/imx8mm/include/imx_sec_def.h
+++ b/plat/imx/imx8m/imx8mm/include/imx_sec_def.h
@@ -213,4 +213,26 @@
CSU_CSL_CAAM = 114,
};
+enum csu_sa_idx {
+ CSU_SA_M4 = 1,
+ CSU_SA_SDMA1 = 2,
+ CSU_SA_PCIE_CTRL1 = 3,
+ CSU_SA_USB1 = 4,
+ CSU_SA_USB2 = 5,
+ CSU_SA_VPU = 6,
+ CSU_SA_GPU = 7,
+ CSU_SA_APBHDMA = 8,
+ CSU_SA_ENET = 9,
+ CSU_SA_USDHC1 = 10,
+ CSU_SA_USDHC2 = 11,
+ CSU_SA_USDHC3 = 12,
+ CSU_SA_HUGO = 13,
+ CSU_SA_DAP = 14,
+ CSU_SA_SDMA2 = 15,
+ CSU_SA_CAAM = 16,
+ CSU_SA_SDMA3 = 17,
+ CSU_SA_LCDIF = 18,
+ CSU_SA_CSI = 19,
+};
+
#endif /* IMX_SEC_DEF_H */
diff --git a/plat/imx/imx8m/imx8mn/include/imx_sec_def.h b/plat/imx/imx8m/imx8mn/include/imx_sec_def.h
index 0ef14a9..83c5fa9 100644
--- a/plat/imx/imx8m/imx8mn/include/imx_sec_def.h
+++ b/plat/imx/imx8m/imx8mn/include/imx_sec_def.h
@@ -207,4 +207,23 @@
CSU_CSL_OCRAM_S = 119,
};
+enum csu_sa_idx {
+ CSU_SA_M7 = 1,
+ CSU_SA_SDMA1 = 2,
+ CSU_SA_USB1 = 4,
+ CSU_SA_GPU = 7,
+ CSU_SA_APBHDMA = 8,
+ CSU_SA_ENET1 = 9,
+ CSU_SA_USDHC1 = 10,
+ CSU_SA_USDHC2 = 11,
+ CSU_SA_USDHC3 = 12,
+ CSU_SA_HUGO = 13,
+ CSU_SA_DAP = 14,
+ CSU_SA_SDMA2 = 15,
+ CSU_SA_CAAM = 16,
+ CSU_SA_SDMA3 = 17,
+ CSU_SA_LCDIF = 18,
+ CSU_SA_ISI = 19,
+};
+
#endif /* IMX_SEC_DEF_H */
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index 43fa064..8e35219 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -63,12 +63,45 @@
static const struct imx_csu_cfg csu_cfg[] = {
/* peripherals csl setting */
- CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED),
- CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED),
+ CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED),
+ CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED),
+ CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
+ CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED),
+ CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED),
/* master HP0~1 */
/* SA setting */
+ CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED),
+ CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED),
/* HP control setting */
diff --git a/plat/imx/imx8m/imx8mp/include/imx_sec_def.h b/plat/imx/imx8m/imx8mp/include/imx_sec_def.h
index ba248b5..1ba3033 100644
--- a/plat/imx/imx8m/imx8mp/include/imx_sec_def.h
+++ b/plat/imx/imx8m/imx8mp/include/imx_sec_def.h
@@ -269,6 +269,41 @@
CSU_CSL_OCRAM_A = 113,
CSU_CSL_OCRAM = 118,
CSU_CSL_OCRAM_S = 119,
+ CSU_CSL_VPU = 120,
+};
+
+enum csu_sa_idx {
+ CSU_SA_M7 = 1,
+ CSU_SA_SDMA1 = 2,
+ CSU_SA_PCIE_CTRL1 = 3,
+ CSU_SA_USB1 = 4,
+ CSU_SA_USB2 = 6,
+ CSU_SA_APB_HDMA = 8,
+ CSU_SA_ENET1 = 9,
+ CSU_SA_USDHC1 = 10,
+ CSU_SA_USDHC2 = 11,
+ CSU_SA_USDHC3 = 12,
+ CSU_SA_HUGO = 13,
+ CSU_SA_DAP = 14,
+ CSU_SA_SDMA2 = 15,
+ CSU_SA_CAAM = 16,
+ CSU_SA_SDMA3 = 17,
+ CSU_SA_LCDIF1 = 18,
+ CSU_SA_ISI = 19,
+ CSU_SA_NPU = 20,
+ CSU_SA_LCDIF2 = 21,
+ CSU_SA_HDMI_TX = 22,
+ CSU_SA_ENET2 = 23,
+ CSU_SA_GPU3D = 24,
+ CSU_SA_GPU2D = 25,
+ CSU_SA_VPU_G1 = 26,
+ CSU_SA_VPU_G2 = 27,
+ CSU_SA_VPU_VC8000E = 28,
+ CSU_SA_AUDIO_EDMA = 29,
+ CSU_SA_ISP1 = 30,
+ CSU_SA_ISP2 = 31,
+ CSU_SA_DEWARP = 32,
+ CSU_SA_GIC500 = 33,
};
#endif /* IMX_SEC_DEF_H */
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index 7065a65..70c2def 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -26,6 +26,7 @@
#include <imx_aipstz.h>
#include <imx_uart.h>
#include <imx8m_caam.h>
+#include <imx8m_ccm.h>
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -145,6 +146,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
int i;
/* enable CSU NS access permission */
@@ -154,7 +156,11 @@
imx_aipstz_init(aipstz);
- console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+ if (console_base == 0U) {
+ console_base = imx8m_uart_get_base();
+ }
+
+ console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
/* This console is only used for boot stage */
console_set_scope(&console, CONSOLE_FLAG_BOOT);
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 2356cbd..6556c7f 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -31,6 +31,7 @@
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx8m_caam.c \
+ plat/imx/imx8m/imx8m_ccm.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mq/gpc.c \
plat/imx/common/imx8_topology.c \
@@ -66,6 +67,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30860000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
ifeq (${SPD},trusty)
diff --git a/plat/imx/imx8m/include/imx8m_csu.h b/plat/imx/imx8m/include/imx8m_csu.h
index dc634ed..3851e91 100644
--- a/plat/imx/imx8m/include/imx8m_csu.h
+++ b/plat/imx/imx8m/include/imx8m_csu.h
@@ -20,6 +20,9 @@
#define CSU_SEC_LEVEL_6 0x03
#define CSU_SEC_LEVEL_7 0x0
+#define SEC_ACCESS 0x0
+#define NON_SEC_ACCESS 0x1
+
#define LOCKED 0x1
#define UNLOCKED 0x0
@@ -27,11 +30,11 @@
#define CSLx_LOCK(x) ((0x1 << (((x) % 2) * 16 + 8)))
#define CSLx_CFG(x, n) ((x) << (((n) % 2) * 16))
-#define CSU_HP_REG(x) (IMX_CSU_BASE + ((x) / 16) * 4 + 0x200)
+#define CSU_HP_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x200)
#define CSU_HP_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
#define CSU_HP_CFG(x, n) ((x) << (((n) % 16) * 2))
-#define CSU_SA_REG(x) (IMX_CSU_BASE + 0x218)
+#define CSU_SA_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x218)
#define CSU_SA_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
#define CSU_SA_CFG(x, n) ((x) << (((n) % 16) * 2))
diff --git a/plat/imx/imx8ulp/xrdc/xrdc_config.h b/plat/imx/imx8ulp/xrdc/xrdc_config.h
index 25edd37..d2af55c 100644
--- a/plat/imx/imx8ulp/xrdc/xrdc_config.h
+++ b/plat/imx/imx8ulp/xrdc/xrdc_config.h
@@ -116,13 +116,15 @@
struct xrdc_pac_msc_config imx8ulp_pdac[] = {
{ 0, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC0 */
+ { 0, 44, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC0 slot 44 for CGC1 */
{ 0, 36, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 36 for CMC1 */
{ 0, 41, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 41 for SIM_AD */
{ 1, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC1 */
- { 1, 0, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */
+ { 1, 0, {0, 7, 7, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */
{ 1, 6, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 6 for LPUART6 */
+ { 1, 7, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 7 for LPUART7 */
{ 1, 9, {0, 7, 7, 7, 0, 0, 0, 7} }, /* SAI5 for HIFI4 and eDMA2 */
- { 1, 12, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */
+ { 1, 12, {0, 7, 7, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */
{ 2, PAC_SLOT_ALL, {7, 7, 7, 7, 0, 0, 7, 7} }, /* PAC2 */
};
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index f9917a0..7d8f244 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -34,6 +34,8 @@
#define PM_INIT_SUSPEND_CB (30U)
#define PM_NOTIFY_CB (32U)
#define EVENT_CPU_PWRDWN (4U)
+#define MBOX_SGI_SHARED_IPI (7U)
+
/* 1 sec of wait timeout for secondary core down */
#define PWRDWN_WAIT_TIMEOUT (1000U)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6)
@@ -97,12 +99,32 @@
{
uint32_t payload[4] = {0};
enum pm_ret_status ret;
+ int ipi_status, i;
VERBOSE("Received IPI FIQ from firmware\n");
console_flush();
(void)plat_ic_acknowledge_interrupt();
+ /* Check status register for each IPI except PMC */
+ for (i = IPI_ID_APU; i <= IPI_ID_5; i++) {
+ ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
+
+ /* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
+ if (ipi_status & IPI_MB_STATUS_RECV_PENDING) {
+ plat_ic_raise_ns_sgi(MBOX_SGI_SHARED_IPI, read_mpidr_el1());
+ break;
+ }
+ }
+
+ /* If PMC has not generated interrupt then end ISR */
+ ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
+ if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0) {
+ plat_ic_end_of_interrupt(id);
+ return 0;
+ }
+
+ /* Handle PMC case */
ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0);
if (ret != PM_RET_SUCCESS) {
payload[0] = ret;