| /* |
| * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #include <arch_helpers.h> |
| #include <assert.h> |
| #include <bl_common.h> |
| #include <debug.h> |
| #include <gic_v2.h> |
| #include <interrupt_mgmt.h> |
| #include <platform.h> |
| #include <stdint.h> |
| #include <tegra_private.h> |
| #include <tegra_def.h> |
| |
| /******************************************************************************* |
| * Place the cpu interface in a state where it can never make a cpu exit wfi as |
| * as result of an asserted interrupt. This is critical for powering down a cpu |
| ******************************************************************************/ |
| void tegra_gic_cpuif_deactivate(void) |
| { |
| unsigned int val; |
| |
| /* Disable secure, non-secure interrupts and disable their bypass */ |
| val = gicc_read_ctlr(TEGRA_GICC_BASE); |
| val &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; |
| val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; |
| gicc_write_ctlr(TEGRA_GICC_BASE, val); |
| } |
| |
| /******************************************************************************* |
| * Enable secure interrupts and set the priority mask register to allow all |
| * interrupts to trickle in. |
| ******************************************************************************/ |
| static void tegra_gic_cpuif_setup(unsigned int gicc_base) |
| { |
| gicc_write_ctlr(gicc_base, ENABLE_GRP0 | ENABLE_GRP1); |
| gicc_write_pmr(gicc_base, GIC_PRI_MASK); |
| } |
| |
| /******************************************************************************* |
| * Global gic distributor setup which will be done by the primary cpu after a |
| * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. |
| * It then enables the secure GIC distributor interface. |
| ******************************************************************************/ |
| static void tegra_gic_distif_setup(unsigned int gicd_base) |
| { |
| unsigned int ctr, num_ints; |
| |
| /* |
| * Mark out non-secure interrupts. Calculate number of |
| * IGROUPR registers to consider. Will be equal to the |
| * number of IT_LINES |
| */ |
| num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; |
| num_ints++; |
| for (ctr = 0; ctr < num_ints; ctr++) |
| gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0); |
| |
| /* enable distributor */ |
| gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); |
| } |
| |
| void tegra_gic_setup(void) |
| { |
| tegra_gic_cpuif_setup(TEGRA_GICC_BASE); |
| tegra_gic_distif_setup(TEGRA_GICD_BASE); |
| } |