plat/arm/common/arm_bl31_setup.c - filogic/atf - Gitiles

 /*
  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *
  * Redistributions of source code must retain the above copyright notice, this
  * list of conditions and the following disclaimer.
  *
  * Redistributions in binary form must reproduce the above copyright notice,
  * this list of conditions and the following disclaimer in the documentation
  * and/or other materials provided with the distribution.
  *
  * Neither the name of ARM nor the names of its contributors may be used
  * to endorse or promote products derived from this software without specific
  * prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */

 #include <arch.h>
 #include <arch_helpers.h>
 #include <arm_def.h>
 #include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <console.h>
 #include <debug.h>
 #include <mmio.h>
 #include <plat_arm.h>
 #include <platform.h>


 /*
  * The next 3 constants identify the extents of the code, RO data region and the
  * limit of the BL3-1 image.  These addresses are used by the MMU setup code and
  * therefore they must be page-aligned.  It is the responsibility of the linker
  * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
  * refer to page-aligned addresses.
  */
 #define BL31_RO_BASE (unsigned long)(&__RO_START__)
 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
 #define BL31_END (unsigned long)(&__BL31_END__)

 #if USE_COHERENT_MEM
 /*
  * The next 2 constants identify the extents of the coherent memory region.
  * These addresses are used by the MMU setup code and therefore they must be
  * page-aligned.  It is the responsibility of the linker script to ensure that
  * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
  * refer to page-aligned addresses.
  */
 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
 #endif

 /*
  * Placeholder variables for copying the arguments that have been passed to
  * BL3-1 from BL2.
  */
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;


 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak bl31_early_platform_setup
 #pragma weak bl31_platform_setup
 #pragma weak bl31_plat_arch_setup
 #pragma weak bl31_plat_get_next_image_ep_info
 #pragma weak plat_get_syscnt_freq


 /*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for the
  * security state specified. BL3-3 corresponds to the non-secure image type
  * while BL3-2 corresponds to the secure image type. A NULL pointer is returned
  * if the image does not exist.
  ******************************************************************************/
 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
 {
 	entry_point_info_t *next_image_info;

 	assert(sec_state_is_valid(type));
 	next_image_info = (type == NON_SECURE)
 			? &bl33_image_ep_info : &bl32_image_ep_info;
 	/*
 	 * None of the images on the ARM development platforms can have 0x0
 	 * as the entrypoint
 	 */
 	if (next_image_info->pc)
 		return next_image_info;
 	else
 		return NULL;
 }

 /*******************************************************************************
  * Perform any BL3-1 early platform setup common to ARM standard platforms.
  * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
  * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
  * done before the MMU is initialized so that the memory layout can be used
  * while creating page tables. BL2 has flushed this information to memory, so
  * we are guaranteed to pick up good data.
  ******************************************************************************/
 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
 				void *plat_params_from_bl2)
 {
 	/* Initialize the console to provide early debug support */
 	console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
 			ARM_CONSOLE_BAUDRATE);

 #if RESET_TO_BL31
 	/* There are no parameters from BL2 if BL3-1 is a reset vector */
 	assert(from_bl2 == NULL);
 	assert(plat_params_from_bl2 == NULL);

 	/* Populate entry point information for BL3-2 and BL3-3 */
 	SET_PARAM_HEAD(&bl32_image_ep_info,
 				PARAM_EP,
 				VERSION_1,
 				0);
 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
 	bl32_image_ep_info.pc = BL32_BASE;
 	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();

 	SET_PARAM_HEAD(&bl33_image_ep_info,
 				PARAM_EP,
 				VERSION_1,
 				0);
 	/*
 	 * Tell BL3-1 where the non-trusted software image
 	 * is located and the entry state information
 	 */
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);

 #else
 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
 	assert(from_bl2 != NULL);
 	assert(from_bl2->h.type == PARAM_BL31);
 	assert(from_bl2->h.version >= VERSION_1);
 	/*
 	 * In debug builds, we pass a special value in 'plat_params_from_bl2'
 	 * to verify platform parameters from BL2 to BL3-1.
 	 * In release builds, it's not used.
 	 */
 	assert(((unsigned long long)plat_params_from_bl2) ==
 		ARM_BL31_PLAT_PARAM_VAL);

 	/*
 	 * Copy BL3-2 and BL3-3 entry point information.
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
 	bl32_image_ep_info = *from_bl2->bl32_ep_info;
 	bl33_image_ep_info = *from_bl2->bl33_ep_info;
 #endif
 }

 void bl31_early_platform_setup(bl31_params_t *from_bl2,
 				void *plat_params_from_bl2)
 {
 	arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);

 	/*
 	 * Initialize CCI for this cluster during cold boot.
 	 * No need for locks as no other CPU is active.
 	 */
 	arm_cci_init();
 #if RESET_TO_BL31
 	/*
 	 * Enable CCI coherency for the primary CPU's cluster
 	 * (if earlier BL has not already done so).
 	 * Platform specific PSCI code will enable coherency for other
 	 * clusters.
 	 */
 	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));

 #endif /* RESET_TO_BL31 */
 }

 /*******************************************************************************
  * Perform any BL3-1 platform setup common to ARM standard platforms
  ******************************************************************************/
 void arm_bl31_platform_setup(void)
 {
 	unsigned int reg_val;

 	/* Initialize the gic cpu and distributor interfaces */
 	plat_arm_gic_init();
 	arm_gic_setup();

 #if RESET_TO_BL31
 	/*
 	 * Do initial security configuration to allow DRAM/device access
 	 * (if earlier BL has not already done so).
 	 */
 	plat_arm_security_setup();

 #endif /* RESET_TO_BL31 */

 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
 			CNTCR_FCREQ(0) | CNTCR_EN);

 	/* Allow access to the System counter timer module */
 	reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
 	reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
 	reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
 	mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);

 	reg_val = (1 << CNTNSAR_NS_SHIFT(1));
 	mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);

 	/* Initialize power controller before setting up topology */
 	plat_arm_pwrc_setup();

 	/* Topologies are best known to the platform. */
 	plat_arm_topology_setup();
 }

 void bl31_platform_setup(void)
 {
 	arm_bl31_platform_setup();
 }

 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
  * moment this is only intializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void arm_bl31_plat_arch_setup(void)
 {
 	arm_configure_mmu_el3(BL31_RO_BASE,
 			      (BL31_END - BL31_RO_BASE),
 			      BL31_RO_BASE,
 			      BL31_RO_LIMIT
 #if USE_COHERENT_MEM
 			      , BL31_COHERENT_RAM_BASE,
 			      BL31_COHERENT_RAM_LIMIT
 #endif
 			      );
 }

 void bl31_plat_arch_setup(void)
 {
 	arm_bl31_plat_arch_setup();
 }

 uint64_t plat_get_syscnt_freq(void)
 {
 	uint64_t counter_base_frequency;

 	/* Read the frequency from Frequency modes table */
 	counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);

 	/* The first entry of the frequency modes table must not be 0 */
 	if (counter_base_frequency == 0)
 		panic();

 	return counter_base_frequency;
 }
	/*
	* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
	*
	* Redistribution and use in source and binary forms, with or without
	* modification, are permitted provided that the following conditions are met:
	*
	* Redistributions of source code must retain the above copyright notice, this
	* list of conditions and the following disclaimer.
	*
	* Redistributions in binary form must reproduce the above copyright notice,
	* this list of conditions and the following disclaimer in the documentation
	* and/or other materials provided with the distribution.
	*
	* Neither the name of ARM nor the names of its contributors may be used
	* to endorse or promote products derived from this software without specific
	* prior written permission.
	*
	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	* POSSIBILITY OF SUCH DAMAGE.
	*/

	#include <arch.h>
	#include <arch_helpers.h>
	#include <arm_def.h>
	#include <arm_gic.h>
	#include <assert.h>
	#include <bl_common.h>
	#include <cci.h>
	#include <console.h>
	#include <debug.h>
	#include <mmio.h>
	#include <plat_arm.h>
	#include <platform.h>


	/*
	* The next 3 constants identify the extents of the code, RO data region and the
	* limit of the BL3-1 image. These addresses are used by the MMU setup code and
	* therefore they must be page-aligned. It is the responsibility of the linker
	* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
	* refer to page-aligned addresses.
	*/
	#define BL31_RO_BASE (unsigned long)(&__RO_START__)
	#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
	#define BL31_END (unsigned long)(&__BL31_END__)

	#if USE_COHERENT_MEM
	/*
	* The next 2 constants identify the extents of the coherent memory region.
	* These addresses are used by the MMU setup code and therefore they must be
	* page-aligned. It is the responsibility of the linker script to ensure that
	* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
	* refer to page-aligned addresses.
	*/
	#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
	#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
	#endif

	/*
	* Placeholder variables for copying the arguments that have been passed to
	* BL3-1 from BL2.
	*/
	static entry_point_info_t bl32_image_ep_info;
	static entry_point_info_t bl33_image_ep_info;


	/* Weak definitions may be overridden in specific ARM standard platform */
	#pragma weak bl31_early_platform_setup
	#pragma weak bl31_platform_setup
	#pragma weak bl31_plat_arch_setup
	#pragma weak bl31_plat_get_next_image_ep_info
	#pragma weak plat_get_syscnt_freq


	/*******************************************************************************
	* Return a pointer to the 'entry_point_info' structure of the next image for the
	* security state specified. BL3-3 corresponds to the non-secure image type
	* while BL3-2 corresponds to the secure image type. A NULL pointer is returned
	* if the image does not exist.
	******************************************************************************/
	entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
	{
	entry_point_info_t *next_image_info;

	assert(sec_state_is_valid(type));
	next_image_info = (type == NON_SECURE)
	? &bl33_image_ep_info : &bl32_image_ep_info;
	/*
	* None of the images on the ARM development platforms can have 0x0
	* as the entrypoint
	*/
	if (next_image_info->pc)
	return next_image_info;
	else
	return NULL;
	}

	/*******************************************************************************
	* Perform any BL3-1 early platform setup common to ARM standard platforms.
	* Here is an opportunity to copy parameters passed by the calling EL (S-EL1
	* in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
	* done before the MMU is initialized so that the memory layout can be used
	* while creating page tables. BL2 has flushed this information to memory, so
	* we are guaranteed to pick up good data.
	******************************************************************************/
	void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
	void *plat_params_from_bl2)
	{
	/* Initialize the console to provide early debug support */
	console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
	ARM_CONSOLE_BAUDRATE);

	#if RESET_TO_BL31
	/* There are no parameters from BL2 if BL3-1 is a reset vector */
	assert(from_bl2 == NULL);
	assert(plat_params_from_bl2 == NULL);

	/* Populate entry point information for BL3-2 and BL3-3 */
	SET_PARAM_HEAD(&bl32_image_ep_info,
	PARAM_EP,
	VERSION_1,
	0);
	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
	bl32_image_ep_info.pc = BL32_BASE;
	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();

	SET_PARAM_HEAD(&bl33_image_ep_info,
	PARAM_EP,
	VERSION_1,
	0);
	/*
	* Tell BL3-1 where the non-trusted software image
	* is located and the entry state information
	*/
	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);

	#else
	/*
	* Check params passed from BL2 should not be NULL,
	*/
	assert(from_bl2 != NULL);
	assert(from_bl2->h.type == PARAM_BL31);
	assert(from_bl2->h.version >= VERSION_1);
	/*
	* In debug builds, we pass a special value in 'plat_params_from_bl2'
	* to verify platform parameters from BL2 to BL3-1.
	* In release builds, it's not used.
	*/
	assert(((unsigned long long)plat_params_from_bl2) ==
	ARM_BL31_PLAT_PARAM_VAL);

	/*
	* Copy BL3-2 and BL3-3 entry point information.
	* They are stored in Secure RAM, in BL2's address space.
	*/
	bl32_image_ep_info = *from_bl2->bl32_ep_info;
	bl33_image_ep_info = *from_bl2->bl33_ep_info;
	#endif
	}

	void bl31_early_platform_setup(bl31_params_t *from_bl2,
	void *plat_params_from_bl2)
	{
	arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);

	/*
	* Initialize CCI for this cluster during cold boot.
	* No need for locks as no other CPU is active.
	*/
	arm_cci_init();
	#if RESET_TO_BL31
	/*
	* Enable CCI coherency for the primary CPU's cluster
	* (if earlier BL has not already done so).
	* Platform specific PSCI code will enable coherency for other
	* clusters.
	*/
	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));

	#endif /* RESET_TO_BL31 */
	}

	/*******************************************************************************
	* Perform any BL3-1 platform setup common to ARM standard platforms
	******************************************************************************/
	void arm_bl31_platform_setup(void)
	{
	unsigned int reg_val;

	/* Initialize the gic cpu and distributor interfaces */
	plat_arm_gic_init();
	arm_gic_setup();

	#if RESET_TO_BL31
	/*
	* Do initial security configuration to allow DRAM/device access
	* (if earlier BL has not already done so).
	*/
	plat_arm_security_setup();

	#endif /* RESET_TO_BL31 */

	/* Enable and initialize the System level generic timer */
	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
	CNTCR_FCREQ(0) \| CNTCR_EN);

	/* Allow access to the System counter timer module */
	reg_val = (1 << CNTACR_RPCT_SHIFT) \| (1 << CNTACR_RVCT_SHIFT);
	reg_val \|= (1 << CNTACR_RFRQ_SHIFT) \| (1 << CNTACR_RVOFF_SHIFT);
	reg_val \|= (1 << CNTACR_RWVT_SHIFT) \| (1 << CNTACR_RWPT_SHIFT);
	mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);

	reg_val = (1 << CNTNSAR_NS_SHIFT(1));
	mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);

	/* Initialize power controller before setting up topology */
	plat_arm_pwrc_setup();

	/* Topologies are best known to the platform. */
	plat_arm_topology_setup();
	}

	void bl31_platform_setup(void)
	{
	arm_bl31_platform_setup();
	}

	/*******************************************************************************
	* Perform the very early platform specific architectural setup here. At the
	* moment this is only intializes the mmu in a quick and dirty way.
	******************************************************************************/
	void arm_bl31_plat_arch_setup(void)
	{
	arm_configure_mmu_el3(BL31_RO_BASE,
	(BL31_END - BL31_RO_BASE),
	BL31_RO_BASE,
	BL31_RO_LIMIT
	#if USE_COHERENT_MEM
	, BL31_COHERENT_RAM_BASE,
	BL31_COHERENT_RAM_LIMIT
	#endif
	);
	}

	void bl31_plat_arch_setup(void)
	{
	arm_bl31_plat_arch_setup();
	}

	uint64_t plat_get_syscnt_freq(void)
	{
	uint64_t counter_base_frequency;

	/* Read the frequency from Frequency modes table */
	counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);

	/* The first entry of the frequency modes table must not be 0 */
	if (counter_base_frequency == 0)
	panic();

	return counter_base_frequency;
	}