feat(sctlr2): add support for FEAT_SCTLR2
Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index f1c872b..7c84e0e 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -268,6 +268,13 @@
scr_el3 |= SCR_RCWMASKEn_BIT;
}
+ if (is_feat_sctlr2_supported()) {
+ /* Set the SCTLR2En bit in SCR_EL3 to enable access to
+ * SCTLR2_ELx registers.
+ */
+ scr_el3 |= SCR_SCTLR2En_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
/* Initialize EL2 context registers */
@@ -1445,6 +1452,10 @@
write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2());
write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2());
}
+
+ if (is_feat_sctlr2_supported()) {
+ write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2());
+ }
}
/*******************************************************************************
@@ -1532,6 +1543,10 @@
write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2));
write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2));
}
+
+ if (is_feat_sctlr2_supported()) {
+ write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2));
+ }
}
#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
@@ -1726,6 +1741,10 @@
write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1());
}
+ if (is_feat_sctlr2_supported()) {
+ write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1());
+ }
+
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@@ -1826,6 +1845,11 @@
write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1));
write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1));
}
+
+ if (is_feat_sctlr2_supported()) {
+ write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1));
+ }
+
}
/*******************************************************************************