plat/qemu/qemu_sbsa/sbsa_topology.c

/*
 * Copyright (c) 2020, Nuvia Inc
 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch.h>
#include <common/debug.h>

#include <platform_def.h>
#include "sbsa_private.h"

/* The power domain tree descriptor */
static unsigned char power_domain_tree_desc[PLATFORM_CLUSTER_COUNT + 1];

/*******************************************************************************
 * This function returns the sbsa-ref default topology tree information.
 ******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
	unsigned int i;

	power_domain_tree_desc[0] = PLATFORM_CLUSTER_COUNT;

	for (i = 0U; i < PLATFORM_CLUSTER_COUNT; i++) {
		power_domain_tree_desc[i + 1] = PLATFORM_MAX_CPUS_PER_CLUSTER;
	}

	return power_domain_tree_desc;
}

/*******************************************************************************
 * This function implements a part of the critical interface between the psci
 * generic layer and the platform that allows the former to query the platform
 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
 * in case the MPIDR is invalid.
 ******************************************************************************/
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
	unsigned int cluster_id, cpu_id;

	mpidr &= MPIDR_AFFINITY_MASK;
	if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) {
		ERROR("Invalid MPIDR\n");
		return -1;
	}

	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;

	if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
		ERROR("cluster_id >= PLATFORM_CLUSTER_COUNT define\n");
		return -1;
	}

	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
		ERROR("cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER define\n");
		return -1;
	}

	return plat_qemu_calc_core_pos(mpidr);
}