feat(intel): add in QSPI ECC for Linux
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 58a9967..af08545 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -423,6 +423,16 @@
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
+ case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */
+ case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */
+ case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */
+ case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */
+ case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */
+ case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */
+ case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */
+ case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */
+ case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
+ case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
return 0;
#endif
default:
@@ -451,7 +461,17 @@
return INTEL_SIP_SMC_STATUS_ERROR;
}
- mmio_write_32(reg_addr, val);
+ switch (reg_addr) {
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
+ case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
+ mmio_write_16(reg_addr, val);
+ break;
+#endif
+ default:
+ mmio_write_32(reg_addr, val);
+ break;
+ }
return intel_secure_reg_read(reg_addr, retval);
}