Support for NXP's i.MX8QM SoC
NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) inside, documentation
can be found in below link:
https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES
This patch adds support for booting up SMP linux kernel (v4.9).
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
diff --git a/plat/imx/imx8qm/include/sec_rsrc.h b/plat/imx/imx8qm/include/sec_rsrc.h
new file mode 100644
index 0000000..a623cd3
--- /dev/null
+++ b/plat/imx/imx8qm/include/sec_rsrc.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* resources that are going to stay in secure partition */
+sc_rsrc_t secure_rsrcs[] = {
+ SC_R_MU_0A,
+ SC_R_A53,
+ SC_R_A53_0,
+ SC_R_A53_1,
+ SC_R_A53_2,
+ SC_R_A53_3,
+ SC_R_A72,
+ SC_R_A72_0,
+ SC_R_A72_1,
+ SC_R_GIC,
+ SC_R_GIC_SMMU,
+ SC_R_CCI,
+ SC_R_SYSTEM,
+ SC_R_IRQSTR_SCU2
+};
+
+/* resources that have register access for non-secure domain */
+sc_rsrc_t ns_access_allowed[] = {
+ SC_R_GIC,
+ SC_R_GIC_SMMU,
+ SC_R_CCI
+};