| /* |
| * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #include <arch.h> |
| #include <arch_helpers.h> |
| #include <assert.h> |
| #include <denver.h> |
| #include <debug.h> |
| #include <delay_timer.h> |
| #include <flowctrl.h> |
| #include <mmio.h> |
| #include <platform_def.h> |
| #include <pmc.h> |
| #include <psci.h> |
| #include <tegra_def.h> |
| #include <tegra_private.h> |
| |
| /* |
| * Register used to clear CPU reset signals. Each CPU has two reset |
| * signals: CPU reset (3:0) and Core reset (19:16) |
| */ |
| #define CPU_CMPLX_RESET_CLR 0x344 |
| #define CPU_CORE_RESET_MASK 0x10001 |
| |
| /* Clock and Reset controller registers for system clock's settings */ |
| #define SCLK_RATE 0x30 |
| #define SCLK_BURST_POLICY 0x28 |
| #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| |
| static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| |
| int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| psci_power_state_t *req_state) |
| { |
| int state_id = psci_get_pstate_id(power_state); |
| int cpu = read_mpidr() & MPIDR_CPU_MASK; |
| |
| /* |
| * Sanity check the requested state id, power level and CPU number. |
| * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU |
| * i.e. CPU 0 |
| */ |
| if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) { |
| ERROR("unsupported state id @ power level\n"); |
| return PSCI_E_INVALID_PARAMS; |
| } |
| |
| /* Set lower power states to PLAT_MAX_OFF_STATE */ |
| for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
| req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| |
| /* Set the SYSTEM_SUSPEND state-id */ |
| req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| PSTATE_ID_SOC_POWERDN; |
| |
| return PSCI_E_SUCCESS; |
| } |
| |
| int tegra_soc_pwr_domain_on(u_register_t mpidr) |
| { |
| int cpu = mpidr & MPIDR_CPU_MASK; |
| uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| |
| if (cpu_powergate_mask[cpu] == 0) { |
| |
| /* Deassert CPU reset signals */ |
| mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
| |
| /* Power on CPU using PMC */ |
| tegra_pmc_cpu_on(cpu); |
| |
| /* Fill in the CPU powergate mask */ |
| cpu_powergate_mask[cpu] = 1; |
| |
| } else { |
| /* Power on CPU using Flow Controller */ |
| tegra_fc_cpu_on(cpu); |
| } |
| |
| return PSCI_E_SUCCESS; |
| } |
| |
| int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
| { |
| tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
| return PSCI_E_SUCCESS; |
| } |
| |
| int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
| { |
| #if DEBUG |
| int cpu = read_mpidr() & MPIDR_CPU_MASK; |
| |
| /* SYSTEM_SUSPEND only on CPU0 */ |
| assert(cpu == 0); |
| #endif |
| |
| /* Allow restarting CPU #1 using PMC on suspend exit */ |
| cpu_powergate_mask[1] = 0; |
| |
| /* Program FC to enter suspend state */ |
| tegra_fc_cpu_powerdn(read_mpidr()); |
| |
| /* Suspend DCO operations */ |
| write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); |
| |
| return PSCI_E_SUCCESS; |
| } |
| |
| int tegra_soc_prepare_system_reset(void) |
| { |
| /* |
| * Set System Clock (SCLK) to POR default so that the clock source |
| * for the PMC APB clock would not be changed due to system reset. |
| */ |
| mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
| SCLK_BURST_POLICY_DEFAULT); |
| mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| |
| /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| mdelay(1); |
| |
| return PSCI_E_SUCCESS; |
| } |