Merge pull request #295 from danh-arm/dh/plat-port-reorg
ARM platform port reorganization
diff --git a/Makefile b/Makefile
index 02bb317..d38a283 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -126,9 +126,14 @@
BUILD_BASE := ./build
BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${BUILD_TYPE}
-PLATFORMS := $(shell ls -I common plat/)
+PLAT_MAKEFILE := platform.mk
+# Generate the platforms list by recursively searching for all directories
+# under /plat containing a PLAT_MAKEFILE. Append each platform with a `|`
+# char and strip out the final '|'.
+PLATFORMS := $(shell find plat/ -name '${PLAT_MAKEFILE}' -print0 | \
+ sed -r 's%[^\x00]*\/([^/]*)\/${PLAT_MAKEFILE}\x00%\1|%g' | \
+ sed -r 's/\|$$//')
SPDS := $(shell ls -I none services/spd)
-HELP_PLATFORMS := $(shell echo ${PLATFORMS} | sed 's/ /|/g')
# Convenience function for adding build definitions
# $(eval $(call add_define,FOO)) will have:
@@ -144,9 +149,10 @@
endef
ifeq (${PLAT},)
- $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform")
endif
-ifeq ($(findstring ${PLAT},${PLATFORMS}),)
+PLAT_MAKEFILE_FULL := $(shell find plat/ -wholename '*/${PLAT}/${PLAT_MAKEFILE}')
+ifeq ($(PLAT_MAKEFILE_FULL),)
$(error "Error: Invalid platform. The following platforms are available: ${PLATFORMS}")
endif
@@ -155,7 +161,7 @@
msg_start:
@echo "Building ${PLAT}"
-include plat/${PLAT}/platform.mk
+include ${PLAT_MAKEFILE_FULL}
# Include the CPU specific operations makefile. By default all CPU errata
# workarounds and CPU specifc optimisations are disabled. This can be
@@ -225,6 +231,9 @@
ASFLAGS += -g -Wa,--gdwarf-2
endif
+# Process PLAT flag
+$(eval $(call add_define,PLAT_${PLAT}))
+
# Process NS_TIMER_SWITCH flag
$(eval $(call assert_boolean,NS_TIMER_SWITCH))
$(eval $(call add_define,NS_TIMER_SWITCH))
@@ -633,7 +642,7 @@
${Q}cscope -b -q -k
help:
- @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> [OPTIONS] [TARGET]"
+ @echo "usage: ${MAKE} PLAT=<${PLATFORMS}> [OPTIONS] [TARGET]"
@echo ""
@echo "PLAT is used to specify which platform you wish to build."
@echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 491fd5c..a5db085 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -114,21 +114,36 @@
INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
-#if DEBUG
- unsigned long sctlr_el3 = read_sctlr_el3();
-#endif
image_info_t bl2_image_info = { {0} };
entry_point_info_t bl2_ep = { {0} };
meminfo_t *bl1_tzram_layout;
meminfo_t *bl2_tzram_layout = 0x0;
int err;
+#if DEBUG
+ unsigned long val;
/*
* Ensure that MMU/Caches and coherency are turned on
*/
+ val = read_sctlr_el3();
+ assert(val | SCTLR_M_BIT);
+ assert(val | SCTLR_C_BIT);
+ assert(val | SCTLR_I_BIT);
+ /*
+ * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
+ * provided platform value
+ */
+ val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
+ /*
+ * If CWG is zero, then no CWG information is available but we can
+ * at least check the platform value is less than the architectural
+ * maximum.
+ */
- assert(sctlr_el3 | SCTLR_M_BIT);
- assert(sctlr_el3 | SCTLR_C_BIT);
- assert(sctlr_el3 | SCTLR_I_BIT);
+ if (val != 0)
+ assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
+ else
+ assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
+#endif
/* Perform remaining generic architectural setup from EL3 */
bl1_arch_setup();
diff --git a/bl32/tsp/tsp.mk b/bl32/tsp/tsp.mk
index f17ef1e..aeda31a 100644
--- a/bl32/tsp/tsp.mk
+++ b/bl32/tsp/tsp.mk
@@ -52,7 +52,7 @@
# Include the platform-specific TSP Makefile
# If no platform-specific TSP Makefile exists, it means TSP is not supported
# on this platform.
-TSP_PLAT_MAKEFILE := plat/${PLAT}/tsp/tsp-${PLAT}.mk
+TSP_PLAT_MAKEFILE := $(shell find plat/ -wholename '*/${PLAT}/tsp/tsp-${PLAT}.mk')
ifeq (,$(wildcard ${TSP_PLAT_MAKEFILE}))
$(error TSP is not supported on platform ${PLAT})
else
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index 7163bad..9abe9ba 100644
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -58,9 +58,9 @@
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
spin_lock(&console_lock);
- VERBOSE("TSP: cpu 0x%x sync fiq request from 0x%llx\n",
+ VERBOSE("TSP: cpu 0x%lx sync fiq request from 0x%lx\n",
mpidr, elr_el3);
- VERBOSE("TSP: cpu 0x%x: %d sync fiq requests, %d sync fiq returns\n",
+ VERBOSE("TSP: cpu 0x%lx: %d sync fiq requests, %d sync fiq returns\n",
mpidr,
tsp_stats[linear_id].sync_fiq_count,
tsp_stats[linear_id].sync_fiq_ret_count);
@@ -104,9 +104,9 @@
tsp_stats[linear_id].fiq_count++;
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
spin_lock(&console_lock);
- VERBOSE("TSP: cpu 0x%x handled fiq %d\n",
+ VERBOSE("TSP: cpu 0x%lx handled fiq %d\n",
mpidr, id);
- VERBOSE("TSP: cpu 0x%x: %d fiq requests\n",
+ VERBOSE("TSP: cpu 0x%lx: %d fiq requests\n",
mpidr, tsp_stats[linear_id].fiq_count);
spin_unlock(&console_lock);
#endif
@@ -121,8 +121,8 @@
tsp_stats[linear_id].irq_count++;
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
spin_lock(&console_lock);
- VERBOSE("TSP: cpu 0x%x received irq\n", mpidr);
- VERBOSE("TSP: cpu 0x%x: %d irq requests\n",
+ VERBOSE("TSP: cpu 0x%lx received irq\n", mpidr);
+ VERBOSE("TSP: cpu 0x%lx: %d irq requests\n",
mpidr, tsp_stats[linear_id].irq_count);
spin_unlock(&console_lock);
#endif
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index d8895b2..2a4ce4f 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -38,12 +38,6 @@
#include <tsp.h>
#include "tsp_private.h"
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __BL32_END__;
/*******************************************************************************
* Lock to control access to the console
diff --git a/common/bl_common.c b/common/bl_common.c
index 8c241ec..b9cc0f2 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -137,7 +137,7 @@
if (pos == BOTTOM)
*free_base = addr + size;
- VERBOSE("Reserved %u bytes (discarded %u bytes %s)\n",
+ VERBOSE("Reserved 0x%lx bytes (discarded 0x%lx bytes %s)\n",
reserved_size, discard_size,
pos == TOP ? "above" : "below");
}
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index 32ae60f..70737b5 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -88,13 +88,9 @@
address is platform dependent but it is usually located in a Trusted ROM area.
The BL1 data section is copied to trusted SRAM at runtime.
-On the ARM FVP port, BL1 code starts execution from the reset vector at address
-`0x00000000` (trusted ROM). The BL1 data section is copied to the start of
-trusted SRAM at address `0x04000000`.
-
-On the Juno ARM development platform port, BL1 code starts execution at
-`0x0BEC0000` (FLASH). The BL1 data section is copied to trusted SRAM at address
-`0x04001000.
+On the ARM development platforms, BL1 code starts execution from the reset
+vector defined by the constant `BL1_RO_BASE`. The BL1 data section is copied
+to the top of trusted SRAM as defined by the constant `BL1_RW_BASE`.
The functionality implemented by this stage is as follows.
@@ -189,9 +185,9 @@
#### Platform initialization
BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from
-the CCI-400 slave interface corresponding to the cluster that includes the
-primary CPU. BL1 also initializes UART0 (PL011 console), which enables access to
-the `printf` family of functions in BL1.
+the CCI slave interface corresponding to the cluster that includes the
+primary CPU. BL1 also initializes a UART (PL011 console), which enables access
+to the `printf` family of functions in BL1.
#### BL2 image load and execution
@@ -247,7 +243,7 @@
to determine whether there is enough space to load the BL3-3 image. A platform
defined base address is used to specify the load address for the BL3-1 image.
It also defines the extents of memory available for use by the BL3-2 image.
-BL2 also initializes UART0 (PL011 console), which enables access to the
+BL2 also initializes a UART (PL011 console), which enables access to the
`printf` family of functions in BL2. Platform security is initialized to allow
access to controlled components. The storage abstraction layer is initialized
which is used to load further bootloader images.
@@ -258,8 +254,8 @@
reset and system control. BL2 loads the optional BL3-0 image from platform
storage into a platform-specific region of secure memory. The subsequent
handling of BL3-0 is platform specific. For example, on the Juno ARM development
-platform port the image is transferred into SCP memory using the SCPI protocol
-after being loaded in the trusted SRAM memory at address `0x04009000`. The SCP
+platform port the image is transferred into SCP's internal memory using the Boot
+Over MHU (BOM) protocol after being loaded in the trusted SRAM memory. The SCP
executes BL3-0 and signals to the Application Processor (AP) for BL2 execution
to continue.
@@ -338,7 +334,7 @@
BL3-1 performs detailed platform initialization, which enables normal world
software to function correctly. It also retrieves entrypoint information for
the BL3-3 image loaded by BL2 from the platform defined memory address populated
-by BL2. BL3-1 also initializes UART0 (PL011 console), which enables
+by BL2. BL3-1 also initializes a UART (PL011 console), which enables
access to the `printf` family of functions in BL3-1. It enables the system
level implementation of the generic timer through the memory mapped interface.
@@ -460,7 +456,8 @@
BL3-1 platform code before the caches are enabled.
ARM Trusted Firmware's BL2 implementation passes a `bl31_params` structure in
-`X0` and the FVP port interprets this in the BL3-1 platform code.
+`X0` and the ARM development platforms interpret this in the BL3-1 platform
+code.
##### MMU, Data caches & Coherency
@@ -490,7 +487,7 @@
The structures using this format are `entry_point_info`, `image_info` and
`bl31_params`. The code that allocates and populates these structures must set
-the header fields appropriately, and the `SET_PARA_HEAD()` a macro is defined
+the header fields appropriately, and the `SET_PARAM_HEAD()` a macro is defined
to simplify this action.
#### Required CPU state for BL3-1 Warm boot initialization
@@ -870,10 +867,10 @@
6. Crash Reporting in BL3-1
----------------------------
-The BL3-1 implements a scheme for reporting the processor state when an unhandled
+BL3-1 implements a scheme for reporting the processor state when an unhandled
exception is encountered. The reporting mechanism attempts to preserve all the
-register contents and report it via the default serial output. The general purpose
-registers, EL3, Secure EL1 and some EL2 state registers are reported.
+register contents and report it via a dedicated UART (PL011 console). BL3-1
+reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
A dedicated per-CPU crash stack is maintained by BL3-1 and this is retrieved via
the per-CPU pointer cache. The implementation attempts to minimise the memory
@@ -1253,27 +1250,37 @@
sections must not overstep. The platform code must provide those.
-#### Memory layout on ARM FVPs
+#### Memory layout on ARM development platforms
-The following list describes the memory layout on the FVP:
+The following list describes the memory layout on the ARM development platforms:
-* A 4KB page of shared memory is used to store the entrypoint mailboxes
- and the parameters passed between bootloaders. The shared memory is located
- at the base of the Trusted SRAM. The amount of Trusted SRAM available to
- load the bootloader images will be reduced by the size of the shared memory.
+* A 4KB page of shared memory is used for communication between Trusted
+ Firmware and the platform's power controller. This is located at the base of
+ Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
+ images is reduced by the size of the shared memory.
-* BL1 is originally sitting in the Trusted ROM at address `0x0`. Its
- read-write data are relocated at the top of the Trusted SRAM at runtime.
+ The shared memory is used to store the entrypoint mailboxes for each CPU.
+ On Juno, this is also used for the MHU payload when passing messages to and
+ from the SCP.
+
+* On FVP, BL1 is originally sitting in the Trusted ROM at address `0x0`. On
+ Juno, BL1 resides in flash memory at address `0x0BEC0000`. BL1 read-write
+ data are relocated to the top of Trusted SRAM at runtime.
* BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS
- sections will overwrite BL1 R/W data.
+ sections will overwrite BL1 R/W data. This implies that BL1 global variables
+ remain valid only until execution reaches the BL3-1 entry point during
+ a cold boot.
* BL2 is loaded below BL3-1.
+* On Juno, BL3-0 is loaded temporarily into the BL3-1 memory region and
+ transfered to the SCP before being overwritten by BL3-1.
+
* BL3-2 can be loaded in one of the following locations:
* Trusted SRAM
- * Trusted DRAM
+ * Trusted DRAM (FVP only)
* Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
controller)
@@ -1282,9 +1289,13 @@
memory as possible when it is loaded into Trusted SRAM.
The location of the BL3-2 image will result in different memory maps. This is
-illustrated in the following diagrams using the TSP as an example.
+illustrated for both FVP and Juno in the following diagrams, using the TSP as
+an example.
-**TSP in Trusted SRAM (default option):**
+Note: Loading the BL3-2 image in TZC secured DRAM doesn't change the memory
+layout of the other images in Trusted SRAM.
+
+**FVP with TSP in Trusted SRAM (default option):**
Trusted SRAM
0x04040000 +----------+ loaded by BL2 ------------------
@@ -1305,7 +1316,7 @@
0x00000000 +----------+
-**TSP in Trusted DRAM:**
+**FVP with TSP in Trusted DRAM:**
Trusted DRAM
0x08000000 +----------+
@@ -1330,7 +1341,7 @@
| BL1 (ro) |
0x00000000 +----------+
-**TSP in the TZC-Secured DRAM:**
+**FVP with TSP in TZC-Secured DRAM:**
DRAM
0xffffffff +----------+
@@ -1359,43 +1370,8 @@
| BL1 (ro) |
0x00000000 +----------+
-Moving the TSP image out of the Trusted SRAM doesn't change the memory layout
-of the other boot loader images in Trusted SRAM.
-
-
-#### Memory layout on Juno ARM development platform
-
-The following list describes the memory layout on Juno:
-
-* Trusted SRAM at 0x04000000 contains the MHU page, BL1 r/w section, BL2
- image, BL3-1 image and, optionally, the BL3-2 image.
-
-* The MHU 4 KB page is used as communication channel between SCP and AP. It
- also contains the entrypoint mailboxes for the AP. Mailboxes are stored in
- the first 128 bytes of the MHU page.
-* BL1 resides in flash memory at address `0x0BEC0000`. Its read-write data
- section is relocated to the top of the Trusted SRAM at runtime.
-
-* BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS
- sections will overwrite BL1 R/W data. This implies that BL1 global variables
- will remain valid only until execution reaches the BL3-1 entry point during
- a cold boot.
-
-* BL2 is loaded below BL3-1.
-
-* BL3-0 is loaded temporarily into the BL3-1 memory region and transfered to
- the SCP before being overwritten by BL3-1.
-
-* The BL3-2 image is optional and can be loaded into one of these two
- locations: Trusted SRAM (right after the MHU page) or DRAM (14 MB starting
- at 0xFF000000 and secured by the TrustZone controller). When loaded into
- Trusted SRAM, its NOBITS sections are allowed to overlap BL2.
-
-Depending on the location of the BL3-2 image, it will result in different memory
-maps, illustrated by the following diagrams.
-
-**BL3-2 in Trusted SRAM (default option):**
+**Juno with BL3-2 in Trusted SRAM (default option):**
Flash0
0x0C000000 +----------+
@@ -1420,7 +1396,7 @@
0x04000000 +----------+
-**BL3-2 in the secure region of DRAM:**
+**Juno with BL3-2 in TZC-secured DRAM:**
DRAM
0xFFE00000 +----------+
@@ -1453,9 +1429,6 @@
| MHU |
0x04000000 +----------+
-Loading the BL3-2 image in DRAM doesn't change the memory layout of the other
-images in Trusted SRAM.
-
10. Firmware Image Package (FIP)
---------------------------------
@@ -1524,15 +1497,16 @@
### Loading from a Firmware Image Package (FIP)
The Firmware Image Package (FIP) driver can load images from a binary package on
-non-volatile platform storage. For the FVPs this is currently NOR FLASH.
+non-volatile platform storage. For the ARM development platforms, this is
+currently NOR FLASH.
-Bootloader images are loaded according to the platform policy as specified in
-`plat/<platform>/plat_io_storage.c`. For the FVPs this means the platform will
-attempt to load images from a Firmware Image Package located at the start of NOR
-FLASH0.
+Bootloader images are loaded according to the platform policy as specified by
+the function `plat_get_image_source()`. For the ARM development platforms, this
+means the platform will attempt to load images from a Firmware Image Package
+located at the start of NOR FLASH0.
-Currently the FVP's policy only allows loading of a known set of images. The
-platform policy can be modified to allow additional images.
+The ARM development platforms' policy is to only allow loading of a known set of
+images. The platform policy can be modified to allow additional images.
11. Use of coherent memory in Trusted Firmware
@@ -1743,7 +1717,6 @@
stages mentioned in the previous sections. The code is also divided into the
following categories (present as directories in the source code):
-* **Architecture specific.** This could be AArch32 or AArch64.
* **Platform specific.** Choice of architecture specific code depends upon
the platform.
* **Common code.** This is platform and architecture agnostic code.
@@ -1761,7 +1734,6 @@
bl1 Yes No No
bl2 No Yes No
bl31 No No Yes
- arch Yes Yes Yes
plat Yes Yes Yes
drivers Yes No Yes
common Yes Yes Yes
@@ -1795,7 +1767,7 @@
- - - - - - - - - - - - - - - - - - - - - - - - - -
-_Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
+_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._
[ARM ARM]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html "ARMv8-A Reference Manual (ARM DDI0487A.E)"
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index fd60097..1e49deb 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -33,13 +33,21 @@
* Setting up the execution context in a certain way, or
* Defining certain constants (for example #defines).
-The platform-specific functions and variables are all declared in
+The platform-specific functions and variables are declared in
[include/plat/common/platform.h]. The firmware provides a default implementation
of variables and functions to fulfill the optional requirements. These
implementations are all weakly defined; they are provided to ease the porting
effort. Each platform port can override them with its own implementation if the
default implementation is inadequate.
+Platform ports that want to be aligned with standard ARM platforms (for example
+FVP and Juno) may also use [include/plat/arm/common/plat_arm.h] and the
+corresponding source files in `plat/arm/common/`. These provide standard
+implementations for some of the required platform porting functions. However,
+using these functions requires the platform port to implement additional
+ARM standard platform porting functions. These additional functions are not
+documented here.
+
Some modifications are common to all Boot Loader (BL) stages. Section 2
discusses these in detail. The subsequent sections discuss the remaining
modifications for each BL stage in detail.
@@ -60,8 +68,8 @@
----------------------------------
A platform port must enable the Memory Management Unit (MMU) with identity
mapped page tables, and enable both the instruction and data caches for each BL
-stage. In the ARM FVP port, each BL stage configures the MMU in its platform-
-specific architecture setup function, for example `blX_plat_arch_setup()`.
+stage. In ARM standard platforms, each BL stage configures the MMU in
+the platform-specific architecture setup function, `blX_plat_arch_setup()`.
If the build option `USE_COHERENT_MEM` is enabled, each platform must allocate a
block of identity mapped secure memory with Device-nGnRE attributes aligned to
@@ -87,18 +95,28 @@
Each platform must ensure that a header file of this name is in the system
include path with the following constants defined. This may require updating the
-list of `PLAT_INCLUDES` in the `platform.mk` file. In the ARM FVP port, this
-file is found in [plat/fvp/include/platform_def.h].
+list of `PLAT_INCLUDES` in the `platform.mk` file. In the ARM development
+platforms, this file is found in `plat/arm/board/<plat_name>/include/`.
+
+Platform ports may optionally use the file [include/plat/common/common_def.h],
+which provides typical values for some of the constants below. These values are
+likely to be suitable for all platform ports.
+
+Platform ports that want to be aligned with standard ARM platforms (for example
+FVP and Juno) may also use [include/plat/arm/common/arm_def.h], which provides
+standard values for some of the constants below. However, this requires the
+platform port to define additional platform porting constants in
+`platform_def.h`. These additional constants are not documented here.
* **#define : PLATFORM_LINKER_FORMAT**
Defines the linker format used by the platform, for example
- `elf64-littleaarch64` used by the FVP.
+ `elf64-littleaarch64`.
* **#define : PLATFORM_LINKER_ARCH**
Defines the processor architecture for the linker by the platform, for
- example `aarch64` used by the FVP.
+ example `aarch64`.
* **#define : PLATFORM_STACK_SIZE**
@@ -106,6 +124,11 @@
by [plat/common/aarch64/platform_mp_stack.S] and
[plat/common/aarch64/platform_up_stack.S].
+* **define : CACHE_WRITEBACK_GRANULE**
+
+ Defines the size in bits of the largest cache line across all the cache
+ levels in the platform.
+
* **#define : FIRMWARE_WELCOME_STR**
Defines the character string printed by BL1 upon entry into the `bl1_main()`
@@ -156,26 +179,11 @@
Name of the BL3-3 Content certificate on the host file-system (mandatory
when Trusted Board Boot is enabled).
-* **#define : PLATFORM_CACHE_LINE_SIZE**
-
- Defines the size (in bytes) of the largest cache line across all the cache
- levels in the platform.
-
-* **#define : PLATFORM_CLUSTER_COUNT**
-
- Defines the total number of clusters implemented by the platform in the
- system.
-
* **#define : PLATFORM_CORE_COUNT**
Defines the total number of CPUs implemented by the platform across all
clusters in the system.
-* **#define : PLATFORM_MAX_CPUS_PER_CLUSTER**
-
- Defines the maximum number of CPUs that can be implemented within a cluster
- on the platform.
-
* **#define : PLATFORM_NUM_AFFS**
Defines the total number of nodes in the affinity heirarchy at all affinity
@@ -301,6 +309,16 @@
Defines the ID of the secure physical generic timer interrupt used by the
TSP's interrupt handling code.
+If the platform port uses the translation table library code, the following
+constant must also be defined:
+
+* **#define : MAX_XLAT_TABLES**
+
+ Defines the maximum number of translation tables that are allocated by the
+ translation table library code. To minimize the amount of runtime memory
+ used, choose the smallest value needed to map the required virtual addresses
+ for each BL stage.
+
If the platform port uses the IO storage framework, the following constants
must also be defined:
@@ -328,7 +346,7 @@
structure for use by the platform layer.
The following constants are optional. They should be defined when the platform
-memory layout implies some image overlaying like on FVP.
+memory layout implies some image overlaying like in ARM standard platforms.
* **#define : BL31_PROGBITS_LIMIT**
@@ -342,8 +360,8 @@
### File : plat_macros.S [mandatory]
Each platform must ensure a file of this name is in the system include path with
-the following macro defined. In the ARM FVP port, this file is found in
-[plat/fvp/include/plat_macros.S].
+the following macro defined. In the ARM development platforms, this file is
+found in `plat/arm/board/<plat_name>/include/plat_macros.S`.
* **Macro : plat_print_gic_regs**
@@ -354,26 +372,12 @@
* **Macro : plat_print_interconnect_regs**
- This macro allows the crash reporting routine to print interconnect registers
- in case of an unhandled exception in BL3-1. This aids in debugging and
- this macro can be defined to be empty in case interconnect register reporting
- is not desired. In the ARM FVP port, the CCI snoop control registers are
- reported.
-
-### Other mandatory modifications
+ This macro allows the crash reporting routine to print interconnect
+ registers in case of an unhandled exception in BL3-1. This aids in debugging
+ and this macro can be defined to be empty in case interconnect register
+ reporting is not desired. In ARM standard platforms, the CCI snoop
+ control registers are reported.
-The following mandatory modifications may be implemented in any file
-the implementer chooses. In the ARM FVP port, they are implemented in
-[plat/fvp/aarch64/plat_common.c].
-
-* **Function : uint64_t plat_get_syscnt_freq(void)**
-
- This function is used by the architecture setup code to retrieve the
- counter frequency for the CPU's generic timer. This value will be
- programmed into the `CNTFRQ_EL0` register.
- In the ARM FVP port, it returns the base frequency of the system counter,
- which is retrieved from the first entry in the frequency modes table.
-
2.2 Handling Reset
------------------
@@ -564,7 +568,7 @@
preserve the values of callee saved registers x19 to x29.
The default implementation doesn't do anything. If a platform needs to override
-the default implementation, refer to the [Firmware Design Guide] for general
+the default implementation, refer to the [Firmware Design] for general
guidelines regarding placement of code in a reset handler.
### Function : plat_disable_acp()
@@ -625,6 +629,17 @@
The following functions need to be implemented by the platform port to enable
BL1 to perform the above tasks.
+
+### Function : bl1_early_platform_setup() [mandatory]
+
+ Argument : void
+ Return : void
+
+This function executes with the MMU and data caches disabled. It is only called
+by the primary CPU.
+
+In ARM standard platforms, this function initializes the console and enables
+snoop requests into the primary CPU's cluster.
### Function : bl1_plat_arch_setup() [mandatory]
@@ -632,12 +647,10 @@
Return : void
This function performs any platform-specific and architectural setup that the
-platform requires. Platform-specific setup might include configuration of
-memory controllers, configuration of the interconnect to allow the cluster
-to service cache snoop requests from another cluster, and so on.
+platform requires. Platform-specific setup might include configuration of
+memory controllers and the interconnect.
-In the ARM FVP port, this function enables CCI snoops into the cluster that the
-primary CPU is part of. It also enables the MMU.
+In ARM standard platforms, this function enables the MMU.
This function helps fulfill requirement 2 above.
@@ -651,8 +664,8 @@
for performing any remaining platform-specific setup that can occur after the
MMU and data cache have been enabled.
-This function is also responsible for initializing the storage abstraction layer
-which is used to load further bootloader images.
+In ARM standard platforms, this function initializes the storage abstraction
+layer used to load the next bootloader image.
This function helps fulfill requirement 3 above.
@@ -692,8 +705,9 @@
Depending upon where BL2 has been loaded in secure RAM (determined by
`BL2_BASE`), BL1 calculates the amount of free memory available for BL2 to use.
BL1 also ensures that its data sections resident in secure RAM are not visible
-to BL2. An illustration of how this is done in the ARM FVP port is given in the
-[User Guide], in the Section "Memory layout on Base FVP".
+to BL2. An illustration of how this is done in ARM standard platforms is given
+in the **Memory layout on ARM development platforms** section in the
+[Firmware Design].
### Function : bl1_plat_set_bl2_ep_info() [mandatory]
@@ -705,8 +719,6 @@
the entry point set by loader and also set the security state and SPSR which
represents the entry point system state for BL2.
-On FVP, we are setting the security state and the SPSR for the BL2 entrypoint
-
3.2 Boot Loader Stage 2 (BL2)
-----------------------------
@@ -772,6 +784,11 @@
copied structure is made available to all BL2 code through the
`bl2_plat_sec_mem_layout()` function.
+In ARM standard platforms, this function also initializes the storage
+abstraction layer used to load further bootloader images. It is necessary to do
+this early on platforms with a BL3-0 image, since the later `bl2_platform_setup`
+must be done after BL3-0 is loaded.
+
### Function : bl2_plat_arch_setup() [mandatory]
@@ -796,14 +813,11 @@
called by the primary CPU.
The purpose of this function is to perform any platform initialization
-specific to BL2. Platform security components are configured if required.
-For the Base FVP the TZC-400 TrustZone controller is configured to only
-grant non-secure access to DRAM. This avoids aliasing between secure and
-non-secure accesses in the TLB and cache - secure execution states can use
-the NS attributes in the MMU translation tables to access the DRAM.
+specific to BL2.
-This function is also responsible for initializing the storage abstraction layer
-which is used to load further bootloader images.
+In ARM standard platforms, this function performs security setup, including
+configuration of the TrustZone controller to allow non-secure masters access
+to most of DRAM. Part of DRAM is reserved for secure world use.
### Function : bl2_plat_sec_mem_layout() [mandatory]
@@ -878,8 +892,8 @@
information for BL3-1 entry point. The location pointed by it should be
accessible from BL1 while processing the synchronous exception to run to BL3-1.
-On FVP this is allocated inside an bl2_to_bl31_params_mem structure which
-is allocated at an address pointed by PARAMS_BASE.
+In ARM standard platforms this is allocated inside a bl2_to_bl31_params_mem
+structure in BL2 memory.
### Function : bl2_plat_set_bl31_ep_info() [mandatory]
@@ -891,8 +905,6 @@
overwrite the entry point set by loader and also set the security state
and SPSR which represents the entry point system state for BL3-1.
-On FVP, we are setting the security state and the SPSR for the BL3-1
-entrypoint.
### Function : bl2_plat_set_bl32_ep_info() [mandatory]
@@ -903,8 +915,6 @@
overwrite the entry point set by loader and also set the security state
and SPSR which represents the entry point system state for BL3-2.
-On FVP, we are setting the security state and the SPSR for the BL3-2
-entrypoint
### Function : bl2_plat_set_bl33_ep_info() [mandatory]
@@ -915,8 +925,6 @@
overwrite the entry point set by loader and also set the security state
and SPSR which represents the entry point system state for BL3-3.
-On FVP, we are setting the security state and the SPSR for the BL3-3
-entrypoint
### Function : bl2_plat_get_bl32_meminfo() [mandatory]
@@ -1012,12 +1020,10 @@
subsequently overwritten by BL3-1 and similarly the `void *` pointing
to the platform data also needs to be saved.
-On the ARM FVP port, BL2 passes a pointer to a `bl31_params` structure populated
-in the secure DRAM at address `0x6000000` in the bl31_params * argument and it
-does not use opaque pointer mentioned earlier. BL3-1 does not copy this
-information to internal data structures as it guarantees that the secure
-DRAM memory will not be overwritten. It maintains an internal reference to this
-information in the `bl2_to_bl31_params` variable.
+In ARM standard platforms, BL2 passes a pointer to a `bl31_params` structure
+in BL2 memory. BL3-1 copies the information in this pointer to internal data
+structures.
+
### Function : bl31_plat_arch_setup() [mandatory]
@@ -1044,12 +1050,11 @@
The purpose of this function is to complete platform initialization so that both
BL3-1 runtime services and normal world software can function correctly.
-The ARM FVP port does the following:
+In ARM standard platforms, this function does the following:
* Initializes the generic interrupt controller.
-* Configures the CLCD controller.
* Enables system-level implementation of the generic timer counter.
* Grants access to the system counter timer module
-* Initializes the FVP power controller device
+* Initializes the power controller device
* Detects the system topology.
@@ -1068,6 +1073,17 @@
(that was copied during `bl31_early_platform_setup()`) if the image exists. It
should return NULL otherwise.
+### Function : plat_get_syscnt_freq() [mandatory]
+
+ Argument : void
+ Return : uint64_t
+
+This function is used by the architecture setup code to retrieve the counter
+frequency for the CPU's generic timer. This value will be programmed into the
+`CNTFRQ_EL0` register. In ARM standard platforms, it returns the base frequency
+of the system counter, which is retrieved from the first entry in the frequency
+modes table.
+
3.3 Power State Coordination Interface (in BL3-1)
------------------------------------------------
@@ -1156,10 +1172,10 @@
the passed pointer with a pointer to BL3-1's private `plat_pm_ops` structure.
A description of each member of this structure is given below. Please refer to
-the ARM FVP specific implementation of these handlers in [plat/fvp/fvp_pm.c]
-as an example. A platform port is expected to implement these handlers if the
-corresponding PSCI operation is to be supported and these handlers are expected
-to succeed if the return type is `void`.
+the ARM FVP specific implementation of these handlers in
+[plat/arm/board/fvp/fvp_pm.c] as an example. A platform port is expected to
+implement these handlers if the corresponding PSCI operation is to be supported
+and these handlers are expected to succeed if the return type is `void`.
#### plat_pm_ops.affinst_standby()
@@ -1268,10 +1284,11 @@
described in the [IMF Design Guide]
A platform should export the following APIs to support the IMF. The following
-text briefly describes each api and its implementation on the FVP port. The API
-implementation depends upon the type of interrupt controller present in the
-platform. The FVP implements an ARM Generic Interrupt Controller (ARM GIC) as
-per the version 2.0 of the [ARM GIC Architecture Specification]
+text briefly describes each api and its implementation in ARM standard
+platforms. The API implementation depends upon the type of interrupt controller
+present in the platform. ARM standard platforms implements an ARM Generic
+Interrupt Controller (ARM GIC) as per the version 2.0 of the
+[ARM GIC Architecture Specification].
### Function : plat_interrupt_type_to_line() [mandatory]
@@ -1291,8 +1308,8 @@
bit position in the `SCR_EL3` register of the respective interrupt trap: IRQ=1,
FIQ=2.
-The FVP port configures the ARM GIC to signal S-EL1 interrupts as FIQs and
-Non-secure interrupts as IRQs from either security state.
+ARM standard platforms configure the ARM GIC to signal S-EL1 interrupts
+as FIQs and Non-secure interrupts as IRQs from either security state.
### Function : plat_ic_get_pending_interrupt_type() [mandatory]
@@ -1306,9 +1323,9 @@
pending. The valid interrupt types that can be returned are `INTR_TYPE_EL3`,
`INTR_TYPE_S_EL1` and `INTR_TYPE_NS`.
-The FVP port reads the _Highest Priority Pending Interrupt Register_
-(`GICC_HPPIR`) to determine the id of the pending interrupt. The type of interrupt
-depends upon the id value as follows.
+ARM standard platforms read the _Highest Priority Pending Interrupt
+Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The type
+of interrupt depends upon the id value as follows.
1. id < 1022 is reported as a S-EL1 interrupt
2. id = 1022 is reported as a Non-secure interrupt.
@@ -1325,9 +1342,9 @@
handler for the pending interrupt if the `IMF_READ_INTERRUPT_ID` build time flag
is set. INTR_ID_UNAVAILABLE is returned when there is no interrupt pending.
-The FVP port reads the _Highest Priority Pending Interrupt Register_
-(`GICC_HPPIR`) to determine the id of the pending interrupt. The id that is
-returned by API depends upon the value of the id read from the interrupt
+ARM standard platforms read the _Highest Priority Pending Interrupt
+Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The id
+that is returned by API depends upon the value of the id read from the interrupt
controller as follows.
1. id < 1022. id is returned as is.
@@ -1346,10 +1363,11 @@
the highest pending interrupt has begun. It should return the id of the
interrupt which is being processed.
-The FVP port reads the _Interrupt Acknowledge Register_ (`GICC_IAR`). This
-changes the state of the highest priority pending interrupt from pending to
-active in the interrupt controller. It returns the value read from the
-`GICC_IAR`. This value is the id of the interrupt whose state has been changed.
+This function in ARM standard platforms reads the _Interrupt Acknowledge
+Register_ (`GICC_IAR`). This changes the state of the highest priority pending
+interrupt from pending to active in the interrupt controller. It returns the
+value read from the `GICC_IAR`. This value is the id of the interrupt whose
+state has been changed.
The TSP uses this API to start processing of the secure physical timer
interrupt.
@@ -1365,7 +1383,7 @@
finished. The id should be the same as the id returned by the
`plat_ic_acknowledge_interrupt()` API.
-The FVP port writes the id to the _End of Interrupt Register_
+ARM standard platforms write the id to the _End of Interrupt Register_
(`GICC_EOIR`). This deactivates the corresponding interrupt in the interrupt
controller.
@@ -1384,10 +1402,12 @@
returned depending upon how the interrupt has been configured by the platform
IC.
+This function in ARM standard platforms configures S-EL1 interrupts
+as Group0 interrupts and Non-secure interrupts as Group1 interrupts. It reads
+the group value corresponding to the interrupt id from the relevant _Interrupt
+Group Register_ (`GICD_IGROUPRn`). It uses the group value to determine the
+type of interrupt.
+
-The FVP port configures S-EL1 interrupts as Group0 interrupts and Non-secure
-interrupts as Group1 interrupts. It reads the group value corresponding to the
-interrupt id from the relevant _Interrupt Group Register_ (`GICD_IGROUPRn`). It
-uses the group value to determine the type of interrupt.
3.5 Crash Reporting mechanism (in BL3-1)
----------------------------------------------
@@ -1409,9 +1429,6 @@
console. It should only use the general purpose registers x0 to x2 to do the
initialization and returns 1 on success.
-The FVP port designates the `PL011_UART0` as the crash console and calls the
-console_core_init() to initialize the console.
-
### Function : plat_crash_console_putc
Argument : int
@@ -1422,9 +1439,6 @@
x2 to do its work. The parameter and the return value are in general purpose
register x0.
-The FVP port designates the `PL011_UART0` as the crash console and calls the
-console_core_putc() to print the character on the console.
-
4. Build flags
---------------
@@ -1493,11 +1507,11 @@
storage access is only required by BL1 and BL2 phases. The `load_image()`
function uses the storage layer to access non-volatile platform storage.
-It is mandatory to implement at least one storage driver. For the FVP the
-Firmware Image Package(FIP) driver is provided as the default means to load data
-from storage (see the "Firmware Image Package" section in the [User Guide]).
-The storage layer is described in the header file
-`include/drivers/io/io_storage.h`. The implementation of the common library
+It is mandatory to implement at least one storage driver. For the ARM
+development platforms the Firmware Image Package (FIP) driver is provided as
+the default means to load data from storage (see the "Firmware Image Package"
+section in the [User Guide]). The storage layer is described in the header file
+`include/drivers/io/io_storage.h`. The implementation of the common library
is in `drivers/io/io_storage.c` and the driver files are located in
`drivers/io/`.
@@ -1533,20 +1547,20 @@
- - - - - - - - - - - - - - - - - - - - - - - - - -
-_Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
+_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._
[ARM GIC Architecture Specification]: http://arminfo.emea.arm.com/help/topic/com.arm.doc.ihi0048b/IHI0048B_gic_architecture_specification.pdf
[IMF Design Guide]: interrupt-framework-design.md
[User Guide]: user-guide.md
[FreeBSD]: http://www.freebsd.org
-[Firmware Design Guide]: firmware-design.md
+[Firmware Design]: firmware-design.md
[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S
[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S
-[plat/fvp/include/platform_def.h]: ../plat/fvp/include/platform_def.h
-[plat/fvp/include/plat_macros.S]: ../plat/fvp/include/plat_macros.S
-[plat/fvp/aarch64/plat_common.c]: ../plat/fvp/aarch64/plat_common.c
-[plat/fvp/plat_pm.c]: ../plat/fvp/plat_pm.c
+[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c
[include/runtime_svc.h]: ../include/runtime_svc.h
+[include/plat/arm/common/arm_def.h]: ../include/plat/arm/common/arm_def.h
+[include/plat/common/common_def.h]: ../include/plat/common/common_def.h
[include/plat/common/platform.h]: ../include/plat/common/platform.h
+[include/plat/arm/common/plat_arm.h]: ../include/plat/arm/common/plat_arm.h]
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 411a870..f10a6f3 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -206,8 +206,8 @@
wants the timer registers to be saved and restored.
* `PLAT`: Choose a platform to build ARM Trusted Firmware for. The chosen
- platform name must be the name of one of the directories under the `plat/`
- directory other than `common`.
+ platform name must be subdirectory of any depth under `plat/`, and must
+ contain a platform makefile named `platform.mk`.
* `SPD`: Choose a Secure Payload Dispatcher component to be built into the
Trusted Firmware. The value should be the path to the directory containing
@@ -320,21 +320,16 @@
* `BL33_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
file that contains the BL3-3 private key in PEM format.
-#### FVP specific build options
+#### ARM development platform specific build options
-* `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
+* `ARM_TSP_RAM_LOCATION_ID`: location of the TSP binary. Options:
- `tsram` : Trusted SRAM (default option)
- - `tdram` : Trusted DRAM
+ - `tdram` : Trusted DRAM (if available)
- `dram` : Secure region in DRAM (configured by the TrustZone controller)
-For a better understanding of FVP options, the FVP memory map is explained in
-the [Firmware Design].
+For a better understanding of these options, the ARM development platform memory
+map is explained in the [Firmware Design].
-#### Juno specific build options
-
-* `PLAT_TSP_LOCATION`: location of the TSP binary. Options:
- - `tsram` : Trusted SRAM (default option)
- - `dram` : Secure region in DRAM (set by the TrustZone controller)
### Creating a Firmware Image Package
@@ -409,8 +404,8 @@
optimizations by using `-O0`.
NOTE: Using `-O0` could cause output images to be larger and base addresses
-might need to be recalculated (see the "Memory layout of BL images" section in
-the [Firmware Design]).
+might need to be recalculated (see the **Memory layout on ARM development
+platforms** section in the [Firmware Design]).
Extra debug options can be passed to the build system by setting `CFLAGS`:
@@ -461,7 +456,7 @@
The `cert_create` tool can be built separately through the following commands:
$ cd tools/cert_create
- $ make [DEBUG=1] [V=1]
+ $ make PLAT=<platform> [DEBUG=1] [V=1]
`DEBUG=1` builds the tool in debug mode. `V=1` makes the build process more
verbose. The following command should be used to obtain help about the tool:
diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S
index 0c781a2..4ed0ceb 100644
--- a/drivers/arm/pl011/pl011_console.S
+++ b/drivers/arm/pl011/pl011_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,40 +31,17 @@
#include <asm_macros.S>
#include <pl011.h>
- .globl console_init
- .globl console_putc
+/*
+ * Pull in generic functions to provide backwards compatibility for
+ * platform makefiles
+ */
+#include "../../console/console.S"
+
+
.globl console_core_init
.globl console_core_putc
- .globl console_getc
-
- /*
- * The console base is in the data section and not in .bss
- * even though it is zero-init. In particular, this allows
- * the console functions to start using this variable before
- * the runtime memory is initialized for images which do not
- * need to copy the .data section from ROM to RAM.
- */
-.section .data.console_base ; .align 3
- console_base: .quad 0x0
+ .globl console_core_getc
- /* -----------------------------------------------
- * int console_init(unsigned long base_addr,
- * unsigned int uart_clk, unsigned int baud_rate)
- * Function to initialize the console without a
- * C Runtime to print debug information. It saves
- * the console base to the data section.
- * In: x0 - console base address
- * w1 - Uart clock in Hz
- * w2 - Baud rate
- * out: return 1 on success.
- * Clobber list : x1 - x3
- * -----------------------------------------------
- */
-func console_init
- adrp x3, console_base
- str x0, [x3, :lo12:console_base]
- b console_core_init
-endfunc console_init
/* -----------------------------------------------
* int console_core_init(unsigned long base_addr,
@@ -76,16 +53,16 @@
* In: x0 - console base address
* w1 - Uart clock in Hz
* w2 - Baud rate
- * Out: return 1 on success
+ * Out: return 1 on success else 0 on error
* Clobber list : x1, x2
* -----------------------------------------------
*/
func console_core_init
/* Check the input base address */
- cbz x0, init_fail
+ cbz x0, core_init_fail
/* Check baud rate and uart clock for sanity */
- cbz w1, init_fail
- cbz w2, init_fail
+ cbz w1, core_init_fail
+ cbz w2, core_init_fail
/* Program the baudrate */
/* Divisor = (Uart clock * 4) / baudrate */
lsl w1, w1, #2
@@ -106,28 +83,14 @@
mov w1, #(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN)
str w1, [x0, #UARTCR]
mov w0, #1
-init_fail:
+ ret
+core_init_fail:
+ mov w0, wzr
ret
endfunc console_core_init
- /* ---------------------------------------------
- * int console_putc(int c)
- * Function to output a character over the
- * console. It returns the character printed on
- * success or -1 on error.
- * In : x0 - character to be printed
- * Out : return -1 on error else return character.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func console_putc
- adrp x2, console_base
- ldr x1, [x2, :lo12:console_base]
- b console_core_putc
-endfunc console_putc
-
/* --------------------------------------------------------
- * int console_core_putc(int c, unsigned int base_addr)
+ * int console_core_putc(int c, unsigned long base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
@@ -160,24 +123,24 @@
endfunc console_core_putc
/* ---------------------------------------------
- * int console_getc(void)
+ * int console_core_getc(unsigned long base_addr)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 on error.
+ * In : x0 - console base address
* Clobber list : x0, x1
* ---------------------------------------------
*/
-func console_getc
- adrp x0, console_base
- ldr x1, [x0, :lo12:console_base]
- cbz x1, getc_error
+func console_core_getc
+ cbz x0, getc_error
1:
/* Check if the receive FIFO is empty */
- ldr w0, [x1, #UARTFR]
- tbnz w0, #PL011_UARTFR_RXFE_BIT, 1b
- ldr w0, [x1, #UARTDR]
+ ldr w1, [x0, #UARTFR]
+ tbnz w1, #PL011_UARTFR_RXFE_BIT, 1b
+ ldr w1, [x0, #UARTDR]
+ mov w0, w1
ret
getc_error:
mov w0, #-1
ret
-endfunc console_getc
+endfunc console_core_getc
diff --git a/drivers/arm/tzc400/tzc400.c b/drivers/arm/tzc400/tzc400.c
index df52c9c..cb89fda 100644
--- a/drivers/arm/tzc400/tzc400.c
+++ b/drivers/arm/tzc400/tzc400.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -191,15 +191,41 @@
BUILD_CONFIG_NR_MASK) + 1;
}
+/*
+ * `tzc_configure_region0` is used to program region 0 into the TrustZone
+ * controller. Region 0 covers the whole address space that is not mapped
+ * to any other region, and is enabled on all filters; this cannot be
+ * changed. This function only changes the access permissions.
+ */
+void tzc_configure_region0(tzc_region_attributes_t sec_attr,
+ uint32_t ns_device_access)
+{
+ assert(tzc.base);
+
+ VERBOSE("TZC : Configuring region 0 (sec_attr=0x%x, ns_devs=0x%x)\n",
+ sec_attr, ns_device_access);
+
+ assert(sec_attr <= TZC_REGION_S_RDWR);
+
+ /* Set secure attributes on region 0 */
+ tzc_write_region_attributes(tzc.base, 0,
+ sec_attr << REG_ATTR_SEC_SHIFT);
+
+ /*
+ * Specify which non-secure devices have permission to access
+ * region 0.
+ */
+ tzc_write_region_id_access(tzc.base, 0, ns_device_access);
+}
+
/*
* `tzc_configure_region` is used to program regions into the TrustZone
* controller. A region can be associated with more than one filter. The
* associated filters are passed in as a bitmap (bit0 = filter0).
* NOTE:
- * The region 0 covers the whole address space and is enabled on all filters,
- * this cannot be changed. It is, however, possible to change some region 0
- * permissions.
+ * Region 0 is special; it is preferable to use tzc_configure_region0
+ * for this region (see comment for that function).
*/
void tzc_configure_region(uint32_t filters,
uint8_t region,
@@ -210,6 +236,13 @@
{
assert(tzc.base);
+ VERBOSE("TZC : Configuring region (filters=0x%x, region=%d, ...\n",
+ filters, region);
+ VERBOSE("TZC : ... base=0x%lx, top=0x%lx, ...\n",
+ region_base, region_top);
+ VERBOSE("TZC : ... sec_attr=0x%x, ns_devs=0x%x)\n",
+ sec_attr, ns_device_access);
+
/* Do range checks on filters and regions. */
assert(((filters >> tzc.num_filters) == 0) &&
(region < tzc.num_regions));
diff --git a/drivers/console/console.S b/drivers/console/console.S
new file mode 100644
index 0000000..85c8f65
--- /dev/null
+++ b/drivers/console/console.S
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <asm_macros.S>
+
+ .globl console_init
+ .globl console_putc
+ .globl console_getc
+
+ /*
+ * The console base is in the data section and not in .bss
+ * even though it is zero-init. In particular, this allows
+ * the console functions to start using this variable before
+ * the runtime memory is initialized for images which do not
+ * need to copy the .data section from ROM to RAM.
+ */
+.section .data.console_base ; .align 3
+ console_base: .quad 0x0
+
+ /* -----------------------------------------------
+ * int console_init(unsigned long base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. It saves
+ * the console base to the data section.
+ * In: x0 - console base address
+ * w1 - Uart clock in Hz
+ * w2 - Baud rate
+ * out: return 1 on success else 0 on error
+ * Clobber list : x1 - x3
+ * -----------------------------------------------
+ */
+func console_init
+ /* Check the input base address */
+ cbz x0, init_fail
+ adrp x3, console_base
+ str x0, [x3, :lo12:console_base]
+ b console_core_init
+init_fail:
+ ret
+endfunc console_init
+
+ /* ---------------------------------------------
+ * int console_putc(int c)
+ * Function to output a character over the
+ * console. It returns the character printed on
+ * success or -1 on error.
+ * In : x0 - character to be printed
+ * Out : return -1 on error else return character.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func console_putc
+ adrp x2, console_base
+ ldr x1, [x2, :lo12:console_base]
+ b console_core_putc
+endfunc console_putc
+
+ /* ---------------------------------------------
+ * int console_getc(void)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on error.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_getc
+ adrp x1, console_base
+ ldr x0, [x1, :lo12:console_base]
+ b console_core_getc
+endfunc console_getc
diff --git a/drivers/console/skeleton_console.S b/drivers/console/skeleton_console.S
new file mode 100644
index 0000000..af78376
--- /dev/null
+++ b/drivers/console/skeleton_console.S
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <asm_macros.S>
+
+ /*
+ * This file contains a skeleton console implementation that can
+ * be used as basis for a real console implementation by platforms
+ * that do not contain PL011 hardware.
+ */
+
+ .globl console_core_init
+ .globl console_core_putc
+ .globl console_core_getc
+
+ /* -----------------------------------------------
+ * int console_core_init(unsigned long base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. This
+ * function will be accessed by console_init and
+ * crash reporting.
+ * In: x0 - console base address
+ * w1 - Uart clock in Hz
+ * w2 - Baud rate
+ * Out: return 1 on success else 0 on error
+ * Clobber list : x1, x2
+ * -----------------------------------------------
+ */
+func console_core_init
+ /* Check the input base address */
+ cbz x0, core_init_fail
+ /* Check baud rate and uart clock for sanity */
+ cbz w1, core_init_fail
+ cbz w2, core_init_fail
+ /* Insert implementation here */
+ mov w0, #1
+ ret
+core_init_fail:
+ mov w0, wzr
+ ret
+endfunc console_core_init
+
+ /* --------------------------------------------------------
+ * int console_core_putc(int c, unsigned long base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func console_core_putc
+ /* Check the input parameter */
+ cbz x1, putc_error
+ /* Insert implementation here */
+ ret
+putc_error:
+ mov w0, #-1
+ ret
+endfunc console_core_putc
+
+ /* ---------------------------------------------
+ * int console_core_getc(unsigned long base_addr)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on error.
+ * In : x0 - console base address
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_core_getc
+ cbz x0, getc_error
+ /* Insert implementation here */
+ ret
+getc_error:
+ mov w0, #-1
+ ret
+endfunc console_core_getc
diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S
index 4dcb5f0..f9e7823 100644
--- a/include/common/asm_macros.S
+++ b/include/common/asm_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,6 +27,8 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __ASM_MACROS_S__
+#define __ASM_MACROS_S__
#include <arch.h>
@@ -204,3 +206,5 @@
_mov_imm16 \_reg, (\_val), 48
.endif
.endm
+
+#endif /* __ASM_MACROS_S__ */
diff --git a/include/common/assert_macros.S b/include/common/assert_macros.S
index 807972f..cb6c78b 100644
--- a/include/common/assert_macros.S
+++ b/include/common/assert_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,6 +27,8 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __ASSERT_MACROS_S__
+#define __ASSERT_MACROS_S__
/*
* Assembler macro to enable asm_assert. Use this macro wherever
@@ -47,3 +49,5 @@
mov x1, __LINE__ ;\
b asm_assert ;\
300:
+
+#endif /* __ASSERT_MACROS_S__ */
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index b36c9d3..33b75f1 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -110,6 +110,26 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+/*
+ * Declarations of linker defined symbols to help determine memory layout of
+ * BL images
+ */
+extern unsigned long __RO_START__;
+extern unsigned long __RO_END__;
+#if IMAGE_BL2
+extern unsigned long __BL2_END__;
+#elif IMAGE_BL31
+extern unsigned long __BL31_END__;
+#elif IMAGE_BL32
+extern unsigned long __BL32_END__;
+#endif /* IMAGE_BLX */
+
+#if USE_COHERENT_MEM
+extern unsigned long __COHERENT_RAM_START__;
+extern unsigned long __COHERENT_RAM_END__;
+#endif
+
+
/*******************************************************************************
* Structure used for telling the next BL how much of a particular type of
* memory is available for its use and how much is already used.
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index d62e67b..7b951d2 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,7 +31,6 @@
#ifndef __TZC400_H__
#define __TZC400_H__
-#include <stdint.h>
#define BUILD_CONFIG_OFF 0x000
#define ACTION_OFF 0x004
@@ -148,9 +147,13 @@
#define TZC_REGION_ACCESS_RDWR(id) \
(TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id))
-/* Filters are bit mapped 0 to 3. */
#define TZC400_COMPONENT_ID 0xb105f00d
+
+#ifndef __ASSEMBLY__
+
+#include <stdint.h>
+
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
@@ -187,6 +190,8 @@
void tzc_init(uint64_t base);
+void tzc_configure_region0(tzc_region_attributes_t sec_attr,
+ uint32_t ns_device_access);
void tzc_configure_region(uint32_t filters,
uint8_t region,
uint64_t region_base,
@@ -197,5 +202,6 @@
void tzc_disable_filters(void);
void tzc_set_action(tzc_action_t action);
+#endif /* __ASSEMBLY__ */
#endif /* __TZC400__ */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 5e21673..912643d 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -302,6 +302,23 @@
((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
+/*
+ * CTR_EL0 definitions
+ */
+#define CTR_CWG_SHIFT 24
+#define CTR_CWG_MASK 0xf
+#define CTR_ERG_SHIFT 20
+#define CTR_ERG_MASK 0xf
+#define CTR_DMINLINE_SHIFT 16
+#define CTR_DMINLINE_MASK 0xf
+#define CTR_L1IP_SHIFT 14
+#define CTR_L1IP_MASK 0x3
+#define CTR_IMINLINE_SHIFT 0
+#define CTR_IMINLINE_MASK 0xf
+
+#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
+#define SIZE_FROM_LOG2_WORDS(n) (4 << (n))
+
/* Physical timer control register bit fields shifts and masks */
#define CNTP_CTL_ENABLE_SHIFT 0
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index ceb88e4..b7ab3da 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -281,6 +281,8 @@
DEFINE_SYSREG_READ_FUNC(isr_el1)
+DEFINE_SYSREG_READ_FUNC(ctr_el0)
+
/* GICv3 System Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 089f09c..72c35fb 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,6 +27,8 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __CPU_MACROS_S__
+#define __CPU_MACROS_S__
#include <arch.h>
@@ -80,3 +82,5 @@
.quad \_name\()_cpu_reg_dump
#endif
.endm
+
+#endif /* __CPU_MACROS_S__ */
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
new file mode 100644
index 0000000..21dee7e
--- /dev/null
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __BOARD_ARM_DEF_H__
+#define __BOARD_ARM_DEF_H__
+
+#include <v2m_def.h>
+
+
+/*
+ * Required platform porting definitions common to all ARM
+ * development platforms
+ */
+
+/* Size of cacheable stacks */
+#if DEBUG_XLAT_TABLE
+# define PLATFORM_STACK_SIZE 0x800
+#elif IMAGE_BL1
+#if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+#else
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+#elif IMAGE_BL2
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif IMAGE_BL31
+# define PLATFORM_STACK_SIZE 0x400
+#elif IMAGE_BL32
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if IMAGE_BL1
+# define PLAT_ARM_MMAP_ENTRIES 6
+#endif
+#if IMAGE_BL2
+# define PLAT_ARM_MMAP_ENTRIES 8
+#endif
+#if IMAGE_BL31
+# define PLAT_ARM_MMAP_ENTRIES 5
+#endif
+#if IMAGE_BL32
+# define PLAT_ARM_MMAP_ENTRIES 4
+#endif
+
+/*
+ * Platform specific page table and MMU setup constants
+ */
+#if IMAGE_BL1
+# if PLAT_fvp || PLAT_juno
+# define MAX_XLAT_TABLES 2
+# else
+# define MAX_XLAT_TABLES 3
+# endif /* PLAT_ */
+#elif IMAGE_BL2
+# define MAX_XLAT_TABLES 3
+#elif IMAGE_BL31
+# define MAX_XLAT_TABLES 2
+#elif IMAGE_BL32
+# if ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
+# define MAX_XLAT_TABLES 3
+# else
+# define MAX_XLAT_TABLES 2
+# endif
+#endif
+
+
+#define MAX_IO_DEVICES 3
+#define MAX_IO_HANDLES 4
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+
+#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE V2M_FLASH0_SIZE
+
+
+#endif /* __BOARD_ARM_DEF_H__ */
diff --git a/plat/fvp/include/platform_oid.h b/include/plat/arm/board/common/board_arm_oid.h
similarity index 95%
rename from plat/fvp/include/platform_oid.h
rename to include/plat/arm/board/common/board_arm_oid.h
index 38aca12..92a9bd1 100644
--- a/plat/fvp/include/platform_oid.h
+++ b/include/plat/arm/board/common/board_arm_oid.h
@@ -28,8 +28,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef PLATFORM_OID_H_
-#define PLATFORM_OID_H_
+#ifndef __BOARD_ARM_OID_H__
+#define __BOARD_ARM_OID_H__
/*
* This is the list of the different extensions containing relevant information
@@ -66,4 +66,5 @@
#define BL33_CONTENT_CERT_PK_OID "1.2.3.12"
#define BL33_HASH_OID "1.2.3.13"
-#endif /* PLATFORM_OID_H_ */
+
+#endif /* __BOARD_ARM_OID_H__ */
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
new file mode 100644
index 0000000..2e32b41
--- /dev/null
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BOARD_CSS_DEF_H__
+#define __BOARD_CSS_DEF_H__
+
+#include <common_def.h>
+#include <soc_css_def.h>
+#include <v2m_def.h>
+
+/*
+ * Definitions common to all ARM CSS-based development platforms
+ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
+#define BOARD_CSS_PLAT_TYPE_RTL 0x00
+#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
+#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
+#define BOARD_CSS_PLAT_TYPE_FVP 0x03
+
+#ifndef __ASSEMBLY__
+
+#include <mmio.h>
+
+#define BOARD_CSS_GET_PLAT_TYPE(addr) \
+ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
+ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+
+#endif /* __ASSEMBLY__ */
+
+
+/*
+ * Required platform porting definitions common to all ARM CSS-based
+ * development platforms
+ */
+
+#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x180000000)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_UART1_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
+
+#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
+#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
+
+
+#endif /* __BOARD_CSS_DEF_H__ */
+
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
new file mode 100644
index 0000000..c16e9bc
--- /dev/null
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __V2M_DEF_H__
+#define __V2M_DEF_H__
+
+#include <xlat_tables.h>
+
+
+/* V2M motherboard system registers & offsets */
+#define V2M_SYSREGS_BASE 0x1c010000
+#define V2M_SYS_ID 0x0
+#define V2M_SYS_SWITCH 0x4
+#define V2M_SYS_LED 0x8
+#define V2M_SYS_CFGDATA 0xa0
+#define V2M_SYS_CFGCTRL 0xa4
+#define V2M_SYS_CFGSTATUS 0xa8
+
+#define V2M_CFGCTRL_START (1 << 31)
+#define V2M_CFGCTRL_RW (1 << 30)
+#define V2M_CFGCTRL_FUNC_SHIFT 20
+#define V2M_CFGCTRL_FUNC(fn) (fn << V2M_CFGCTRL_FUNC_SHIFT)
+#define V2M_FUNC_CLK_GEN 0x01
+#define V2M_FUNC_TEMP 0x04
+#define V2M_FUNC_DB_RESET 0x05
+#define V2M_FUNC_SCC_CFG 0x06
+#define V2M_FUNC_SHUTDOWN 0x08
+#define V2M_FUNC_REBOOT 0x09
+
+/*
+ * V2M sysled bit definitions. The values written to this
+ * register are defined in arch.h & runtime_svc.h. Only
+ * used by the primary cpu to diagnose any cold boot issues.
+ *
+ * SYS_LED[0] - Security state (S=0/NS=1)
+ * SYS_LED[2:1] - Exception Level (EL3-EL0)
+ * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
+ *
+ */
+#define V2M_SYS_LED_SS_SHIFT 0x0
+#define V2M_SYS_LED_EL_SHIFT 0x1
+#define V2M_SYS_LED_EC_SHIFT 0x3
+
+#define V2M_SYS_LED_SS_MASK 0x1
+#define V2M_SYS_LED_EL_MASK 0x3
+#define V2M_SYS_LED_EC_MASK 0x1f
+
+/* V2M sysid register bits */
+#define V2M_SYS_ID_REV_SHIFT 28
+#define V2M_SYS_ID_HBI_SHIFT 16
+#define V2M_SYS_ID_BLD_SHIFT 12
+#define V2M_SYS_ID_ARCH_SHIFT 8
+#define V2M_SYS_ID_FPGA_SHIFT 0
+
+#define V2M_SYS_ID_REV_MASK 0xf
+#define V2M_SYS_ID_HBI_MASK 0xfff
+#define V2M_SYS_ID_BLD_MASK 0xf
+#define V2M_SYS_ID_ARCH_MASK 0xf
+#define V2M_SYS_ID_FPGA_MASK 0xff
+
+#define V2M_SYS_ID_BLD_LENGTH 4
+
+
+/* NOR Flash */
+#define V2M_FLASH0_BASE 0x08000000
+#define V2M_FLASH0_SIZE 0x04000000
+
+#define V2M_IOFPGA_BASE 0x1c000000
+#define V2M_IOFPGA_SIZE 0x03000000
+
+/* PL011 UART related constants */
+#define V2M_IOFPGA_UART0_BASE 0x1c090000
+#define V2M_IOFPGA_UART1_BASE 0x1c0a0000
+#define V2M_IOFPGA_UART2_BASE 0x1c0b0000
+#define V2M_IOFPGA_UART3_BASE 0x1c0c0000
+
+#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000
+#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000
+#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000
+#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000
+
+
+#define V2M_MAP_FLASH0 MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+ V2M_FLASH0_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
+#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
+ V2M_IOFPGA_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+
+
+#endif /* __V2M_DEF_H__ */
diff --git a/plat/juno/include/plat_macros.S b/include/plat/arm/common/aarch64/arm_macros.S
similarity index 79%
rename from plat/juno/include/plat_macros.S
rename to include/plat/arm/common/aarch64/arm_macros.S
index ac1077b..594b096 100644
--- a/plat/juno/include/plat_macros.S
+++ b/include/plat/arm/common/aarch64/arm_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,33 +27,33 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __ARM_MACROS_S__
+#define __ARM_MACROS_S__
#include <cci.h>
#include <gic_v2.h>
-#include "platform_def.h"
-#include "../juno_def.h"
+#include <platform_def.h>
.section .rodata.gic_reg_name, "aS"
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
+ " Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
.asciz ":\t\t0x"
-
/* ---------------------------------------------
- * The below macro prints out relevant GIC
+ * The below utility macro prints out relevant GIC
* registers whenever an unhandled exception is
- * taken in BL3-1.
- * Clobbers: x0 - x10, x16, sp
+ * taken in BL3-1 on ARM standard platforms.
+ * Expects: GICD base in x16, GICC base in x17
+ * Clobbers: x0 - x10, sp
* ---------------------------------------------
*/
- .macro plat_print_gic_regs
- mov_imm x16, GICD_BASE
- mov_imm x17, GICC_BASE
+ .macro arm_print_gic_regs
/* Load the gicc reg list to x6 */
adr x6, gicc_regs
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
@@ -85,25 +85,31 @@
exit_print_gic_regs:
.endm
+
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ------------------------------------------------
- * The below macro prints out relevant interconnect
- * registers whenever an unhandled exception is
- * taken in BL3-1.
+ * The below required platform porting macro prints
+ * out relevant interconnect registers whenever an
+ * unhandled exception is taken in BL3-1.
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
.macro plat_print_interconnect_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
- mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET)
+ mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
+ PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX))
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
- mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET)
+ mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
+ PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX))
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
.endm
+
+
+#endif /* __ARM_MACROS_S__ */
diff --git a/include/plat/common/plat_config.h b/include/plat/arm/common/arm_config.h
similarity index 68%
rename from include/plat/common/plat_config.h
rename to include/plat/arm/common/arm_config.h
index 20d3c03..21f394c 100644
--- a/include/plat/common/plat_config.h
+++ b/include/plat/arm/common/arm_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,27 +27,20 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PLAT_CONFIG_H__
-#define __PLAT_CONFIG_H__
+#ifndef __ARM_CONFIG_H__
+#define __ARM_CONFIG_H__
-#define CONFIG_GICC_BASE_OFFSET 0x4
-
-#ifndef __ASSEMBLY__
-
-#include <cassert.h>
-
-
-enum plat_config_flags {
- /* Whether Base FVP memory map is in use */
- CONFIG_BASE_MMAP = 0x1,
+enum arm_config_flags {
+ /* Whether Base memory map is in use */
+ ARM_CONFIG_BASE_MMAP = 0x1,
/* Whether CCI should be enabled */
- CONFIG_HAS_CCI = 0x2,
+ ARM_CONFIG_HAS_CCI = 0x2,
/* Whether TZC should be configured */
- CONFIG_HAS_TZC = 0x4
+ ARM_CONFIG_HAS_TZC = 0x4
};
-typedef struct plat_config {
+typedef struct arm_config {
unsigned int gicd_base;
unsigned int gicc_base;
unsigned int gich_base;
@@ -55,24 +48,16 @@
unsigned int max_aff0;
unsigned int max_aff1;
unsigned long flags;
-} plat_config_t;
+} arm_config_t;
-inline const plat_config_t *get_plat_config();
+/* If used, arm_config must be defined and populated in the platform port */
+extern arm_config_t arm_config;
-CASSERT(CONFIG_GICC_BASE_OFFSET == __builtin_offsetof(
- plat_config_t, gicc_base),
- assert_gicc_base_offset_mismatch);
-
-/* If used, plat_config must be defined and populated in the platform port*/
-extern plat_config_t plat_config;
-
-inline const plat_config_t *get_plat_config()
+inline const arm_config_t *get_arm_config(void)
{
- return &plat_config;
+ return &arm_config;
}
-#endif /* __ASSEMBLY__ */
-
-#endif /* __PLAT_CONFIG_H__ */
+#endif /* __ARM_CONFIG_H__ */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
new file mode 100644
index 0000000..c93b684
--- /dev/null
+++ b/include/plat/arm/common/arm_def.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ARM_DEF_H__
+#define __ARM_DEF_H__
+
+#include <common_def.h>
+#include <platform_def.h>
+#include <xlat_tables.h>
+
+
+/******************************************************************************
+ * Definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/* Special value used to verify platform parameters from BL2 to BL3-1 */
+#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+
+#define ARM_CLUSTER_COUNT 2ull
+
+#define ARM_CACHE_WRITEBACK_SHIFT 6
+
+/* Memory location options for TSP */
+#define ARM_TRUSTED_SRAM_ID 0
+#define ARM_TRUSTED_DRAM_ID 1
+#define ARM_DRAM_ID 2
+
+/* The first 4KB of Trusted SRAM are used as shared memory */
+#define ARM_TRUSTED_SRAM_BASE 0x04000000
+#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
+#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
+ ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
+ ARM_SHARED_RAM_SIZE)
+
+/*
+ * The top 16MB of DRAM1 is configured as secure access only using the TZC
+ * - SCP TZC DRAM: If present, DRAM reserved for SCP use
+ * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
+ */
+#define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000)
+
+#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - \
+ ARM_SCP_TZC_DRAM1_SIZE)
+#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
+#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
+ ARM_SCP_TZC_DRAM1_SIZE - 1)
+
+#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - \
+ ARM_TZC_DRAM1_SIZE)
+#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
+ ARM_SCP_TZC_DRAM1_SIZE)
+#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE - 1)
+
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ ARM_TZC_DRAM1_SIZE)
+#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
+ ARM_NS_DRAM1_SIZE - 1)
+
+#define ARM_DRAM1_BASE MAKE_ULL(0x80000000)
+#define ARM_DRAM1_SIZE MAKE_ULL(0x80000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - 1)
+
+#define ARM_DRAM2_BASE MAKE_ULL(0x880000000)
+#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
+#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
+ ARM_DRAM2_SIZE - 1)
+
+#define ARM_IRQ_SEC_PHY_TIMER 29
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+#define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \
+ MT_MEMORY : MT_DEVICE) \
+ | MT_RW | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
+ ARM_SHARED_RAM_BASE, \
+ ARM_SHARED_RAM_SIZE, \
+ ARM_SHARED_RAM_ATTR)
+
+#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
+ TSP_SEC_MEM_BASE, \
+ TSP_SEC_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+
+/*
+ * The number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#if USE_COHERENT_MEM
+#define ARM_BL_REGIONS 3
+#else
+#define ARM_BL_REGIONS 2
+#endif
+
+#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
+ ARM_BL_REGIONS)
+
+/* Memory mapped Generic timer interfaces */
+#define ARM_SYS_CNTCTL_BASE 0x2a430000
+#define ARM_SYS_CNTREAD_BASE 0x2a800000
+#define ARM_SYS_TIMCTL_BASE 0x2a810000
+
+#define ARM_CONSOLE_BAUDRATE 115200
+
+/* TZC related constants */
+#define ARM_TZC_BASE 0x2a4a0000
+
+
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+#define ADDR_SPACE_SIZE (1ull << 32)
+
+#define PLATFORM_NUM_AFFS (ARM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
+
+#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \
+ PLAT_ARM_CLUSTER1_CORE_COUNT)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
+
+#if !USE_COHERENT_MEM
+/*
+ * Size of the per-cpu data in bytes that should be reserved in the generic
+ * per-cpu data structure for the ARM platform port.
+ */
+#define PLAT_PCPU_DATA_SIZE 2
+#endif
+
+
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
+ * addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
+ + PLAT_ARM_TRUSTED_ROM_SIZE)
+/*
+ * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
+ * the current BL1 RW debug size plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE - \
+ 0x8000)
+#else
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE - \
+ 0x6000)
+#endif
+#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+#define BL2_BASE (BL31_BASE - 0x1C000)
+#else
+#define BL2_BASE (BL31_BASE - 0xC000)
+#endif
+#define BL2_LIMIT BL31_BASE
+
+/*******************************************************************************
+ * BL3-1 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
+ * current BL3-1 debug size plus a little space for growth.
+ */
+#define BL31_BASE (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE - \
+ 0x1D000)
+#define BL31_PROGBITS_LIMIT BL1_RW_BASE
+#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+
+/*******************************************************************************
+ * BL3-2 specific defines.
+ ******************************************************************************/
+/*
+ * On ARM standard platforms, the TSP can execute from Trusted SRAM,
+ * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
+ * controller.
+ */
+#if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
+# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
+# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
+# define TSP_PROGBITS_LIMIT BL2_BASE
+# define BL32_BASE ARM_BL_RAM_BASE
+# define BL32_LIMIT BL31_BASE
+#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
+# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
+# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
+# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
+# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
+ + (1 << 21))
+#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
+# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
+# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
+# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
+# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE)
+#else
+# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the TSP.
+ */
+#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
+
+
+#endif /* __ARM_DEF_H__ */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
new file mode 100644
index 0000000..e1221a9
--- /dev/null
+++ b/include/plat/arm/common/plat_arm.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __PLAT_ARM_H__
+#define __PLAT_ARM_H__
+
+#include <bakery_lock.h>
+#include <bl_common.h>
+#include <cassert.h>
+#include <cpu_data.h>
+#include <stdint.h>
+
+
+/*
+ * Extern declarations common to ARM standard platforms
+ */
+extern const mmap_region_t plat_arm_mmap[];
+
+#define ARM_CASSERT_MMAP \
+ CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \
+ <= MAX_MMAP_REGIONS, \
+ assert_max_mmap_regions);
+
+/*
+ * Utility functions common to ARM standard platforms
+ */
+
+void arm_configure_mmu_el1(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit
+#if USE_COHERENT_MEM
+ , unsigned long coh_start,
+ unsigned long coh_limit
+#endif
+);
+void arm_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit
+#if USE_COHERENT_MEM
+ , unsigned long coh_start,
+ unsigned long coh_limit
+#endif
+);
+
+#if IMAGE_BL31
+#if USE_COHERENT_MEM
+
+/*
+ * Use this macro to instantiate lock before it is used in below
+ * arm_lock_xxx() macros
+ */
+#define ARM_INSTANTIATE_LOCK bakery_lock_t arm_lock \
+ __attribute__ ((section("tzfw_coherent_mem")));
+
+/*
+ * These are wrapper macros to the Coherent Memory Bakery Lock API.
+ */
+#define arm_lock_init() bakery_lock_init(&arm_lock)
+#define arm_lock_get() bakery_lock_get(&arm_lock)
+#define arm_lock_release() bakery_lock_release(&arm_lock)
+
+#else
+
+/*******************************************************************************
+ * Constants to specify how many bakery locks this platform implements. These
+ * are used if the platform chooses not to use coherent memory for bakery lock
+ * data structures.
+ ******************************************************************************/
+#define ARM_MAX_BAKERIES 1
+#define ARM_PWRC_BAKERY_ID 0
+
+/* Empty definition */
+#define ARM_INSTANTIATE_LOCK
+
+/*******************************************************************************
+ * Definition of structure which holds platform specific per-cpu data. Currently
+ * it holds only the bakery lock information for each cpu.
+ ******************************************************************************/
+typedef struct arm_cpu_data {
+ bakery_info_t pcpu_bakery_info[ARM_MAX_BAKERIES];
+} arm_cpu_data_t;
+
+/* Macro to define the offset of bakery_info_t in arm_cpu_data_t */
+#define ARM_CPU_DATA_LOCK_OFFSET __builtin_offsetof\
+ (arm_cpu_data_t, pcpu_bakery_info)
+
+
+/*******************************************************************************
+ * Helper macros for bakery lock api when using the above arm_cpu_data_t for
+ * bakery lock data structures. It assumes that the bakery_info is at the
+ * beginning of the platform specific per-cpu data.
+ ******************************************************************************/
+#define arm_lock_init() /* No init required */
+#define arm_lock_get() bakery_lock_get(ARM_PWRC_BAKERY_ID, \
+ CPU_DATA_PLAT_PCPU_OFFSET + \
+ ARM_CPU_DATA_LOCK_OFFSET)
+#define arm_lock_release() bakery_lock_release(ARM_PWRC_BAKERY_ID, \
+ CPU_DATA_PLAT_PCPU_OFFSET + \
+ ARM_CPU_DATA_LOCK_OFFSET)
+
+/*
+ * Ensure that the size of the platform specific per-cpu data structure and
+ * the size of the memory allocated in generic per-cpu data for the platform
+ * are the same.
+ */
+CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(arm_cpu_data_t),
+ arm_pcpu_data_size_mismatch);
+
+#endif /* USE_COHERENT_MEM */
+
+#else
+
+/*
+* Dummy macros for all other BL stages other than BL3-1
+*/
+#define ARM_INSTANTIATE_LOCK
+#define arm_lock_init()
+#define arm_lock_get()
+#define arm_lock_release()
+
+#endif /* IMAGE_BL31 */
+
+
+/* CCI utility functions */
+void arm_cci_init(void);
+
+/* IO storage utility functions */
+void arm_io_setup(void);
+
+/* Security utility functions */
+void arm_tzc_setup(void);
+
+/* PM utility functions */
+int32_t arm_do_affinst_actions(unsigned int afflvl, unsigned int state);
+int arm_validate_power_state(unsigned int power_state);
+
+/* BL1 utility functions */
+void arm_bl1_early_platform_setup(void);
+void arm_bl1_platform_setup(void);
+void arm_bl1_plat_arch_setup(void);
+
+/* BL2 utility functions */
+void arm_bl2_early_platform_setup(meminfo_t *mem_layout);
+void arm_bl2_platform_setup(void);
+void arm_bl2_plat_arch_setup(void);
+uint32_t arm_get_spsr_for_bl32_entry(void);
+uint32_t arm_get_spsr_for_bl33_entry(void);
+
+/* BL3-1 utility functions */
+void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
+ void *plat_params_from_bl2);
+void arm_bl31_platform_setup(void);
+void arm_bl31_plat_arch_setup(void);
+
+/* TSP utility functions */
+void arm_tsp_early_platform_setup(void);
+
+
+/*
+ * Mandatory functions required in ARM standard platforms
+ */
+void plat_arm_gic_init(void);
+void plat_arm_security_setup(void);
+void plat_arm_pwrc_setup(void);
+
+/*
+ * Optional functions required in ARM standard platforms
+ */
+void plat_arm_io_setup(void);
+int plat_arm_get_alt_image_source(
+ const uintptr_t image_spec,
+ uintptr_t *dev_handle);
+void plat_arm_topology_setup(void);
+
+
+#endif /* __PLAT_ARM_H__ */
diff --git a/plat/fvp/fvp_trusted_boot.c b/include/plat/arm/css/common/aarch64/css_macros.S
similarity index 73%
copy from plat/fvp/fvp_trusted_boot.c
copy to include/plat/arm/css/common/aarch64/css_macros.S
index e7dcc01..2a26eb7 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/include/plat/arm/css/common/aarch64/css_macros.S
@@ -27,19 +27,24 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __CSS_MACROS_S__
+#define __CSS_MACROS_S__
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#include <arm_macros.S>
+#include <platform_def.h>
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant GIC registers whenever an
+ * unhandled exception is taken in BL3-1.
+ * Clobbers: x0 - x10, x16, x17, sp
+ * ---------------------------------------------
+ */
+ .macro plat_print_gic_regs
+ mov_imm x16, PLAT_CSS_GICD_BASE
+ mov_imm x17, PLAT_CSS_GICC_BASE
+ arm_print_gic_regs
+ .endm
+
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
-{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
-}
+#endif /* __CSS_MACROS_S__ */
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
new file mode 100644
index 0000000..12a0550
--- /dev/null
+++ b/include/plat/arm/css/common/css_def.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CSS_DEF_H__
+#define __CSS_DEF_H__
+
+#include <arm_def.h>
+#include <tzc400.h>
+
+/*************************************************************************
+ * Definitions common to all ARM Compute SubSystems (CSS)
+ *************************************************************************/
+#define MHU_SECURE_BASE ARM_SHARED_RAM_BASE
+#define MHU_SECURE_SIZE ARM_SHARED_RAM_SIZE
+#define MHU_PAYLOAD_CACHED 0
+
+#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE
+#define TRUSTED_MAILBOX_SHIFT 4
+
+#define NSROM_BASE 0x1f000000
+#define NSROM_SIZE 0x00001000
+
+/* Following covers CSS Peripherals excluding NSROM and NSRAM */
+#define CSS_DEVICE_BASE 0x20000000
+#define CSS_DEVICE_SIZE 0x0e000000
+#define MHU_BASE 0x2b1f0000
+
+#define NSRAM_BASE 0x2e000000
+#define NSRAM_SIZE 0x00008000
+
+/* The slave_bootsecure controls access to GPU, DMC and CS. */
+#define CSS_NIC400_SLAVE_BOOTSECURE 8
+
+/* Interrupt handling constants */
+#define CSS_IRQ_MHU 69
+#define CSS_IRQ_GPU_SMMU_0 71
+#define CSS_IRQ_GPU_SMMU_1 73
+#define CSS_IRQ_ETR_SMMU 75
+#define CSS_IRQ_TZC 80
+#define CSS_IRQ_TZ_WDOG 86
+
+/* SCP <=> AP boot configuration */
+#define SCP_BOOT_CFG_ADDR 0x04000080
+#define PRIMARY_CPU_SHIFT 8
+#define PRIMARY_CPU_MASK 0xf
+
+
+#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
+ CSS_DEVICE_BASE, \
+ CSS_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+
+/*************************************************************************
+ * Required platform porting definitions common to all
+ * ARM Compute SubSystems (CSS)
+ ************************************************************************/
+
+/*
+ * Load address of BL3-0 in CSS platform ports
+ * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
+ * SCP, it is discarded and BL3-1 is loaded over the top.
+ */
+#define BL30_BASE BL31_BASE
+
+#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED
+
+/* Load address of Non-Secure Image for CSS platform ports */
+#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
+
+/* TZC related constants */
+#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL
+
+
+#endif /* __CSS_DEF_H__ */
diff --git a/plat/fvp/fvp_trusted_boot.c b/include/plat/arm/soc/common/soc_css.h
similarity index 83%
copy from plat/fvp/fvp_trusted_boot.c
copy to include/plat/arm/soc/common/soc_css.h
index e7dcc01..58f0f09 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/include/plat/arm/soc/common/soc_css.h
@@ -28,18 +28,20 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#ifndef __SOC_CSS_H__
+#define __SOC_CSS_H__
/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
+ * Utility functions for ARM CSS SoCs
*/
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+void soc_css_init_nic400(void);
+void soc_css_init_pcie(void);
+
+inline void soc_css_security_setup(void)
{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
+ soc_css_init_nic400();
+ soc_css_init_pcie();
}
+
+
+#endif /* __SOC_CSS_H__ */
diff --git a/include/plat/arm/soc/common/soc_css_def.h b/include/plat/arm/soc/common/soc_css_def.h
new file mode 100644
index 0000000..8b43e4c
--- /dev/null
+++ b/include/plat/arm/soc/common/soc_css_def.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC_CSS_DEF_H__
+#define __SOC_CSS_DEF_H__
+
+#include <common_def.h>
+#include <xlat_tables.h>
+
+
+/*
+ * Definitions common to all ARM CSS SoCs
+ */
+
+/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */
+#define SOC_CSS_DEVICE_BASE 0x40000000
+#define SOC_CSS_DEVICE_SIZE 0x40000000
+#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000
+
+/* PL011 UART related constants */
+#define SOC_CSS_UART0_BASE 0x7ff80000
+#define SOC_CSS_UART1_BASE 0x7ff70000
+
+#define SOC_CSS_UART0_CLK_IN_HZ 7273800
+#define SOC_CSS_UART1_CLK_IN_HZ 7273800
+
+/* SoC NIC-400 Global Programmers View (GPV) */
+#define SOC_CSS_NIC400_BASE 0x7fd00000
+
+#define SOC_CSS_NIC400_USB_EHCI 0
+#define SOC_CSS_NIC400_TLX_MASTER 1
+#define SOC_CSS_NIC400_USB_OHCI 2
+#define SOC_CSS_NIC400_PL354_SMC 3
+/*
+ * The apb4_bridge controls access to:
+ * - the PCIe configuration registers
+ * - the MMU units for USB, HDLCD and DMA
+ */
+#define SOC_CSS_NIC400_APB4_BRIDGE 4
+
+
+#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \
+ SOC_CSS_DEVICE_BASE, \
+ SOC_CSS_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+
+/*
+ * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
+ */
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
+
+/*
+ * Required platform porting definitions common to all ARM CSS SoCs
+ */
+
+/* 2MB used for SCP DDR retraining */
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x00200000)
+
+
+#endif /* __SOC_CSS_DEF_H__ */
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
new file mode 100644
index 0000000..1e2a417
--- /dev/null
+++ b/include/plat/common/common_def.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __COMMON_DEF_H__
+#define __COMMON_DEF_H__
+
+/******************************************************************************
+ * Required platform porting definitions that are expected to be common to
+ * all platforms
+ *****************************************************************************/
+
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+
+/*
+ * Generic platform constants
+ */
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
+
+/* Trusted Boot Firmware BL2 */
+#define BL2_IMAGE_NAME "bl2.bin"
+
+/* SCP Firmware BL3-0 */
+#define BL30_IMAGE_NAME "bl30.bin"
+
+/* EL3 Runtime Firmware BL31 */
+#define BL31_IMAGE_NAME "bl31.bin"
+
+/* Secure Payload BL32 (Trusted OS) */
+#define BL32_IMAGE_NAME "bl32.bin"
+
+/* Non-Trusted Firmware BL33 */
+#define BL33_IMAGE_NAME "bl33.bin"
+
+/* Firmware Image Package */
+#define FIP_IMAGE_NAME "fip.bin"
+
+#if TRUSTED_BOARD_BOOT
+/* Certificates */
+# define BL2_CERT_NAME "bl2.crt"
+# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
+
+# define BL30_KEY_CERT_NAME "bl30_key.crt"
+# define BL31_KEY_CERT_NAME "bl31_key.crt"
+# define BL32_KEY_CERT_NAME "bl32_key.crt"
+# define BL33_KEY_CERT_NAME "bl33_key.crt"
+
+# define BL30_CERT_NAME "bl30.crt"
+# define BL31_CERT_NAME "bl31.crt"
+# define BL32_CERT_NAME "bl32.crt"
+# define BL33_CERT_NAME "bl33.crt"
+#endif /* TRUSTED_BOARD_BOOT */
+
+/*
+ * Some of the platform porting definitions use the 'ull' suffix in order to
+ * avoid subtle integer overflow errors due to implicit integer type promotion
+ * when working with 32-bit values.
+ *
+ * The TSP linker script includes some of these definitions to define the BL3-2
+ * memory map, but the GNU LD does not support the 'ull' suffix, causing the
+ * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
+ * will add the 'ull' suffix only when the macro __LINKER__ is not defined
+ * (__LINKER__ is defined in the command line to preprocess the linker script).
+ * Constants in the linker script will not have the 'ull' suffix, but this is
+ * not a problem since the linker evaluates all constant expressions to 64 bit
+ * (assuming the target architecture is 64 bit).
+ */
+#ifndef __LINKER__
+ #define MAKE_ULL(x) x##ull
+#else
+ #define MAKE_ULL(x) x
+#endif
+
+
+#endif /* __COMMON_DEF_H__ */
+
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/common/aarch64/board_arm_helpers.S
similarity index 67%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/board/common/aarch64/board_arm_helpers.S
index e7dcc01..80c5759 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/common/aarch64/board_arm_helpers.S
@@ -27,19 +27,31 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include <asm_macros.S>
+#include <bl_common.h>
+#include <v2m_def.h>
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+ .globl plat_report_exception
+
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
-{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
-}
+ /* ---------------------------------------------
+ * void plat_report_exception(unsigned int type)
+ * Function to report an unhandled exception
+ * with platform-specific means.
+ * On FVP platform, it updates the LEDs
+ * to indicate where we are
+ * ---------------------------------------------
+ */
+func plat_report_exception
+ mrs x1, CurrentEl
+ lsr x1, x1, #MODE_EL_SHIFT
+ lsl x1, x1, #V2M_SYS_LED_EL_SHIFT
+ lsl x0, x0, #V2M_SYS_LED_EC_SHIFT
+ mov x2, #(SECURE << V2M_SYS_LED_SS_SHIFT)
+ orr x0, x0, x2
+ orr x0, x0, x1
+ mov x1, #V2M_SYSREGS_BASE
+ add x1, x1, #V2M_SYS_LED
+ str w0, [x1]
+ ret
+endfunc plat_report_exception
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
similarity index 94%
rename from plat/fvp/fvp_trusted_boot.c
rename to plat/arm/board/common/board_arm_trusted_boot.c
index e7dcc01..c6ad68a 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -28,11 +28,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
-
+/* Weak definition may be overridden in specific platform */
+#pragma weak plat_match_rotpk
/*
* Check the validity of the key
*
diff --git a/plat/fvp/tsp/tsp-fvp.mk b/plat/arm/board/common/board_css.mk
similarity index 73%
copy from plat/fvp/tsp/tsp-fvp.mk
copy to plat/arm/board/common/board_css.mk
index d2e112a..691999b 100644
--- a/plat/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/board/common/board_css.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -28,11 +28,20 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# TSP source files specific to FVP platform
-BL32_SOURCES += drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/common/plat_gic.c \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/tsp/tsp_fvp_setup.c
+PLAT_INCLUDES += -Iinclude/plat/arm/board/common/
+
+PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/pl011_console.S \
+ plat/arm/board/common/aarch64/board_arm_helpers.S \
+ plat/arm/board/common/board_css_common.c
+
+
+#BL1_SOURCES +=
+
+#BL2_SOURCES +=
+
+#BL31_SOURCES +=
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+ BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
+ BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
+endif
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/common/board_css_common.c
similarity index 62%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/board/common/board_css_common.c
index e7dcc01..3bb3dd6 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/common/board_css_common.c
@@ -27,19 +27,53 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#include <arm_def.h>
+#include <plat_arm.h>
/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
+ * Table of regions for different BL stages to map using the MMU.
+ * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
+ * arm_configure_mmu_elx() will give the available subset of that,
*/
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
-{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
-}
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_FLASH0,
+ V2M_MAP_IOFPGA,
+ CSS_MAP_DEVICE,
+ SOC_CSS_MAP_DEVICE,
+ {0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_FLASH0,
+ V2M_MAP_IOFPGA,
+ CSS_MAP_DEVICE,
+ SOC_CSS_MAP_DEVICE,
+ ARM_MAP_NS_DRAM1,
+ ARM_MAP_TSP_SEC_MEM,
+ {0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_IOFPGA,
+ CSS_MAP_DEVICE,
+ SOC_CSS_MAP_DEVICE,
+ {0}
+};
+#endif
+#if IMAGE_BL32
+const mmap_region_t plat_arm_mmap[] = {
+ V2M_MAP_IOFPGA,
+ CSS_MAP_DEVICE,
+ SOC_CSS_MAP_DEVICE,
+ {0}
+};
+#endif
+
+ARM_CASSERT_MMAP
+
diff --git a/plat/arm/board/fvp/aarch64/fvp_common.c b/plat/arm/board/fvp/aarch64/fvp_common.c
new file mode 100644
index 0000000..a876313
--- /dev/null
+++ b/plat/arm/board/fvp/aarch64/fvp_common.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_config.h>
+#include <arm_def.h>
+#include <arm_gic.h>
+#include <cci.h>
+#include <debug.h>
+#include <mmio.h>
+#include <plat_arm.h>
+#include <v2m_def.h>
+#include "../fvp_def.h"
+
+/*******************************************************************************
+ * arm_config holds the characteristics of the differences between the three FVP
+ * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
+ * at each boot stage by the primary before enabling the MMU (to allow cci
+ * configuration) & used thereafter. Each BL will have its own copy to allow
+ * independent operation.
+ ******************************************************************************/
+arm_config_t arm_config;
+
+#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
+ DEVICE0_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
+ DEVICE1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
+ * Table of regions for various BL stages to map using the MMU.
+ * This doesn't include TZRAM as the 'mem_layout' argument passed to
+ * arm_configure_mmu_elx() will give the available subset of that,
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_FLASH0,
+ V2M_MAP_IOFPGA,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_FLASH0,
+ V2M_MAP_IOFPGA,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ ARM_MAP_NS_DRAM1,
+ ARM_MAP_TSP_SEC_MEM,
+ {0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_IOFPGA,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
+#endif
+#if IMAGE_BL32
+const mmap_region_t plat_arm_mmap[] = {
+ V2M_MAP_IOFPGA,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
+#endif
+
+ARM_CASSERT_MMAP
+
+
+#if IMAGE_BL31 || IMAGE_BL32
+/* Array of secure interrupts to be configured by the gic driver */
+const unsigned int irq_sec_array[] = {
+ IRQ_TZ_WDOG,
+ ARM_IRQ_SEC_PHY_TIMER,
+ ARM_IRQ_SEC_SGI_0,
+ ARM_IRQ_SEC_SGI_1,
+ ARM_IRQ_SEC_SGI_2,
+ ARM_IRQ_SEC_SGI_3,
+ ARM_IRQ_SEC_SGI_4,
+ ARM_IRQ_SEC_SGI_5,
+ ARM_IRQ_SEC_SGI_6,
+ ARM_IRQ_SEC_SGI_7
+};
+
+void plat_arm_gic_init(void)
+{
+ arm_gic_init(arm_config.gicc_base,
+ arm_config.gicd_base,
+ BASE_GICR_BASE,
+ irq_sec_array,
+ ARRAY_SIZE(irq_sec_array));
+}
+
+#endif
+
+/*******************************************************************************
+ * A single boot loader stack is expected to work on both the Foundation FVP
+ * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
+ * SYS_ID register provides a mechanism for detecting the differences between
+ * these platforms. This information is stored in a per-BL array to allow the
+ * code to take the correct path.Per BL platform configuration.
+ ******************************************************************************/
+void fvp_config_setup(void)
+{
+ unsigned int rev, hbi, bld, arch, sys_id;
+
+ sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
+ rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
+ hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
+ bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
+ arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
+
+ if (arch != ARCH_MODEL) {
+ ERROR("This firmware is for FVP models\n");
+ panic();
+ }
+
+ /*
+ * The build field in the SYS_ID tells which variant of the GIC
+ * memory is implemented by the model.
+ */
+ switch (bld) {
+ case BLD_GIC_VE_MMAP:
+ arm_config.gicd_base = VE_GICD_BASE;
+ arm_config.gicc_base = VE_GICC_BASE;
+ arm_config.gich_base = VE_GICH_BASE;
+ arm_config.gicv_base = VE_GICV_BASE;
+ break;
+ case BLD_GIC_A53A57_MMAP:
+ arm_config.gicd_base = BASE_GICD_BASE;
+ arm_config.gicc_base = BASE_GICC_BASE;
+ arm_config.gich_base = BASE_GICH_BASE;
+ arm_config.gicv_base = BASE_GICV_BASE;
+ break;
+ default:
+ ERROR("Unsupported board build %x\n", bld);
+ panic();
+ }
+
+ /*
+ * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
+ * for the Foundation FVP.
+ */
+ switch (hbi) {
+ case HBI_FOUNDATION_FVP:
+ arm_config.max_aff0 = 4;
+ arm_config.max_aff1 = 1;
+ arm_config.flags = 0;
+
+ /*
+ * Check for supported revisions of Foundation FVP
+ * Allow future revisions to run but emit warning diagnostic
+ */
+ switch (rev) {
+ case REV_FOUNDATION_FVP_V2_0:
+ case REV_FOUNDATION_FVP_V2_1:
+ case REV_FOUNDATION_FVP_v9_1:
+ break;
+ default:
+ WARN("Unrecognized Foundation FVP revision %x\n", rev);
+ break;
+ }
+ break;
+ case HBI_BASE_FVP:
+ arm_config.max_aff0 = 4;
+ arm_config.max_aff1 = 2;
+ arm_config.flags |= ARM_CONFIG_BASE_MMAP |
+ ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC;
+
+ /*
+ * Check for supported revisions
+ * Allow future revisions to run but emit warning diagnostic
+ */
+ switch (rev) {
+ case REV_BASE_FVP_V0:
+ break;
+ default:
+ WARN("Unrecognized Base FVP revision %x\n", rev);
+ break;
+ }
+ break;
+ default:
+ ERROR("Unsupported board HBI number 0x%x\n", hbi);
+ panic();
+ }
+}
+
+
+void fvp_cci_init(void)
+{
+ /*
+ * Initialize CCI-400 driver
+ */
+ if (arm_config.flags & ARM_CONFIG_HAS_CCI)
+ arm_cci_init();
+}
+
+void fvp_cci_enable(void)
+{
+ if (arm_config.flags & ARM_CONFIG_HAS_CCI)
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
+
+void fvp_cci_disable(void)
+{
+ if (arm_config.flags & ARM_CONFIG_HAS_CCI)
+ cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
diff --git a/plat/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S
similarity index 75%
rename from plat/fvp/aarch64/fvp_helpers.S
rename to plat/arm/board/fvp/aarch64/fvp_helpers.S
index c661ff3..dd56687 100644
--- a/plat/fvp/aarch64/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,24 +30,21 @@
#include <arch.h>
#include <asm_macros.S>
-#include <bl_common.h>
#include <gic_v2.h>
#include <platform_def.h>
-#include <pl011.h>
+#include <v2m_def.h>
#include "../drivers/pwrc/fvp_pwrc.h"
+#include "../fvp_def.h"
- .globl platform_get_entrypoint
.globl plat_secondary_cold_boot_setup
+ .globl platform_get_entrypoint
.globl platform_mem_init
- .globl plat_report_exception
.globl platform_is_primary_cpu
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
- ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
+ ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
ldr \w_tmp, [\x_tmp]
- ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
+ ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
cmp \w_tmp, #BLD_GIC_VE_MMAP
csel \res, \param1, \param2, eq
.endm
@@ -143,7 +140,7 @@
*/
ldr x10, =MBOX_BASE
bl platform_get_core_pos
- lsl x0, x0, #CACHE_WRITEBACK_SHIFT
+ lsl x0, x0, #ARM_CACHE_WRITEBACK_SHIFT
ldr x0, [x10, x0]
cbz x0, _panic
exit:
@@ -174,27 +171,6 @@
ret
endfunc platform_mem_init
- /* ---------------------------------------------
- * void plat_report_exception(unsigned int type)
- * Function to report an unhandled exception
- * with platform-specific means.
- * On FVP platform, it updates the LEDs
- * to indicate where we are
- * ---------------------------------------------
- */
-func plat_report_exception
- mrs x1, CurrentEl
- lsr x1, x1, #MODE_EL_SHIFT
- lsl x1, x1, #SYS_LED_EL_SHIFT
- lsl x0, x0, #SYS_LED_EC_SHIFT
- mov x2, #(SECURE << SYS_LED_SS_SHIFT)
- orr x0, x0, x2
- orr x0, x0, x1
- mov x1, #VE_SYSREGS_BASE
- add x1, x1, #V2M_SYS_LED
- str w0, [x1]
- ret
-endfunc plat_report_exception
func platform_is_primary_cpu
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
@@ -202,32 +178,3 @@
cset x0, eq
ret
endfunc platform_is_primary_cpu
-
- /* Define a crash console for the plaform */
-#define FVP_CRASH_CONSOLE_BASE PL011_UART1_BASE
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize the crash console
- * without a C Runtime to print crash report.
- * Clobber list : x0, x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_init
- mov_imm x0, FVP_CRASH_CONSOLE_BASE
- mov_imm x1, PL011_UART1_CLK_IN_HZ
- mov_imm x2, PL011_BAUDRATE
- b console_core_init
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(int c)
- * Function to print a character on the crash
- * console without a C Runtime.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov_imm x1, FVP_CRASH_CONSOLE_BASE
- b console_core_putc
-endfunc plat_crash_console_putc
diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.c b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
similarity index 81%
rename from plat/fvp/drivers/pwrc/fvp_pwrc.c
rename to plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
index 0497c2b..e004281 100644
--- a/plat/fvp/drivers/pwrc/fvp_pwrc.c
+++ b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,6 +30,7 @@
#include <bakery_lock.h>
#include <mmio.h>
+#include <plat_arm.h>
#include "../../fvp_def.h"
#include "../../fvp_private.h"
#include "fvp_pwrc.h"
@@ -38,12 +39,7 @@
* TODO: Someday there will be a generic power controller api. At the moment
* each platform has its own pwrc so just exporting functions is fine.
*/
-#if USE_COHERENT_MEM
-static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem")));
-#define LOCK_ARG &pwrc_lock
-#else
-#define LOCK_ARG FVP_PWRC_BAKERY_ID
-#endif
+ARM_INSTANTIATE_LOCK
unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr)
{
@@ -53,56 +49,54 @@
unsigned int fvp_pwrc_read_psysr(unsigned long mpidr)
{
unsigned int rc;
- fvp_lock_get(LOCK_ARG);
+ arm_lock_get();
mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
- fvp_lock_release(LOCK_ARG);
+ arm_lock_release();
return rc;
}
void fvp_pwrc_write_pponr(unsigned long mpidr)
{
- fvp_lock_get(LOCK_ARG);
+ arm_lock_get();
mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
- fvp_lock_release(LOCK_ARG);
+ arm_lock_release();
}
void fvp_pwrc_write_ppoffr(unsigned long mpidr)
{
- fvp_lock_get(LOCK_ARG);
+ arm_lock_get();
mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
- fvp_lock_release(LOCK_ARG);
+ arm_lock_release();
}
void fvp_pwrc_set_wen(unsigned long mpidr)
{
- fvp_lock_get(LOCK_ARG);
+ arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) (PWKUPR_WEN | mpidr));
- fvp_lock_release(LOCK_ARG);
+ arm_lock_release();
}
void fvp_pwrc_clr_wen(unsigned long mpidr)
{
- fvp_lock_get(LOCK_ARG);
+ arm_lock_get();
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
(unsigned int) mpidr);
- fvp_lock_release(LOCK_ARG);
+ arm_lock_release();
}
void fvp_pwrc_write_pcoffr(unsigned long mpidr)
{
- fvp_lock_get(LOCK_ARG);
+ arm_lock_get();
mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
- fvp_lock_release(LOCK_ARG);
+ arm_lock_release();
}
/* Nothing else to do here apart from initializing the lock */
-int fvp_pwrc_setup(void)
+void plat_arm_pwrc_setup(void)
{
- fvp_lock_init(LOCK_ARG);
-
- return 0;
+ arm_lock_init();
}
diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.h b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h
similarity index 96%
rename from plat/fvp/drivers/pwrc/fvp_pwrc.h
rename to plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h
index ad1ea85..5b755af 100644
--- a/plat/fvp/drivers/pwrc/fvp_pwrc.h
+++ b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -63,7 +63,6 @@
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
-int fvp_pwrc_setup(void);
void fvp_pwrc_write_pcoffr(unsigned long);
void fvp_pwrc_write_ppoffr(unsigned long);
void fvp_pwrc_write_pponr(unsigned long);
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_bl1_setup.c
similarity index 68%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/board/fvp/fvp_bl1_setup.c
index e7dcc01..33712d1 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,18 +28,27 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
+#include <plat_arm.h>
#include "fvp_private.h"
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+
+/*******************************************************************************
+ * Perform any BL1 specific platform actions.
+ ******************************************************************************/
+void bl1_early_platform_setup(void)
{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
+ arm_bl1_early_platform_setup();
+
+ /* Initialize the platform config for future decision making */
+ fvp_config_setup();
+
+ /*
+ * Initialize CCI for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ fvp_cci_init();
+ /*
+ * Enable CCI coherency for the primary CPU's cluster.
+ */
+ fvp_cci_enable();
}
diff --git a/plat/juno/scp_bootloader.h b/plat/arm/board/fvp/fvp_bl2_setup.c
similarity index 81%
copy from plat/juno/scp_bootloader.h
copy to plat/arm/board/fvp/fvp_bl2_setup.c
index e872513..a08f42c 100644
--- a/plat/juno/scp_bootloader.h
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,9 +28,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __SCP_BOOTLOADER_H__
-#define __SCP_BOOTLOADER_H__
+#include <plat_arm.h>
+#include "fvp_private.h"
-int scp_bootloader_transfer(void *image, unsigned int image_size);
+
+void bl2_early_platform_setup(meminfo_t *mem_layout)
+{
+ arm_bl2_early_platform_setup(mem_layout);
-#endif
+ /* Initialize the platform config for future decision making */
+ fvp_config_setup();
+}
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_bl31_setup.c
similarity index 67%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/board/fvp/fvp_bl31_setup.c
index e7dcc01..b50ae55 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,18 +28,30 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
+#include <plat_arm.h>
#include "fvp_private.h"
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+
+void bl31_early_platform_setup(bl31_params_t *from_bl2,
+ void *plat_params_from_bl2)
{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
+ arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
+
+ /* Initialize the platform config for future decision making */
+ fvp_config_setup();
+
+ /*
+ * Initialize CCI for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ fvp_cci_init();
+#if RESET_TO_BL31
+ /*
+ * Enable CCI coherency for the primary CPU's cluster
+ * (if earlier BL has not already done so).
+ * FVP PSCI code will enable coherency for other clusters.
+ */
+ fvp_cci_enable();
+
+#endif /* RESET_TO_BL31 */
}
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
new file mode 100644
index 0000000..47723c7
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FVP_DEF_H__
+#define __FVP_DEF_H__
+
+#include <arm_def.h>
+
+
+#define FVP_MAX_CPUS_PER_CLUSTER 4
+
+#define FVP_PRIMARY_CPU 0x0
+
+/*******************************************************************************
+ * FVP memory map related constants
+ ******************************************************************************/
+
+#define FLASH1_BASE 0x0c000000
+#define FLASH1_SIZE 0x04000000
+
+#define PSRAM_BASE 0x14000000
+#define PSRAM_SIZE 0x04000000
+
+#define VRAM_BASE 0x18000000
+#define VRAM_SIZE 0x02000000
+
+/* Aggregate of all devices in the first GB */
+#define DEVICE0_BASE 0x20000000
+#define DEVICE0_SIZE 0x0c200000
+
+#define DEVICE1_BASE 0x2f000000
+#define DEVICE1_SIZE 0x200000
+
+#define NSRAM_BASE 0x2e000000
+#define NSRAM_SIZE 0x10000
+
+#define PCIE_EXP_BASE 0x40000000
+#define TZRNG_BASE 0x7fe60000
+#define TZNVCTR_BASE 0x7fe70000
+#define TZROOTKEY_BASE 0x7fe80000
+
+/* Constants to distinguish FVP type */
+#define HBI_BASE_FVP 0x020
+#define REV_BASE_FVP_V0 0x0
+
+#define HBI_FOUNDATION_FVP 0x010
+#define REV_FOUNDATION_FVP_V2_0 0x0
+#define REV_FOUNDATION_FVP_V2_1 0x1
+#define REV_FOUNDATION_FVP_v9_1 0x2
+
+#define BLD_GIC_VE_MMAP 0x0
+#define BLD_GIC_A53A57_MMAP 0x1
+
+#define ARCH_MODEL 0x1
+
+/* FVP Power controller base address*/
+#define PWRC_BASE 0x1c100000
+
+
+/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+/* VE compatible GIC memory map */
+#define VE_GICD_BASE 0x2c001000
+#define VE_GICC_BASE 0x2c002000
+#define VE_GICH_BASE 0x2c004000
+#define VE_GICV_BASE 0x2c006000
+
+/* Base FVP compatible GIC memory map */
+#define BASE_GICD_BASE 0x2f000000
+#define BASE_GICR_BASE 0x2f100000
+#define BASE_GICC_BASE 0x2c000000
+#define BASE_GICH_BASE 0x2c010000
+#define BASE_GICV_BASE 0x2c02f000
+
+#define IRQ_TZ_WDOG 56
+
+
+/*******************************************************************************
+ * TrustZone address space controller related constants
+ ******************************************************************************/
+
+/* NSAIDs used by devices in TZC filter 0 on FVP */
+#define FVP_NSAID_DEFAULT 0
+#define FVP_NSAID_PCI 1
+#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
+#define FVP_NSAID_AP 9 /* Application Processors */
+#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
+
+/* NSAIDs used by devices in TZC filter 2 on FVP */
+#define FVP_NSAID_HDLCD0 2
+#define FVP_NSAID_CLCD 7
+
+/*******************************************************************************
+ * Shared Data
+ ******************************************************************************/
+
+/* Entrypoint mailboxes */
+#define MBOX_BASE ARM_SHARED_RAM_BASE
+#define MBOX_SIZE 0x200
+
+
+#endif /* __FVP_DEF_H__ */
diff --git a/plat/arm/board/fvp/fvp_io_storage.c b/plat/arm/board/fvp/fvp_io_storage.c
new file mode 100644
index 0000000..0284c3d
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_io_storage.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <debug.h>
+#include <io_driver.h>
+#include <io_storage.h>
+#include <io_semihosting.h>
+#include <plat_arm.h>
+
+/* IO devices */
+static const io_dev_connector_t *sh_dev_con;
+static uintptr_t sh_dev_handle;
+
+
+static int open_semihosting(const uintptr_t spec)
+{
+ int result = IO_FAIL;
+ uintptr_t local_image_handle;
+
+ /* See if the file exists on semi-hosting.*/
+ result = io_dev_init(sh_dev_handle, (uintptr_t)NULL);
+ if (result == IO_SUCCESS) {
+ result = io_open(sh_dev_handle, spec, &local_image_handle);
+ if (result == IO_SUCCESS) {
+ VERBOSE("Using Semi-hosting IO\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+void plat_arm_io_setup(void)
+{
+ int io_result;
+
+ arm_io_setup();
+
+ /* Register the additional IO devices on this platform */
+ io_result = register_io_dev_sh(&sh_dev_con);
+ assert(io_result == IO_SUCCESS);
+
+ /* Open connections to devices and cache the handles */
+ io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle);
+ assert(io_result == IO_SUCCESS);
+
+ /* Ignore improbable errors in release builds */
+ (void)io_result;
+}
+
+int plat_arm_get_alt_image_source(
+ const uintptr_t image_spec,
+ uintptr_t *dev_handle)
+{
+ int result = open_semihosting(image_spec);
+ if (result == IO_SUCCESS)
+ *dev_handle = sh_dev_handle;
+
+ return result;
+}
diff --git a/plat/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
similarity index 82%
rename from plat/fvp/fvp_pm.c
rename to plat/arm/board/fvp/fvp_pm.c
index 3737ecf..b1431c4 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -29,21 +29,25 @@
*/
#include <arch_helpers.h>
+#include <arm_config.h>
#include <arm_gic.h>
#include <assert.h>
-#include <bakery_lock.h>
-#include <cci.h>
#include <debug.h>
+#include <errno.h>
#include <mmio.h>
#include <platform.h>
-#include <plat_config.h>
-#include <platform_def.h>
+#include <plat_arm.h>
#include <psci.h>
-#include <errno.h>
+#include <v2m_def.h>
#include "drivers/pwrc/fvp_pwrc.h"
#include "fvp_def.h"
#include "fvp_private.h"
+
+typedef volatile struct mailbox {
+ unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
+} mailbox_t;
+
/*******************************************************************************
* Private FVP function to program the mailbox for a cpu before it is released
* from reset.
@@ -89,33 +93,6 @@
}
/*******************************************************************************
- * Private FVP function which is used to determine if any platform actions
- * should be performed for the specified affinity instance given its
- * state. Nothing needs to be done if the 'state' is not off or if this is not
- * the highest affinity level which will enter the 'state'.
- ******************************************************************************/
-static int32_t fvp_do_plat_actions(unsigned int afflvl, unsigned int state)
-{
- unsigned int max_phys_off_afflvl;
-
- assert(afflvl <= MPIDR_AFFLVL1);
-
- if (state != PSCI_STATE_OFF)
- return -EAGAIN;
-
- /*
- * Find the highest affinity level which will be suspended and postpone
- * all the platform specific actions until that level is hit.
- */
- max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
- assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
- if (afflvl != max_phys_off_afflvl)
- return -EAGAIN;
-
- return 0;
-}
-
-/*******************************************************************************
* FVP handler called when an affinity instance is about to enter standby.
******************************************************************************/
void fvp_affinst_standby(unsigned int power_state)
@@ -179,7 +156,7 @@
unsigned int state)
{
/* Determine if any platform actions need to be executed */
- if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
+ if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/*
@@ -212,7 +189,7 @@
unsigned long mpidr;
/* Determine if any platform actions need to be executed. */
- if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
+ if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/* Get the mpidr for this cpu */
@@ -245,7 +222,7 @@
unsigned long mpidr;
/* Determine if any platform actions need to be executed. */
- if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
+ if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/* Get the mpidr for this cpu */
@@ -303,8 +280,10 @@
static void __dead2 fvp_system_off(void)
{
/* Write the System Configuration Control Register */
- mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
- CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_SHUTDOWN));
+ mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
+ V2M_CFGCTRL_START |
+ V2M_CFGCTRL_RW |
+ V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
wfi();
ERROR("FVP System Off: operation not handled.\n");
panic();
@@ -313,38 +292,16 @@
static void __dead2 fvp_system_reset(void)
{
/* Write the System Configuration Control Register */
- mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
- CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_REBOOT));
+ mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
+ V2M_CFGCTRL_START |
+ V2M_CFGCTRL_RW |
+ V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
wfi();
ERROR("FVP System Reset: operation not handled.\n");
panic();
}
/*******************************************************************************
- * FVP handler called to check the validity of the power state parameter.
- ******************************************************************************/
-int fvp_validate_power_state(unsigned int power_state)
-{
- /* Sanity check the requested state */
- if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
- /*
- * It's possible to enter standby only on affinity level 0
- * i.e. a cpu on the fvp. Ignore any other affinity level.
- */
- if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
- return PSCI_E_INVALID_PARAMS;
- }
-
- /*
- * We expect the 'state id' to be zero.
- */
- if (psci_get_pstate_id(power_state))
- return PSCI_E_INVALID_PARAMS;
-
- return PSCI_E_SUCCESS;
-}
-
-/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
static const plat_pm_ops_t fvp_plat_pm_ops = {
@@ -356,7 +313,7 @@
.affinst_suspend_finish = fvp_affinst_suspend_finish,
.system_off = fvp_system_off,
.system_reset = fvp_system_reset,
- .validate_power_state = fvp_validate_power_state
+ .validate_power_state = arm_validate_power_state
};
/*******************************************************************************
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_private.h
similarity index 74%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/board/fvp/fvp_private.h
index e7dcc01..e88a45e 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/fvp/fvp_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,18 +28,20 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#ifndef __FVP_PRIVATE_H__
+#define __FVP_PRIVATE_H__
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
-{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
-}
+#include <plat_arm.h>
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+
+void fvp_config_setup(void);
+
+void fvp_cci_init(void);
+void fvp_cci_enable(void);
+void fvp_cci_disable(void);
+
+
+#endif /* __FVP_PRIVATE_H__ */
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_security.c
similarity index 70%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/board/fvp/fvp_security.c
index e7dcc01..0cf8450 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/fvp/fvp_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,18 +28,23 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#include <arm_config.h>
+#include <plat_arm.h>
/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
+ * We assume that all security programming is done by the primary core.
*/
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+void plat_arm_security_setup(void)
{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
+ /*
+ * The Base FVP has a TrustZone address space controller, the Foundation
+ * FVP does not. Trying to program the device on the foundation FVP will
+ * cause an abort.
+ *
+ * If the platform had additional peripheral specific security
+ * configurations, those would be configured here.
+ */
+
+ if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC)
+ arm_tzc_setup();
}
diff --git a/plat/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
similarity index 95%
rename from plat/fvp/fvp_topology.c
rename to plat/arm/board/fvp/fvp_topology.c
index 11ca107..168864a 100644
--- a/plat/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,11 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include <arch.h>
#include <assert.h>
#include <platform_def.h>
/* TODO: Reusing psci error codes & state information. Get our own! */
#include <psci.h>
#include "drivers/pwrc/fvp_pwrc.h"
+#include "fvp_def.h"
/* We treat '255' as an invalid affinity instance */
#define AFFINST_INVAL 0xff
@@ -57,7 +59,7 @@
* is a separate array for each affinity level i.e. cpus and clusters. The child
* and sibling references allow traversal inside and in between the two arrays.
******************************************************************************/
-static affinity_info_t fvp_aff1_topology_map[PLATFORM_CLUSTER_COUNT];
+static affinity_info_t fvp_aff1_topology_map[ARM_CLUSTER_COUNT];
static affinity_info_t fvp_aff0_topology_map[PLATFORM_CORE_COUNT];
/* Simple global variable to safeguard us from stupidity */
@@ -113,7 +115,7 @@
case 0:
/* Assert if the cluster id is anything apart from 0 or 1 */
parent_aff_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- assert(parent_aff_id < PLATFORM_CLUSTER_COUNT);
+ assert(parent_aff_id < ARM_CLUSTER_COUNT);
/* Fetch the starting index in the aff0 array */
for (ctr = fvp_aff1_topology_map[parent_aff_id].child;
@@ -181,19 +183,19 @@
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
-int fvp_setup_topology(void)
+int plat_arm_topology_setup(void)
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;
topology_setup_done = 0;
- for (aff1 = 0; aff1 < PLATFORM_CLUSTER_COUNT; aff1++) {
+ for (aff1 = 0; aff1 < ARM_CLUSTER_COUNT; aff1++) {
fvp_aff1_topology_map[aff1].child = aff0_offset;
fvp_aff1_topology_map[aff1].sibling = aff1 + 1;
- for (aff0 = 0; aff0 < PLATFORM_MAX_CPUS_PER_CLUSTER; aff0++) {
+ for (aff0 = 0; aff0 < FVP_MAX_CPUS_PER_CLUSTER; aff0++) {
mpidr = aff1 << MPIDR_AFF1_SHIFT;
mpidr |= aff0 << MPIDR_AFF0_SHIFT;
diff --git a/plat/arm/board/fvp/include/plat_macros.S b/plat/arm/board/fvp/include/plat_macros.S
new file mode 100644
index 0000000..2feffbe
--- /dev/null
+++ b/plat/arm/board/fvp/include/plat_macros.S
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+#include <arm_macros.S>
+#include <v2m_def.h>
+#include "../fvp_def.h"
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant GIC registers whenever an
+ * unhandled exception is taken in BL3-1.
+ * Clobbers: x0 - x10, x16, x17, sp
+ * ---------------------------------------------
+ */
+ .macro plat_print_gic_regs
+ /*
+ * Detect if we're using the base memory map or
+ * the legacy VE memory map
+ */
+ mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
+ ldr w16, [x0]
+ /* Extract BLD (12th - 15th bits) from the SYS_ID */
+ ubfx x16, x16, #V2M_SYS_ID_BLD_SHIFT, #4
+ /* Check if VE mmap */
+ cmp w16, #BLD_GIC_VE_MMAP
+ b.eq use_ve_mmap
+ /* Check if Cortex-A53/A57 mmap */
+ cmp w16, #BLD_GIC_A53A57_MMAP
+ b.ne exit_print_gic_regs
+ mov_imm x17, BASE_GICC_BASE
+ mov_imm x16, BASE_GICD_BASE
+ b print_gicc_regs
+use_ve_mmap:
+ mov_imm x17, VE_GICC_BASE
+ mov_imm x16, VE_GICD_BASE
+print_gicc_regs:
+ arm_print_gic_regs
+ .endm
+
+#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
new file mode 100644
index 0000000..c2a7d6a
--- /dev/null
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arm_def.h>
+#include <board_arm_def.h>
+#include <common_def.h>
+#include <tzc400.h>
+#include <v2m_def.h>
+#include "../fvp_def.h"
+
+
+/*
+ * Most platform porting definitions provided by included headers
+ */
+
+/*
+ * Required ARM standard platform porting definitions
+ */
+#define PLAT_ARM_CLUSTER0_CORE_COUNT 4
+#define PLAT_ARM_CLUSTER1_CORE_COUNT 4
+
+#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
+#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
+
+#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000
+#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
+
+/* No SCP in FVP */
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0)
+
+#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000)
+
+#define PLAT_ARM_SHARED_RAM_CACHED 1
+
+/*
+ * Load address of BL3-3 for this platform port
+ */
+#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000)
+
+
+/*
+ * PL011 related constants
+ */
+#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE V2M_IOFPGA_UART1_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
+
+#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
+#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
+
+/* CCI related constants */
+#define PLAT_ARM_CCI_BASE 0x2c090000
+#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
+#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
+
+/* TrustZone controller related constants
+ *
+ * Currently only filters 0 and 2 are connected on Base FVP.
+ * Filter 0 : CPU clusters (no access to DRAM by default)
+ * Filter 1 : not connected
+ * Filter 2 : LCDs (access to VRAM allowed by default)
+ * Filter 3 : not connected
+ * Programming unconnected filters will have no effect at the
+ * moment. These filter could, however, be connected in future.
+ * So care should be taken not to configure the unused filters.
+ *
+ * Allow only non-secure access to all DRAM to supported devices.
+ * Give access to the CPUs and Virtio. Some devices
+ * would normally use the default ID so allow that too.
+ */
+#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0)
+
+#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
+
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/juno/scp_bootloader.h b/plat/arm/board/fvp/include/platform_oid.h
similarity index 87%
copy from plat/juno/scp_bootloader.h
copy to plat/arm/board/fvp/include/platform_oid.h
index e872513..1e44cf7 100644
--- a/plat/juno/scp_bootloader.h
+++ b/plat/arm/board/fvp/include/platform_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,10 +27,9 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "../../../../../include/plat/arm/board/common/board_arm_oid.h"
-#ifndef __SCP_BOOTLOADER_H__
-#define __SCP_BOOTLOADER_H__
-
-int scp_bootloader_transfer(void *image, unsigned int image_size);
-
-#endif
+/*
+ * Required platform OIDs
+ * (Provided by included header)
+ */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
new file mode 100644
index 0000000..cba18c7
--- /dev/null
+++ b/plat/arm/board/fvp/platform.mk
@@ -0,0 +1,72 @@
+#
+# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+PLAT_INCLUDES := -Iinclude/plat/arm/board/common \
+ -Iplat/arm/board/fvp/include
+
+
+PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
+ plat/arm/board/fvp/aarch64/fvp_common.c
+
+BL1_SOURCES += drivers/io/io_semihosting.c \
+ lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/aarch64/semihosting_call.S \
+ plat/arm/board/fvp/aarch64/fvp_helpers.S \
+ plat/arm/board/fvp/fvp_bl1_setup.c \
+ plat/arm/board/fvp/fvp_io_storage.c
+
+BL2_SOURCES += drivers/io/io_semihosting.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/aarch64/semihosting_call.S \
+ plat/arm/board/fvp/fvp_bl2_setup.c \
+ plat/arm/board/fvp/fvp_io_storage.c \
+ plat/arm/board/fvp/fvp_security.c
+
+BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ plat/arm/board/fvp/fvp_bl31_setup.c \
+ plat/arm/board/fvp/fvp_pm.c \
+ plat/arm/board/fvp/fvp_security.c \
+ plat/arm/board/fvp/fvp_topology.c \
+ plat/arm/board/fvp/aarch64/fvp_helpers.S \
+ plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+ BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
+ BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
+endif
+
+
+include plat/arm/common/arm_common.mk
diff --git a/plat/juno/scp_bootloader.h b/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
similarity index 82%
copy from plat/juno/scp_bootloader.h
copy to plat/arm/board/fvp/tsp/fvp_tsp_setup.c
index e872513..64246db 100644
--- a/plat/juno/scp_bootloader.h
+++ b/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,9 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __SCP_BOOTLOADER_H__
-#define __SCP_BOOTLOADER_H__
+#include <plat_arm.h>
+#include "../fvp_private.h"
-int scp_bootloader_transfer(void *image, unsigned int image_size);
+void tsp_early_platform_setup(void)
+{
+ arm_tsp_early_platform_setup();
-#endif
+ /* Initialize the platform config for future decision making */
+ fvp_config_setup();
+}
diff --git a/plat/fvp/tsp/tsp-fvp.mk b/plat/arm/board/fvp/tsp/tsp-fvp.mk
similarity index 81%
copy from plat/fvp/tsp/tsp-fvp.mk
copy to plat/arm/board/fvp/tsp/tsp-fvp.mk
index d2e112a..8773ee0 100644
--- a/plat/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/board/fvp/tsp/tsp-fvp.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -29,10 +29,6 @@
#
# TSP source files specific to FVP platform
-BL32_SOURCES += drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/common/plat_gic.c \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/tsp/tsp_fvp_setup.c
+BL32_SOURCES += plat/arm/board/fvp/tsp/fvp_tsp_setup.c
+
+include plat/arm/common/tsp/arm_tsp.mk
diff --git a/plat/juno/aarch64/plat_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S
similarity index 63%
rename from plat/juno/aarch64/plat_helpers.S
rename to plat/arm/board/juno/aarch64/juno_helpers.S
index 6fa66e1..6d31847 100644
--- a/plat/juno/aarch64/plat_helpers.S
+++ b/plat/arm/board/juno/aarch64/juno_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -32,90 +32,12 @@
#include <asm_macros.S>
#include <bl_common.h>
#include <cortex_a57.h>
-#include <cpu_macros.S>
-#include <platform_def.h>
+#include <v2m_def.h>
#include "../juno_def.h"
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl plat_report_exception
- .globl plat_reset_handler
- .globl platform_get_core_pos
- .globl platform_mem_init
-
- /* Define a crash console for the plaform */
-#define JUNO_CRASH_CONSOLE_BASE PL011_UART3_BASE
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize the crash console
- * without a C Runtime to print crash report.
- * Clobber list : x0, x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_init
- mov_imm x0, JUNO_CRASH_CONSOLE_BASE
- mov_imm x1, PL011_UART3_CLK_IN_HZ
- mov_imm x2, PL011_BAUDRATE
- b console_core_init
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(int c)
- * Function to print a character on the crash
- * console without a C Runtime.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov_imm x1, JUNO_CRASH_CONSOLE_BASE
- b console_core_putc
-endfunc plat_crash_console_putc
-
- /* ---------------------------------------------
- * void plat_report_exception(unsigned int type)
- * Function to report an unhandled exception
- * with platform-specific means.
- * On Juno platform, it updates the LEDs
- * to indicate where we are
- * ---------------------------------------------
- */
-func plat_report_exception
- mrs x1, CurrentEl
- lsr x1, x1, #MODE_EL_SHIFT
- lsl x1, x1, #SYS_LED_EL_SHIFT
- lsl x0, x0, #SYS_LED_EC_SHIFT
- mov x2, #(SECURE << SYS_LED_SS_SHIFT)
- orr x0, x0, x2
- orr x0, x0, x1
- mov x1, #VE_SYSREGS_BASE
- add x1, x1, #V2M_SYS_LED
- str w0, [x1]
- ret
-endfunc plat_report_exception
- /*
- * Return 0 to 3 for the A53s and 4 or 5 for the A57s
- */
-func platform_get_core_pos
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap A53/A57 order
- add x0, x1, x0, LSR #6
- ret
-endfunc platform_get_core_pos
-
+ .globl plat_reset_handler
- /* -----------------------------------------------------
- * void platform_mem_init(void);
- *
- * We don't need to carry out any memory initialization
- * on Juno. The Secure RAM is accessible straight away.
- * -----------------------------------------------------
- */
-func platform_mem_init
- ret
-endfunc platform_mem_init
/* --------------------------------------------------------------------
* void plat_reset_handler(void);
@@ -149,10 +71,10 @@
* --------------------------------------------------------------------
*/
/* Read the V2M SYS_ID register */
- mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
+ mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
ldr w1, [x0]
/* Extract board revision from the SYS_ID */
- ubfx x1, x1, #SYS_ID_REV_SHIFT, #4
+ ubfx x1, x1, #V2M_SYS_ID_REV_SHIFT, #4
/*
* On Juno R0: x2 := REV_JUNO_R0 - 1 = 0
* On Juno R1: x2 := REV_JUNO_R1 - 1 = 1
@@ -183,7 +105,8 @@
mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES
cbnz x2, apply_l2_ram_latencies
/* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */
- orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)
+ orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << \
+ L2CTLR_TAG_RAM_LATENCY_SHIFT)
apply_l2_ram_latencies:
msr L2CTLR_EL1, x0
diff --git a/plat/juno/scp_bootloader.h b/plat/arm/board/juno/include/plat_macros.S
similarity index 84%
copy from plat/juno/scp_bootloader.h
copy to plat/arm/board/juno/include/plat_macros.S
index e872513..db0c1d2 100644
--- a/plat/juno/scp_bootloader.h
+++ b/plat/arm/board/juno/include/plat_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,10 +27,15 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
-#ifndef __SCP_BOOTLOADER_H__
-#define __SCP_BOOTLOADER_H__
+#include <css_macros.S>
-int scp_bootloader_transfer(void *image, unsigned int image_size);
+/*
+ * Required platform porting macros
+ * (Provided by included headers)
+ */
+
-#endif
+#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
new file mode 100644
index 0000000..d2122ad
--- /dev/null
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arm_def.h>
+#include <board_arm_def.h>
+#include <board_css_def.h>
+#include <common_def.h>
+#include <css_def.h>
+#include <soc_css_def.h>
+#include <tzc400.h>
+#include <v2m_def.h>
+#include "../juno_def.h"
+
+
+/*
+ * Most platform porting definitions provided by included headers
+ */
+
+/*
+ * Required ARM standard platform porting definitions
+ */
+#define PLAT_ARM_CLUSTER0_CORE_COUNT 2
+#define PLAT_ARM_CLUSTER1_CORE_COUNT 4
+
+/* Use the bypass address */
+#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
+
+/*
+ * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
+ * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of
+ * flash
+ */
+#if TRUSTED_BOARD_BOOT
+#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000
+#else
+#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000
+#endif /* TRUSTED_BOARD_BOOT */
+
+
+/* CCI related constants */
+#define PLAT_ARM_CCI_BASE 0x2c090000
+#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
+#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3
+
+/* TZC related constants */
+#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \
+ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
+
+/*
+ * Required ARM CSS based platform porting definitions
+ */
+
+/* GIC related constants (no GICR in GIC-400) */
+#define PLAT_CSS_GICD_BASE 0x2c010000
+#define PLAT_CSS_GICR_BASE 0x0
+#define PLAT_CSS_GICC_BASE 0x2c02f000
+#define PLAT_CSS_GICH_BASE 0x2c04f000
+#define PLAT_CSS_GICV_BASE 0x2c06f000
+
+#define PLAT_CSS_IRQ_SEC_LIST CSS_IRQ_MHU, \
+ CSS_IRQ_GPU_SMMU_0, \
+ CSS_IRQ_GPU_SMMU_1, \
+ CSS_IRQ_ETR_SMMU, \
+ CSS_IRQ_TZC, \
+ CSS_IRQ_TZ_WDOG
+
+/*
+ * Required ARM CSS SoC based platform porting definitions
+ */
+
+/* CSS SoC NIC-400 Global Programmers View (GPV) */
+#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000
+
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/juno/scp_bootloader.h b/plat/arm/board/juno/include/platform_oid.h
similarity index 87%
copy from plat/juno/scp_bootloader.h
copy to plat/arm/board/juno/include/platform_oid.h
index e872513..1e44cf7 100644
--- a/plat/juno/scp_bootloader.h
+++ b/plat/arm/board/juno/include/platform_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,10 +27,9 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "../../../../../include/plat/arm/board/common/board_arm_oid.h"
-#ifndef __SCP_BOOTLOADER_H__
-#define __SCP_BOOTLOADER_H__
-
-int scp_bootloader_transfer(void *image, unsigned int image_size);
-
-#endif
+/*
+ * Required platform OIDs
+ * (Provided by included header)
+ */
diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h
new file mode 100644
index 0000000..8fe3835
--- /dev/null
+++ b/plat/arm/board/juno/juno_def.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __JUNO_DEF_H__
+#define __JUNO_DEF_H__
+
+
+/*******************************************************************************
+ * Juno memory map related constants
+ ******************************************************************************/
+
+/* Board revisions */
+#define REV_JUNO_R0 0x1 /* Rev B */
+#define REV_JUNO_R1 0x2 /* Rev C */
+
+/* Bypass offset from start of NOR flash */
+#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
+
+#define EMMC_BASE 0x0c000000
+#define EMMC_SIZE 0x04000000
+
+#define PSRAM_BASE 0x14000000
+#define PSRAM_SIZE 0x02000000
+
+
+/*******************************************************************************
+ * TZC-400 related constants
+ ******************************************************************************/
+#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
+#define TZC400_NSAID_PCIE 1
+#define TZC400_NSAID_HDLCD0 2
+#define TZC400_NSAID_HDLCD1 3
+#define TZC400_NSAID_USB 4
+#define TZC400_NSAID_DMA330 5
+#define TZC400_NSAID_THINLINKS 6
+#define TZC400_NSAID_AP 9
+#define TZC400_NSAID_GPU 10
+#define TZC400_NSAID_SCP 11
+#define TZC400_NSAID_CORESIGHT 12
+
+/*******************************************************************************
+ * MMU-401 related constants
+ ******************************************************************************/
+#define MMU401_SSD_OFFSET 0x4000
+#define MMU401_DMA330_BASE 0x7fb00000
+
+
+#endif /* __JUNO_DEF_H__ */
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
new file mode 100644
index 0000000..1de38c3
--- /dev/null
+++ b/plat/arm/board/juno/juno_security.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mmio.h>
+#include <plat_arm.h>
+#include <soc_css.h>
+#include "juno_def.h"
+
+
+/*******************************************************************************
+ * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
+ * assigned to Non-Secure except some for the DMA-330. Assign those back to the
+ * Non-Secure world as well, otherwise EL1 may end up erroneously generating
+ * (untranslated) Secure transactions if it turns the SMMU on.
+ ******************************************************************************/
+static void init_mmu401(void)
+{
+ uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
+ reg |= 0x1FF;
+ mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
+}
+
+/*******************************************************************************
+ * Initialize the secure environment.
+ ******************************************************************************/
+void plat_arm_security_setup(void)
+{
+ /* Initialize the TrustZone Controller */
+ arm_tzc_setup();
+ /* Do ARM CSS SoC security setup */
+ soc_css_security_setup();
+ /* Initialize the SMMU SSD tables*/
+ init_mmu401();
+}
diff --git a/plat/fvp/tsp/tsp-fvp.mk b/plat/arm/board/juno/platform.mk
similarity index 64%
copy from plat/fvp/tsp/tsp-fvp.mk
copy to plat/arm/board/juno/platform.mk
index d2e112a..d8d4f14 100644
--- a/plat/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -28,11 +28,28 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# TSP source files specific to FVP platform
-BL32_SOURCES += drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/common/plat_gic.c \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/tsp/tsp_fvp_setup.c
+PLAT_INCLUDES := -Iplat/arm/board/juno/include
+
+PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S
+
+BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S
+
+BL2_SOURCES += plat/arm/board/juno/juno_security.c \
+
+BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S
+
+
+# Enable workarounds for selected Cortex-A57 erratas.
+ERRATA_A57_806969 := 0
+ERRATA_A57_813420 := 1
+
+# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
+# power down sequence
+SKIP_A57_L1_FLUSH_PWR_DWN := 1
+
+include plat/arm/board/common/board_css.mk
+include plat/arm/common/arm_common.mk
+include plat/arm/soc/common/soc_css.mk
+include plat/arm/css/common/css_common.mk
diff --git a/plat/juno/tsp/tsp-juno.mk b/plat/arm/board/juno/tsp/tsp-juno.mk
similarity index 80%
rename from plat/juno/tsp/tsp-juno.mk
rename to plat/arm/board/juno/tsp/tsp-juno.mk
index 4d56ea2..55b031a 100644
--- a/plat/juno/tsp/tsp-juno.mk
+++ b/plat/arm/board/juno/tsp/tsp-juno.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -28,10 +28,4 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# TSP source files specific to Juno platform
-BL32_SOURCES += drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/juno/aarch64/juno_common.c \
- plat/juno/aarch64/plat_helpers.S \
- plat/juno/tsp/tsp_plat_setup.c
+include plat/arm/common/tsp/arm_tsp.mk
diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c
new file mode 100644
index 0000000..48b4ac8
--- /dev/null
+++ b/plat/arm/common/aarch64/arm_common.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch.h>
+#include <arch_helpers.h>
+#include <cci.h>
+#include <mmio.h>
+#include <plat_arm.h>
+#include <xlat_tables.h>
+
+
+static const int cci_map[] = {
+ PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX,
+ PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX
+};
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak plat_get_ns_image_entrypoint
+
+
+/*******************************************************************************
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ ******************************************************************************/
+#if USE_COHERENT_MEM
+#define DEFINE_CONFIGURE_MMU_EL(_el) \
+ void arm_configure_mmu_el##_el(unsigned long total_base, \
+ unsigned long total_size, \
+ unsigned long ro_start, \
+ unsigned long ro_limit, \
+ unsigned long coh_start, \
+ unsigned long coh_limit) \
+ { \
+ mmap_add_region(total_base, total_base, \
+ total_size, \
+ MT_MEMORY | MT_RW | MT_SECURE); \
+ mmap_add_region(ro_start, ro_start, \
+ ro_limit - ro_start, \
+ MT_MEMORY | MT_RO | MT_SECURE); \
+ mmap_add_region(coh_start, coh_start, \
+ coh_limit - coh_start, \
+ MT_DEVICE | MT_RW | MT_SECURE); \
+ mmap_add(plat_arm_mmap); \
+ init_xlat_tables(); \
+ \
+ enable_mmu_el##_el(0); \
+ }
+#else
+#define DEFINE_CONFIGURE_MMU_EL(_el) \
+ void arm_configure_mmu_el##_el(unsigned long total_base, \
+ unsigned long total_size, \
+ unsigned long ro_start, \
+ unsigned long ro_limit) \
+ { \
+ mmap_add_region(total_base, total_base, \
+ total_size, \
+ MT_MEMORY | MT_RW | MT_SECURE); \
+ mmap_add_region(ro_start, ro_start, \
+ ro_limit - ro_start, \
+ MT_MEMORY | MT_RO | MT_SECURE); \
+ mmap_add(plat_arm_mmap); \
+ init_xlat_tables(); \
+ \
+ enable_mmu_el##_el(0); \
+ }
+#endif
+
+/* Define EL1 and EL3 variants of the function initialising the MMU */
+DEFINE_CONFIGURE_MMU_EL(1)
+DEFINE_CONFIGURE_MMU_EL(3)
+
+
+unsigned long plat_get_ns_image_entrypoint(void)
+{
+ return PLAT_ARM_NS_IMAGE_OFFSET;
+}
+
+/*******************************************************************************
+ * Gets SPSR for BL32 entry
+ ******************************************************************************/
+uint32_t arm_get_spsr_for_bl32_entry(void)
+{
+ /*
+ * The Secure Payload Dispatcher service is responsible for
+ * setting the SPSR prior to entry into the BL3-2 image.
+ */
+ return 0;
+}
+
+/*******************************************************************************
+ * Gets SPSR for BL33 entry
+ ******************************************************************************/
+uint32_t arm_get_spsr_for_bl33_entry(void)
+{
+ unsigned long el_status;
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
+ el_status &= ID_AA64PFR0_ELX_MASK;
+
+ mode = (el_status) ? MODE_EL2 : MODE_EL1;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+
+
+void arm_cci_init(void)
+{
+ cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+}
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/common/aarch64/arm_helpers.S
similarity index 61%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/common/aarch64/arm_helpers.S
index e7dcc01..25b67f3 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/common/aarch64/arm_helpers.S
@@ -27,19 +27,36 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include <asm_macros.S>
+#include <platform_def.h>
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0, x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, PLAT_ARM_CRASH_UART_BASE
+ mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ
+ mov_imm x2, ARM_CONSOLE_BAUDRATE
+ b console_core_init
+endfunc plat_crash_console_init
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
-{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
-}
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, PLAT_ARM_CRASH_UART_BASE
+ b console_core_putc
+endfunc plat_crash_console_putc
diff --git a/plat/fvp/bl1_fvp_setup.c b/plat/arm/common/arm_bl1_setup.c
similarity index 68%
rename from plat/fvp/bl1_fvp_setup.c
rename to plat/arm/common/arm_bl1_setup.c
index 4b421d7..6970aa3 100644
--- a/plat/fvp/bl1_fvp_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,26 +28,17 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <arch_helpers.h>
-#include <assert.h>
+#include <arch.h>
+#include <arm_def.h>
#include <bl_common.h>
-#include <debug.h>
+#include <cci.h>
#include <console.h>
-#include <mmio.h>
-#include <platform.h>
#include <platform_def.h>
+#include <plat_arm.h>
#include "../../bl1/bl1_private.h"
-#include "fvp_def.h"
-#include "fvp_private.h"
-#if USE_COHERENT_MEM
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
+#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -59,6 +50,15 @@
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak bl1_early_platform_setup
+#pragma weak bl1_plat_arch_setup
+#pragma weak bl1_platform_setup
+#pragma weak bl1_plat_sec_mem_layout
+#pragma weak bl1_plat_set_bl2_ep_info
+
+
/* Data structure which holds the extents of the trusted SRAM for BL1*/
static meminfo_t bl1_tzram_layout;
@@ -68,54 +68,53 @@
}
/*******************************************************************************
- * Perform any BL1 specific platform actions.
+ * BL1 specific platform actions shared between ARM standard platforms.
******************************************************************************/
-void bl1_early_platform_setup(void)
+void arm_bl1_early_platform_setup(void)
{
const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
/* Initialize the console to provide early debug support */
- console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
+ console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
+ ARM_CONSOLE_BAUDRATE);
/* Allow BL1 to see the whole Trusted RAM */
- bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
- bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
+ bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
+ bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
/* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
- bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
+ bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
+ bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
reserve_mem(&bl1_tzram_layout.free_base,
&bl1_tzram_layout.free_size,
BL1_RAM_BASE,
bl1_size);
-
- /* Initialize the platform config for future decision making */
- fvp_config_setup();
}
-/*******************************************************************************
- * Function which will evaluate how much of the trusted ram has been gobbled
- * up by BL1 and return the base and size of whats available for loading BL2.
- * Its called after coherency and the MMU have been turned on.
- ******************************************************************************/
-void bl1_platform_setup(void)
+void bl1_early_platform_setup(void)
{
- /* Initialise the IO layer and register platform IO devices */
- fvp_io_setup();
-}
+ arm_bl1_early_platform_setup();
+ /*
+ * Initialize CCI for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ arm_cci_init();
+ /*
+ * Enable CCI coherency for the primary CPU's cluster.
+ */
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
-/*******************************************************************************
- * Perform the very early platform specific architecture setup here. At the
- * moment this only does basic initialization. Later architectural setup
- * (bl1_arch_setup()) does not do anything platform specific.
- ******************************************************************************/
-void bl1_plat_arch_setup(void)
+/******************************************************************************
+ * Perform the very early platform specific architecture setup shared between
+ * ARM standard platforms. This only does basic initialization. Later
+ * architectural setup (bl1_arch_setup()) does not do anything platform
+ * specific.
+ *****************************************************************************/
+void arm_bl1_plat_arch_setup(void)
{
- fvp_cci_init();
- fvp_cci_enable();
-
- fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
+ arm_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE,
BL1_RO_LIMIT
@@ -126,12 +125,31 @@
);
}
+void bl1_plat_arch_setup(void)
+{
+ arm_bl1_plat_arch_setup();
+}
+
+/*
+ * Perform the platform specific architecture setup shared between
+ * ARM standard platforms.
+ */
+void arm_bl1_platform_setup(void)
+{
+ /* Initialise the IO layer and register platform IO devices */
+ plat_arm_io_setup();
+}
+
+void bl1_platform_setup(void)
+{
+ arm_bl1_platform_setup();
+}
/*******************************************************************************
* Before calling this function BL2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL2 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
+ * On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
entry_point_info_t *bl2_ep)
diff --git a/plat/juno/bl2_plat_setup.c b/plat/arm/common/arm_bl2_setup.c
similarity index 65%
rename from plat/juno/bl2_plat_setup.c
rename to plat/arm/common/arm_bl2_setup.c
index 8e7b2a0..a44ec1d 100644
--- a/plat/juno/bl2_plat_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -29,28 +29,13 @@
*/
#include <arch_helpers.h>
-#include <assert.h>
+#include <arm_def.h>
#include <bl_common.h>
#include <console.h>
-#include <debug.h>
-#include <platform.h>
#include <platform_def.h>
+#include <plat_arm.h>
#include <string.h>
-#include "juno_def.h"
-#include "juno_private.h"
-#include "scp_bootloader.h"
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted RAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __RO_END__;
-
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
/*
* The next 2 constants identify the extents of the code & RO data region.
@@ -73,15 +58,45 @@
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
-/* Data structure which holds the extents of the trusted RAM for BL2 */
-static meminfo_t bl2_tzram_layout
-__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE)));
+/* Data structure which holds the extents of the trusted SRAM for BL2 */
+static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
+
/*******************************************************************************
- * Structure which holds the arguments which need to be passed to BL3-1
+ * This structure represents the superset of information that is passed to
+ * BL3-1, e.g. while passing control to it from BL2, bl31_params
+ * and other platform specific params
******************************************************************************/
+typedef struct bl2_to_bl31_params_mem {
+ bl31_params_t bl31_params;
+ image_info_t bl31_image_info;
+ image_info_t bl32_image_info;
+ image_info_t bl33_image_info;
+ entry_point_info_t bl33_ep_info;
+ entry_point_info_t bl32_ep_info;
+ entry_point_info_t bl31_ep_info;
+} bl2_to_bl31_params_mem_t;
+
+
static bl2_to_bl31_params_mem_t bl31_params_mem;
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak bl2_early_platform_setup
+#pragma weak bl2_platform_setup
+#pragma weak bl2_plat_arch_setup
+#pragma weak bl2_plat_sec_mem_layout
+#pragma weak bl2_plat_get_bl31_params
+#pragma weak bl2_plat_get_bl31_ep_info
+#pragma weak bl2_plat_flush_bl31_params
+#pragma weak bl2_plat_set_bl31_ep_info
+#pragma weak bl2_plat_get_bl30_meminfo
+#pragma weak bl2_plat_get_bl32_meminfo
+#pragma weak bl2_plat_set_bl32_ep_info
+#pragma weak bl2_plat_get_bl33_meminfo
+#pragma weak bl2_plat_set_bl33_ep_info
+
+
meminfo_t *bl2_plat_sec_mem_layout(void)
{
return &bl2_tzram_layout;
@@ -140,6 +155,13 @@
return bl2_to_bl31_params;
}
+/* Flush the TF params and the TF plat params */
+void bl2_plat_flush_bl31_params(void)
+{
+ flush_dcache_range((unsigned long)&bl31_params_mem,
+ sizeof(bl2_to_bl31_params_mem_t));
+}
+
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
@@ -147,179 +169,146 @@
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
{
#if DEBUG
- bl31_params_mem.bl31_ep_info.args.arg1 = JUNO_BL31_PLAT_PARAM_VAL;
+ bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL;
#endif
return &bl31_params_mem.bl31_ep_info;
}
/*******************************************************************************
- * BL1 has passed the extents of the trusted RAM that should be visible to BL2
- * in x0. This memory layout is sitting at the base of the free trusted RAM.
- * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
+ * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
+ * in x0. This memory layout is sitting at the base of the free trusted SRAM.
+ * Copy it to a safe location before its reclaimed by later BL2 functionality.
******************************************************************************/
-void bl2_early_platform_setup(meminfo_t *mem_layout)
+void arm_bl2_early_platform_setup(meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
- console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
+ console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
+ ARM_CONSOLE_BAUDRATE);
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
/* Initialise the IO layer and register platform IO devices */
- io_setup();
+ plat_arm_io_setup();
}
-/*******************************************************************************
- * Perform platform specific setup, i.e. initialize the IO layer, load BL3-0
- * image and initialise the memory location to use for passing arguments to
- * BL3-1.
- ******************************************************************************/
-void bl2_platform_setup(void)
+void bl2_early_platform_setup(meminfo_t *mem_layout)
+{
+ arm_bl2_early_platform_setup(mem_layout);
+}
+
+/*
+ * Perform ARM standard platform setup.
+ */
+void arm_bl2_platform_setup(void)
{
/* Initialize the secure environment */
- plat_security_setup();
+ plat_arm_security_setup();
}
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
+void bl2_platform_setup(void)
{
- flush_dcache_range((unsigned long)&bl31_params_mem,
- sizeof(bl2_to_bl31_params_mem_t));
+ arm_bl2_platform_setup();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
-void bl2_plat_arch_setup(void)
+void arm_bl2_plat_arch_setup(void)
{
- configure_mmu_el1(bl2_tzram_layout.total_base,
- bl2_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT
+ arm_configure_mmu_el1(bl2_tzram_layout.total_base,
+ bl2_tzram_layout.total_size,
+ BL2_RO_BASE,
+ BL2_RO_LIMIT
#if USE_COHERENT_MEM
- , BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT
+ , BL2_COHERENT_RAM_BASE,
+ BL2_COHERENT_RAM_LIMIT
#endif
- );
+ );
}
-/*******************************************************************************
- * Populate the extents of memory available for loading BL3-0, i.e. anywhere
- * in trusted RAM as long as it doesn't overwrite BL2.
- ******************************************************************************/
-void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
+void bl2_plat_arch_setup(void)
{
- *bl30_meminfo = bl2_tzram_layout;
+ arm_bl2_plat_arch_setup();
}
/*******************************************************************************
- * Transfer BL3-0 from Trusted RAM using the SCP Download protocol.
- * Return 0 on success, -1 otherwise.
+ * Populate the extents of memory available for loading BL3-0 (if used),
+ * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
******************************************************************************/
-int bl2_plat_handle_bl30(image_info_t *bl30_image_info)
+void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
{
- int ret;
-
- ret = scp_bootloader_transfer((void *)bl30_image_info->image_base,
- bl30_image_info->image_size);
-
- if (ret == 0)
- INFO("BL2: BL3-0 transferred to SCP\n\r");
- else
- ERROR("BL2: BL3-0 transfer failure\n\r");
-
- return ret;
+ *bl30_meminfo = bl2_tzram_layout;
}
/*******************************************************************************
- * Before calling this function BL31 is loaded in memory and its entrypoint
+ * Before calling this function BL3-1 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
+ * the entrypoint of BL3-1 and set SPSR and security state.
+ * On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
- entry_point_info_t *bl31_ep_info)
+ entry_point_info_t *bl31_ep_info)
{
SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
+ DISABLE_ALL_EXCEPTIONS);
}
/*******************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
+ * Before calling this function BL3-2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
+ * the entrypoint of BL3-2 and set SPSR and security state.
+ * On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
- entry_point_info_t *bl32_ep_info)
+ entry_point_info_t *bl32_ep_info)
{
SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
- /*
- * The Secure Payload Dispatcher service is responsible for
- * setting the SPSR prior to entry into the BL32 image.
- */
- bl32_ep_info->spsr = 0;
+ bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
}
/*******************************************************************************
- * Before calling this function BL33 is loaded in memory and its entrypoint
+ * Before calling this function BL3-3 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
+ * the entrypoint of BL3-3 and set SPSR and security state.
+ * On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl33_ep_info(image_info_t *image,
- entry_point_info_t *bl33_ep_info)
+ entry_point_info_t *bl33_ep_info)
{
- unsigned long el_status;
- unsigned int mode;
-
- /* Figure out what mode we enter the non-secure world in */
- el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
- el_status &= ID_AA64PFR0_ELX_MASK;
- if (el_status)
- mode = MODE_EL2;
- else
- mode = MODE_EL1;
-
- /*
- * TODO: Consider the possibility of specifying the SPSR in
- * the FIP ToC and allowing the platform to have a say as
- * well.
- */
- bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
+ bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
}
/*******************************************************************************
- * Populate the extents of memory available for loading BL3-2
+ * Populate the extents of memory available for loading BL32
******************************************************************************/
void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
- * Populate the extents of memory available for loading BL3-2.
+ * Populate the extents of memory available for loading BL32.
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl32_meminfo->free_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
}
/*******************************************************************************
- * Populate the extents of memory available for loading BL3-3
+ * Populate the extents of memory available for loading BL33
******************************************************************************/
void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
{
- bl33_meminfo->total_base = DRAM_NS_BASE;
- bl33_meminfo->total_size = DRAM_NS_SIZE;
- bl33_meminfo->free_base = DRAM_NS_BASE;
- bl33_meminfo->free_size = DRAM_NS_SIZE;
+ bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
+ bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
+ bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
+ bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
new file mode 100644
index 0000000..5c321fa
--- /dev/null
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <arm_def.h>
+#include <arm_gic.h>
+#include <assert.h>
+#include <bl_common.h>
+#include <cci.h>
+#include <console.h>
+#include <debug.h>
+#include <mmio.h>
+#include <plat_arm.h>
+#include <platform.h>
+
+
+/*
+ * The next 3 constants identify the extents of the code, RO data region and the
+ * limit of the BL3-1 image. These addresses are used by the MMU setup code and
+ * therefore they must be page-aligned. It is the responsibility of the linker
+ * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
+ * refer to page-aligned addresses.
+ */
+#define BL31_RO_BASE (unsigned long)(&__RO_START__)
+#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
+#define BL31_END (unsigned long)(&__BL31_END__)
+
+#if USE_COHERENT_MEM
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned. It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
+ * refer to page-aligned addresses.
+ */
+#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#endif
+
+/*
+ * Placeholder variables for copying the arguments that have been passed to
+ * BL3-1 from BL2.
+ */
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak bl31_early_platform_setup
+#pragma weak bl31_platform_setup
+#pragma weak bl31_plat_arch_setup
+#pragma weak bl31_plat_get_next_image_ep_info
+#pragma weak plat_get_syscnt_freq
+
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for the
+ * security state specified. BL3-3 corresponds to the non-secure image type
+ * while BL3-2 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ assert(sec_state_is_valid(type));
+ next_image_info = (type == NON_SECURE)
+ ? &bl33_image_ep_info : &bl32_image_ep_info;
+ /*
+ * None of the images on the ARM development platforms can have 0x0
+ * as the entrypoint
+ */
+ if (next_image_info->pc)
+ return next_image_info;
+ else
+ return NULL;
+}
+
+/*******************************************************************************
+ * Perform any BL3-1 early platform setup common to ARM standard platforms.
+ * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
+ * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
+ * done before the MMU is initialized so that the memory layout can be used
+ * while creating page tables. BL2 has flushed this information to memory, so
+ * we are guaranteed to pick up good data.
+ ******************************************************************************/
+void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
+ void *plat_params_from_bl2)
+{
+ /* Initialize the console to provide early debug support */
+ console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
+ ARM_CONSOLE_BAUDRATE);
+
+#if RESET_TO_BL31
+ /* There are no parameters from BL2 if BL3-1 is a reset vector */
+ assert(from_bl2 == NULL);
+ assert(plat_params_from_bl2 == NULL);
+
+ /* Populate entry point information for BL3-2 and BL3-3 */
+ SET_PARAM_HEAD(&bl32_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+ SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+ bl32_image_ep_info.pc = BL32_BASE;
+ bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+
+ SET_PARAM_HEAD(&bl33_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+ /*
+ * Tell BL3-1 where the non-trusted software image
+ * is located and the entry state information
+ */
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+#else
+ /*
+ * Check params passed from BL2 should not be NULL,
+ */
+ assert(from_bl2 != NULL);
+ assert(from_bl2->h.type == PARAM_BL31);
+ assert(from_bl2->h.version >= VERSION_1);
+ /*
+ * In debug builds, we pass a special value in 'plat_params_from_bl2'
+ * to verify platform parameters from BL2 to BL3-1.
+ * In release builds, it's not used.
+ */
+ assert(((unsigned long long)plat_params_from_bl2) ==
+ ARM_BL31_PLAT_PARAM_VAL);
+
+ /*
+ * Copy BL3-2 and BL3-3 entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
+ bl32_image_ep_info = *from_bl2->bl32_ep_info;
+ bl33_image_ep_info = *from_bl2->bl33_ep_info;
+#endif
+}
+
+void bl31_early_platform_setup(bl31_params_t *from_bl2,
+ void *plat_params_from_bl2)
+{
+ arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
+
+ /*
+ * Initialize CCI for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ arm_cci_init();
+#if RESET_TO_BL31
+ /*
+ * Enable CCI coherency for the primary CPU's cluster
+ * (if earlier BL has not already done so).
+ * Platform specific PSCI code will enable coherency for other
+ * clusters.
+ */
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+
+#endif /* RESET_TO_BL31 */
+}
+
+/*******************************************************************************
+ * Perform any BL3-1 platform setup common to ARM standard platforms
+ ******************************************************************************/
+void arm_bl31_platform_setup(void)
+{
+ unsigned int reg_val;
+
+ /* Initialize the gic cpu and distributor interfaces */
+ plat_arm_gic_init();
+ arm_gic_setup();
+
+#if RESET_TO_BL31
+ /*
+ * Do initial security configuration to allow DRAM/device access
+ * (if earlier BL has not already done so).
+ */
+ plat_arm_security_setup();
+
+#endif /* RESET_TO_BL31 */
+
+ /* Enable and initialize the System level generic timer */
+ mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
+ CNTCR_FCREQ(0) | CNTCR_EN);
+
+ /* Allow access to the System counter timer module */
+ reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
+ reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
+ reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
+ mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
+
+ reg_val = (1 << CNTNSAR_NS_SHIFT(1));
+ mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
+
+ /* Initialize power controller before setting up topology */
+ plat_arm_pwrc_setup();
+
+ /* Topologies are best known to the platform. */
+ plat_arm_topology_setup();
+}
+
+void bl31_platform_setup(void)
+{
+ arm_bl31_platform_setup();
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup here. At the
+ * moment this is only intializes the mmu in a quick and dirty way.
+ ******************************************************************************/
+void arm_bl31_plat_arch_setup(void)
+{
+ arm_configure_mmu_el3(BL31_RO_BASE,
+ (BL31_END - BL31_RO_BASE),
+ BL31_RO_BASE,
+ BL31_RO_LIMIT
+#if USE_COHERENT_MEM
+ , BL31_COHERENT_RAM_BASE,
+ BL31_COHERENT_RAM_LIMIT
+#endif
+ );
+}
+
+void bl31_plat_arch_setup(void)
+{
+ arm_bl31_plat_arch_setup();
+}
+
+uint64_t plat_get_syscnt_freq(void)
+{
+ uint64_t counter_base_frequency;
+
+ /* Read the frequency from Frequency modes table */
+ counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
+
+ /* The first entry of the frequency modes table must not be 0 */
+ if (counter_base_frequency == 0)
+ panic();
+
+ return counter_base_frequency;
+}
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
new file mode 100644
index 0000000..3b7c057
--- /dev/null
+++ b/plat/arm/common/arm_common.mk
@@ -0,0 +1,85 @@
+#
+# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
+# DRAM (if available) or the TZC secured area of DRAM.
+# Trusted SRAM is the default.
+
+ARM_TSP_RAM_LOCATION := tsram
+ifeq (${ARM_TSP_RAM_LOCATION}, tsram)
+ ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
+else ifeq (${ARM_TSP_RAM_LOCATION}, tdram)
+ ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID
+else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
+ ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
+else
+ $(error "Unsupported ARM_TSP_RAM_LOCATION value")
+endif
+
+# Process flags
+$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
+
+PLAT_INCLUDES += -Iinclude/plat/arm/common \
+ -Iinclude/plat/arm/common/aarch64
+
+
+PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \
+ plat/arm/common/aarch64/arm_common.c \
+ plat/arm/common/aarch64/arm_helpers.S \
+ plat/common/aarch64/plat_common.c
+
+BL1_SOURCES += drivers/arm/cci/cci.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/common/arm_bl1_setup.c \
+ plat/arm/common/arm_io_storage.c \
+ plat/common/aarch64/platform_up_stack.S
+
+BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/common/arm_bl2_setup.c \
+ plat/arm/common/arm_io_storage.c \
+ plat/arm/common/arm_security.c \
+ plat/common/aarch64/platform_up_stack.S
+
+BL31_SOURCES += drivers/arm/cci/cci.c \
+ drivers/arm/gic/arm_gic.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/gic/gic_v3.c \
+ drivers/arm/tzc400/tzc400.c \
+ plat/arm/common/arm_bl31_setup.c \
+ plat/arm/common/arm_pm.c \
+ plat/arm/common/arm_security.c \
+ plat/arm/common/arm_topology.c \
+ plat/common/plat_gic.c \
+ plat/common/aarch64/platform_mp_stack.S
diff --git a/plat/juno/plat_io_storage.c b/plat/arm/common/arm_io_storage.c
similarity index 84%
rename from plat/juno/plat_io_storage.c
rename to plat/arm/common/arm_io_storage.c
index b31865e..ea29313 100644
--- a/plat/juno/plat_io_storage.c
+++ b/plat/arm/common/arm_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,7 +27,6 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-
#include <assert.h>
#include <debug.h>
#include <io_driver.h>
@@ -40,16 +39,13 @@
/* IO devices */
static const io_dev_connector_t *fip_dev_con;
-static uintptr_t fip_dev_spec;
static uintptr_t fip_dev_handle;
static const io_dev_connector_t *memmap_dev_con;
-static uintptr_t memmap_dev_spec;
-static uintptr_t memmap_init_params;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
- .offset = FLASH_BASE,
- .length = FLASH_SIZE
+ .offset = PLAT_ARM_FIP_BASE,
+ .length = PLAT_ARM_FIP_MAX_SIZE
};
static const io_file_spec_t bl2_file_spec = {
@@ -227,16 +223,25 @@
}
};
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak plat_arm_io_setup
+#pragma weak plat_arm_get_alt_image_source
+
static int open_fip(const uintptr_t spec)
{
- int result = IO_FAIL;
+ int result;
+ uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME);
if (result == IO_SUCCESS) {
- INFO("Using FIP\n");
- /*TODO: Check image defined in spec is present in FIP. */
+ result = io_open(fip_dev_handle, spec, &local_image_handle);
+ if (result == IO_SUCCESS) {
+ VERBOSE("Using FIP\n");
+ io_close(local_image_handle);
+ }
}
return result;
}
@@ -244,25 +249,25 @@
static int open_memmap(const uintptr_t spec)
{
- int result = IO_FAIL;
+ int result;
uintptr_t local_image_handle;
- result = io_dev_init(memmap_dev_handle, memmap_init_params);
+ result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
if (result == IO_SUCCESS) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == IO_SUCCESS) {
- /* INFO("Using Memmap IO\n"); */
+ VERBOSE("Using Memmap\n");
io_close(local_image_handle);
}
}
return result;
}
-void io_setup(void)
+
+void arm_io_setup(void)
{
- int io_result = IO_FAIL;
+ int io_result;
- /* Register the IO devices on this platform */
io_result = register_io_dev_fip(&fip_dev_con);
assert(io_result == IO_SUCCESS);
@@ -270,10 +275,11 @@
assert(io_result == IO_SUCCESS);
/* Open connections to devices and cache the handles */
- io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle);
+ io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
+ &fip_dev_handle);
assert(io_result == IO_SUCCESS);
- io_result = io_dev_open(memmap_dev_con, memmap_dev_spec,
+ io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
&memmap_dev_handle);
assert(io_result == IO_SUCCESS);
@@ -281,6 +287,18 @@
(void)io_result;
}
+void plat_arm_io_setup(void)
+{
+ arm_io_setup();
+}
+
+int plat_arm_get_alt_image_source(
+ const uintptr_t image_spec __attribute__((unused)),
+ uintptr_t *dev_handle __attribute__((unused)))
+{
+ /* By default do not try an alternative */
+ return IO_FAIL;
+}
/* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy */
@@ -301,6 +319,14 @@
*dev_handle = *(policy->dev_handle);
break;
}
+ VERBOSE("Trying alternative IO\n");
+ result = plat_arm_get_alt_image_source(
+ policy->image_spec,
+ dev_handle);
+ if (result == IO_SUCCESS) {
+ *image_spec = policy->image_spec;
+ break;
+ }
}
policy++;
}
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
new file mode 100644
index 0000000..67c2b73
--- /dev/null
+++ b/plat/arm/common/arm_pm.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <errno.h>
+#include <psci.h>
+
+
+/*******************************************************************************
+ * ARM standard platform utility function which is used to determine if any
+ * platform actions should be performed for the specified affinity instance
+ * given its state. Nothing needs to be done if the 'state' is not off or if
+ * this is not the highest affinity level which will enter the 'state'.
+ ******************************************************************************/
+int32_t arm_do_affinst_actions(unsigned int afflvl, unsigned int state)
+{
+ unsigned int max_phys_off_afflvl;
+
+ assert(afflvl <= MPIDR_AFFLVL1);
+
+ if (state != PSCI_STATE_OFF)
+ return -EAGAIN;
+
+ /*
+ * Find the highest affinity level which will be suspended and postpone
+ * all the platform specific actions until that level is hit.
+ */
+ max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
+ assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
+ if (afflvl != max_phys_off_afflvl)
+ return -EAGAIN;
+
+ return 0;
+}
+
+/*******************************************************************************
+ * ARM standard platform handler called to check the validity of the power state
+ * parameter.
+ ******************************************************************************/
+int arm_validate_power_state(unsigned int power_state)
+{
+ /* Sanity check the requested state */
+ if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
+ /*
+ * It's possible to enter standby only on affinity level 0
+ * (i.e. a CPU on ARM standard platforms).
+ * Ignore any other affinity level.
+ */
+ if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ /*
+ * We expect the 'state id' to be zero.
+ */
+ if (psci_get_pstate_id(power_state))
+ return PSCI_E_INVALID_PARAMS;
+
+ return PSCI_E_SUCCESS;
+}
diff --git a/plat/arm/common/arm_security.c b/plat/arm/common/arm_security.c
new file mode 100644
index 0000000..8bee4fe
--- /dev/null
+++ b/plat/arm/common/arm_security.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_def.h>
+#include <debug.h>
+#include <platform_def.h>
+#include <tzc400.h>
+
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak plat_arm_security_setup
+
+
+/*******************************************************************************
+ * Initialize the TrustZone Controller for ARM standard platforms.
+ * Configure Region 0 with no access, Region 1 with secure access only, and
+ * the remaining DRAM regions access from the given Non-Secure masters.
+ ******************************************************************************/
+void arm_tzc_setup(void)
+{
+ INFO("Configuring TrustZone Controller\n");
+
+ tzc_init(ARM_TZC_BASE);
+
+ /* Disable filters. */
+ tzc_disable_filters();
+
+ /* Region 0 set to no access by default */
+ tzc_configure_region0(TZC_REGION_S_NONE, 0);
+
+ /* Region 1 set to cover Secure part of DRAM */
+ tzc_configure_region(PLAT_ARM_TZC_FILTERS, 1,
+ ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
+ TZC_REGION_S_RDWR,
+ 0);
+
+ /* Region 2 set to cover Non-Secure access to 1st DRAM address range.
+ * Apply the same configuration to given filters in the TZC. */
+ tzc_configure_region(PLAT_ARM_TZC_FILTERS, 2,
+ ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
+ TZC_REGION_S_NONE,
+ PLAT_ARM_TZC_NS_DEV_ACCESS);
+
+ /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
+ tzc_configure_region(PLAT_ARM_TZC_FILTERS, 3,
+ ARM_DRAM2_BASE, ARM_DRAM2_END,
+ TZC_REGION_S_NONE,
+ PLAT_ARM_TZC_NS_DEV_ACCESS);
+
+ /*
+ * Raise an exception if a NS device tries to access secure memory
+ * TODO: Add interrupt handling support.
+ */
+ tzc_set_action(TZC_ACTION_ERR);
+
+ /* Enable filters. */
+ tzc_enable_filters();
+}
+
+void plat_arm_security_setup(void)
+{
+ arm_tzc_setup();
+}
diff --git a/plat/juno/plat_topology.c b/plat/arm/common/arm_topology.c
similarity index 81%
rename from plat/juno/plat_topology.c
rename to plat/arm/common/arm_topology.c
index 24be767..94faa9f 100644
--- a/plat/juno/plat_topology.c
+++ b/plat/arm/common/arm_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,8 +28,18 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <platform_def.h>
+#include <arch.h>
#include <psci.h>
+#include <platform_def.h>
+
+/*
+ * Weak definitions use fixed topology. Strong definitions could make topology
+ * configurable
+ */
+#pragma weak plat_get_aff_count
+#pragma weak plat_get_aff_state
+#pragma weak plat_arm_topology_setup
+
unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
{
@@ -38,9 +48,10 @@
return 1;
if (aff_lvl == MPIDR_AFFLVL1)
- return 2; /* We have two clusters */
+ return ARM_CLUSTER_COUNT;
- return mpidr & 0x100 ? 4 : 2; /* 4 cpus in cluster 1, 2 in cluster 0 */
+ return mpidr & 0x100 ? PLAT_ARM_CLUSTER1_CORE_COUNT :
+ PLAT_ARM_CLUSTER0_CORE_COUNT;
}
unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
@@ -48,8 +59,6 @@
return aff_lvl <= MPIDR_AFFLVL1 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
}
-int plat_setup_topology(void)
+void plat_arm_topology_setup(void)
{
- /* Juno todo: Make topology configurable via SCC */
- return 0;
}
diff --git a/plat/fvp/tsp/tsp-fvp.mk b/plat/arm/common/tsp/arm_tsp.mk
similarity index 85%
rename from plat/fvp/tsp/tsp-fvp.mk
rename to plat/arm/common/tsp/arm_tsp.mk
index d2e112a..fc6bd93 100644
--- a/plat/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/common/tsp/arm_tsp.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -28,11 +28,9 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# TSP source files specific to FVP platform
+# TSP source files common to ARM standard platforms
BL32_SOURCES += drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
+ plat/arm/common/tsp/arm_tsp_setup.c \
plat/common/aarch64/platform_mp_stack.S \
- plat/common/plat_gic.c \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/tsp/tsp_fvp_setup.c
+ plat/common/plat_gic.c
diff --git a/plat/fvp/tsp/tsp_fvp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
similarity index 81%
rename from plat/fvp/tsp/tsp_fvp_setup.c
rename to plat/arm/common/tsp/arm_tsp_setup.c
index d8f46bd..78db160 100644
--- a/plat/fvp/tsp/tsp_fvp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,24 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include <arm_def.h>
#include <bl_common.h>
#include <console.h>
+#include <platform_def.h>
#include <platform_tsp.h>
-#include "../fvp_def.h"
-#include "../fvp_private.h"
+#include <plat_arm.h>
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __RO_END__;
-extern unsigned long __BL32_END__;
-
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
/*
* The next 3 constants identify the extents of the code & RO data region and
@@ -70,19 +59,29 @@
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak tsp_early_platform_setup
+#pragma weak tsp_platform_setup
+#pragma weak tsp_plat_arch_setup
+
+
/*******************************************************************************
* Initialize the UART
******************************************************************************/
-void tsp_early_platform_setup(void)
+void arm_tsp_early_platform_setup(void)
{
/*
* Initialize a different console than already in use to display
* messages from TSP
*/
- console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
+ console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ,
+ ARM_CONSOLE_BAUDRATE);
+}
- /* Initialize the platform config for future decision making */
- fvp_config_setup();
+void tsp_early_platform_setup(void)
+{
+ arm_tsp_early_platform_setup();
}
/*******************************************************************************
@@ -90,7 +89,7 @@
******************************************************************************/
void tsp_platform_setup(void)
{
- fvp_gic_init();
+ plat_arm_gic_init();
}
/*******************************************************************************
@@ -99,7 +98,7 @@
******************************************************************************/
void tsp_plat_arch_setup(void)
{
- fvp_configure_mmu_el1(BL32_RO_BASE,
+ arm_configure_mmu_el1(BL32_RO_BASE,
(BL32_END - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT
diff --git a/plat/juno/aarch64/bl1_plat_helpers.S b/plat/arm/css/common/aarch64/css_helpers.S
similarity index 67%
rename from plat/juno/aarch64/bl1_plat_helpers.S
rename to plat/arm/css/common/aarch64/css_helpers.S
index 9b92979..1eee762 100644
--- a/plat/juno/aarch64/bl1_plat_helpers.S
+++ b/plat/arm/css/common/aarch64/css_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -27,33 +27,17 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-
#include <arch.h>
#include <asm_macros.S>
-#include "../juno_def.h"
+#include <cpu_macros.S>
+#include <css_def.h>
- .globl platform_is_primary_cpu
- .globl platform_get_entrypoint
- .globl platform_cold_boot_init
- .globl plat_secondary_cold_boot_setup
+ .weak plat_secondary_cold_boot_setup
+ .weak platform_get_entrypoint
+ .weak platform_mem_init
+ .globl platform_get_core_pos
+ .weak platform_is_primary_cpu
- /* -----------------------------------------------------
- * unsigned int platform_is_primary_cpu (unsigned int mpid);
- *
- * Given the mpidr say whether this cpu is the primary
- * cpu (applicable ony after a cold boot)
- * -----------------------------------------------------
- */
-func platform_is_primary_cpu
- mov x9, x30
- bl platform_get_core_pos
- ldr x1, =SCP_BOOT_CFG_ADDR
- ldr x1, [x1]
- ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK
- cmp x0, x1
- cset x0, eq
- ret x9
-endfunc platform_is_primary_cpu
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
@@ -65,12 +49,11 @@
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
- /* Juno todo: Implement secondary CPU cold boot setup on Juno */
+ /* todo: Implement secondary CPU cold boot setup on CSS platforms */
cb_panic:
b cb_panic
endfunc plat_secondary_cold_boot_setup
-
/* -----------------------------------------------------
* void platform_get_entrypoint (unsigned int mpid);
*
@@ -95,52 +78,45 @@
ret x9
endfunc platform_get_entrypoint
+ /*
+ * Override the default implementation to swap the cluster order.
+ * This is necessary in order to match the format of the boot
+ * information passed by the SCP and read in platform_is_primary_cpu
+ * below.
+ */
+func platform_get_core_pos
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
+ add x0, x1, x0, LSR #6
+ ret
+endfunc platform_get_core_pos
/* -----------------------------------------------------
- * void platform_cold_boot_init (bl1_main function);
+ * void platform_mem_init(void);
*
- * Routine called only by the primary cpu after a cold
- * boot to perform early platform initialization
+ * We don't need to carry out any memory initialization
+ * on CSS platforms. The Secure RAM is accessible straight away.
* -----------------------------------------------------
*/
-func platform_cold_boot_init
- mov x20, x0
+func platform_mem_init
+ ret
+endfunc platform_mem_init
- /* ---------------------------------------------
- * Give ourselves a small coherent stack to
- * ease the pain of initializing the MMU and
- * CCI in assembler
- * ---------------------------------------------
- */
- mrs x0, mpidr_el1
- bl platform_set_coherent_stack
-
- /* ---------------------------------------------
- * Architectural init. can be generic e.g.
- * enabling stack alignment and platform spec-
- * ific e.g. MMU & page table setup as per the
- * platform memory map. Perform the latter here
- * and the former in bl1_main.
- * ---------------------------------------------
- */
- bl bl1_early_platform_setup
- bl bl1_plat_arch_setup
-
- /* ---------------------------------------------
- * Give ourselves a stack allocated in Normal
- * -IS-WBWA memory
- * ---------------------------------------------
- */
- mrs x0, mpidr_el1
- bl platform_set_stack
-
- /* ---------------------------------------------
- * Jump to the main function. Returning from it
- * is a terminal error.
- * ---------------------------------------------
+ /* -----------------------------------------------------
+ * unsigned int platform_is_primary_cpu (unsigned int mpid);
+ *
+ * Given the mpidr say whether this cpu is the primary
+ * cpu (applicable ony after a cold boot)
+ * -----------------------------------------------------
*/
- blr x20
-
-cb_init_panic:
- b cb_init_panic
-endfunc platform_cold_boot_init
+func platform_is_primary_cpu
+ mov x9, x30
+ bl platform_get_core_pos
+ ldr x1, =SCP_BOOT_CFG_ADDR
+ ldr x1, [x1]
+ ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK
+ cmp x0, x1
+ cset x0, eq
+ ret x9
+endfunc platform_is_primary_cpu
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/css/common/css_bl2_setup.c
similarity index 68%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/css/common/css_bl2_setup.c
index e7dcc01..2ca7a0b 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/css/common/css_bl2_setup.c
@@ -28,18 +28,28 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
+#include <bl_common.h>
#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#include "css_scp_bootloader.h"
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+/* Weak definition may be overridden in specific CSS based platform */
+#pragma weak bl2_plat_handle_bl30
+
+/*******************************************************************************
+ * Transfer BL3-0 from Trusted RAM using the SCP Download protocol.
+ * Return 0 on success, -1 otherwise.
+ ******************************************************************************/
+int bl2_plat_handle_bl30(image_info_t *bl30_image_info)
{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
+ int ret;
+
+ ret = scp_bootloader_transfer((void *)bl30_image_info->image_base,
+ bl30_image_info->image_size);
+
+ if (ret == 0)
+ INFO("BL2: BL3-0 transferred to SCP\n\r");
+ else
+ ERROR("BL2: BL3-0 transfer failure\n\r");
+
+ return ret;
}
diff --git a/plat/fvp/fvp_trusted_boot.c b/plat/arm/css/common/css_common.c
similarity index 70%
copy from plat/fvp/fvp_trusted_boot.c
copy to plat/arm/css/common/css_common.c
index e7dcc01..91813f2 100644
--- a/plat/fvp/fvp_trusted_boot.c
+++ b/plat/arm/css/common/css_common.c
@@ -28,18 +28,37 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <assert.h>
-#include <debug.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
+#include <arm_gic.h>
+#include <bl_common.h>
+#include <platform_def.h>
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
+
+#if IMAGE_BL31 || IMAGE_BL32
+
+const unsigned int irq_sec_array[] = {
+ PLAT_CSS_IRQ_SEC_LIST,
+ ARM_IRQ_SEC_PHY_TIMER,
+ ARM_IRQ_SEC_SGI_0,
+ ARM_IRQ_SEC_SGI_1,
+ ARM_IRQ_SEC_SGI_2,
+ ARM_IRQ_SEC_SGI_3,
+ ARM_IRQ_SEC_SGI_4,
+ ARM_IRQ_SEC_SGI_5,
+ ARM_IRQ_SEC_SGI_6,
+ ARM_IRQ_SEC_SGI_7
+};
+
+
+/* Weak definitions may be overridden in specific CSS based platform */
+#pragma weak plat_arm_gic_init
+
+void plat_arm_gic_init(void)
{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
+ arm_gic_init(PLAT_CSS_GICC_BASE,
+ PLAT_CSS_GICD_BASE,
+ PLAT_CSS_GICR_BASE,
+ irq_sec_array,
+ ARRAY_SIZE(irq_sec_array));
}
+
+#endif /* IMAGE_BL31 || IMAGE_BL32 */
diff --git a/plat/fvp/tsp/tsp-fvp.mk b/plat/arm/css/common/css_common.mk
similarity index 65%
copy from plat/fvp/tsp/tsp-fvp.mk
copy to plat/arm/css/common/css_common.mk
index d2e112a..edbfe1e 100644
--- a/plat/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/css/common/css_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -28,11 +28,28 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# TSP source files specific to FVP platform
-BL32_SOURCES += drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/common/plat_gic.c \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/tsp/tsp_fvp_setup.c
+PLAT_INCLUDES += -Iinclude/plat/arm/css/common \
+ -Iinclude/plat/arm/css/common/aarch64
+
+
+PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S \
+ plat/arm/css/common/css_common.c
+
+#BL1_SOURCES +=
+
+BL2_SOURCES += plat/arm/css/common/css_bl2_setup.c \
+ plat/arm/css/common/css_mhu.c \
+ plat/arm/css/common/css_scp_bootloader.c \
+ plat/arm/css/common/css_scpi.c
+
+BL31_SOURCES += plat/arm/css/common/css_mhu.c \
+ plat/arm/css/common/css_pm.c \
+ plat/arm/css/common/css_scpi.c
+
+
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL3-1 as the reset vector is not supported on CSS platforms. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
+NEED_BL30 := yes
diff --git a/plat/juno/mhu.c b/plat/arm/css/common/css_mhu.c
similarity index 80%
rename from plat/juno/mhu.c
rename to plat/arm/css/common/css_mhu.c
index c1c414c..fa4a81d 100644
--- a/plat/juno/mhu.c
+++ b/plat/arm/css/common/css_mhu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,10 +30,10 @@
#include <arch_helpers.h>
#include <bakery_lock.h>
+#include <css_def.h>
#include <mmio.h>
-#include "juno_def.h"
-#include "juno_private.h"
-#include "mhu.h"
+#include <plat_arm.h>
+#include "css_mhu.h"
/* SCP MHU secure channel registers */
#define SCP_INTR_S_STAT 0x200
@@ -45,20 +45,15 @@
#define CPU_INTR_S_SET 0x308
#define CPU_INTR_S_CLEAR 0x310
-#if IMAGE_BL31
-#if USE_COHERENT_MEM
-static bakery_lock_t mhu_secure_lock __attribute__ ((section("tzfw_coherent_mem")));
-#define LOCK_ARG &mhu_secure_lock
-#else
-#define LOCK_ARG JUNO_MHU_BAKERY_ID
-#endif /*__USE_COHERENT_MEM__ */
-#else
-#define LOCK_ARG /* Locks required only for BL3-1 images */
-#endif /* __IMAGE_BL31__ */
+ARM_INSTANTIATE_LOCK
+
+/* Weak definition may be overridden in specific CSS based platform */
+#pragma weak plat_arm_pwrc_setup
+
void mhu_secure_message_start(void)
{
- juno_lock_get(LOCK_ARG);
+ arm_lock_get();
/* Make sure any previous command has finished */
while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0)
@@ -85,15 +80,18 @@
void mhu_secure_message_end(void)
{
- /* Clear any response we got by writing all ones to the CLEAR register */
+ /*
+ * Clear any response we got by writing all ones to the CLEAR
+ * register
+ */
mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 0xffffffffu);
- juno_lock_release(LOCK_ARG);
+ arm_lock_release();
}
void mhu_secure_init(void)
{
- juno_lock_init(LOCK_ARG);
+ arm_lock_init();
/*
* Clear the CPU's INTR register to make sure we don't see a stale
@@ -101,3 +99,8 @@
*/
mmio_write_32(MHU_BASE + CPU_INTR_S_CLEAR, 0xffffffffu);
}
+
+void plat_arm_pwrc_setup(void)
+{
+ mhu_secure_init();
+}
diff --git a/plat/juno/mhu.h b/plat/arm/css/common/css_mhu.h
similarity index 95%
rename from plat/juno/mhu.h
rename to plat/arm/css/common/css_mhu.h
index 5149c82..c2e5327 100644
--- a/plat/juno/mhu.h
+++ b/plat/arm/css/common/css_mhu.h
@@ -28,8 +28,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __MHU_H__
-#define __MHU_H__
+#ifndef __CSS_MHU_H__
+#define __CSS_MHU_H__
#include <stdint.h>
@@ -40,4 +40,4 @@
extern void mhu_secure_init(void);
-#endif /* __MHU_H__ */
+#endif /* __CSS_MHU_H__ */
diff --git a/plat/juno/plat_pm.c b/plat/arm/css/common/css_pm.c
similarity index 67%
rename from plat/juno/plat_pm.c
rename to plat/arm/css/common/css_pm.c
index 953e5f7..7b0282e 100644
--- a/plat/juno/plat_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -32,20 +32,20 @@
#include <arch_helpers.h>
#include <arm_gic.h>
#include <cci.h>
+#include <css_def.h>
#include <debug.h>
#include <errno.h>
+#include <plat_arm.h>
#include <platform.h>
#include <platform_def.h>
#include <psci.h>
-#include "juno_def.h"
-#include "juno_private.h"
-#include "scpi.h"
+#include "css_scpi.h"
/*******************************************************************************
- * Private Juno function to program the mailbox for a cpu before it is released
+ * Private function to program the mailbox for a cpu before it is released
* from reset.
******************************************************************************/
-static void juno_program_mailbox(uint64_t mpidr, uint64_t address)
+static void css_program_mailbox(uint64_t mpidr, uint64_t address)
{
uint64_t linear_id;
uint64_t mbox;
@@ -57,63 +57,10 @@
}
/*******************************************************************************
- * Private Juno function which is used to determine if any platform actions
- * should be performed for the specified affinity instance given its
- * state. Nothing needs to be done if the 'state' is not off or if this is not
- * the highest affinity level which will enter the 'state'.
- ******************************************************************************/
-static int32_t juno_do_plat_actions(uint32_t afflvl, uint32_t state)
-{
- uint32_t max_phys_off_afflvl;
-
- assert(afflvl <= MPIDR_AFFLVL1);
-
- if (state != PSCI_STATE_OFF)
- return -EAGAIN;
-
- /*
- * Find the highest affinity level which will be suspended and postpone
- * all the platform specific actions until that level is hit.
- */
- max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
- assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
- assert(psci_get_suspend_afflvl() >= max_phys_off_afflvl);
- if (afflvl != max_phys_off_afflvl)
- return -EAGAIN;
-
- return 0;
-}
-
-/*******************************************************************************
- * Juno handler called to check the validity of the power state parameter.
- ******************************************************************************/
-int32_t juno_validate_power_state(unsigned int power_state)
-{
- /* Sanity check the requested state */
- if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
- /*
- * It's possible to enter standby only on affinity level 0 i.e.
- * a cpu on the Juno. Ignore any other affinity level.
- */
- if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
- return PSCI_E_INVALID_PARAMS;
- }
-
- /*
- * We expect the 'state id' to be zero.
- */
- if (psci_get_pstate_id(power_state))
- return PSCI_E_INVALID_PARAMS;
-
- return PSCI_E_SUCCESS;
-}
-
-
-/*******************************************************************************
- * Juno handler called when an affinity instance is about to be turned on. The
+ * Handler called when an affinity instance is about to be turned on. The
* level and mpidr determine the affinity instance.
******************************************************************************/
-int32_t juno_affinst_on(uint64_t mpidr,
+int32_t css_affinst_on(uint64_t mpidr,
uint64_t sec_entrypoint,
uint32_t afflvl,
uint32_t state)
@@ -128,7 +75,7 @@
/*
* Setup mailbox with address for CPU entrypoint when it next powers up
*/
- juno_program_mailbox(mpidr, sec_entrypoint);
+ css_program_mailbox(mpidr, sec_entrypoint);
scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on,
scpi_power_on);
@@ -137,18 +84,18 @@
}
/*******************************************************************************
- * Juno handler called when an affinity instance has just been powered on after
+ * Handler called when an affinity instance has just been powered on after
* being turned off earlier. The level and mpidr determine the affinity
* instance. The 'state' arg. allows the platform to decide whether the cluster
* was turned off prior to wakeup and do what's necessary to setup it up
* correctly.
******************************************************************************/
-void juno_affinst_on_finish(uint32_t afflvl, uint32_t state)
+void css_affinst_on_finish(uint32_t afflvl, uint32_t state)
{
unsigned long mpidr;
/* Determine if any platform actions need to be executed. */
- if (juno_do_plat_actions(afflvl, state) == -EAGAIN)
+ if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/* Get the mpidr for this cpu */
@@ -164,20 +111,20 @@
/* Enable the gic cpu interface */
arm_gic_cpuif_setup();
- /* Juno todo: Is this setup only needed after a cold boot? */
+ /* todo: Is this setup only needed after a cold boot? */
arm_gic_pcpu_distif_setup();
/* Clear the mailbox for this cpu. */
- juno_program_mailbox(mpidr, 0);
+ css_program_mailbox(mpidr, 0);
}
/*******************************************************************************
* Common function called while turning a cpu off or suspending it. It is called
- * from juno_off() or juno_suspend() when these functions in turn are called for
+ * from css_off() or css_suspend() when these functions in turn are called for
* the highest affinity level which will be powered down. It performs the
* actions common to the OFF and SUSPEND calls.
******************************************************************************/
-static void juno_power_down_common(uint32_t afflvl)
+static void css_power_down_common(uint32_t afflvl)
{
uint32_t cluster_state = scpi_power_on;
@@ -211,13 +158,13 @@
* global variables across calls. It will be wise to do flush a write to the
* global to prevent unpredictable results.
******************************************************************************/
-static void juno_affinst_off(uint32_t afflvl, uint32_t state)
+static void css_affinst_off(uint32_t afflvl, uint32_t state)
{
/* Determine if any platform actions need to be executed */
- if (juno_do_plat_actions(afflvl, state) == -EAGAIN)
+ if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
- juno_power_down_common(afflvl);
+ css_power_down_common(afflvl);
}
/*******************************************************************************
@@ -232,39 +179,39 @@
* global variables across calls. It will be wise to do flush a write to the
* global to prevent unpredictable results.
******************************************************************************/
-static void juno_affinst_suspend(uint64_t sec_entrypoint,
+static void css_affinst_suspend(uint64_t sec_entrypoint,
uint32_t afflvl,
uint32_t state)
{
/* Determine if any platform actions need to be executed */
- if (juno_do_plat_actions(afflvl, state) == -EAGAIN)
+ if (arm_do_affinst_actions(afflvl, state) == -EAGAIN)
return;
/*
* Setup mailbox with address for CPU entrypoint when it next powers up.
*/
- juno_program_mailbox(read_mpidr_el1(), sec_entrypoint);
+ css_program_mailbox(read_mpidr_el1(), sec_entrypoint);
- juno_power_down_common(afflvl);
+ css_power_down_common(afflvl);
}
/*******************************************************************************
- * Juno handler called when an affinity instance has just been powered on after
+ * Handler called when an affinity instance has just been powered on after
* having been suspended earlier. The level and mpidr determine the affinity
* instance.
* TODO: At the moment we reuse the on finisher and reinitialize the secure
* context. Need to implement a separate suspend finisher.
******************************************************************************/
-static void juno_affinst_suspend_finish(uint32_t afflvl,
+static void css_affinst_suspend_finish(uint32_t afflvl,
uint32_t state)
{
- juno_affinst_on_finish(afflvl, state);
+ css_affinst_on_finish(afflvl, state);
}
/*******************************************************************************
- * Juno handlers to shutdown/reboot the system
+ * Handlers to shutdown/reboot the system
******************************************************************************/
-static void __dead2 juno_system_off(void)
+static void __dead2 css_system_off(void)
{
uint32_t response;
@@ -272,15 +219,15 @@
response = scpi_sys_power_state(scpi_system_shutdown);
if (response != SCP_OK) {
- ERROR("Juno System Off: SCP error %u.\n", response);
+ ERROR("CSS System Off: SCP error %u.\n", response);
panic();
}
wfi();
- ERROR("Juno System Off: operation not handled.\n");
+ ERROR("CSS System Off: operation not handled.\n");
panic();
}
-static void __dead2 juno_system_reset(void)
+static void __dead2 css_system_reset(void)
{
uint32_t response;
@@ -288,18 +235,18 @@
response = scpi_sys_power_state(scpi_system_reboot);
if (response != SCP_OK) {
- ERROR("Juno System Reset: SCP error %u.\n", response);
+ ERROR("CSS System Reset: SCP error %u.\n", response);
panic();
}
wfi();
- ERROR("Juno System Reset: operation not handled.\n");
+ ERROR("CSS System Reset: operation not handled.\n");
panic();
}
/*******************************************************************************
* Handler called when an affinity instance is about to enter standby.
******************************************************************************/
-void juno_affinst_standby(unsigned int power_state)
+void css_affinst_standby(unsigned int power_state)
{
unsigned int scr;
@@ -320,16 +267,16 @@
/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
-static const plat_pm_ops_t juno_ops = {
- .affinst_on = juno_affinst_on,
- .affinst_on_finish = juno_affinst_on_finish,
- .affinst_off = juno_affinst_off,
- .affinst_standby = juno_affinst_standby,
- .affinst_suspend = juno_affinst_suspend,
- .affinst_suspend_finish = juno_affinst_suspend_finish,
- .system_off = juno_system_off,
- .system_reset = juno_system_reset,
- .validate_power_state = juno_validate_power_state
+static const plat_pm_ops_t css_ops = {
+ .affinst_on = css_affinst_on,
+ .affinst_on_finish = css_affinst_on_finish,
+ .affinst_off = css_affinst_off,
+ .affinst_standby = css_affinst_standby,
+ .affinst_suspend = css_affinst_suspend,
+ .affinst_suspend_finish = css_affinst_suspend_finish,
+ .system_off = css_system_off,
+ .system_reset = css_system_reset,
+ .validate_power_state = arm_validate_power_state
};
/*******************************************************************************
@@ -337,6 +284,6 @@
******************************************************************************/
int32_t platform_setup_pm(const plat_pm_ops_t **plat_ops)
{
- *plat_ops = &juno_ops;
+ *plat_ops = &css_ops;
return 0;
}
diff --git a/plat/juno/scp_bootloader.c b/plat/arm/css/common/css_scp_bootloader.c
similarity index 97%
rename from plat/juno/scp_bootloader.c
rename to plat/arm/css/common/css_scp_bootloader.c
index a6d25d4..b0bd417 100644
--- a/plat/juno/scp_bootloader.c
+++ b/plat/arm/css/common/css_scp_bootloader.c
@@ -29,11 +29,11 @@
*/
#include <arch_helpers.h>
+#include <css_def.h>
#include <platform.h>
-#include "juno_def.h"
-#include "mhu.h"
-#include "scp_bootloader.h"
-#include "scpi.h"
+#include "css_mhu.h"
+#include "css_scp_bootloader.h"
+#include "css_scpi.h"
/* Boot commands sent from AP -> SCP */
#define BOOT_CMD_START 0x01
diff --git a/plat/juno/scp_bootloader.h b/plat/arm/css/common/css_scp_bootloader.h
similarity index 93%
rename from plat/juno/scp_bootloader.h
rename to plat/arm/css/common/css_scp_bootloader.h
index e872513..07b8972 100644
--- a/plat/juno/scp_bootloader.h
+++ b/plat/arm/css/common/css_scp_bootloader.h
@@ -28,9 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __SCP_BOOTLOADER_H__
-#define __SCP_BOOTLOADER_H__
+#ifndef __CSS_SCP_BOOTLOADER_H__
+#define __CSS_SCP_BOOTLOADER_H__
int scp_bootloader_transfer(void *image, unsigned int image_size);
-#endif
+#endif /* __CSS_SCP_BOOTLOADER_H__ */
diff --git a/plat/juno/scpi.c b/plat/arm/css/common/css_scpi.c
similarity index 97%
rename from plat/juno/scpi.c
rename to plat/arm/css/common/css_scpi.c
index 950c00b..5bfa2cf 100644
--- a/plat/juno/scpi.c
+++ b/plat/arm/css/common/css_scpi.c
@@ -29,10 +29,10 @@
*/
#include <arch_helpers.h>
+#include <css_def.h>
#include <platform.h>
-#include "juno_def.h"
-#include "mhu.h"
-#include "scpi.h"
+#include "css_mhu.h"
+#include "css_scpi.h"
#define MHU_SECURE_SCP_TO_AP_PAYLOAD (MHU_SECURE_BASE+0x0080)
#define MHU_SECURE_AP_TO_SCP_PAYLOAD (MHU_SECURE_BASE+0x0280)
diff --git a/plat/juno/scpi.h b/plat/arm/css/common/css_scpi.h
similarity index 88%
rename from plat/juno/scpi.h
rename to plat/arm/css/common/css_scpi.h
index 8a5ef65..965b36f 100644
--- a/plat/juno/scpi.h
+++ b/plat/arm/css/common/css_scpi.h
@@ -28,15 +28,16 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __SCPI_H__
-#define __SCPI_H__
+#ifndef __CSS_SCPI_H__
+#define __CSS_SCPI_H__
#include <stddef.h>
#include <stdint.h>
extern void *scpi_secure_message_start(void);
extern void scpi_secure_message_send(unsigned command, size_t size);
-extern unsigned scpi_secure_message_receive(void **message_out, size_t *size_out);
+extern unsigned scpi_secure_message_receive(void **message_out,
+ size_t *size_out);
extern void scpi_secure_message_end(void);
@@ -75,8 +76,11 @@
} scpi_system_state_t;
extern int scpi_wait_ready(void);
-extern void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state,
- scpi_power_state_t cluster_state, scpi_power_state_t css_state);
+extern void scpi_set_css_power_state(unsigned mpidr,
+ scpi_power_state_t cpu_state,
+ scpi_power_state_t cluster_state,
+ scpi_power_state_t css_state);
uint32_t scpi_sys_power_state(scpi_system_state_t system_state);
-#endif /* __SCPI_H__ */
+
+#endif /* __CSS_SCPI_H__ */
diff --git a/plat/juno/tsp/tsp-juno.mk b/plat/arm/soc/common/soc_css.mk
similarity index 80%
copy from plat/juno/tsp/tsp-juno.mk
copy to plat/arm/soc/common/soc_css.mk
index 4d56ea2..fd51b7f 100644
--- a/plat/juno/tsp/tsp-juno.mk
+++ b/plat/arm/soc/common/soc_css.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -28,10 +28,13 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-# TSP source files specific to Juno platform
-BL32_SOURCES += drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/juno/aarch64/juno_common.c \
- plat/juno/aarch64/plat_helpers.S \
- plat/juno/tsp/tsp_plat_setup.c
+PLAT_INCLUDES += -Iinclude/plat/arm/soc/common/
+
+#PLAT_BL_COMMON_SOURCES +=
+
+
+#BL1_SOURCES +=
+
+BL2_SOURCES += plat/arm/soc/common/soc_css_security.c
+
+#BL31_SOURCES +=
diff --git a/plat/arm/soc/common/soc_css_security.c b/plat/arm/soc/common/soc_css_security.c
new file mode 100644
index 0000000..36f59ea
--- /dev/null
+++ b/plat/arm/soc/common/soc_css_security.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <board_css_def.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <soc_css_def.h>
+
+/*
+ * Address of slave 'n' security setting in the NIC-400 address region
+ * control
+ * TODO: Ideally this macro should be moved in a "nic-400.h" header file but
+ * it would be the only thing in there so it's not worth it at the moment.
+ */
+#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4)
+
+void soc_css_init_nic400(void)
+{
+ /*
+ * NIC-400 Access Control Initialization
+ *
+ * Define access privileges by setting each corresponding bit to:
+ * 0 = Secure access only
+ * 1 = Non-secure access allowed
+ */
+
+ /*
+ * Allow non-secure access to some SOC regions, excluding UART1, which
+ * remains secure.
+ * Note: This is the NIC-400 device on the SOC
+ */
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0);
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0);
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0);
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
+ mmio_write_32(SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
+ ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
+
+ /*
+ * Allow non-secure access to some CSS regions.
+ * Note: This is the NIC-400 device on the CSS
+ */
+ mmio_write_32(PLAT_SOC_CSS_NIC400_BASE +
+ NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
+ ~0);
+}
+
+
+#define PCIE_SECURE_REG 0x3000
+/* Mask uses REG and MEM access bits */
+#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1))
+
+void soc_css_init_pcie(void)
+{
+#if !PLAT_juno
+ /*
+ * Do not initialize PCIe in emulator environment.
+ * Platform ID register not supported on Juno
+ */
+ if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) ==
+ BOARD_CSS_PLAT_TYPE_EMULATOR)
+ return;
+#endif /* PLAT_juno */
+
+ /*
+ * PCIE Root Complex Security settings to enable non-secure
+ * access to config registers.
+ */
+ mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG,
+ PCIE_SEC_ACCESS_MASK);
+}
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
deleted file mode 100644
index a8afb4e..0000000
--- a/plat/fvp/aarch64/fvp_common.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <arm_gic.h>
-#include <bl_common.h>
-#include <cci.h>
-#include <debug.h>
-#include <mmio.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <plat_config.h>
-#include <xlat_tables.h>
-#include "../fvp_def.h"
-
-/*******************************************************************************
- * plat_config holds the characteristics of the differences between the three
- * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
- * boot at each boot stage by the primary before enabling the MMU (to allow cci
- * configuration) & used thereafter. Each BL will have its own copy to allow
- * independent operation.
- ******************************************************************************/
-plat_config_t plat_config;
-
-#define MAP_SHARED_RAM MAP_REGION_FLAT(FVP_SHARED_MEM_BASE, \
- FVP_SHARED_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
- FLASH0_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
-
-#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
- DEVICE0_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
- DEVICE1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
- DRAM1_NS_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
-
-#define MAP_TSP_SEC_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
- TSP_SEC_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-/*
- * Table of regions for various BL stages to map using the MMU.
- * This doesn't include TZRAM as the 'mem_layout' argument passed to
- * configure_mmu_elx() will give the available subset of that,
- */
-#if IMAGE_BL1
-const mmap_region_t fvp_mmap[] = {
- MAP_SHARED_RAM,
- MAP_FLASH0,
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-#if IMAGE_BL2
-const mmap_region_t fvp_mmap[] = {
- MAP_SHARED_RAM,
- MAP_FLASH0,
- MAP_DEVICE0,
- MAP_DEVICE1,
- MAP_DRAM1_NS,
- MAP_TSP_SEC_MEM,
- {0}
-};
-#endif
-#if IMAGE_BL31
-const mmap_region_t fvp_mmap[] = {
- MAP_SHARED_RAM,
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-#if IMAGE_BL32
-const mmap_region_t fvp_mmap[] = {
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-
-CASSERT(ARRAY_SIZE(fvp_mmap) + FVP_BL_REGIONS \
- <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
-
-/* Array of secure interrupts to be configured by the gic driver */
-const unsigned int irq_sec_array[] = {
- IRQ_TZ_WDOG,
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0,
- IRQ_SEC_SGI_1,
- IRQ_SEC_SGI_2,
- IRQ_SEC_SGI_3,
- IRQ_SEC_SGI_4,
- IRQ_SEC_SGI_5,
- IRQ_SEC_SGI_6,
- IRQ_SEC_SGI_7
-};
-
-/*******************************************************************************
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- ******************************************************************************/
-#if USE_COHERENT_MEM
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void fvp_configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit, \
- unsigned long coh_start, \
- unsigned long coh_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add_region(coh_start, coh_start, \
- coh_limit - coh_start, \
- MT_DEVICE | MT_RW | MT_SECURE); \
- mmap_add(fvp_mmap); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#else
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void fvp_configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add(fvp_mmap); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#endif
-
-/* Define EL1 and EL3 variants of the function initialising the MMU */
-DEFINE_CONFIGURE_MMU_EL(1)
-DEFINE_CONFIGURE_MMU_EL(3)
-
-/*******************************************************************************
- * A single boot loader stack is expected to work on both the Foundation FVP
- * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
- * SYS_ID register provides a mechanism for detecting the differences between
- * these platforms. This information is stored in a per-BL array to allow the
- * code to take the correct path.Per BL platform configuration.
- ******************************************************************************/
-int fvp_config_setup(void)
-{
- unsigned int rev, hbi, bld, arch, sys_id;
-
- sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
- rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
- hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
- bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
- arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
-
- if (arch != ARCH_MODEL) {
- ERROR("This firmware is for FVP models\n");
- panic();
- }
-
- /*
- * The build field in the SYS_ID tells which variant of the GIC
- * memory is implemented by the model.
- */
- switch (bld) {
- case BLD_GIC_VE_MMAP:
- plat_config.gicd_base = VE_GICD_BASE;
- plat_config.gicc_base = VE_GICC_BASE;
- plat_config.gich_base = VE_GICH_BASE;
- plat_config.gicv_base = VE_GICV_BASE;
- break;
- case BLD_GIC_A53A57_MMAP:
- plat_config.gicd_base = BASE_GICD_BASE;
- plat_config.gicc_base = BASE_GICC_BASE;
- plat_config.gich_base = BASE_GICH_BASE;
- plat_config.gicv_base = BASE_GICV_BASE;
- break;
- default:
- ERROR("Unsupported board build %x\n", bld);
- panic();
- }
-
- /*
- * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
- * for the Foundation FVP.
- */
- switch (hbi) {
- case HBI_FOUNDATION:
- plat_config.max_aff0 = 4;
- plat_config.max_aff1 = 1;
- plat_config.flags = 0;
-
- /*
- * Check for supported revisions of Foundation FVP
- * Allow future revisions to run but emit warning diagnostic
- */
- switch (rev) {
- case REV_FOUNDATION_V2_0:
- case REV_FOUNDATION_V2_1:
- break;
- default:
- WARN("Unrecognized Foundation FVP revision %x\n", rev);
- break;
- }
- break;
- case HBI_FVP_BASE:
- plat_config.max_aff0 = 4;
- plat_config.max_aff1 = 2;
- plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
- CONFIG_HAS_TZC;
-
- /*
- * Check for supported revisions
- * Allow future revisions to run but emit warning diagnostic
- */
- switch (rev) {
- case REV_FVP_BASE_V0:
- break;
- default:
- WARN("Unrecognized Base FVP revision %x\n", rev);
- break;
- }
- break;
- default:
- ERROR("Unsupported board HBI number 0x%x\n", hbi);
- panic();
- }
-
- return 0;
-}
-
-unsigned long plat_get_ns_image_entrypoint(void)
-{
- return NS_IMAGE_OFFSET;
-}
-
-uint64_t plat_get_syscnt_freq(void)
-{
- uint64_t counter_base_frequency;
-
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
-
- /* The first entry of the frequency modes table must not be 0 */
- if (counter_base_frequency == 0)
- panic();
-
- return counter_base_frequency;
-}
-
-/* Map of CCI masters with the slave interfaces they are connected */
-static const int cci_map[] = {
- CCI400_CLUSTER0_SL_IFACE_IX,
- CCI400_CLUSTER1_SL_IFACE_IX
-};
-
-void fvp_cci_init(void)
-{
- /*
- * Initialize CCI-400 driver
- */
- if (plat_config.flags & CONFIG_HAS_CCI)
- cci_init(CCI400_BASE,
- cci_map,
- ARRAY_SIZE(cci_map));
-}
-
-void fvp_cci_enable(void)
-{
- if (plat_config.flags & CONFIG_HAS_CCI)
- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-}
-
-void fvp_cci_disable(void)
-{
- if (plat_config.flags & CONFIG_HAS_CCI)
- cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-}
-
-void fvp_gic_init(void)
-{
- arm_gic_init(plat_config.gicc_base,
- plat_config.gicd_base,
- BASE_GICR_BASE,
- irq_sec_array,
- ARRAY_SIZE(irq_sec_array));
-}
-
-
-/*******************************************************************************
- * Gets SPSR for BL32 entry
- ******************************************************************************/
-uint32_t fvp_get_spsr_for_bl32_entry(void)
-{
- /*
- * The Secure Payload Dispatcher service is responsible for
- * setting the SPSR prior to entry into the BL32 image.
- */
- return 0;
-}
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-uint32_t fvp_get_spsr_for_bl33_entry(void)
-{
- unsigned long el_status;
- unsigned int mode;
- uint32_t spsr;
-
- /* Figure out what mode we enter the non-secure world in */
- el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
- el_status &= ID_AA64PFR0_ELX_MASK;
-
- if (el_status)
- mode = MODE_EL2;
- else
- mode = MODE_EL1;
-
- /*
- * TODO: Consider the possibility of specifying the SPSR in
- * the FIP ToC and allowing the platform to have a say as
- * well.
- */
- spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
- return spsr;
-}
diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c
deleted file mode 100644
index 364833f..0000000
--- a/plat/fvp/bl2_fvp_setup.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <console.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <string.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
-
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __RO_END__;
-
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
-
-/*
- * The next 2 constants identify the extents of the code & RO data region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
- */
-#define BL2_RO_BASE (unsigned long)(&__RO_START__)
-#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-/* Data structure which holds the extents of the trusted SRAM for BL2 */
-static meminfo_t bl2_tzram_layout
-__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE)));
-
-/* Assert that BL3-1 parameters fit in shared memory */
-CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
- (FVP_SHARED_MEM_BASE + FVP_SHARED_MEM_SIZE),
- assert_bl31_params_do_not_fit_in_shared_memory);
-
-/*******************************************************************************
- * Reference to structures which holds the arguments which need to be passed
- * to BL31
- ******************************************************************************/
-static bl31_params_t *bl2_to_bl31_params;
-static entry_point_info_t *bl31_ep_info;
-
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
- return &bl2_tzram_layout;
-}
-
-/*******************************************************************************
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem_t structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- ******************************************************************************/
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
- bl2_to_bl31_params_mem_t *bl31_params_mem;
-
- /*
- * Allocate the memory for all the arguments that needs to
- * be passed to BL31
- */
- bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
- memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t));
-
- /* Assign memory for TF related information */
- bl2_to_bl31_params = &bl31_params_mem->bl31_params;
- SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
- /* Fill BL31 related information */
- bl31_ep_info = &bl31_params_mem->bl31_ep_info;
- bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- /* Fill BL32 related information if it exists */
- if (BL32_BASE) {
- bl2_to_bl31_params->bl32_ep_info =
- &bl31_params_mem->bl32_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info,
- PARAM_EP, VERSION_1, 0);
- bl2_to_bl31_params->bl32_image_info =
- &bl31_params_mem->bl32_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
- PARAM_IMAGE_BINARY,
- VERSION_1, 0);
- }
-
- /* Fill BL33 related information */
- bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
- PARAM_EP, VERSION_1, 0);
- bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- return bl2_to_bl31_params;
-}
-
-
-/*******************************************************************************
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- ******************************************************************************/
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
- bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL;
-#endif
- return bl31_ep_info;
-}
-
-
-/*******************************************************************************
- * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
- * in x0. This memory layout is sitting at the base of the free trusted SRAM.
- * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
- ******************************************************************************/
-void bl2_early_platform_setup(meminfo_t *mem_layout)
-{
- /* Initialize the console to provide early debug support */
- console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
-
- /* Setup the BL2 memory layout */
- bl2_tzram_layout = *mem_layout;
-
- /* Initialize the platform config for future decision making */
- fvp_config_setup();
-
- /* Initialise the IO layer and register platform IO devices */
- fvp_io_setup();
-}
-
-/*******************************************************************************
- * Perform platform specific setup. For now just initialize the memory location
- * to use for passing arguments to BL31.
- ******************************************************************************/
-void bl2_platform_setup(void)
-{
- /*
- * Do initial security configuration to allow DRAM/device access. On
- * Base FVP only DRAM security is programmable (via TrustZone), but
- * other platforms might have more programmable security devices
- * present.
- */
- fvp_security_setup();
-}
-
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
-{
- flush_dcache_range((unsigned long)PARAMS_BASE, \
- sizeof(bl2_to_bl31_params_mem_t));
-}
-
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
- ******************************************************************************/
-void bl2_plat_arch_setup(void)
-{
- fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
- bl2_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT
-#if USE_COHERENT_MEM
- , BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT
-#endif
- );
-}
-
-/*******************************************************************************
- * Before calling this function BL31 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
- entry_point_info_t *bl31_ep_info)
-{
- SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
- bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
-}
-
-
-/*******************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
- entry_point_info_t *bl32_ep_info)
-{
- SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
- bl32_ep_info->spsr = fvp_get_spsr_for_bl32_entry();
-}
-
-/*******************************************************************************
- * Before calling this function BL33 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
- entry_point_info_t *bl33_ep_info)
-{
- SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
- bl33_ep_info->spsr = fvp_get_spsr_for_bl33_entry();
-}
-
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
- /*
- * Populate the extents of memory available for loading BL32.
- */
- bl32_meminfo->total_base = BL32_BASE;
- bl32_meminfo->free_base = BL32_BASE;
- bl32_meminfo->total_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
- bl32_meminfo->free_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-}
-
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL33
- ******************************************************************************/
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
- bl33_meminfo->total_base = DRAM1_NS_BASE;
- bl33_meminfo->total_size = DRAM1_NS_SIZE;
- bl33_meminfo->free_base = DRAM1_NS_BASE;
- bl33_meminfo->free_size = DRAM1_NS_SIZE;
-}
diff --git a/plat/fvp/bl31_fvp_setup.c b/plat/fvp/bl31_fvp_setup.c
deleted file mode 100644
index 3874413..0000000
--- a/plat/fvp/bl31_fvp_setup.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <arm_gic.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <bl31.h>
-#include <console.h>
-#include <mmio.h>
-#include <platform.h>
-#include <stddef.h>
-#include "drivers/pwrc/fvp_pwrc.h"
-#include "fvp_def.h"
-#include "fvp_private.h"
-
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __RO_END__;
-extern unsigned long __BL31_END__;
-
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
-
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL3-1 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-#define BL31_END (unsigned long)(&__BL31_END__)
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-#if RESET_TO_BL31
-static entry_point_info_t bl32_image_ep_info;
-static entry_point_info_t bl33_image_ep_info;
-#else
-/*******************************************************************************
- * Reference to structure which holds the arguments that have been passed to
- * BL31 from BL2.
- ******************************************************************************/
-static bl31_params_t *bl2_to_bl31_params;
-#endif
-
-/*******************************************************************************
- * Return a pointer to the 'entry_point_info' structure of the next image for the
- * security state specified. BL33 corresponds to the non-secure image type
- * while BL32 corresponds to the secure image type. A NULL pointer is returned
- * if the image does not exist.
- ******************************************************************************/
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
-#if RESET_TO_BL31
- assert(sec_state_is_valid(type));
-
- if (type == NON_SECURE)
- return &bl33_image_ep_info;
- else
- return &bl32_image_ep_info;
-#else
- entry_point_info_t *next_image_info;
-
- assert(sec_state_is_valid(type));
-
- next_image_info = (type == NON_SECURE) ?
- bl2_to_bl31_params->bl33_ep_info :
- bl2_to_bl31_params->bl32_ep_info;
-
- /* None of the images on this platform can have 0x0 as the entrypoint */
- if (next_image_info->pc)
- return next_image_info;
- else
- return NULL;
-#endif
-}
-
-/*******************************************************************************
- * Perform any BL31 specific platform actions. Here is an opportunity to copy
- * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
- * are lost (potentially). This needs to be done before the MMU is initialized
- * so that the memory layout can be used while creating page tables. On the FVP
- * we know that BL2 has populated the parameters in secure DRAM. So we just use
- * the reference passed in 'from_bl2' instead of copying. The 'data' parameter
- * is not used since all the information is contained in 'from_bl2'. Also, BL2
- * has flushed this information to memory, so we are guaranteed to pick up good
- * data
- ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
-{
- /* Initialize the console to provide early debug support */
- console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
-
- /* Initialize the platform config for future decision making */
- fvp_config_setup();
-
-#if RESET_TO_BL31
- /* There are no parameters from BL2 if BL31 is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
-
- /*
- * Do initial security configuration to allow DRAM/device access. On
- * Base FVP only DRAM security is programmable (via TrustZone), but
- * other platforms might have more programmable security devices
- * present.
- */
- fvp_security_setup();
-
- /* Populate entry point information for BL3-2 and BL3-3 */
- SET_PARAM_HEAD(&bl32_image_ep_info,
- PARAM_EP,
- VERSION_1,
- 0);
- SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
- bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry();
-
- SET_PARAM_HEAD(&bl33_image_ep_info,
- PARAM_EP,
- VERSION_1,
- 0);
- /*
- * Tell BL31 where the non-trusted software image
- * is located and the entry state information
- */
- bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
- bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry();
- SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-
-#else
- /* Check params passed from BL2 should not be NULL,
- * We are not checking plat_params_from_bl2 as NULL as we are not
- * using it on FVP
- */
- assert(from_bl2 != NULL);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
-
- bl2_to_bl31_params = from_bl2;
- assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL);
-#endif
-}
-
-/*******************************************************************************
- * Initialize the gic, configure the CLCD and zero out variables needed by the
- * secondaries to boot up correctly.
- ******************************************************************************/
-void bl31_platform_setup(void)
-{
- unsigned int reg_val;
-
- /* Initialize the gic cpu and distributor interfaces */
- fvp_gic_init();
- arm_gic_setup();
-
- /*
- * TODO: Configure the CLCD before handing control to
- * linux. Need to see if a separate driver is needed
- * instead.
- */
- mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
- mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
- (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
-
- /* Enable and initialize the System level generic timer */
- mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
-
- /* Allow access to the System counter timer module */
- reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
- reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
- reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
-
- reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
- mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
-
- /* Intialize the power controller */
- fvp_pwrc_setup();
-
- /* Topologies are best known to the platform. */
- fvp_setup_topology();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
- ******************************************************************************/
-void bl31_plat_arch_setup(void)
-{
- fvp_cci_init();
-#if RESET_TO_BL31
- fvp_cci_enable();
-#endif
- fvp_configure_mmu_el3(BL31_RO_BASE,
- (BL31_END - BL31_RO_BASE),
- BL31_RO_BASE,
- BL31_RO_LIMIT
-#if USE_COHERENT_MEM
- , BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT
-#endif
- );
-}
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
deleted file mode 100644
index a2f2da8..0000000
--- a/plat/fvp/fvp_def.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __FVP_DEF_H__
-#define __FVP_DEF_H__
-
-/* Firmware Image Package */
-#define FIP_IMAGE_NAME "fip.bin"
-#define FVP_PRIMARY_CPU 0x0
-
-/* Memory location options for TSP */
-#define FVP_TRUSTED_SRAM_ID 0
-#define FVP_TRUSTED_DRAM_ID 1
-#define FVP_DRAM_ID 2
-
-/*
- * Some of the definitions in this file use the 'ull' suffix in order to avoid
- * subtle integer overflow errors due to implicit integer type promotion when
- * working with 32-bit values.
- *
- * The TSP linker script includes some of these definitions to define the BL3-2
- * memory map, but the GNU LD does not support the 'ull' suffix, causing the
- * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
- * will add the 'ull' suffix only when the macro __LINKER__ is not defined
- * (__LINKER__ is defined in the command line to preprocess the linker script).
- * Constants in the linker script will not have the 'ull' suffix, but this is
- * not a problem since the linker evaluates all constant expressions to 64 bit
- * (assuming the target architecture is 64 bit).
- */
-#ifndef __LINKER__
- #define MAKE_ULL(x) x##ull
-#else
- #define MAKE_ULL(x) x
-#endif
-
-/*******************************************************************************
- * FVP memory map related constants
- ******************************************************************************/
-
-#define FVP_TRUSTED_ROM_BASE 0x00000000
-#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
-
-/* The first 4KB of Trusted SRAM are used as shared memory */
-#define FVP_SHARED_MEM_BASE 0x04000000
-#define FVP_SHARED_MEM_SIZE 0x00001000 /* 4 KB */
-
-/* The remaining Trusted SRAM is used to load the BL images */
-#define FVP_TRUSTED_SRAM_BASE 0x04001000
-#define FVP_TRUSTED_SRAM_SIZE 0x0003F000 /* 252 KB */
-
-#define FVP_TRUSTED_DRAM_BASE 0x06000000
-#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
-
-#define FLASH0_BASE 0x08000000
-#define FLASH0_SIZE 0x04000000
-
-#define FLASH1_BASE 0x0c000000
-#define FLASH1_SIZE 0x04000000
-
-#define PSRAM_BASE 0x14000000
-#define PSRAM_SIZE 0x04000000
-
-#define VRAM_BASE 0x18000000
-#define VRAM_SIZE 0x02000000
-
-/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE 0x1a000000
-#define DEVICE0_SIZE 0x12200000
-
-#define DEVICE1_BASE 0x2f000000
-#define DEVICE1_SIZE 0x200000
-
-#define NSRAM_BASE 0x2e000000
-#define NSRAM_SIZE 0x10000
-
-#define DRAM1_BASE MAKE_ULL(0x80000000)
-#define DRAM1_SIZE MAKE_ULL(0x80000000)
-#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
-
-/* Define the top 16 MB of DRAM1 as secure */
-#define DRAM1_SEC_SIZE MAKE_ULL(0x01000000)
-#define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE)
-#define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1)
-
-#define DRAM1_NS_BASE DRAM1_BASE
-#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE)
-#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1)
-
-#define DRAM_BASE DRAM1_BASE
-#define DRAM_SIZE DRAM1_SIZE
-
-#define DRAM2_BASE MAKE_ULL(0x880000000)
-#define DRAM2_SIZE MAKE_ULL(0x780000000)
-#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
-
-#define PCIE_EXP_BASE 0x40000000
-#define TZRNG_BASE 0x7fe60000
-#define TZNVCTR_BASE 0x7fe70000
-#define TZROOTKEY_BASE 0x7fe80000
-
-/* Memory mapped Generic timer interfaces */
-#define SYS_CNTCTL_BASE 0x2a430000
-#define SYS_CNTREAD_BASE 0x2a800000
-#define SYS_TIMCTL_BASE 0x2a810000
-
-/* V2M motherboard system registers & offsets */
-#define VE_SYSREGS_BASE 0x1c010000
-#define V2M_SYS_ID 0x0
-#define V2M_SYS_SWITCH 0x4
-#define V2M_SYS_LED 0x8
-#define V2M_SYS_CFGDATA 0xa0
-#define V2M_SYS_CFGCTRL 0xa4
-#define V2M_SYS_CFGSTATUS 0xa8
-
-#define CFGCTRL_START (1 << 31)
-#define CFGCTRL_RW (1 << 30)
-#define CFGCTRL_FUNC_SHIFT 20
-#define CFGCTRL_FUNC(fn) (fn << CFGCTRL_FUNC_SHIFT)
-#define FUNC_CLK_GEN 0x01
-#define FUNC_TEMP 0x04
-#define FUNC_DB_RESET 0x05
-#define FUNC_SCC_CFG 0x06
-#define FUNC_SHUTDOWN 0x08
-#define FUNC_REBOOT 0x09
-
-/*
- * The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU.
- */
-#if USE_COHERENT_MEM
-#define FVP_BL_REGIONS 3
-#else
-#define FVP_BL_REGIONS 2
-#endif
-
-/*
- * The FVP_MAX_MMAP_REGIONS depend on the number of entries in fvp_mmap[]
- * defined for each BL stage in fvp_common.c.
- */
-#if IMAGE_BL1
-#define FVP_MMAP_ENTRIES 5
-#endif
-#if IMAGE_BL2
-#define FVP_MMAP_ENTRIES 7
-#endif
-#if IMAGE_BL31
-#define FVP_MMAP_ENTRIES 4
-#endif
-#if IMAGE_BL32
-#define FVP_MMAP_ENTRIES 3
-#endif
-
-/* Load address of BL33 in the FVP port */
-#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
-
-/* Special value used to verify platform parameters from BL2 to BL3-1 */
-#define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
-
-/*
- * V2M sysled bit definitions. The values written to this
- * register are defined in arch.h & runtime_svc.h. Only
- * used by the primary cpu to diagnose any cold boot issues.
- *
- * SYS_LED[0] - Security state (S=0/NS=1)
- * SYS_LED[2:1] - Exception Level (EL3-EL0)
- * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
- *
- */
-#define SYS_LED_SS_SHIFT 0x0
-#define SYS_LED_EL_SHIFT 0x1
-#define SYS_LED_EC_SHIFT 0x3
-
-#define SYS_LED_SS_MASK 0x1
-#define SYS_LED_EL_MASK 0x3
-#define SYS_LED_EC_MASK 0x1f
-
-/* V2M sysid register bits */
-#define SYS_ID_REV_SHIFT 28
-#define SYS_ID_HBI_SHIFT 16
-#define SYS_ID_BLD_SHIFT 12
-#define SYS_ID_ARCH_SHIFT 8
-#define SYS_ID_FPGA_SHIFT 0
-
-#define SYS_ID_REV_MASK 0xf
-#define SYS_ID_HBI_MASK 0xfff
-#define SYS_ID_BLD_MASK 0xf
-#define SYS_ID_ARCH_MASK 0xf
-#define SYS_ID_FPGA_MASK 0xff
-
-#define SYS_ID_BLD_LENGTH 4
-
-#define HBI_FVP_BASE 0x020
-#define REV_FVP_BASE_V0 0x0
-
-#define HBI_FOUNDATION 0x010
-#define REV_FOUNDATION_V2_0 0x0
-#define REV_FOUNDATION_V2_1 0x1
-
-#define BLD_GIC_VE_MMAP 0x0
-#define BLD_GIC_A53A57_MMAP 0x1
-
-#define ARCH_MODEL 0x1
-
-/* FVP Power controller base address*/
-#define PWRC_BASE 0x1c100000
-
-
-/*******************************************************************************
- * CCI-400 related constants
- ******************************************************************************/
-#define CCI400_BASE 0x2c090000
-#define CCI400_CLUSTER0_SL_IFACE_IX 3
-#define CCI400_CLUSTER1_SL_IFACE_IX 4
-
-/*******************************************************************************
- * GIC-400 & interrupt handling related constants
- ******************************************************************************/
-/* VE compatible GIC memory map */
-#define VE_GICD_BASE 0x2c001000
-#define VE_GICC_BASE 0x2c002000
-#define VE_GICH_BASE 0x2c004000
-#define VE_GICV_BASE 0x2c006000
-
-/* Base FVP compatible GIC memory map */
-#define BASE_GICD_BASE 0x2f000000
-#define BASE_GICR_BASE 0x2f100000
-#define BASE_GICC_BASE 0x2c000000
-#define BASE_GICH_BASE 0x2c010000
-#define BASE_GICV_BASE 0x2c02f000
-
-#define IRQ_TZ_WDOG 56
-#define IRQ_SEC_PHY_TIMER 29
-#define IRQ_SEC_SGI_0 8
-#define IRQ_SEC_SGI_1 9
-#define IRQ_SEC_SGI_2 10
-#define IRQ_SEC_SGI_3 11
-#define IRQ_SEC_SGI_4 12
-#define IRQ_SEC_SGI_5 13
-#define IRQ_SEC_SGI_6 14
-#define IRQ_SEC_SGI_7 15
-
-/*******************************************************************************
- * PL011 related constants
- ******************************************************************************/
-#define PL011_UART0_BASE 0x1c090000
-#define PL011_UART1_BASE 0x1c0a0000
-#define PL011_UART2_BASE 0x1c0b0000
-#define PL011_UART3_BASE 0x1c0c0000
-
-#define PL011_BAUDRATE 115200
-
-#define PL011_UART0_CLK_IN_HZ 24000000
-#define PL011_UART1_CLK_IN_HZ 24000000
-#define PL011_UART2_CLK_IN_HZ 24000000
-#define PL011_UART3_CLK_IN_HZ 24000000
-
-/*******************************************************************************
- * TrustZone address space controller related constants
- ******************************************************************************/
-#define TZC400_BASE 0x2a4a0000
-
-/*
- * The NSAIDs for this platform as used to program the TZC400.
- */
-
-/* NSAIDs used by devices in TZC filter 0 on FVP */
-#define FVP_NSAID_DEFAULT 0
-#define FVP_NSAID_PCI 1
-#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
-#define FVP_NSAID_AP 9 /* Application Processors */
-#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
-
-/* NSAIDs used by devices in TZC filter 2 on FVP */
-#define FVP_NSAID_HDLCD0 2
-#define FVP_NSAID_CLCD 7
-
-/*******************************************************************************
- * Shared Data
- ******************************************************************************/
-
-/* Entrypoint mailboxes */
-#define MBOX_BASE FVP_SHARED_MEM_BASE
-#define MBOX_SIZE 0x200
-
-/* Base address where parameters to BL31 are stored */
-#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
-
-#endif /* __FVP_DEF_H__ */
diff --git a/plat/fvp/fvp_io_storage.c b/plat/fvp/fvp_io_storage.c
deleted file mode 100644
index ec1fe58..0000000
--- a/plat/fvp/fvp_io_storage.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <debug.h>
-#include <io_driver.h>
-#include <io_fip.h>
-#include <io_memmap.h>
-#include <io_storage.h>
-#include <io_semihosting.h>
-#include <platform_def.h>
-#include <semihosting.h> /* For FOPEN_MODE_... */
-#include <string.h>
-
-/* IO devices */
-static const io_dev_connector_t *sh_dev_con;
-static uintptr_t sh_dev_spec;
-static uintptr_t sh_init_params;
-static uintptr_t sh_dev_handle;
-static const io_dev_connector_t *fip_dev_con;
-static uintptr_t fip_dev_spec;
-static uintptr_t fip_dev_handle;
-static const io_dev_connector_t *memmap_dev_con;
-static uintptr_t memmap_dev_spec;
-static uintptr_t memmap_init_params;
-static uintptr_t memmap_dev_handle;
-
-static const io_block_spec_t fip_block_spec = {
- .offset = FLASH0_BASE,
- .length = FLASH0_SIZE
-};
-
-static const io_file_spec_t bl2_file_spec = {
- .path = BL2_IMAGE_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl31_file_spec = {
- .path = BL31_IMAGE_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl32_file_spec = {
- .path = BL32_IMAGE_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl33_file_spec = {
- .path = BL33_IMAGE_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-#if TRUSTED_BOARD_BOOT
-static const io_file_spec_t bl2_cert_file_spec = {
- .path = BL2_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t trusted_key_cert_file_spec = {
- .path = TRUSTED_KEY_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl30_key_cert_file_spec = {
- .path = BL30_KEY_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl31_key_cert_file_spec = {
- .path = BL31_KEY_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl32_key_cert_file_spec = {
- .path = BL32_KEY_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl33_key_cert_file_spec = {
- .path = BL33_KEY_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl30_cert_file_spec = {
- .path = BL30_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl31_cert_file_spec = {
- .path = BL31_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl32_cert_file_spec = {
- .path = BL32_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-
-static const io_file_spec_t bl33_cert_file_spec = {
- .path = BL33_CERT_NAME,
- .mode = FOPEN_MODE_RB
-};
-#endif /* TRUSTED_BOARD_BOOT */
-
-static int open_fip(const uintptr_t spec);
-static int open_memmap(const uintptr_t spec);
-
-struct plat_io_policy {
- char *image_name;
- uintptr_t *dev_handle;
- uintptr_t image_spec;
- int (*check)(const uintptr_t spec);
-};
-
-static const struct plat_io_policy policies[] = {
- {
- FIP_IMAGE_NAME,
- &memmap_dev_handle,
- (uintptr_t)&fip_block_spec,
- open_memmap
- }, {
- BL2_IMAGE_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl2_file_spec,
- open_fip
- }, {
- BL31_IMAGE_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl31_file_spec,
- open_fip
- }, {
- BL32_IMAGE_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl32_file_spec,
- open_fip
- }, {
- BL33_IMAGE_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl33_file_spec,
- open_fip
- }, {
-#if TRUSTED_BOARD_BOOT
- BL2_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl2_cert_file_spec,
- open_fip
- }, {
- TRUSTED_KEY_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&trusted_key_cert_file_spec,
- open_fip
- }, {
- BL30_KEY_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl30_key_cert_file_spec,
- open_fip
- }, {
- BL31_KEY_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl31_key_cert_file_spec,
- open_fip
- }, {
- BL32_KEY_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl32_key_cert_file_spec,
- open_fip
- }, {
- BL33_KEY_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl33_key_cert_file_spec,
- open_fip
- }, {
- BL30_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl30_cert_file_spec,
- open_fip
- }, {
- BL31_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl31_cert_file_spec,
- open_fip
- }, {
- BL32_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl32_cert_file_spec,
- open_fip
- }, {
- BL33_CERT_NAME,
- &fip_dev_handle,
- (uintptr_t)&bl33_cert_file_spec,
- open_fip
- }, {
-#endif /* TRUSTED_BOARD_BOOT */
- 0, 0, 0
- }
-};
-
-
-static int open_fip(const uintptr_t spec)
-{
- int result = IO_FAIL;
-
- /* See if a Firmware Image Package is available */
- result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME);
- if (result == IO_SUCCESS) {
- VERBOSE("Using FIP\n");
- /*TODO: Check image defined in spec is present in FIP. */
- }
- return result;
-}
-
-
-static int open_memmap(const uintptr_t spec)
-{
- int result = IO_FAIL;
- uintptr_t local_image_handle;
-
- result = io_dev_init(memmap_dev_handle, memmap_init_params);
- if (result == IO_SUCCESS) {
- result = io_open(memmap_dev_handle, spec, &local_image_handle);
- if (result == IO_SUCCESS) {
- VERBOSE("Using Memmap IO\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-
-static int open_semihosting(const uintptr_t spec)
-{
- int result = IO_FAIL;
- uintptr_t local_image_handle;
-
- /* See if the file exists on semi-hosting.*/
- result = io_dev_init(sh_dev_handle, sh_init_params);
- if (result == IO_SUCCESS) {
- result = io_open(sh_dev_handle, spec, &local_image_handle);
- if (result == IO_SUCCESS) {
- VERBOSE("Using Semi-hosting IO\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-void fvp_io_setup (void)
-{
- int io_result = IO_FAIL;
-
- /* Register the IO devices on this platform */
- io_result = register_io_dev_sh(&sh_dev_con);
- assert(io_result == IO_SUCCESS);
-
- io_result = register_io_dev_fip(&fip_dev_con);
- assert(io_result == IO_SUCCESS);
-
- io_result = register_io_dev_memmap(&memmap_dev_con);
- assert(io_result == IO_SUCCESS);
-
- /* Open connections to devices and cache the handles */
- io_result = io_dev_open(sh_dev_con, sh_dev_spec, &sh_dev_handle);
- assert(io_result == IO_SUCCESS);
-
- io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle);
- assert(io_result == IO_SUCCESS);
-
- io_result = io_dev_open(memmap_dev_con, memmap_dev_spec,
- &memmap_dev_handle);
- assert(io_result == IO_SUCCESS);
-
- /* Ignore improbable errors in release builds */
- (void)io_result;
-}
-
-
-/* Return an IO device handle and specification which can be used to access
- * an image. Use this to enforce platform load policy */
-int plat_get_image_source(const char *image_name, uintptr_t *dev_handle,
- uintptr_t *image_spec)
-{
- int result = IO_FAIL;
- const struct plat_io_policy *policy;
-
- if ((image_name != NULL) && (dev_handle != NULL) &&
- (image_spec != NULL)) {
- policy = policies;
- while (policy->image_name != NULL) {
- if (strcmp(policy->image_name, image_name) == 0) {
- result = policy->check(policy->image_spec);
- if (result == IO_SUCCESS) {
- *image_spec = policy->image_spec;
- *dev_handle = *(policy->dev_handle);
- break;
- } else {
- result = open_semihosting(
- policy->image_spec);
- if (result == IO_SUCCESS) {
- *dev_handle = sh_dev_handle;
- *image_spec =
- policy->image_spec;
- }
- }
- }
- policy++;
- }
- } else {
- result = IO_FAIL;
- }
- return result;
-}
diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h
deleted file mode 100644
index 4f60a16..0000000
--- a/plat/fvp/fvp_private.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __FVP_PRIVATE_H__
-#define __FVP_PRIVATE_H__
-
-#include <bakery_lock.h>
-#include <bl_common.h>
-#include <cpu_data.h>
-#include <platform_def.h>
-
-
-typedef volatile struct mailbox {
- unsigned long value
- __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
-} mailbox_t;
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31 e.g. while passing control to it from BL2 which is bl31_params
- * and bl31_plat_params and its elements
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
- bl31_params_t bl31_params;
- image_info_t bl31_image_info;
- image_info_t bl32_image_info;
- image_info_t bl33_image_info;
- entry_point_info_t bl33_ep_info;
- entry_point_info_t bl32_ep_info;
- entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-#if USE_COHERENT_MEM
-/*
- * These are wrapper macros to the Coherent Memory Bakery Lock API.
- */
-#define fvp_lock_init(_lock_arg) bakery_lock_init(_lock_arg)
-#define fvp_lock_get(_lock_arg) bakery_lock_get(_lock_arg)
-#define fvp_lock_release(_lock_arg) bakery_lock_release(_lock_arg)
-
-#else
-
-/*******************************************************************************
- * Constants to specify how many bakery locks this platform implements. These
- * are used if the platform chooses not to use coherent memory for bakery lock
- * data structures.
- ******************************************************************************/
-#define FVP_MAX_BAKERIES 1
-#define FVP_PWRC_BAKERY_ID 0
-
-/*******************************************************************************
- * Definition of structure which holds platform specific per-cpu data. Currently
- * it holds only the bakery lock information for each cpu. Constants to
- * specify how many bakeries this platform implements and bakery ids are
- * specified in fvp_def.h
- ******************************************************************************/
-typedef struct fvp_cpu_data {
- bakery_info_t pcpu_bakery_info[FVP_MAX_BAKERIES];
-} fvp_cpu_data_t;
-
-/* Macro to define the offset of bakery_info_t in fvp_cpu_data_t */
-#define FVP_CPU_DATA_LOCK_OFFSET __builtin_offsetof\
- (fvp_cpu_data_t, pcpu_bakery_info)
-
-
-/*******************************************************************************
- * Helper macros for bakery lock api when using the above fvp_cpu_data_t for
- * bakery lock data structures. It assumes that the bakery_info is at the
- * beginning of the platform specific per-cpu data.
- ******************************************************************************/
-#define fvp_lock_init(_lock_arg) /* No init required */
-#define fvp_lock_get(_lock_arg) bakery_lock_get(_lock_arg, \
- CPU_DATA_PLAT_PCPU_OFFSET + \
- FVP_CPU_DATA_LOCK_OFFSET)
-#define fvp_lock_release(_lock_arg) bakery_lock_release(_lock_arg, \
- CPU_DATA_PLAT_PCPU_OFFSET + \
- FVP_CPU_DATA_LOCK_OFFSET)
-
-/*
- * Ensure that the size of the FVP specific per-cpu data structure and the size
- * of the memory allocated in generic per-cpu data for the platform are the same.
- */
-CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(fvp_cpu_data_t), \
- fvp_pcpu_data_size_mismatch);
-
-#endif /* __USE_COHERENT_MEM__ */
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void fvp_configure_mmu_el1(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long
-#if USE_COHERENT_MEM
- , unsigned long,
- unsigned long
-#endif
- );
-void fvp_configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long
-#if USE_COHERENT_MEM
- , unsigned long,
- unsigned long
-#endif
- );
-
-int fvp_config_setup(void);
-
-void fvp_cci_init(void);
-void fvp_cci_enable(void);
-void fvp_cci_disable(void);
-
-void fvp_gic_init(void);
-
-/* Declarations for fvp_topology.c */
-int fvp_setup_topology(void);
-
-/* Declarations for fvp_io_storage.c */
-void fvp_io_setup(void);
-
-/* Declarations for fvp_security.c */
-void fvp_security_setup(void);
-
-/* Gets the SPR for BL32 entry */
-uint32_t fvp_get_spsr_for_bl32_entry(void);
-
-/* Gets the SPSR for BL33 entry */
-uint32_t fvp_get_spsr_for_bl33_entry(void);
-
-
-#endif /* __FVP_PRIVATE_H__ */
diff --git a/plat/fvp/fvp_security.c b/plat/fvp/fvp_security.c
deleted file mode 100644
index 62bde08..0000000
--- a/plat/fvp/fvp_security.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <debug.h>
-#include <plat_config.h>
-#include <tzc400.h>
-#include "fvp_def.h"
-#include "fvp_private.h"
-
-/* Used to improve readability for configuring regions. */
-#define FILTER_SHIFT(filter) (1 << filter)
-
-/*
- * For the moment we assume that all security programming is done by the
- * primary core.
- * TODO:
- * Might want to enable interrupt on violations when supported?
- */
-void fvp_security_setup(void)
-{
- /*
- * The Base FVP has a TrustZone address space controller, the Foundation
- * FVP does not. Trying to program the device on the foundation FVP will
- * cause an abort.
- *
- * If the platform had additional peripheral specific security
- * configurations, those would be configured here.
- */
-
- if (!(get_plat_config()->flags & CONFIG_HAS_TZC))
- return;
-
- /*
- * The TrustZone controller controls access to main DRAM. Give
- * full NS access for the moment to use with OS.
- */
- INFO("Configuring TrustZone Controller\n");
-
- /*
- * The driver does some error checking and will assert.
- * - Provide base address of device on platform.
- * - Provide width of ACE-Lite IDs on platform.
- */
- tzc_init(TZC400_BASE);
-
- /*
- * Currently only filters 0 and 2 are connected on Base FVP.
- * Filter 0 : CPU clusters (no access to DRAM by default)
- * Filter 1 : not connected
- * Filter 2 : LCDs (access to VRAM allowed by default)
- * Filter 3 : not connected
- * Programming unconnected filters will have no effect at the
- * moment. These filter could, however, be connected in future.
- * So care should be taken not to configure the unused filters.
- */
-
- /* Disable all filters before programming. */
- tzc_disable_filters();
-
- /*
- * Allow only non-secure access to all DRAM to supported devices.
- * Give access to the CPUs and Virtio. Some devices
- * would normally use the default ID so allow that too. We use
- * two regions to cover the blocks of physical memory in the FVPs
- * plus one region to reserve some memory as secure.
- *
- * Software executing in the secure state, such as a secure
- * boot-loader, can access the DRAM by using the NS attributes in
- * the MMU translation tables and descriptors.
- */
-
- /* Region 1 set to cover the Non-Secure DRAM */
- tzc_configure_region(FILTER_SHIFT(0), 1,
- DRAM1_NS_BASE, DRAM1_NS_END,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
-
- /* Region 2 set to cover the Secure DRAM */
- tzc_configure_region(FILTER_SHIFT(0), 2,
- DRAM1_SEC_BASE, DRAM1_SEC_END,
- TZC_REGION_S_RDWR,
- 0x0);
-
- /* Region 3 set to cover the second block of DRAM */
- tzc_configure_region(FILTER_SHIFT(0), 3,
- DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
- TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
-
- /*
- * TODO: Interrupts are not currently supported. The only
- * options we have are for access errors to occur quietly or to
- * cause an exception. We choose to cause an exception.
- */
- tzc_set_action(TZC_ACTION_ERR);
-
- /* Enable filters. */
- tzc_enable_filters();
-}
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
deleted file mode 100644
index 9e5ef4d..0000000
--- a/plat/fvp/include/plat_macros.S
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-#include <cci.h>
-#include <gic_v2.h>
-#include <plat_config.h>
-#include "../fvp_def.h"
-
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
- .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
-newline:
- .asciz "\n"
-spacer:
- .asciz ":\t\t0x"
-
- /* ---------------------------------------------
- * The below macro prints out relevant GIC
- * registers whenever an unhandled exception is
- * taken in BL3-1.
- * Clobbers: x0 - x10, x16, x17, sp
- * ---------------------------------------------
- */
- .macro plat_print_gic_regs
- mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
- ldr w16, [x0]
- /* Extract BLD (12th - 15th bits) from the SYS_ID */
- ubfx x16, x16, #SYS_ID_BLD_SHIFT, #4
- /* Check if VE mmap */
- cmp w16, #BLD_GIC_VE_MMAP
- b.eq use_ve_mmap
- /* Check if Cortex-A53/A57 mmap */
- cmp w16, #BLD_GIC_A53A57_MMAP
- b.ne exit_print_gic_regs
- mov_imm x17, BASE_GICC_BASE
- mov_imm x16, BASE_GICD_BASE
- b print_gicc_regs
-use_ve_mmap:
- mov_imm x17, VE_GICC_BASE
- mov_imm x16, VE_GICD_BASE
-print_gicc_regs:
- /* gicc base address is now in x17 */
- adr x6, gicc_regs /* Load the gicc reg list to x6 */
- /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
- ldr w8, [x17, #GICC_HPPIR]
- ldr w9, [x17, #GICC_AHPPIR]
- ldr w10, [x17, #GICC_CTLR]
- /* Store to the crash buf and print to console */
- bl str_in_crash_buf_print
-
- /* Print the GICD_ISPENDR regs */
- add x7, x16, #GICD_ISPENDR
- adr x4, gicd_pend_reg
- bl asm_print_str
-gicd_ispendr_loop:
- sub x4, x7, x16
- cmp x4, #0x280
- b.eq exit_print_gic_regs
- bl asm_print_hex
- adr x4, spacer
- bl asm_print_str
- ldr x4, [x7], #8
- bl asm_print_hex
- adr x4, newline
- bl asm_print_str
- b gicd_ispendr_loop
-exit_print_gic_regs:
- .endm
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
- .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
- /* ------------------------------------------------
- * The below macro prints out relevant interconnect
- * registers whenever an unhandled exception is
- * taken in BL3-1.
- * Clobbers: x0 - x9, sp
- * ------------------------------------------------
- */
- .macro plat_print_interconnect_regs
- adr x6, cci_iface_regs
- /* Store in x7 the base address of the first interface */
- mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET)
- ldr w8, [x7, #SNOOP_CTRL_REG]
- /* Store in x7 the base address of the second interface */
- mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET)
- ldr w9, [x7, #SNOOP_CTRL_REG]
- /* Store to the crash buf and print to console */
- bl str_in_crash_buf_print
- .endm
diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h
deleted file mode 100644
index 6713c5c..0000000
--- a/plat/fvp/include/platform_def.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
-
-#include <arch.h>
-#include "../fvp_def.h"
-
-
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH aarch64
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE 0x1000
-#else
-#define PLATFORM_STACK_SIZE 0x440
-#endif
-#elif IMAGE_BL2
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE 0x1000
-#else
-#define PLATFORM_STACK_SIZE 0x400
-#endif
-#elif IMAGE_BL31
-#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL32
-#define PLATFORM_STACK_SIZE 0x440
-#endif
-
-#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_NAME "bl2.bin"
-
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_NAME "bl31.bin"
-
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_NAME "bl32.bin"
-
-/* Non-Trusted Firmware BL33 */
-#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
-
-#if TRUSTED_BOARD_BOOT
-/* Certificates */
-# define BL2_CERT_NAME "bl2.crt"
-# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
-
-# define BL30_KEY_CERT_NAME "bl30_key.crt"
-# define BL31_KEY_CERT_NAME "bl31_key.crt"
-# define BL32_KEY_CERT_NAME "bl32_key.crt"
-# define BL33_KEY_CERT_NAME "bl33_key.crt"
-
-# define BL30_CERT_NAME "bl30.crt"
-# define BL31_CERT_NAME "bl31.crt"
-# define BL32_CERT_NAME "bl32.crt"
-# define BL33_CERT_NAME "bl33.crt"
-#endif /* TRUSTED_BOARD_BOOT */
-
-#define PLATFORM_CACHE_LINE_SIZE 64
-#define PLATFORM_CLUSTER_COUNT 2ull
-#define PLATFORM_CLUSTER0_CORE_COUNT 4
-#define PLATFORM_CLUSTER1_CORE_COUNT 4
-#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
- PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
-#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT)
-#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
-#define MAX_IO_DEVICES 3
-#define MAX_IO_HANDLES 4
-
-/*******************************************************************************
- * BL1 specific defines.
- * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
- * addresses.
- ******************************************************************************/
-#define BL1_RO_BASE FVP_TRUSTED_ROM_BASE
-#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
- + FVP_TRUSTED_ROM_SIZE)
-/*
- * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
- * the current BL1 RW debug size plus a little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE - 0x8000)
-#else
-#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE - 0x6000)
-#endif
-#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE)
-
-/*******************************************************************************
- * BL2 specific defines.
- ******************************************************************************/
-/*
- * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
- * size plus a little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-#define BL2_BASE (BL31_BASE - 0x1C000)
-#else
-#define BL2_BASE (BL31_BASE - 0xC000)
-#endif
-#define BL2_LIMIT BL31_BASE
-
-/*******************************************************************************
- * BL31 specific defines.
- ******************************************************************************/
-/*
- * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth.
- */
-#define BL31_BASE (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE - 0x1D000)
-#define BL31_PROGBITS_LIMIT BL1_RW_BASE
-#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE)
-
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-/*
- * On FVP, the TSP can execute from Trusted SRAM, Trusted DRAM or the DRAM
- * region secured by the TrustZone controller.
- */
-#if FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_SRAM_ID
-# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
-# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
-# define TSP_PROGBITS_LIMIT BL2_BASE
-# define BL32_BASE FVP_TRUSTED_SRAM_BASE
-# define BL32_LIMIT BL31_BASE
-#elif FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_DRAM_ID
-# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
-# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
-# define BL32_BASE FVP_TRUSTED_DRAM_BASE
-# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
-#elif FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
-# define TSP_SEC_MEM_BASE DRAM1_SEC_BASE
-# define TSP_SEC_MEM_SIZE DRAM1_SEC_SIZE
-# define BL32_BASE DRAM1_SEC_BASE
-# define BL32_LIMIT (DRAM1_SEC_BASE + DRAM1_SEC_SIZE)
-#else
-# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
-#endif
-
-/*
- * ID of the secure physical generic timer interrupt used by the TSP.
- */
-#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
-
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define ADDR_SPACE_SIZE (1ull << 32)
-
-#if IMAGE_BL1
-# define MAX_XLAT_TABLES 2
-#elif IMAGE_BL2
-# define MAX_XLAT_TABLES 3
-#elif IMAGE_BL31
-# define MAX_XLAT_TABLES 2
-#elif IMAGE_BL32
-# if FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
-# define MAX_XLAT_TABLES 3
-# else
-# define MAX_XLAT_TABLES 2
-# endif
-#endif
-
-#define MAX_MMAP_REGIONS (FVP_MMAP_ENTRIES + FVP_BL_REGIONS)
-
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT 6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-#if !USE_COHERENT_MEM
-/*******************************************************************************
- * Size of the per-cpu data in bytes that should be reserved in the generic
- * per-cpu data structure for the FVP port.
- ******************************************************************************/
-#define PLAT_PCPU_DATA_SIZE 2
-#endif
-
-#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
deleted file mode 100644
index 7cf571e..0000000
--- a/plat/fvp/platform.mk
+++ /dev/null
@@ -1,96 +0,0 @@
-#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# Neither the name of ARM nor the names of its contributors may be used
-# to endorse or promote products derived from this software without specific
-# prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-
-# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
-# Trusted SRAM is the default.
-FVP_TSP_RAM_LOCATION := tsram
-ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
- FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_SRAM_ID
-else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
- FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_DRAM_ID
-else ifeq (${FVP_TSP_RAM_LOCATION}, dram)
- FVP_TSP_RAM_LOCATION_ID := FVP_DRAM_ID
-else
- $(error "Unsupported FVP_TSP_RAM_LOCATION value")
-endif
-
-# Process flags
-$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
-
-PLAT_INCLUDES := -Iplat/fvp/include/
-
-PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- lib/aarch64/xlat_tables.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/aarch64/semihosting_call.S \
- plat/common/aarch64/plat_common.c \
- plat/fvp/fvp_io_storage.c
-
-BL1_SOURCES += drivers/arm/cci/cci.c \
- lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- plat/common/aarch64/platform_up_stack.S \
- plat/fvp/bl1_fvp_setup.c \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/aarch64/fvp_helpers.S
-
-BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
- plat/common/aarch64/platform_up_stack.S \
- plat/fvp/bl2_fvp_setup.c \
- plat/fvp/fvp_security.c \
- plat/fvp/aarch64/fvp_common.c
-
-BL31_SOURCES += drivers/arm/cci/cci.c \
- drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- drivers/arm/gic/gic_v3.c \
- drivers/arm/tzc400/tzc400.c \
- lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- plat/common/plat_gic.c \
- plat/common/aarch64/platform_mp_stack.S \
- plat/fvp/bl31_fvp_setup.c \
- plat/fvp/fvp_pm.c \
- plat/fvp/fvp_security.c \
- plat/fvp/fvp_topology.c \
- plat/fvp/aarch64/fvp_helpers.S \
- plat/fvp/aarch64/fvp_common.c \
- plat/fvp/drivers/pwrc/fvp_pwrc.c
-
-ifneq (${TRUSTED_BOARD_BOOT},0)
- BL1_SOURCES += plat/fvp/fvp_trusted_boot.c
- BL2_SOURCES += plat/fvp/fvp_trusted_boot.c
-endif
diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c
deleted file mode 100644
index 6b6e185..0000000
--- a/plat/juno/aarch64/juno_common.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch_helpers.h>
-#include <arm_gic.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <cci.h>
-#include <debug.h>
-#include <mmio.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <xlat_tables.h>
-#include "../juno_def.h"
-
-#define MAP_MHU_SECURE MAP_REGION_FLAT(MHU_SECURE_BASE, \
- MHU_SECURE_SIZE, \
- (MHU_PAYLOAD_CACHED ? \
- MT_MEMORY : MT_DEVICE) \
- | MT_RW | MT_SECURE)
-
-#define MAP_FLASH MAP_REGION_FLAT(FLASH_BASE, \
- FLASH_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
-
-#define MAP_IOFPGA MAP_REGION_FLAT(IOFPGA_BASE, \
- IOFPGA_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
- DEVICE0_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
- DEVICE1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \
- DRAM_NS_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
-
-#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
- TSP_SEC_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-/*
- * Table of regions for different BL stages to map using the MMU.
- * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
- * configure_mmu_elx() will give the available subset of that,
- */
-#if IMAGE_BL1
-static const mmap_region_t juno_mmap[] = {
- MAP_MHU_SECURE,
- MAP_FLASH,
- MAP_IOFPGA,
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-#if IMAGE_BL2
-static const mmap_region_t juno_mmap[] = {
- MAP_MHU_SECURE,
- MAP_FLASH,
- MAP_IOFPGA,
- MAP_DEVICE0,
- MAP_DEVICE1,
- MAP_NS_DRAM,
- MAP_TSP_MEM,
- {0}
-};
-#endif
-#if IMAGE_BL31
-static const mmap_region_t juno_mmap[] = {
- MAP_MHU_SECURE,
- MAP_IOFPGA,
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-#if IMAGE_BL32
-static const mmap_region_t juno_mmap[] = {
- MAP_IOFPGA,
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-
-CASSERT(ARRAY_SIZE(juno_mmap) + JUNO_BL_REGIONS \
- <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
-
-/* Array of secure interrupts to be configured by the gic driver */
-const unsigned int irq_sec_array[] = {
- IRQ_MHU,
- IRQ_GPU_SMMU_0,
- IRQ_GPU_SMMU_1,
- IRQ_ETR_SMMU,
- IRQ_TZC400,
- IRQ_TZ_WDOG,
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0,
- IRQ_SEC_SGI_1,
- IRQ_SEC_SGI_2,
- IRQ_SEC_SGI_3,
- IRQ_SEC_SGI_4,
- IRQ_SEC_SGI_5,
- IRQ_SEC_SGI_6,
- IRQ_SEC_SGI_7
-};
-
-static const int cci_map[] = {
- CCI400_CLUSTER0_SL_IFACE_IX,
- CCI400_CLUSTER1_SL_IFACE_IX
-};
-
-void plat_cci_init(void)
-{
- cci_init(CCI400_BASE,
- cci_map,
- ARRAY_SIZE(cci_map));
-}
-
-/*******************************************************************************
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- ******************************************************************************/
-#if USE_COHERENT_MEM
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit, \
- unsigned long coh_start, \
- unsigned long coh_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add_region(coh_start, coh_start, \
- coh_limit - coh_start, \
- MT_DEVICE | MT_RW | MT_SECURE); \
- mmap_add(juno_mmap); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#else
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add(juno_mmap); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#endif
-/* Define EL1 and EL3 variants of the function initialising the MMU */
-DEFINE_CONFIGURE_MMU_EL(1)
-DEFINE_CONFIGURE_MMU_EL(3)
-
-
-unsigned long plat_get_ns_image_entrypoint(void)
-{
- return NS_IMAGE_OFFSET;
-}
-
-uint64_t plat_get_syscnt_freq(void)
-{
- uint64_t counter_base_frequency;
-
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
-
- /* The first entry of the frequency modes table must not be 0 */
- if (counter_base_frequency == 0)
- panic();
-
- return counter_base_frequency;
-}
-
-void plat_gic_init(void)
-{
- arm_gic_init(GICC_BASE,
- GICD_BASE,
- 0,
- irq_sec_array,
- ARRAY_SIZE(irq_sec_array));
-}
diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c
deleted file mode 100644
index 3b3471a..0000000
--- a/plat/juno/bl1_plat_setup.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <cci.h>
-#include <console.h>
-#include <debug.h>
-#include <mmio.h>
-#include <platform.h>
-#include <platform_def.h>
-#include "../../bl1/bl1_private.h"
-#include "juno_def.h"
-#include "juno_private.h"
-
-#if USE_COHERENT_MEM
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted RAM
- ******************************************************************************/
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-/* Data structure which holds the extents of the trusted RAM for BL1 */
-static meminfo_t bl1_tzram_layout;
-
-meminfo_t *bl1_plat_sec_mem_layout(void)
-{
- return &bl1_tzram_layout;
-}
-
-/*******************************************************************************
- * Perform any BL1 specific platform actions.
- ******************************************************************************/
-void bl1_early_platform_setup(void)
-{
- const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
-
- /* Initialize the console to provide early debug support */
- console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
-
- /*
- * Enable CCI-400 for this cluster. No need for locks as no other cpu is
- * active at the moment
- */
- plat_cci_init();
- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-
- /* Allow BL1 to see the whole Trusted RAM */
- bl1_tzram_layout.total_base = TZRAM_BASE;
- bl1_tzram_layout.total_size = TZRAM_SIZE;
-
- /* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = TZRAM_BASE;
- bl1_tzram_layout.free_size = TZRAM_SIZE;
- reserve_mem(&bl1_tzram_layout.free_base,
- &bl1_tzram_layout.free_size,
- BL1_RAM_BASE,
- bl1_size);
-
- INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
- bl1_size);
-}
-
-
-/*
- * Address of slave 'n' security setting in the NIC-400 address region
- * control
- * TODO: Ideally this macro should be moved in a "nic-400.h" header file but
- * it would be the only thing in there so it's not worth it at the moment.
- */
-#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4)
-
-static void init_nic400(void)
-{
- /*
- * NIC-400 Access Control Initialization
- *
- * Define access privileges by setting each corresponding bit to:
- * 0 = Secure access only
- * 1 = Non-secure access allowed
- */
-
- /*
- * Allow non-secure access to some SOC regions, excluding UART1, which
- * remains secure.
- * Note: This is the NIC-400 device on the SOC
- */
- mmio_write_32(SOC_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0);
- mmio_write_32(SOC_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0);
- mmio_write_32(SOC_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0);
- mmio_write_32(SOC_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0);
- mmio_write_32(SOC_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0);
- mmio_write_32(SOC_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE),
- ~SOC_NIC400_BOOTSEC_BRIDGE_UART1);
-
- /*
- * Allow non-secure access to some CSS regions.
- * Note: This is the NIC-400 device on the CSS
- */
- mmio_write_32(CSS_NIC400_BASE +
- NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
- ~0);
-}
-
-
-#define PCIE_SECURE_REG 0x3000
-#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */
-
-static void init_pcie(void)
-{
- /*
- * PCIE Root Complex Security settings to enable non-secure
- * access to config registers.
- */
- mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
-}
-
-
-/*******************************************************************************
- * Function which will perform any remaining platform-specific setup that can
- * occur after the MMU and data cache have been enabled.
- ******************************************************************************/
-void bl1_platform_setup(void)
-{
- init_nic400();
- init_pcie();
-
- /* Initialise the IO layer and register platform IO devices */
- io_setup();
-
- /* Enable and initialize the System level generic timer */
- mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
-}
-
-
-/*******************************************************************************
- * Perform the very early platform specific architecture setup here. At the
- * moment this only does basic initialization. Later architectural setup
- * (bl1_arch_setup()) does not do anything platform specific.
- ******************************************************************************/
-void bl1_plat_arch_setup(void)
-{
- configure_mmu_el3(bl1_tzram_layout.total_base,
- bl1_tzram_layout.total_size,
- TZROM_BASE,
- TZROM_BASE + TZROM_SIZE
-#if USE_COHERENT_MEM
- , BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT
-#endif
- );
-}
-
-/*******************************************************************************
- * Before calling this function BL2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL2 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
- ******************************************************************************/
-void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
- entry_point_info_t *bl2_ep)
-{
- SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
- bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-}
diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c
deleted file mode 100644
index 194d620..0000000
--- a/plat/juno/bl31_plat_setup.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <arch.h>
-#include <arm_gic.h>
-#include <assert.h>
-#include <bl31.h>
-#include <bl_common.h>
-#include <cci.h>
-#include <console.h>
-#include <mmio.h>
-#include <platform.h>
-#include <stddef.h>
-#include "juno_def.h"
-#include "juno_private.h"
-#include "mhu.h"
-
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted RAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __RO_END__;
-extern unsigned long __BL31_END__;
-
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
-
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL3-1 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-#define BL31_END (unsigned long)(&__BL31_END__)
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-/******************************************************************************
- * Placeholder variables for copying the arguments that have been passed to
- * BL3-1 from BL2.
- ******************************************************************************/
-static entry_point_info_t bl32_ep_info;
-static entry_point_info_t bl33_ep_info;
-
-/*******************************************************************************
- * Return a pointer to the 'entry_point_info' structure of the next image for
- * the security state specified. BL3-3 corresponds to the non-secure image type
- * while BL3-2 corresponds to the secure image type. A NULL pointer is returned
- * if the image does not exist.
- ******************************************************************************/
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
- entry_point_info_t *next_image_info;
-
- next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
-
- /* None of the images on this platform can have 0x0 as the entrypoint */
- if (next_image_info->pc)
- return next_image_info;
- else
- return NULL;
-}
-
-/*******************************************************************************
- * Perform any BL3-1 specific platform actions. Here is an opportunity to copy
- * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
- * are lost (potentially). This needs to be done before the MMU is initialized
- * so that the memory layout can be used while creating page tables. Also, BL2
- * has flushed this information to memory, so we are guaranteed to pick up good
- * data
- ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
-{
- /* Initialize the console to provide early debug support */
- console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
-
- /*
- * Initialise the CCI-400 driver for BL31 so that it is accessible after
- * a warm boot. BL1 should have already enabled CCI coherency for this
- * cluster during cold boot.
- */
- plat_cci_init();
-
- /*
- * Check params passed from BL2 should not be NULL,
- */
- assert(from_bl2 != NULL);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
- /*
- * In debug builds, we pass a special value in 'plat_params_from_bl2'
- * to verify platform parameters from BL2 to BL3-1.
- * In release builds, it's not used.
- */
- assert(((unsigned long long)plat_params_from_bl2) ==
- JUNO_BL31_PLAT_PARAM_VAL);
-
- /*
- * Copy BL3-2 and BL3-3 entry point information.
- * They are stored in Secure RAM, in BL2's address space.
- */
- bl32_ep_info = *from_bl2->bl32_ep_info;
- bl33_ep_info = *from_bl2->bl33_ep_info;
-}
-
-/*******************************************************************************
- * Initialize the MHU and the GIC.
- ******************************************************************************/
-void bl31_platform_setup(void)
-{
- unsigned int reg_val;
-
- mhu_secure_init();
-
- /* Initialize the gic cpu and distributor interfaces */
- plat_gic_init();
- arm_gic_setup();
-
- /* Enable and initialize the System level generic timer */
- mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
-
- /* Allow access to the System counter timer module */
- reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
- reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
- reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
-
- reg_val = (1 << CNTNSAR_NS_SHIFT(1));
- mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
-
- /* Topologies are best known to the platform. */
- plat_setup_topology();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
- ******************************************************************************/
-void bl31_plat_arch_setup(void)
-{
- configure_mmu_el3(BL31_RO_BASE,
- (BL31_END - BL31_RO_BASE),
- BL31_RO_BASE,
- BL31_RO_LIMIT
-#if USE_COHERENT_MEM
- ,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT
-#endif
- );
-}
diff --git a/plat/juno/include/platform_def.h b/plat/juno/include/platform_def.h
deleted file mode 100644
index 9eb3053..0000000
--- a/plat/juno/include/platform_def.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
-
-#include <arch.h>
-#include "../juno_def.h"
-
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH aarch64
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#if TRUSTED_BOARD_BOOT && (IMAGE_BL1 || IMAGE_BL2)
-#define PLATFORM_STACK_SIZE 0x1000
-#else
-#define PLATFORM_STACK_SIZE 0x800
-#endif
-
-#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_NAME "bl2.bin"
-
-/* EL3 Runtime Firmware BL3-1 */
-#define BL31_IMAGE_NAME "bl31.bin"
-
-/* SCP Firmware BL3-0 */
-#define BL30_IMAGE_NAME "bl30.bin"
-
-/* Secure Payload BL3-2 (Trusted OS) */
-#define BL32_IMAGE_NAME "bl32.bin"
-
-/* Non-Trusted Firmware BL3-3 */
-#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
-
-/* Firmware Image Package */
-#define FIP_IMAGE_NAME "fip.bin"
-
-#if TRUSTED_BOARD_BOOT
-/* Certificates */
-# define BL2_CERT_NAME "bl2.crt"
-# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
-
-# define BL30_KEY_CERT_NAME "bl30_key.crt"
-# define BL31_KEY_CERT_NAME "bl31_key.crt"
-# define BL32_KEY_CERT_NAME "bl32_key.crt"
-# define BL33_KEY_CERT_NAME "bl33_key.crt"
-
-# define BL30_CERT_NAME "bl30.crt"
-# define BL31_CERT_NAME "bl31.crt"
-# define BL32_CERT_NAME "bl32.crt"
-# define BL33_CERT_NAME "bl33.crt"
-#endif /* TRUSTED_BOARD_BOOT */
-
-#define PLATFORM_CACHE_LINE_SIZE 64
-#define PLATFORM_CLUSTER_COUNT 2
-#define PLATFORM_CORE_COUNT 6
-#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT)
-#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
-#define MAX_IO_DEVICES 3
-#define MAX_IO_HANDLES 4
-
-/*******************************************************************************
- * BL1 specific defines.
- * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
- * addresses.
- ******************************************************************************/
-#define BL1_RO_BASE TZROM_BASE
-#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
-
-/*
- * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
- * the current BL1 RW debug size plus a little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x8000)
-#else
-#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
-#endif
-#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
-
-/*******************************************************************************
- * BL2 specific defines.
- ******************************************************************************/
-/*
- * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
- * size plus a little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-#define BL2_BASE (BL31_BASE - 0x1D000)
-#else
-#define BL2_BASE (BL31_BASE - 0xC000)
-#endif
-#define BL2_LIMIT BL31_BASE
-
-/*******************************************************************************
- * Load address of BL3-0 in the Juno port
- * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
- * SCP, it is discarded and BL3-1 is loaded over the top.
- ******************************************************************************/
-#define BL30_BASE BL31_BASE
-
-/*******************************************************************************
- * BL3-1 specific defines.
- ******************************************************************************/
-/*
- * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth.
- */
-#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
-#define BL31_PROGBITS_LIMIT BL1_RW_BASE
-#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
-
-/*******************************************************************************
- * BL3-2 specific defines.
- ******************************************************************************/
-#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID)
-# define TSP_SEC_MEM_BASE TZRAM_BASE
-# define TSP_SEC_MEM_SIZE TZRAM_SIZE
-# define BL32_BASE TZRAM_BASE
-# define BL32_LIMIT BL31_BASE
-# define BL32_PROGBITS_LIMIT BL2_BASE
-#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID)
-# define TSP_SEC_MEM_BASE DRAM_SEC_BASE
-# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE)
-# define BL32_BASE DRAM_SEC_BASE
-# define BL32_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE - \
- DRAM_SCP_SIZE)
-#else
-# error "Unsupported PLAT_TSP_LOCATION_ID value"
-#endif
-
-/*******************************************************************************
- * Load address of BL3-3 in the Juno port
- ******************************************************************************/
-#define NS_IMAGE_OFFSET 0xE0000000
-
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define ADDR_SPACE_SIZE (1ull << 32)
-
-#if IMAGE_BL1 || IMAGE_BL31
-# define MAX_XLAT_TABLES 2
-#endif
-
-#if IMAGE_BL2 || IMAGE_BL32
-# define MAX_XLAT_TABLES 3
-#endif
-
-#define MAX_MMAP_REGIONS (JUNO_MMAP_ENTRIES + JUNO_BL_REGIONS)
-
-/*******************************************************************************
- * ID of the secure physical generic timer interrupt used by the TSP
- ******************************************************************************/
-#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
-
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT 6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-#if !USE_COHERENT_MEM
-/*******************************************************************************
- * Size of the per-cpu data in bytes that should be reserved in the generic
- * per-cpu data structure for the Juno port.
- ******************************************************************************/
-#define PLAT_PCPU_DATA_SIZE 2
-#endif
-
-#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/juno/include/platform_oid.h b/plat/juno/include/platform_oid.h
deleted file mode 100644
index 38aca12..0000000
--- a/plat/juno/include/platform_oid.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef PLATFORM_OID_H_
-#define PLATFORM_OID_H_
-
-/*
- * This is the list of the different extensions containing relevant information
- * to establish the chain of trust.
- *
- * The OIDs shown here are just an example. Real OIDs should be obtained from
- * the ITU-T.
- */
-
-/* Non-volatile counter extensions */
-#define TZ_FW_NVCOUNTER_OID "1.2.3.1"
-#define NTZ_FW_NVCOUNTER_OID "1.2.3.2"
-
-/* BL2 extensions */
-#define BL2_HASH_OID "1.2.3.3"
-
-/* Trusted Key extensions */
-#define TZ_WORLD_PK_OID "1.2.3.4"
-#define NTZ_WORLD_PK_OID "1.2.3.5"
-
-/* BL3-1 extensions */
-#define BL31_CONTENT_CERT_PK_OID "1.2.3.6"
-#define BL31_HASH_OID "1.2.3.7"
-
-/* BL3-0 extensions */
-#define BL30_CONTENT_CERT_PK_OID "1.2.3.8"
-#define BL30_HASH_OID "1.2.3.9"
-
-/* BL3-2 extensions */
-#define BL32_CONTENT_CERT_PK_OID "1.2.3.10"
-#define BL32_HASH_OID "1.2.3.11"
-
-/* BL3-3 extensions */
-#define BL33_CONTENT_CERT_PK_OID "1.2.3.12"
-#define BL33_HASH_OID "1.2.3.13"
-
-#endif /* PLATFORM_OID_H_ */
diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h
deleted file mode 100644
index 2134ee4..0000000
--- a/plat/juno/juno_def.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __JUNO_DEF_H__
-#define __JUNO_DEF_H__
-
-/* Special value used to verify platform parameters from BL2 to BL3-1 */
-#define JUNO_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
-
-/*******************************************************************************
- * Juno memory map related constants
- ******************************************************************************/
-#define FLASH_BASE 0x08000000
-#define FLASH_SIZE 0x04000000
-
-/* Bypass offset from start of NOR flash */
-#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
-
-#ifndef TZROM_BASE
-/* Use the bypass address */
-#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET
-#endif
-/* Actual ROM size on Juno is 64 KB, but TBB requires at least 80 KB in debug
- * mode. We can test TBB on Juno bypassing the ROM and using 128 KB of flash */
-#if TRUSTED_BOARD_BOOT
-#define TZROM_SIZE 0x00020000
-#else
-#define TZROM_SIZE 0x00010000
-#endif
-
-#define TZRAM_BASE 0x04001000
-#define TZRAM_SIZE 0x0003F000
-
-#define PLAT_TRUSTED_SRAM_ID 0
-#define PLAT_DRAM_ID 1
-
-#define MHU_SECURE_BASE 0x04000000
-#define MHU_SECURE_SIZE 0x00001000
-
-#define MHU_PAYLOAD_CACHED 0
-
-#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE
-#define TRUSTED_MAILBOX_SHIFT 4
-
-#define EMMC_BASE 0x0c000000
-#define EMMC_SIZE 0x04000000
-
-#define PSRAM_BASE 0x14000000
-#define PSRAM_SIZE 0x02000000
-
-#define IOFPGA_BASE 0x1c000000
-#define IOFPGA_SIZE 0x03000000
-
-#define NSROM_BASE 0x1f000000
-#define NSROM_SIZE 0x00001000
-
-/* Following covers Columbus Peripherals excluding NSROM and NSRAM */
-#define DEVICE0_BASE 0x20000000
-#define DEVICE0_SIZE 0x0e000000
-#define MHU_BASE 0x2b1f0000
-
-#define NSRAM_BASE 0x2e000000
-#define NSRAM_SIZE 0x00008000
-
-/* Following covers Juno Peripherals and PCIe expansion area */
-#define DEVICE1_BASE 0x40000000
-#define DEVICE1_SIZE 0x40000000
-#define PCIE_CONTROL_BASE 0x7ff20000
-
-#define DRAM_BASE 0x80000000
-#define DRAM_SIZE 0x80000000
-
-/*
- * DRAM at 0x8000_0000 is divided in two regions:
- * - Secure DRAM (default is the top 16MB except for the last 2MB, which are
- * used by the SCP for DDR retraining)
- * - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE)
- */
-
-#define DRAM_SCP_SIZE 0x00200000
-#define DRAM_SCP_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SCP_SIZE)
-
-#define DRAM_SEC_SIZE 0x00E00000
-#define DRAM_SEC_BASE (DRAM_SCP_BASE - DRAM_SEC_SIZE)
-
-#define DRAM_NS_BASE DRAM_BASE
-#define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SCP_SIZE - DRAM_SEC_SIZE)
-
-/* Second region of DRAM */
-#define DRAM2_BASE 0x880000000
-#define DRAM2_SIZE 0x180000000
-
-/* Memory mapped Generic timer interfaces */
-#define SYS_CNTCTL_BASE 0x2a430000
-#define SYS_CNTREAD_BASE 0x2a800000
-#define SYS_TIMCTL_BASE 0x2a810000
-
-/*
- * Base memory address of the V2M-Juno motherboard APB system registers in the
- * IOFPGA
- */
-#define VE_SYSREGS_BASE 0x1c010000
-/* APB system registers in address offset order from the base memory address */
-#define V2M_SYS_ID 0x0
-#define V2M_SYS_LED 0x8
-
-/* V2M SYS_ID register bits */
-#define SYS_ID_REV_SHIFT 28
-#define SYS_ID_REV_MASK 0xf
-
-/* Board revisions */
-#define REV_JUNO_R0 0x1 /* Rev B */
-#define REV_JUNO_R1 0x2 /* Rev C */
-
-/*
- * V2M sysled bit definitions. The values written to this
- * register are defined in arch.h & runtime_svc.h. Only
- * used by the primary cpu to diagnose any cold boot issues.
- *
- * SYS_LED[0] - Security state (S=0/NS=1)
- * SYS_LED[2:1] - Exception Level (EL3-EL0)
- * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
- *
- */
-#define SYS_LED_SS_SHIFT 0x0
-#define SYS_LED_EL_SHIFT 0x1
-#define SYS_LED_EC_SHIFT 0x3
-
-/*
- * The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU.
- */
-#if USE_COHERENT_MEM
-#define JUNO_BL_REGIONS 3
-#else
-#define JUNO_BL_REGIONS 2
-#endif
-
-/*
- * The JUNO_MAX_MMAP_REGIONS depend on the number of entries in juno_mmap[]
- * defined for each BL stage in juno_common.c.
- */
-#if IMAGE_BL1
-#define JUNO_MMAP_ENTRIES 6
-#endif
-#if IMAGE_BL2
-#define JUNO_MMAP_ENTRIES 8
-#endif
-#if IMAGE_BL31
-#define JUNO_MMAP_ENTRIES 5
-#endif
-#if IMAGE_BL32
-#define JUNO_MMAP_ENTRIES 4
-#endif
-
-/*******************************************************************************
- * GIC-400 & interrupt handling related constants
- ******************************************************************************/
-#define GICD_BASE 0x2c010000
-#define GICC_BASE 0x2c02f000
-#define GICH_BASE 0x2c04f000
-#define GICV_BASE 0x2c06f000
-
-#define IRQ_MHU 69
-#define IRQ_GPU_SMMU_0 71
-#define IRQ_GPU_SMMU_1 73
-#define IRQ_ETR_SMMU 75
-#define IRQ_TZC400 80
-#define IRQ_TZ_WDOG 86
-
-#define IRQ_SEC_PHY_TIMER 29
-#define IRQ_SEC_SGI_0 8
-#define IRQ_SEC_SGI_1 9
-#define IRQ_SEC_SGI_2 10
-#define IRQ_SEC_SGI_3 11
-#define IRQ_SEC_SGI_4 12
-#define IRQ_SEC_SGI_5 13
-#define IRQ_SEC_SGI_6 14
-#define IRQ_SEC_SGI_7 15
-
-/*******************************************************************************
- * PL011 related constants
- ******************************************************************************/
-/* FPGA UART0 */
-#define PL011_UART0_BASE 0x1c090000
-/* FPGA UART1 */
-#define PL011_UART1_BASE 0x1c0a0000
-/* SoC UART0 */
-#define PL011_UART2_BASE 0x7ff80000
-/* SoC UART1 */
-#define PL011_UART3_BASE 0x7ff70000
-
-#define PL011_BAUDRATE 115200
-
-#define PL011_UART0_CLK_IN_HZ 24000000
-#define PL011_UART1_CLK_IN_HZ 24000000
-#define PL011_UART2_CLK_IN_HZ 7273800
-#define PL011_UART3_CLK_IN_HZ 7273800
-
-/*******************************************************************************
- * NIC-400 related constants
- ******************************************************************************/
-
-/* CSS NIC-400 Global Programmers View (GPV) */
-#define CSS_NIC400_BASE 0x2a000000
-
-/* The slave_bootsecure controls access to GPU, DMC and CS. */
-#define CSS_NIC400_SLAVE_BOOTSECURE 8
-
-/* SoC NIC-400 Global Programmers View (GPV) */
-#define SOC_NIC400_BASE 0x7fd00000
-
-#define SOC_NIC400_USB_EHCI 0
-#define SOC_NIC400_TLX_MASTER 1
-#define SOC_NIC400_USB_OHCI 2
-#define SOC_NIC400_PL354_SMC 3
-/*
- * The apb4_bridge controls access to:
- * - the PCIe configuration registers
- * - the MMU units for USB, HDLCD and DMA
- */
-#define SOC_NIC400_APB4_BRIDGE 4
-/*
- * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
- */
-#define SOC_NIC400_BOOTSEC_BRIDGE 5
-#define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
-
-/*******************************************************************************
- * TZC-400 related constants
- ******************************************************************************/
-#define TZC400_BASE 0x2a4a0000
-
-#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
-#define TZC400_NSAID_PCIE 1
-#define TZC400_NSAID_HDLCD0 2
-#define TZC400_NSAID_HDLCD1 3
-#define TZC400_NSAID_USB 4
-#define TZC400_NSAID_DMA330 5
-#define TZC400_NSAID_THINLINKS 6
-#define TZC400_NSAID_AP 9
-#define TZC400_NSAID_GPU 10
-#define TZC400_NSAID_SCP 11
-#define TZC400_NSAID_CORESIGHT 12
-
-/*******************************************************************************
- * CCI-400 related constants
- ******************************************************************************/
-#define CCI400_BASE 0x2c090000
-#define CCI400_CLUSTER0_SL_IFACE_IX 4
-#define CCI400_CLUSTER1_SL_IFACE_IX 3
-
-/*******************************************************************************
- * SCP <=> AP boot configuration
- ******************************************************************************/
-#define SCP_BOOT_CFG_ADDR 0x04000080
-#define PRIMARY_CPU_SHIFT 8
-#define PRIMARY_CPU_MASK 0xf
-
-/*******************************************************************************
- * MMU-401 related constants
- ******************************************************************************/
-#define MMU401_SSD_OFFSET 0x4000
-#define MMU401_DMA330_BASE 0x7fb00000
-
-#endif /* __JUNO_DEF_H__ */
diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h
deleted file mode 100644
index afb1bfc..0000000
--- a/plat/juno/juno_private.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __JUNO_PRIVATE_H__
-#define __JUNO_PRIVATE_H__
-
-#include <bakery_lock.h>
-#include <bl_common.h>
-#include <cpu_data.h>
-#include <platform_def.h>
-#include <stdint.h>
-
-/*******************************************************************************
- * Forward declarations
- ******************************************************************************/
-struct plat_pm_ops;
-struct meminfo;
-struct bl31_params;
-struct image_info;
-struct entry_point_info;
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL3-1 e.g. while passing control to it from BL2 which is bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
- struct bl31_params bl31_params;
- struct image_info bl31_image_info;
- struct image_info bl32_image_info;
- struct image_info bl33_image_info;
- struct entry_point_info bl33_ep_info;
- struct entry_point_info bl32_ep_info;
- struct entry_point_info bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-#if IMAGE_BL31
-#if USE_COHERENT_MEM
-/*
- * These are wrapper macros to the Coherent Memory Bakery Lock API.
- */
-#define juno_lock_init(_lock_arg) bakery_lock_init(_lock_arg)
-#define juno_lock_get(_lock_arg) bakery_lock_get(_lock_arg)
-#define juno_lock_release(_lock_arg) bakery_lock_release(_lock_arg)
-
-#else
-
-/*******************************************************************************
- * Constants that specify how many bakeries this platform implements and bakery
- * ids.
- ******************************************************************************/
-#define JUNO_MAX_BAKERIES 1
-#define JUNO_MHU_BAKERY_ID 0
-
-/*******************************************************************************
- * Definition of structure which holds platform specific per-cpu data. Currently
- * it holds only the bakery lock information for each cpu. Constants to specify
- * how many bakeries this platform implements and bakery ids are specified in
- * juno_def.h
- ******************************************************************************/
-typedef struct juno_cpu_data {
- bakery_info_t pcpu_bakery_info[JUNO_MAX_BAKERIES];
-} juno_cpu_data_t;
-
-/* Macro to define the offset of bakery_info_t in juno_cpu_data_t */
-#define JUNO_CPU_DATA_LOCK_OFFSET __builtin_offsetof\
- (juno_cpu_data_t, pcpu_bakery_info)
-
-/*******************************************************************************
- * Helper macros for bakery lock api when using the above juno_cpu_data_t for
- * bakery lock data structures. It assumes that the bakery_info is at the
- * beginning of the platform specific per-cpu data.
- ******************************************************************************/
-#define juno_lock_init(_lock_arg) /* No init required */
-#define juno_lock_get(_lock_arg) bakery_lock_get(_lock_arg, \
- CPU_DATA_PLAT_PCPU_OFFSET + \
- JUNO_CPU_DATA_LOCK_OFFSET)
-#define juno_lock_release(_lock_arg) bakery_lock_release(_lock_arg, \
- CPU_DATA_PLAT_PCPU_OFFSET + \
- JUNO_CPU_DATA_LOCK_OFFSET)
-
-/*
- * Ensure that the size of the Juno specific per-cpu data structure and the size
- * of the memory allocated in generic per-cpu data for the platform are the same.
- */
-CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(juno_cpu_data_t), \
- juno_pcpu_data_size_mismatch);
-#endif /* __USE_COHERENT_MEM__ */
-#else
-/*
- * Dummy wrapper macros for all other BL stages other than BL3-1
- */
-#define juno_lock_init(_lock_arg)
-#define juno_lock_get(_lock_arg)
-#define juno_lock_release(_lock_arg)
-
-#endif /* __IMAGE_BL31__ */
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void bl1_plat_arch_setup(void);
-void bl2_plat_arch_setup(void);
-void bl31_plat_arch_setup(void);
-int platform_setup_pm(const struct plat_pm_ops **plat_ops);
-unsigned int platform_get_core_pos(unsigned long mpidr);
-void configure_mmu_el1(unsigned long total_base,
- unsigned long total_size,
- unsigned long ro_start,
- unsigned long ro_limit
-#if USE_COHERENT_MEM
- , unsigned long coh_start,
- unsigned long coh_limit
-#endif
- );
-void configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long ro_start,
- unsigned long ro_limit
-#if USE_COHERENT_MEM
- , unsigned long coh_start,
- unsigned long coh_limit
-#endif
- );
-void plat_report_exception(unsigned long type);
-unsigned long plat_get_ns_image_entrypoint(void);
-unsigned long platform_get_stack(unsigned long mpidr);
-uint64_t plat_get_syscnt_freq(void);
-void plat_gic_init(void);
-void plat_cci_init(void);
-
-/* Declarations for plat_topology.c */
-int plat_setup_topology(void);
-unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr);
-unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr);
-
-/* Declarations for plat_io_storage.c */
-void io_setup(void);
-int plat_get_image_source(const char *image_name,
- uintptr_t *dev_handle,
- uintptr_t *image_spec);
-
-/* Declarations for security.c */
-void plat_security_setup(void);
-
-/*
- * Before calling this function BL2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL2 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
- */
-void bl1_plat_set_bl2_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-/*
- * Before calling this function BL3-1 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-1 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
- */
-void bl2_plat_set_bl31_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-/*
- * Before calling this function BL3-2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-2 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
- */
-void bl2_plat_set_bl32_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-/*
- * Before calling this function BL3-3 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-3 and set SPSR and security state.
- * On Juno we are only setting the security state, entrypoint
- */
-void bl2_plat_set_bl33_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-/* Gets the memory layout for BL3-2 */
-void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
-
-/* Gets the memory layout for BL3-3 */
-void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
-
-#endif /* __JUNO_PRIVATE_H__ */
diff --git a/plat/juno/juno_trusted_boot.c b/plat/juno/juno_trusted_boot.c
deleted file mode 100644
index e63d4b2..0000000
--- a/plat/juno/juno_trusted_boot.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <debug.h>
-#include "juno_def.h"
-#include "juno_private.h"
-
-/*
- * Check the validity of the key
- *
- * 0 = success, Otherwise = error
- */
-int plat_match_rotpk(const unsigned char *key_buf, unsigned int key_len)
-{
- /* TODO: check against the ROT key stored in the platform */
- return 0;
-}
diff --git a/plat/juno/plat-tsp.ld.S b/plat/juno/plat-tsp.ld.S
deleted file mode 100644
index 16d6c17..0000000
--- a/plat/juno/plat-tsp.ld.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
- ASSERT(__BL32_END__ <= BL2_BASE, "BL3-2 image overlaps BL2 image.")
diff --git a/plat/juno/plat_security.c b/plat/juno/plat_security.c
deleted file mode 100644
index 254357d..0000000
--- a/plat/juno/plat_security.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <debug.h>
-#include <mmio.h>
-#include <tzc400.h>
-#include "juno_def.h"
-
-/*******************************************************************************
- * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
- * and allow Non-Secure masters full access
- ******************************************************************************/
-static void init_tzc400(void)
-{
- tzc_init(TZC400_BASE);
-
- /* Disable filters. */
- tzc_disable_filters();
-
- /* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
- * same configuration to all filters in the TZC. */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 1,
- DRAM_NS_BASE, DRAM_NS_BASE + DRAM_NS_SIZE - 1,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
-
- /* Region 2 set to cover Secure DRAM */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 2,
- DRAM_SEC_BASE, DRAM_SEC_BASE + DRAM_SEC_SIZE - 1,
- TZC_REGION_S_RDWR,
- 0);
-
- /* Region 3 set to cover DRAM used by SCP for DDR retraining */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 3,
- DRAM_SCP_BASE, DRAM_SCP_BASE + DRAM_SCP_SIZE - 1,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP));
-
- /* Region 4 set to cover Non-Secure DRAM at 0x8_8000_0000 */
- tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 4,
- DRAM2_BASE, DRAM2_BASE + DRAM2_SIZE - 1,
- TZC_REGION_S_NONE,
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
- TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT));
-
- /* Raise an exception if a NS device tries to access secure memory */
- tzc_set_action(TZC_ACTION_ERR);
-
- /* Enable filters. */
- tzc_enable_filters();
-}
-
-/*******************************************************************************
- * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
- * assigned to Non-Secure except some for the DMA-330. Assign those back to the
- * Non-Secure world as well, otherwise EL1 may end up erroneously generating
- * (untranslated) Secure transactions if it turns the SMMU on.
- ******************************************************************************/
-static void init_mmu401(void)
-{
- uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
- reg |= 0x1FF;
- mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
-}
-
-/*******************************************************************************
- * Initialize the secure environment. At this moment only the TrustZone
- * Controller is initialized.
- ******************************************************************************/
-void plat_security_setup(void)
-{
- /* Initialize the TrustZone Controller */
- init_tzc400();
- /* Initialize the SMMU SSD tables*/
- init_mmu401();
-}
diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk
deleted file mode 100644
index 6877814..0000000
--- a/plat/juno/platform.mk
+++ /dev/null
@@ -1,111 +0,0 @@
-#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# Redistributions of source code must retain the above copyright notice, this
-# list of conditions and the following disclaimer.
-#
-# Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# Neither the name of ARM nor the names of its contributors may be used
-# to endorse or promote products derived from this software without specific
-# prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-
-# On Juno, the Secure Payload can be loaded either in Trusted SRAM (default) or
-# Secure DRAM allocated by the TrustZone Controller.
-
-PLAT_TSP_LOCATION := tsram
-
-ifeq (${PLAT_TSP_LOCATION}, tsram)
- PLAT_TSP_LOCATION_ID := PLAT_TRUSTED_SRAM_ID
-else ifeq (${PLAT_TSP_LOCATION}, dram)
- PLAT_TSP_LOCATION_ID := PLAT_DRAM_ID
-else
- $(error "Unsupported PLAT_TSP_LOCATION value")
-endif
-
-# Process flags
-$(eval $(call add_define,PLAT_TSP_LOCATION_ID))
-
-
-PLAT_INCLUDES := -Iplat/juno/include/
-
-PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- drivers/io/io_storage.c \
- lib/aarch64/xlat_tables.c \
- plat/common/aarch64/plat_common.c \
- plat/common/plat_gic.c \
- plat/juno/plat_io_storage.c
-
-BL1_SOURCES += drivers/arm/cci/cci.c \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- plat/common/aarch64/platform_up_stack.S \
- plat/juno/bl1_plat_setup.c \
- plat/juno/aarch64/bl1_plat_helpers.S \
- plat/juno/aarch64/plat_helpers.S \
- plat/juno/aarch64/juno_common.c
-
-BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
- plat/common/aarch64/platform_up_stack.S \
- plat/juno/bl2_plat_setup.c \
- plat/juno/mhu.c \
- plat/juno/plat_security.c \
- plat/juno/aarch64/plat_helpers.S \
- plat/juno/aarch64/juno_common.c \
- plat/juno/scp_bootloader.c \
- plat/juno/scpi.c
-
-BL31_SOURCES += drivers/arm/cci/cci.c \
- drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- drivers/arm/gic/gic_v3.c \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- plat/common/aarch64/platform_mp_stack.S \
- plat/juno/bl31_plat_setup.c \
- plat/juno/mhu.c \
- plat/juno/aarch64/plat_helpers.S \
- plat/juno/aarch64/juno_common.c \
- plat/juno/plat_pm.c \
- plat/juno/plat_topology.c \
- plat/juno/scpi.c
-
-ifneq (${TRUSTED_BOARD_BOOT},0)
- BL1_SOURCES += plat/juno/juno_trusted_boot.c
- BL2_SOURCES += plat/juno/juno_trusted_boot.c
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL3-1 as the reset vector is not supported on Juno. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-NEED_BL30 := yes
-
-# Enable workarounds for selected Cortex-A57 erratas.
-ERRATA_A57_806969 := 0
-ERRATA_A57_813420 := 1
-
-# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
-# power down sequence
-SKIP_A57_L1_FLUSH_PWR_DWN := 1
diff --git a/plat/juno/tsp/tsp_plat_setup.c b/plat/juno/tsp/tsp_plat_setup.c
deleted file mode 100644
index 8293a13..0000000
--- a/plat/juno/tsp/tsp_plat_setup.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <bl_common.h>
-#include <console.h>
-#include <platform_tsp.h>
-#include "../juno_def.h"
-#include "../juno_private.h"
-
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-extern unsigned long __RO_START__;
-extern unsigned long __RO_END__;
-extern unsigned long __BL32_END__;
-
-#if USE_COHERENT_MEM
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-#endif
-
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL3-2 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL32_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL32_RO_BASE (unsigned long)(&__RO_START__)
-#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
-#define BL32_END (unsigned long)(&__BL32_END__)
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
-/*******************************************************************************
- * Initialize the UART
- ******************************************************************************/
-void tsp_early_platform_setup(void)
-{
- /*
- * Initialize a different console than already in use to display
- * messages from TSP
- */
- console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
-}
-
-/*******************************************************************************
- * Perform platform specific setup placeholder
- ******************************************************************************/
-void tsp_platform_setup(void)
-{
- plat_gic_init();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this only intializes the MMU
- ******************************************************************************/
-void tsp_plat_arch_setup(void)
-{
- configure_mmu_el1(BL32_RO_BASE,
- (BL32_END - BL32_RO_BASE),
- BL32_RO_BASE,
- BL32_RO_LIMIT
-#if USE_COHERENT_MEM
- , BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT
-#endif
- );
-}
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index f1aa797..eac8cec 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -47,7 +47,13 @@
# Check the platform
ifeq (${PLAT},none)
- $(error Error: No platform defined. Use PLAT=<platform>.)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform")
+endif
+PLAT_MAKEFILE := platform.mk
+PLAT_INCLUDE := $(shell find ../../plat/ -wholename '*/${PLAT}/${PLAT_MAKEFILE}' | \
+ sed 's/${PLAT_MAKEFILE}/include/')
+ifeq ($(PLAT_INCLUDE),)
+ $(error "Error: Invalid platform '${PLAT}'")
endif
ifeq (${DEBUG},1)
@@ -63,7 +69,7 @@
# Make soft links and include from local directory otherwise wrong headers
# could get pulled in from firmware tree.
-INC_DIR := -I ./include -I ../../plat/${PLAT}/include
+INC_DIR := -I ./include -I ${PLAT_INCLUDE}
LIB_DIR :=
LIB := -lssl -lcrypto