refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
Continuing the refactoring of the various definition for platforms based
on N2/V2 CPU, refactor the definitions in the nrd_soc_css_def_v2.h file
into the following files as appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions
- nrd_plat_arm_def2.h: includes platform port related definitions
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib447e67a0a42722735297b27b7f5017bc146156c
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h
index ebe5a7a..7f653c4 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h
@@ -23,6 +23,9 @@
#define NRD_DEVICE_BASE UL(0x20000000)
#define NRD_DEVICE_SIZE UL(0x20000000)
+/* NS RAM Error record */
+#define SOC_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
+
/*Secure Watchdog */
#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h
index f385e76..d4c2b4f 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h
@@ -42,6 +42,9 @@
* RAS config
******************************************************************************/
+#define NS_RAM_ECC_CE_INT U(87)
+#define NS_RAM_ECC_UE_INT U(88)
+
#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) \
&& ENABLE_FEAT_RAS && FFH_SUPPORT
/*
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
index a219cd7..a2d8efe 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
@@ -13,7 +13,10 @@
#ifndef NRD_PLAT_ARM_DEF2_H
#define NRD_PLAT_ARM_DEF2_H
-#include <nrd_soc_css_def_v2.h>
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
#include <plat/arm/common/arm_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/arm/css/common/css_def.h>
@@ -221,7 +224,106 @@
* Flash config
******************************************************************************/
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+#define V2M_SYS_LED U(0x8)
+
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+#define V2M_SYSREGS_BASE UL(0x0C010000)
+
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*******************************************************************************
+ * Platform type identification macro
+ ******************************************************************************/
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
+#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
+#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
+#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
+
+#ifndef __ASSEMBLER__
+#define BOARD_CSS_GET_PLAT_TYPE(addr) \
+ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
+ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+#endif /* __ASSEMBLER__ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0)
+
+/*******************************************************************************
+ * ROS peripheral config
+ ******************************************************************************/
+
+#define SOC_CSS_NIC400_USB_EHCI U(0)
+#define SOC_CSS_NIC400_TLX_MASTER U(1)
+#define SOC_CSS_NIC400_USB_OHCI U(2)
+#define SOC_CSS_NIC400_PL354_SMC U(3)
+#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
+
+#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
+
+/* SoC NIC-400 Global Programmers View (GPV) */
+#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
+
+/* Non-volatile counters */
+#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE +\
+ 0x0000)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE +\
+ 0x0004)
+#define NTFW_CTR_SIZE U(4)
+
+/* Keys */
+#define SOC_KEYS_BASE UL(0x0EE80000)
+#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
+#define TZ_PUB_KEY_HASH_SIZE U(32)
+#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
+#define HU_KEY_SIZE U(16)
+#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
+#define END_KEY_SIZE U(32)
+
+/*******************************************************************************
+ * MMU config
+ ******************************************************************************/
+
+#define V2M_MAP_FLASH0_RW \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define V2M_MAP_FLASH0_RO \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_RO_DATA | MT_SECURE)
+
#endif /* NRD_PLAT_ARM_DEF2_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h
index fc633c4..ff1371b 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h
@@ -26,4 +26,12 @@
#define SOC_MEMCNTRL_BASE UL(0x10000000)
#define SOC_MEMCNTRL_SIZE UL(0x10000000)
+/* System peripherals */
+#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
+#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
+
+/* Platform peripherals */
+#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
+
#endif /* NRD_ROS_DEF2_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h
index e2e3c4f..5b12f18 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h
@@ -17,6 +17,27 @@
* MMU mapping
******************************************************************************/
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE \
+ MAP_REGION_FLAT( \
+ SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#if SPM_MM
+
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
+ MAP_REGION_FLAT( \
+ SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
+#define SOC_SYSTEM_PERIPH_MAP_DEVICE \
+ MAP_REGION_FLAT( \
+ SOC_SYSTEM_PERIPH_BASE, \
+ SOC_SYSTEM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
#define SOC_MEMCNTRL_MAP_DEVICE \
MAP_REGION_FLAT( \
SOC_MEMCNTRL_BASE, \
@@ -42,6 +63,14 @@
CSS_NOR2_FLASH_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define NRD_MAP_FLASH0_RO \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+
/*******************************************************************************
* TZ config
******************************************************************************/
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_soc_css_def_v2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_soc_css_def_v2.h
deleted file mode 100644
index 33f9b4b..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_soc_css_def_v2.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_CSS_DEF_V2_H
-#define NRD_SOC_CSS_DEF_V2_H
-
-#include <lib/utils_def.h>
-#include <plat/common/common_def.h>
-
-/*
- * Definitions common to all ARM CSS SoCs
- */
-
-/* Following covers ARM CSS SoC Peripherals */
-
-#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
-#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
-
-#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
-#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
-
-#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
-
-/* Memory controller */
-#define SOC_MEMCNTRL_BASE UL(0x10000000)
-#define SOC_MEMCNTRL_SIZE UL(0x10000000)
-
-/* SoC NIC-400 Global Programmers View (GPV) */
-#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
-
-#define SOC_CSS_NIC400_USB_EHCI U(0)
-#define SOC_CSS_NIC400_TLX_MASTER U(1)
-#define SOC_CSS_NIC400_USB_OHCI U(2)
-#define SOC_CSS_NIC400_PL354_SMC U(3)
-/*
- * The apb4_bridge controls access to:
- * - the PCIe configuration registers
- * - the MMU units for USB, HDLCD and DMA
- */
-#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
-
-/* Non-volatile counters */
-#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000)
-#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
-#define TFW_NVCTR_SIZE U(4)
-#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
-#define NTFW_CTR_SIZE U(4)
-
-/* Keys */
-#define SOC_KEYS_BASE UL(0x0EE80000)
-#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
-#define TZ_PUB_KEY_HASH_SIZE U(32)
-#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
-#define HU_KEY_SIZE U(16)
-#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
-#define END_KEY_SIZE U(32)
-
-/* Base Element RAM error definitions */
-#define SOC_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
-#define NS_RAM_ECC_CE_INT U(87)
-#define NS_RAM_ECC_UE_INT U(88)
-
-#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
- SOC_PLATFORM_PERIPH_BASE, \
- SOC_PLATFORM_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#if SPM_MM
-/*
- * Memory map definition for the platform peripheral memory region that is
- * accessible from S-EL0 (with secure user mode access).
- */
-#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
- MAP_REGION_FLAT( \
- SOC_PLATFORM_PERIPH_BASE, \
- SOC_PLATFORM_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-#endif
-
-#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
- SOC_SYSTEM_PERIPH_BASE, \
- SOC_SYSTEM_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \
- SOC_MEMCNTRL_BASE, \
- SOC_MEMCNTRL_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \
- SOC_MEMCNTRL_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-/*
- * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
- */
-#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
-#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
-
-/*
- * Required platform porting definitions common to all ARM CSS SoCs
- */
-/* 2MB used for SCP DDR retraining */
-#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000)
-
-/* V2M motherboard system registers & offsets */
-#define V2M_SYSREGS_BASE UL(0x0C010000)
-#define V2M_SYS_LED U(0x8)
-
-/*
- * V2M sysled bit definitions. The values written to this
- * register are defined in arch.h & runtime_svc.h. Only
- * used by the primary cpu to diagnose any cold boot issues.
- *
- * SYS_LED[0] - Security state (S=0/NS=1)
- * SYS_LED[2:1] - Exception Level (EL3-EL0)
- * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
- *
- */
-#define V2M_SYS_LED_SS_SHIFT U(0)
-#define V2M_SYS_LED_EL_SHIFT U(1)
-#define V2M_SYS_LED_EC_SHIFT U(3)
-
-#define V2M_SYS_LED_SS_MASK U(0x01)
-#define V2M_SYS_LED_EL_MASK U(0x03)
-#define V2M_SYS_LED_EC_MASK U(0x1f)
-
-/* NOR Flash */
-#define V2M_FLASH0_BASE UL(0x08000000)
-#define V2M_FLASH0_SIZE UL(0x04000000)
-#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
-
-/*
- * The flash can be mapped either as read-only or read-write.
- *
- * If it is read-write then it should also be mapped as device memory because
- * NOR flash programming involves sending a fixed, ordered sequence of commands.
- *
- * If it is read-only then it should also be mapped as:
- * - Normal memory, because reading from NOR flash is transparent, it is like
- * reading from RAM.
- * - Non-executable by default. If some parts of the flash need to be executable
- * then platform code is responsible for re-mapping the appropriate portion
- * of it as executable.
- */
-#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
- V2M_FLASH0_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
- V2M_FLASH0_SIZE, \
- MT_RO_DATA | MT_SECURE)
-
-#define NRD_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
- V2M_FLASH0_SIZE, \
- MT_DEVICE | MT_RO | MT_SECURE)
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0)
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
-#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
-#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
-#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
-#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
-#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
-#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
-
-#ifndef __ASSEMBLER__
-
-#include <lib/mmio.h>
-
-#define BOARD_CSS_GET_PLAT_TYPE(addr) \
- ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
- >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-
-#endif /* __ASSEMBLER__ */
-
-
-#define MAX_IO_DEVICES U(3)
-#define MAX_IO_HANDLES U(4)
-
-/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#if ARM_GPT_SUPPORT
-/*
- * Offset of the FIP in the GPT image. BL1 component uses this option
- * as it does not load the partition table to get the FIP base
- * address. At sector 34 by default (i.e. after reserved sectors 0-33)
- * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
- */
-#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
-#endif /* ARM_GPT_SUPPORT */
-
-#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#endif /* NRD_SOC_CSS_DEF_V2_H */