rockchip: support the suspend/resume for rk3399
This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
diff --git a/plat/rockchip/common/pmusram/pmu_sram.h b/plat/rockchip/common/pmusram/pmu_sram.h
index a2ab460..f290461 100644
--- a/plat/rockchip/common/pmusram/pmu_sram.h
+++ b/plat/rockchip/common/pmusram/pmu_sram.h
@@ -27,21 +27,14 @@
#define __PMU_SRAM_H__
/*****************************************************************************
- * cpu up status
- *****************************************************************************/
-#define PMU_SYS_SLP_MODE 0xa5
-#define PMU_SYS_ON_MODE 0x0
-
-/*****************************************************************************
* define data offset in struct psram_data
*****************************************************************************/
#define PSRAM_DT_SP 0x0
#define PSRAM_DT_DDR_FUNC 0x8
#define PSRAM_DT_DDR_DATA 0x10
#define PSRAM_DT_DDRFLAG 0x18
-#define PSRAM_DT_SYS_MODE 0x1c
-#define PSRAM_DT_MPIDR 0x20
-#define PSRAM_DT_END 0x24
+#define PSRAM_DT_MPIDR 0x1c
+#define PSRAM_DT_END 0x20
/******************************************************************************
* Allocate data region for struct psram_data_t in pmusram
******************************************************************************/
@@ -67,7 +60,6 @@
uint64_t ddr_func;
uint64_t ddr_data;
uint32_t ddr_flag;
- uint32_t sys_mode;
uint32_t boot_mpidr;
};
@@ -81,8 +73,6 @@
assert_psram_dt_ddr_data_offset_mistmatch);
CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG,
assert_psram_dt_ddr_flag_offset_mistmatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, sys_mode) == PSRAM_DT_SYS_MODE,
- assert_psram_dt_sys_mode_offset_mistmatch);
CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR,
assert_psram_dt_mpidr_offset_mistmatch);
void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes);
diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 33a4646..9f94b0c 100644
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -35,11 +35,6 @@
func pmu_cpuson_entrypoint
pmu_cpuson_entrypoint_start:
ldr x5, psram_data
- ldr w0, [x5, #PSRAM_DT_SYS_MODE]
- cmp w0, #PMU_SYS_SLP_MODE
- b.eq check_wake_cpus
- ldr x6, warm_boot_func
- br x6
check_wake_cpus:
mrs x0, MPIDR_EL1
and x1, x0, #MPIDR_CPU_MASK
@@ -74,8 +69,6 @@
.align 3
psram_data:
.quad PSRAM_DT_BASE
-warm_boot_func:
- .quad platform_cpu_warmboot
sys_wakeup_entry:
.quad psci_entrypoint
pmu_cpuson_entrypoint_end: