rockchip: support the suspend/resume for rk3399
This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index a90dcd7..1bbb614 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -189,6 +189,7 @@
* cpus online or resume enterpoint
* --------------------------------------------------------------------
*/
+ .align 16
func platform_cpu_warmboot
mrs x0, MPIDR_EL1
and x1, x0, #MPIDR_CPU_MASK
@@ -207,12 +208,6 @@
add x4, x4, x0, lsl #2
ldr w1, [x4]
/* --------------------------------------------------------------------
- * get per cpuup boot addr
- * --------------------------------------------------------------------
- */
- adr x5, cpuson_entry_point
- ldr x2, [x5, x0, lsl #3]
- /* --------------------------------------------------------------------
* check cpuon reason
* --------------------------------------------------------------------
*/
@@ -231,8 +226,15 @@
wfe
b wfe_loop
boot_entry:
- mov w0, #0
- str w0, [x4]
+ mov w1, #0
+ str w1, [x4]
+ /* --------------------------------------------------------------------
+ * get per cpuup boot addr
+ * --------------------------------------------------------------------
+ */
+ adr x5, cpuson_entry_point
+ ldr x2, [x5, x0, lsl #3]
+
br x2
endfunc platform_cpu_warmboot
@@ -248,5 +250,5 @@
.endr
cpuson_flags:
.rept PLATFORM_CORE_COUNT
- .quad 0
+ .word 0
.endr
diff --git a/plat/rockchip/common/drivers/pmu/pmu_com.h b/plat/rockchip/common/drivers/pmu/pmu_com.h
index 0cab53c..4cffb61 100644
--- a/plat/rockchip/common/drivers/pmu/pmu_com.h
+++ b/plat/rockchip/common/drivers/pmu/pmu_com.h
@@ -27,13 +27,19 @@
#ifndef __PMU_COM_H__
#define __PMU_COM_H__
+/*
+ * Use this macro to instantiate lock before it is used in below
+ * rockchip_pd_lock_xxx() macros
+ */
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
+/*
+ * These are wrapper macros to the powe domain Bakery Lock API.
+ */
+#define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock)
#define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock)
-
#define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock)
-#define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock)
/*****************************************************************************
* power domain on or off
*****************************************************************************/
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 67fb827..e05bda4 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -77,7 +77,7 @@
#endif
#ifndef BITS_WITH_WMASK
-#define BITS_WITH_WMASK(msk, bits, shift)\
+#define BITS_WITH_WMASK(bits, msk, shift)\
(BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
#endif
@@ -108,6 +108,8 @@
void plat_rockchip_soc_init(void);
void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops);
+void platform_cpu_warmboot(void);
+
extern const unsigned char rockchip_power_domain_tree_desc[];
extern void *pmu_cpuson_entrypoint_start;
diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c
index fcd47a8..43558b6 100644
--- a/plat/rockchip/common/plat_pm.c
+++ b/plat/rockchip/common/plat_pm.c
@@ -52,7 +52,6 @@
static void plat_rockchip_sys_pwr_domain_resume(void)
{
- plat_rockchip_gic_init();
if (rockchip_ops && rockchip_ops->sys_pwr_dm_resume)
rockchip_ops->sys_pwr_dm_resume();
}
@@ -62,8 +61,6 @@
if (rockchip_ops && rockchip_ops->cores_pwr_dm_resume)
rockchip_ops->cores_pwr_dm_resume();
- /* Enable the gic cpu interface */
- plat_rockchip_gic_pcpu_init();
/* Program the gic per-cpu distributor or re-distributor interface */
plat_rockchip_gic_cpuif_enable();
}
diff --git a/plat/rockchip/common/pmusram/pmu_sram.h b/plat/rockchip/common/pmusram/pmu_sram.h
index a2ab460..f290461 100644
--- a/plat/rockchip/common/pmusram/pmu_sram.h
+++ b/plat/rockchip/common/pmusram/pmu_sram.h
@@ -27,21 +27,14 @@
#define __PMU_SRAM_H__
/*****************************************************************************
- * cpu up status
- *****************************************************************************/
-#define PMU_SYS_SLP_MODE 0xa5
-#define PMU_SYS_ON_MODE 0x0
-
-/*****************************************************************************
* define data offset in struct psram_data
*****************************************************************************/
#define PSRAM_DT_SP 0x0
#define PSRAM_DT_DDR_FUNC 0x8
#define PSRAM_DT_DDR_DATA 0x10
#define PSRAM_DT_DDRFLAG 0x18
-#define PSRAM_DT_SYS_MODE 0x1c
-#define PSRAM_DT_MPIDR 0x20
-#define PSRAM_DT_END 0x24
+#define PSRAM_DT_MPIDR 0x1c
+#define PSRAM_DT_END 0x20
/******************************************************************************
* Allocate data region for struct psram_data_t in pmusram
******************************************************************************/
@@ -67,7 +60,6 @@
uint64_t ddr_func;
uint64_t ddr_data;
uint32_t ddr_flag;
- uint32_t sys_mode;
uint32_t boot_mpidr;
};
@@ -81,8 +73,6 @@
assert_psram_dt_ddr_data_offset_mistmatch);
CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG,
assert_psram_dt_ddr_flag_offset_mistmatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, sys_mode) == PSRAM_DT_SYS_MODE,
- assert_psram_dt_sys_mode_offset_mistmatch);
CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR,
assert_psram_dt_mpidr_offset_mistmatch);
void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes);
diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 33a4646..9f94b0c 100644
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -35,11 +35,6 @@
func pmu_cpuson_entrypoint
pmu_cpuson_entrypoint_start:
ldr x5, psram_data
- ldr w0, [x5, #PSRAM_DT_SYS_MODE]
- cmp w0, #PMU_SYS_SLP_MODE
- b.eq check_wake_cpus
- ldr x6, warm_boot_func
- br x6
check_wake_cpus:
mrs x0, MPIDR_EL1
and x1, x0, #MPIDR_CPU_MASK
@@ -74,8 +69,6 @@
.align 3
psram_data:
.quad PSRAM_DT_BASE
-warm_boot_func:
- .quad platform_cpu_warmboot
sys_wakeup_entry:
.quad psci_entrypoint
pmu_cpuson_entrypoint_end: