Merge changes from topic "nrd1_refactor" into integration
* changes:
feat(rdn1edge): remove RD-N1-Edge from deprecated list
feat(sgi575): remove SGI-575 from deprecated list
fix(rdn1edge): update RD-N1-Edge's changelog title
feat(neoverse-rd): add scope for RD-V1-MC
feat(neoverse-rd): add scope for RD-V1
feat(neoverse-rd): add scope for SGI-575
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for A75/V1/N1 platforms
feat(neoverse-rd): enable AMU if supported by the platform
refactor(neoverse-rd): clean-up nrd_plat_arm_def1.h file
refactor(neoverse-rd): remove unused defines from platform_def.h
refactor(neoverse-rd): move defines out of platform_def.h
refactor(neoverse-rd): rename definitions in nrd_ros_fw_def1.h file
refactor(neoverse-rd): rename definitions in nrd_ros_def1.h file
refactor(neoverse-rd): rename definitions in nrd_css_fw_def1.h file
refactor(neoverse-rd): rename definitions in nrd_css_def1.h file
refactor(neoverse-rd): rewrite CSS and RoS device mmap macros
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
refactor(neoverse-rd): migrate mmap entry from nrd_plat1.c
refactor(neoverse-rd): rename nrd_plat.c file
refactor(neoverse-rd): refactor nrd_soc_css_def.h file
refactor(neoverse-rd): refactor nrd_soc_platform_def.h file
refactor(neoverse-rd): move away from nrd_base_platform_def.h
refactor(neoverse-rd): remove inclusion of nrd_base_platform_def.h
refactor(neoverse-rd): header files for first generation platforms
refactor(neoverse-rd): refactor scope for Neoverse RD platforms
diff --git a/changelog.yaml b/changelog.yaml
index b7f281c..bfcfcdb 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -215,26 +215,28 @@
- title: N1SDP
scope: n1sdp
- - title: RD
- scope: rd
+ - title: Neoverse-RD
+ scope: neoverse-rd
subsections:
- - title: RD-N1 Edge
+ - title: SGI-575
+ scope: sgi575
+
+ - title: RD-N1-Edge
scope: rdn1edge
+ - title: RD-V1
+ scope: rdv1
+
+ - title: RD-V1-MC
+ scope: rdv1mc
+
- title: RD-N2
scope: rdn2
deprecated:
- board/rdn2
- - title: SGI
- scope: sgi
-
- deprecated:
- - plat/sgi
- - plat/arm/sgi
-
- title: TC
scope: tc
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 12afa44..702726e 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -70,9 +70,8 @@
+----------------+----------------+--------------------+--------------------+
| Platform | Vendor | Deprecated version | Deleted version |
+================+================+====================+====================+
-| sgi575 | Arm | 2.8 | TBD |
-+----------------+----------------+--------------------+--------------------+
-| rdn1edge | Arm | 2.8 | TBD |
+| None at this | | | |
+| time. | | | |
+----------------+----------------+--------------------+--------------------+
--------------
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
new file mode 100644
index 0000000..74835f6
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the CSS specific memory and interrupt map
+ * definitions for the first generation platforms based on the A75, N1 and V1
+ * CPUs. There are minor differences in the memory map of these platforms and
+ * those differences are not in the scope of this file.
+ */
+
+#ifndef NRD_CSS_DEF1_H
+#define NRD_CSS_DEF1_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* On-Chip ROM */
+#define NRD_CSS_TRUSTED_ROM_BASE UL(0x00000000)
+#define NRD_CSS_TRUSTED_ROM_SIZE UL(0x00080000) /* 512KB */
+
+/* On-Chip RAM */
+#define NRD_CSS_TRUSTED_SRAM_SIZE UL(0x00080000) /* 512KB */
+#define NRD_CSS_NONTRUSTED_SRAM_BASE UL(0x06000000)
+#define NRD_CSS_NONTRUSTED_SRAM_SIZE UL(0x00080000) /* 512KB */
+
+/* PL011 UART */
+#define NRD_CSS_SEC_UART_BASE UL(0x2A410000)
+#define NRD_CSS_UART_SIZE UL(0x10000)
+
+/* CSS peripherals */
+#define NRD_CSS_PERIPH_BASE UL(0x20000000)
+#define NRD_CSS_PERIPH_SIZE UL(0x40000000)
+
+/* Secure Watchdog */
+#define NRD_CSS_WDOG_BASE UL(0x2A480000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_BASE ULL(0x8080000000)
+#define NRD_CSS_DRAM2_SIZE ULL(0x180000000)
+
+#endif /* NRD_CSS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
new file mode 100644
index 0000000..70a7d49
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the CSS firmware specific definitions for
+ * the first generation platforms based on the A75, N1 and V1 CPUs.
+ */
+
+#ifndef NRD1_CSS_FW_DEF1_H
+#define NRD1_CSS_FW_DEF1_H
+
+#include <nrd_css_def1.h>
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */
+
+#if TRUSTED_BOARD_BOOT
+# define NRD_CSS_BL2_SIZE UL(0x28000)
+#else
+# define NRD_CSS_BL2_SIZE UL(0x14000)
+#endif
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
+ * and BL1-RW.
+ */
+#define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
+
+/*******************************************************************************
+ * Watchdog config
+ ******************************************************************************/
+
+#define NRD_CSS_WDOG_TIMEOUT UL(100)
+
+/*******************************************************************************
+ * Platform ID
+ ******************************************************************************/
+
+/* Platform ID address */
+#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
+#ifndef __ASSEMBLER__
+/* SSC_VERSION related accessors */
+/* Returns the part number of the platform */
+#define GET_NRD_PART_NUM \
+ GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
+/* Returns the configuration number of the platform */
+#define GET_NRD_CONFIG_NUM \
+ GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
+#endif /* __ASSEMBLER__ */
+
+/*******************************************************************************
+ * MMU mappings
+ ******************************************************************************/
+
+#define NRD_CSS_PERIPH_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_CSS_PERIPH_BASE, \
+ NRD_CSS_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_CSS_SHARED_RAM_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ ARM_SHARED_RAM_BASE, \
+ ARM_SHARED_RAM_SIZE, \
+ MT_NON_CACHEABLE | MT_RW | MT_SECURE)
+
+#if SPM_MM
+/*
+ * Stand-alone MM logs would be routed via secure UART. Define page table
+ * entry for secure UART which would be common to all platforms.
+ */
+#define NRD_CSS_SECURE_UART_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_CSS_SEC_UART_BASE, \
+ NRD_CSS_UART_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
+#endif /* NRD_CSS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
new file mode 100644
index 0000000..bca095c
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the platform port definitions for the
+ * first generation platforms based on the A75, N1 and V1 CPUs.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF1_H
+#define NRD_PLAT_ARM_DEF1_H
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+#include <plat/common/common_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_ros_fw_def1.h>
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
+ PLAT_ARM_CLUSTER_COUNT * \
+ NRD_MAX_CPUS_PER_CLUSTER * \
+ NRD_MAX_PE_PER_CPU)
+
+/*******************************************************************************
+ * PA/VA config
+ ******************************************************************************/
+
+#ifdef __aarch64__
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#endif
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+#if defined(IMAGE_BL31)
+# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
+# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 3))
+# define PLAT_SP_IMAGE_MMAP_REGIONS U(12)
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES U(14)
+# else
+# define PLAT_ARM_MMAP_ENTRIES (5 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (6 + ((NRD_CHIP_COUNT - 1) * 3))
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES U(8)
+# define MAX_XLAT_TABLES U(5)
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES (11 + (NRD_CHIP_COUNT - 1))
+
+/*
+ * MAX_XLAT_TABLES entries need to be doubled because when the address width
+ * exceeds 40 bits an additional level of translation is required. In case of
+ * multichip platforms peripherals also fall into address space with width
+ * > 40 bits.
+ */
+# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2))
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES U(11)
+# define MAX_XLAT_TABLES U(7)
+#else
+# define PLAT_ARM_MMAP_ENTRIES U(12)
+# define MAX_XLAT_TABLES U(6)
+#endif
+
+/*******************************************************************************
+ * Stack size
+ ******************************************************************************/
+
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE U(0x1000)
+# else
+# define PLATFORM_STACK_SIZE U(0x440)
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE U(0x1000)
+# else
+# define PLATFORM_STACK_SIZE U(0x400)
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE U(0x400)
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+# define PLATFORM_STACK_SIZE U(0x500)
+# else
+# define PLATFORM_STACK_SIZE U(0x400)
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE U(0x440)
+#endif
+
+#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
+/*
+ * Secure partition stack follows right after the memory region that is shared
+ * between EL3 and S-EL0.
+ */
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
+#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0xe000)
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
+#endif
+
+#define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
+ */
+#define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \
+ ((NRD_CHIP_COUNT - 1) * 0x2000))
+
+#define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \
+ PLAT_ARM_MAX_BL2_SIZE + \
+ PLAT_ARM_MAX_BL1_RW_SIZE)
+
+/*******************************************************************************
+ * ROM, SRAM and DRAM config
+ ******************************************************************************/
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_TRUSTED_SRAM_SIZE
+
+#define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_TRUSTED_ROM_BASE
+#define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_TRUSTED_ROM_SIZE
+
+#define PLAT_ARM_NSRAM_BASE NRD_CSS_NONTRUSTED_SRAM_BASE
+#define PLAT_ARM_NSRAM_SIZE NRD_CSS_NONTRUSTED_SRAM_SIZE
+
+#define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE
+#define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * Timer config
+ ******************************************************************************/
+
+#define PLAT_ARM_NSTIMER_FRAME_ID (0)
+
+/*******************************************************************************
+ * Power config
+ ******************************************************************************/
+
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*******************************************************************************
+ * Flash config
+ ******************************************************************************/
+
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+/* IO storage framework */
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+/*******************************************************************************
+ * SCMI config
+ ******************************************************************************/
+
+/* Number of SCMI channels on the platform */
+#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
+
+/*******************************************************************************
+ * SDS config
+ ******************************************************************************/
+
+/* Index of SDS region used in the communication with SCP */
+#define SDS_SCP_AP_REGION_ID U(0)
+/* SDS ID for unusable CPU MPID list structure */
+#define SDS_ISOLATED_CPU_LIST_ID U(128)
+
+/*******************************************************************************
+ * GIC/EHF config
+ ******************************************************************************/
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+#define PLAT_SP_PRI U(0x10)
+
+/*******************************************************************************
+ * Platform type identification macro
+ ******************************************************************************/
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0f)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x0)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
+
+#ifndef __ASSEMBLER__
+#define BOARD_CSS_GET_PLAT_TYPE(addr) \
+ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
+ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+#endif /* __ASSEMBLER__ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_BASE + \
+ UL(0x00fe00e0)
+
+#endif /* NRD_PLAT_ARM_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
new file mode 100644
index 0000000..b86ab21
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS specific definitions for the first
+ * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
+ * is used to refer to the part of the reference design platform that excludes
+ * CSS.
+ */
+
+#ifndef NRD_ROS_DEF1_H
+#define NRD_ROS_DEF1_H
+
+/*******************************************************************************
+ * ROS configs
+ ******************************************************************************/
+
+/* RoS Peripherals */
+#define NRD_ROS_PERIPH_BASE UL(0x60000000)
+#define NRD_ROS_PERIPH_SIZE UL(0x20000000)
+
+/* System Reg */
+#define NRD_ROS_SYSTEMREG_BASE UL(0x1C010000)
+#define NRD_ROS_SYSTEMREG_SIZE UL(0x00010000)
+
+/* NOR Flash 2 */
+#define NRD_ROS_NOR2_FLASH_BASE UL(0x10000000)
+#define NRD_ROS_NOR2_FLASH_SIZE UL(0x04000000)
+
+/* RoS Platform */
+#define NRD_ROS_PLATFORM_BASE UL(0x7F000000)
+#define NRD_ROS_PLATFORM_SIZE UL(0x20000000)
+
+#endif /* NRD_ROS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
new file mode 100644
index 0000000..c521043
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS firmware specific definitions for the
+ * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
+ * System) is used to refer to the part of the reference design platform that
+ * excludes CSS.
+ */
+
+#ifndef NRD_ROS_FW_DEF1_H
+#define NRD_ROS_FW_DEF1_H
+
+#include <nrd_ros_def1.h>
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_ROS_PERIPH_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_ROS_PERIPH_BASE, \
+ NRD_ROS_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_ROS_SYSTEMREG_BASE, \
+ NRD_ROS_SYSTEMREG_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define NRD_ROS_SECURE_NOR2_USER_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_ROS_NOR2_FLASH_BASE, \
+ NRD_ROS_NOR2_FLASH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define NRD_MAP_FLASH0_RO \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+/*******************************************************************************
+ * TZ config
+ ******************************************************************************/
+
+/*
+ * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
+ * where both the DRAM regions are marked for non-secure access. This applies
+ * to multi-chip platforms.
+ */
+#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n) \
+ {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
+ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
+ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
+
+#endif /* NRD_ROS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def.h
deleted file mode 100644
index 7c1f5ae..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_CSS_DEF_H
-#define NRD_SOC_CSS_DEF_H
-
-#include <lib/utils_def.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-#include <plat/common/common_def.h>
-
-/*
- * Definitions common to all ARM CSSv1-based development platforms
- */
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x7ffe00e0)
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
-#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
-
-#ifndef __ASSEMBLER__
-
-#include <lib/mmio.h>
-
-#define BOARD_CSS_GET_PLAT_TYPE(addr) \
- ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
- >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-
-#endif /* __ASSEMBLER__ */
-
-#define MAX_IO_DEVICES 3
-#define MAX_IO_HANDLES 4
-
-/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#endif /* NRD_SOC_CSS_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def.h
deleted file mode 100644
index 0024e49..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_PLATFORM_DEF_H
-#define NRD_SOC_PLATFORM_DEF_H
-
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-
-#include <nrd_base_platform_def.h>
-#include <nrd_soc_css_def.h>
-
-/* Map the System registers to access from S-EL0 */
-#define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000)
-#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000)
-#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \
- CSS_SYSTEMREG_DEVICE_BASE, \
- CSS_SYSTEMREG_DEVICE_SIZE, \
- (MT_DEVICE | MT_RW | \
- MT_SECURE | MT_USER))
-
-/* Map the NOR2 Flash to access from S-EL0 */
-#define CSS_NOR2_FLASH_DEVICE_BASE (0x10000000)
-#define CSS_NOR2_FLASH_DEVICE_SIZE (0x04000000)
-#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \
- CSS_NOR2_FLASH_DEVICE_BASE, \
- CSS_NOR2_FLASH_DEVICE_SIZE, \
- (MT_DEVICE | MT_RW | \
- MT_SECURE | MT_USER))
-
-#endif /* NRD_SOC_PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/common/nrd_image_load.c b/plat/arm/board/neoverse_rd/common/nrd_image_load.c
index 39de0ab..15d90be 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_image_load.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_image_load.c
@@ -14,7 +14,6 @@
#include <plat/common/platform.h>
#include <platform_def.h>
-#include <nrd_base_platform_def.h>
#include <nrd_variant.h>
/*
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat.c b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
similarity index 85%
rename from plat/arm/board/neoverse_rd/common/nrd_plat.c
rename to plat/arm/board/neoverse_rd/common/nrd_plat1.c
index 0c59271..32444f4 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
@@ -17,15 +17,10 @@
#include <plat/common/platform.h>
#include <drivers/arm/sbsa.h>
-#include <nrd_base_platform_def.h>
-
#if SPM_MM
#include <services/spm_mm_partition.h>
#endif
-#define NRD_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
- V2M_FLASH0_SIZE, \
- MT_DEVICE | MT_RO | MT_SECURE)
/*
* Table of regions for different BL stages to map using the MMU.
* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
@@ -37,8 +32,8 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
NRD_MAP_FLASH0_RO,
- NRD_MAP_DEVICE,
- SOC_CSS_MAP_DEVICE,
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PERIPH_MMAP(0),
{0}
};
#endif
@@ -49,17 +44,17 @@
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- NRD_MAP_DEVICE,
- SOC_CSS_MAP_DEVICE,
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PERIPH_MMAP(0),
ARM_MAP_NS_DRAM1,
#if NRD_CHIP_COUNT > 1
- NRD_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_CSS_PERIPH_MMAP(1),
#endif
#if NRD_CHIP_COUNT > 2
- NRD_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_CSS_PERIPH_MMAP(2),
#endif
#if NRD_CHIP_COUNT > 3
- NRD_MAP_DEVICE_REMOTE_CHIP(3),
+ NRD_CSS_PERIPH_MMAP(3),
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
@@ -77,11 +72,11 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
- NRD_MAP_DEVICE,
+ NRD_CSS_PERIPH_MMAP(0),
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
- SOC_CSS_MAP_DEVICE,
+ NRD_ROS_PERIPH_MMAP(0),
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
@@ -90,15 +85,11 @@
#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
- PLAT_ARM_SECURE_MAP_SYSTEMREG,
- PLAT_ARM_SECURE_MAP_NOR2,
- SOC_PLATFORM_SECURE_UART,
- PLAT_ARM_SECURE_MAP_DEVICE,
+ NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
+ NRD_ROS_SECURE_NOR2_USER_MMAP,
+ NRD_CSS_SECURE_UART_MMAP,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
-#if ENABLE_FEAT_RAS && FFH_SUPPORT
- NRD_SP_CPER_BUF_MMAP,
-#endif
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,
{0}
@@ -170,12 +161,12 @@
void plat_arm_secure_wdt_start(void)
{
- sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+ sbsa_wdog_start(NRD_CSS_WDOG_BASE, NRD_CSS_WDOG_TIMEOUT);
}
void plat_arm_secure_wdt_stop(void)
{
- sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+ sbsa_wdog_stop(NRD_CSS_WDOG_BASE);
}
static sds_region_desc_t nrd_sds_regions[] = {
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
index 83590eb..5c27fc3 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
@@ -8,9 +8,14 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
-
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
#include <nrd_sdei.h>
-#include <nrd_soc_platform_def.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define NRD_MAX_CPUS_PER_CLUSTER U(4)
@@ -22,33 +27,14 @@
#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
-/* System power domain level */
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* Maximum number of address bits used per chip */
#define NRD_ADDR_BITS_PER_CHIP U(42)
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
#define RDN1E1_CHIP0_SPI_START U(32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
index 8f21314..15fc9bb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
-
# GIC-600 configuration
GICV3_IMPL_GIC600_MULTICHIP := 1
@@ -13,11 +11,12 @@
RDN1EDGE_BASE = plat/arm/board/neoverse_rd/platform/rdn1edge
-PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/
+PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
+ -I${RDN1EDGE_BASE}/include/
NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
BL1_SOURCES += ${NRD_CPU_SOURCES} \
${RDN1EDGE_BASE}/rdn1edge_err.c
@@ -73,6 +72,7 @@
endif
override CTX_INCLUDE_AARCH32_REGS := 0
+override SPMD_SPM_AT_SEL2 := 0
# Enable the flag since RD-N1-EDGE has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
index 0c6756c..1a6bed6 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
@@ -10,13 +10,12 @@
#include <plat/common/platform.h>
#include <nrd_plat.h>
-#include <nrd_soc_platform_def.h>
#if defined(IMAGE_BL31)
static const mmap_region_t rdn1edge_dynamic_mmap[] = {
- ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- NRD_MAP_DEVICE_REMOTE_CHIP(1),
- SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
+ NRD_CSS_SHARED_RAM_MMAP(1),
+ NRD_CSS_PERIPH_MMAP(1),
+ NRD_ROS_PERIPH_MMAP(1)
};
static struct gic600_multichip_data rdn1e1_multichip_data __init = {
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
index f889561..cd40117 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
@@ -8,8 +8,13 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
-#include <nrd_soc_platform_def.h>
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define NRD_MAX_CPUS_PER_CLUSTER U(1)
@@ -18,9 +23,6 @@
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
@@ -49,20 +51,8 @@
/* Maximum number of address bits used per chip */
#define NRD_ADDR_BITS_PER_CHIP U(42)
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
index 0950df2..fe87779 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
@@ -10,11 +10,12 @@
RDV1_BASE = plat/arm/board/neoverse_rd/platform/rdv1
-PLAT_INCLUDES += -I${RDV1_BASE}/include/
+PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
+ -I${RDV1_BASE}/include/
NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
BL1_SOURCES += ${NRD_CPU_SOURCES} \
${RDV1_BASE}/rdv1_err.c
@@ -57,7 +58,8 @@
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
-override ENABLE_FEAT_AMU := 1
+override ENABLE_FEAT_AMU := 2
+override SPMD_SPM_AT_SEL2 := 0
ifneq ($(NRD_PLATFORM_VARIANT),0)
$(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
index 3e7c9b5..2cec57c 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
@@ -8,7 +8,13 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
-#include <nrd_soc_platform_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#define PLAT_ARM_CLUSTER_COUNT U(4)
#define NRD_MAX_CPUS_PER_CLUSTER U(1)
@@ -17,9 +23,6 @@
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
@@ -49,15 +52,8 @@
/* Remote chip address offset (4TB per chip) */
#define NRD_ADDR_BITS_PER_CHIP U(42)
-/* Physical and virtual address space limits for MMU in AARCH64 mode */
-#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000)
#define RDV1MC_CHIP0_SPI_START U(32)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
index 9d878c3..a0a1204 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
@@ -11,11 +11,12 @@
RDV1MC_BASE = plat/arm/board/neoverse_rd/platform/rdv1mc
-PLAT_INCLUDES += -I${RDV1MC_BASE}/include/
+PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
+ -I${RDV1MC_BASE}/include/
NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
BL1_SOURCES += ${NRD_CPU_SOURCES} \
${RDV1MC_BASE}/rdv1mc_err.c
@@ -68,7 +69,8 @@
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
-override ENABLE_FEAT_AMU := 1
+override ENABLE_FEAT_AMU := 2
+override SPMD_SPM_AT_SEL2 := 0
ifneq ($(NRD_PLATFORM_VARIANT),0)
$(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
index 4455ec4..e316a1c 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
@@ -10,22 +10,21 @@
#include <plat/common/platform.h>
#include <nrd_plat.h>
-#include <nrd_soc_platform_def.h>
#if defined(IMAGE_BL31)
static const mmap_region_t rdv1mc_dynamic_mmap[] = {
- ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
- NRD_MAP_DEVICE_REMOTE_CHIP(1),
- SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
+ NRD_CSS_SHARED_RAM_MMAP(1),
+ NRD_CSS_PERIPH_MMAP(1),
+ NRD_ROS_PERIPH_MMAP(1),
#if (NRD_CHIP_COUNT > 2)
- ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
- NRD_MAP_DEVICE_REMOTE_CHIP(2),
- SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
+ NRD_CSS_SHARED_RAM_MMAP(2),
+ NRD_CSS_PERIPH_MMAP(2),
+ NRD_ROS_PERIPH_MMAP(2),
#endif
#if (NRD_CHIP_COUNT > 3)
- ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
- NRD_MAP_DEVICE_REMOTE_CHIP(3),
- SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
+ NRD_CSS_SHARED_RAM_MMAP(3),
+ NRD_CSS_PERIPH_MMAP(3),
+ NRD_ROS_PERIPH_MMAP(3)
#endif
};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
index 7fca31a..1e59831 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
@@ -18,20 +18,20 @@
static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
{
/* TZC memory regions for second chip */
- NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
+ NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
{}
},
#if NRD_CHIP_COUNT > 2
{
/* TZC memory regions for third chip */
- NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
+ NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
{}
},
#endif
#if NRD_CHIP_COUNT > 3
{
/* TZC memory regions for fourth chip */
- NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
+ NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
{}
},
#endif
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
index 9658ee1..0797017 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
@@ -8,9 +8,14 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
-
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
#include <nrd_sdei.h>
-#include <nrd_soc_platform_def.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define NRD_MAX_CPUS_PER_CLUSTER U(4)
@@ -22,28 +27,11 @@
#define SGI575_DMC620_BASE0 UL(0x4e000000)
#define SGI575_DMC620_BASE1 UL(0x4e100000)
-/* System power domain level */
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* Maximum number of address bits used per chip */
#define NRD_ADDR_BITS_PER_CHIP U(36)
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
index d34e555..37306be 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
@@ -4,17 +4,16 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
-
include plat/arm/board/neoverse_rd/common/nrd-common.mk
SGI575_BASE = plat/arm/board/neoverse_rd/platform/sgi575
-PLAT_INCLUDES += -I${SGI575_BASE}/include/
+PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
+ -I${SGI575_BASE}/include/
NRD_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
BL1_SOURCES += ${NRD_CPU_SOURCES} \
${SGI575_BASE}/sgi575_err.c
@@ -65,3 +64,5 @@
$(error "NRD_PLATFORM_VARIANT for SGI575 should always be 0,\
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+
+override SPMD_SPM_AT_SEL2 := 0