| /* |
| * Copyright (C) 2016 Marvell International Ltd. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| * https://spdx.org/licenses |
| */ |
| |
| #ifndef A3700_CONSOLE_H |
| #define A3700_CONSOLE_H |
| |
| /* MVEBU UART Registers */ |
| #define UART_RX_REG 0x00 |
| #define UART_TX_REG 0x04 |
| #define UART_CTRL_REG 0x08 |
| #define UART_STATUS_REG 0x0c |
| #define UART_BAUD_REG 0x10 |
| #define UART_POSSR_REG 0x14 |
| |
| /* FIFO Control Register bits */ |
| #define UARTFCR_FIFOMD_16450 (0 << 6) |
| #define UARTFCR_FIFOMD_16550 (1 << 6) |
| #define UARTFCR_RXTRIG_1 (0 << 6) |
| #define UARTFCR_RXTRIG_4 (1 << 6) |
| #define UARTFCR_RXTRIG_8 (2 << 6) |
| #define UARTFCR_RXTRIG_16 (3 << 6) |
| #define UARTFCR_TXTRIG_1 (0 << 4) |
| #define UARTFCR_TXTRIG_4 (1 << 4) |
| #define UARTFCR_TXTRIG_8 (2 << 4) |
| #define UARTFCR_TXTRIG_16 (3 << 4) |
| #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ |
| #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ |
| #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ |
| #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ |
| |
| /* Line Control Register bits */ |
| #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ |
| #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ |
| #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ |
| #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ |
| #define UARTLCR_PAR (1 << 3) /* Parity */ |
| #define UARTLCR_STOP (1 << 2) /* Stop Bit */ |
| #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ |
| #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ |
| #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ |
| #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ |
| |
| /* Line Status Register bits */ |
| #define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */ |
| |
| /* UART Control Register bits */ |
| #define UART_CTRL_RXFIFO_RESET (1 << 14) |
| #define UART_CTRL_TXFIFO_RESET (1 << 15) |
| #define UARTLSR_TXFIFOEMPTY (1 << 6) |
| |
| #endif /* A3700_CONSOLE_H */ |