| /* |
| * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <drivers/arm/gicv2.h> |
| #include <drivers/arm/gic_common.h> |
| #include <platform_def.h> |
| |
| static const interrupt_prop_t qemu_interrupt_props[] = { |
| PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), |
| PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) |
| }; |
| |
| static const struct gicv2_driver_data plat_gicv2_driver_data = { |
| .gicd_base = GICD_BASE, |
| .gicc_base = GICC_BASE, |
| .interrupt_props = qemu_interrupt_props, |
| .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), |
| }; |
| |
| void plat_qemu_gic_init(void) |
| { |
| /* Initialize the gic cpu and distributor interfaces */ |
| gicv2_driver_init(&plat_gicv2_driver_data); |
| gicv2_distif_init(); |
| gicv2_pcpu_distif_init(); |
| gicv2_cpuif_enable(); |
| } |
| |
| void qemu_pwr_gic_on_finish(void) |
| { |
| /* TODO: This setup is needed only after a cold boot */ |
| gicv2_pcpu_distif_init(); |
| |
| /* Enable the gic cpu interface */ |
| gicv2_cpuif_enable(); |
| } |
| |
| void qemu_pwr_gic_off(void) |
| { |
| gicv2_cpuif_disable(); |
| } |