Merge "fix(xilinx): check proc variable before use" into integration

commit: 3465757b7f96990e9edb7274dec773b29d7cd9fb [log] [tgz]
author: Joanna Farley <joanna.farley@arm.com> Thu May 02 09:28:03 2024 +0200
committer: TrustedFirmware Code Review <review@review.trustedfirmware.org> Thu May 02 09:28:03 2024 +0200
tree: e4d7d40470317469652b688cd5e0c03e0f5f1a04
parent: fa2c4000db45dc3b6503722bb22b5a860471a9f8 [diff]
parent: b8eca3b349578e40eb9675de1f395055cbdf07af [diff]
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 6fe5511..1dfdc45 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -39,27 +39,6 @@
 #endif
 
 /*******************************************************************************
- * Helper utility to calculate the BL2 memory layout taking into consideration
- * the BL1 RW data assuming that it is at the top of the memory layout.
- ******************************************************************************/
-void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
-			meminfo_t *bl2_mem_layout)
-{
-	assert(bl1_mem_layout != NULL);
-	assert(bl2_mem_layout != NULL);
-
-	/*
-	 * Remove BL1 RW data from the scope of memory visible to BL2.
-	 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
-	 */
-	assert(BL1_RW_BASE > bl1_mem_layout->total_base);
-	bl2_mem_layout->total_base = bl1_mem_layout->total_base;
-	bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
-
-	flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
-}
-
-/*******************************************************************************
  * Setup function for BL1.
  ******************************************************************************/
 void bl1_setup(void)

diff --git a/changelog.yaml b/changelog.yaml
index b7f281c..aebb792 100644
--- a/changelog.yaml
+++ b/changelog.yaml

@@ -215,26 +215,28 @@
           - title: N1SDP
             scope: n1sdp
 
-          - title: RD
-            scope: rd
+          - title: Neoverse-RD
+            scope: neoverse-rd
 
             subsections:
-              - title: RD-N1 Edge
+              - title: SGI-575
+                scope: sgi575
+
+              - title: RD-N1-Edge
                 scope: rdn1edge
 
+              - title: RD-V1
+                scope: rdv1
+
+              - title: RD-V1-MC
+                scope: rdv1mc
+
               - title: RD-N2
                 scope: rdn2
 
                 deprecated:
                   - board/rdn2
 
-          - title: SGI
-            scope: sgi
-
-            deprecated:
-              - plat/sgi
-              - plat/arm/sgi
-
           - title: TC
             scope: tc
 
@@ -955,11 +957,12 @@
             deprecated:
               - drivers/arm/mhu
 
-          - title: RSS
-            scope: rss
+          - title: RSE
+            scope: rse
 
             deprecated:
               - drivers/arm/rss
+              - rss
 
           - title: TZC
             scope: tzc

diff --git a/docs/about/features.rst b/docs/about/features.rst
index c12509d..9b7bdf9 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst

@@ -128,7 +128,7 @@
 in a platform:
 
 -  MPU translation library ``lib/xlat_mpu``
--  RSS comms driver ``drivers/arm/rss``
+-  RSE comms driver ``drivers/arm/rse``
 
 Still to come
 -------------

diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 6d34339..66ec176 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst

@@ -337,12 +337,12 @@
 :|F|: include/drivers/arm/mhu.h
 :|F|: drivers/arm/mhu
 
-Runtime Security Subsystem (RSS) comms driver
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Runtime Security Engine (RSE) comms driver
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: David Vincze <david.vincze@arm.com>
 :|G|: `davidvincze`_
-:|F|: include/drivers/arm/rss_comms.h
-:|F|: drivers/arm/rss
+:|F|: include/drivers/arm/rse_comms.h
+:|F|: drivers/arm/rse
 
 Libfdt wrappers
 ^^^^^^^^^^^^^^^
@@ -524,6 +524,8 @@
 :|G|: `thomas-arm`_
 :|M|: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
 :|G|: `vijayenthiran-arm`_
+:|M|: Rohit Mathew <Rohit.Mathew@arm.com>
+:|G|: `rohit-arm`_
 :|F|: plat/arm/board/neoverse_rd/common
 :|F|: plat/arm/board/neoverse_rd/platform/rdn1edge/
 :|F|: plat/arm/board/neoverse_rd/platform/rdn2/
@@ -800,10 +802,12 @@
 :|G|: `jwerner-chromium`_
 :|F|: plat/rockchip/
 
-STM32MP1 platform port
-^^^^^^^^^^^^^^^^^^^^^^
+STMicroelectronics platform ports
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Yann Gautier <yann.gautier@st.com>
 :|G|: `Yann-lms`_
+:|M|: Maxime Méré <maxime.mere@foss.st.com>
+:|G|: `meremST`_
 :|F|: docs/plat/st/*
 :|F|: docs/plat/stm32mp1.rst
 :|F|: drivers/st/
@@ -811,6 +815,7 @@
 :|F|: include/drivers/st/
 :|F|: include/dt-bindings/\*/stm32\*
 :|F|: plat/st/
+:|F|: tools/fiptool/plat_fiptool/st/
 :|F|: tools/stm32image/
 
 Synquacer platform port
@@ -955,95 +960,97 @@
 :|G|: `CJKay`_
 :|F|: tools/conventional-changelog-tf-a
 
+.. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
+.. _Akshay-Belsare: https://github.com/Akshay-Belsare
 .. _AlexeiFedorov: https://github.com/AlexeiFedorov
+.. _amit-nagal: https://github.com/amit-nagal
 .. _andersdellien-arm: https://github.com/andersdellien-arm
 .. _Andre-ARM: https://github.com/Andre-ARM
 .. _Anson-Huang: https://github.com/Anson-Huang
+.. _anukou: https://github.com/anukou
+.. _arugan02: https://github.com/arugan02
+.. _arve-android: https://github.com/arve-android
+.. _avifishman: https://github.com/avifishman
+.. _b49020: https://github.com/b49020
+.. _BenjaminLimJL: https://github.com/BenjaminLimJL
 .. _bijucdas: https://github.com/bijucdas
+.. _bipinravi-arm: https://github.com/bipinravi-arm
 .. _bryanodonoghue: https://github.com/bryanodonoghue
-.. _b49020: https://github.com/b49020
+.. _bytefire: https://github.com/bytefire
 .. _carlocaione: https://github.com/carlocaione
+.. _chandnich: https://github.com/chandnich
+.. _ChiaweiW: https://github.com/chiaweiw
+.. _CJKay: https://github.com/cjkay
 .. _danh-arm: https://github.com/danh-arm
 .. _davidvincze: https://github.com/davidvincze
 .. _etienne-lms: https://github.com/etienne-lms
 .. _glneo: https://github.com/glneo
 .. _grandpaul: https://github.com/grandpaul
+.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
+.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
 .. _hzhuang1: https://github.com/hzhuang1
 .. _JackyBai: https://github.com/JackyBai
+.. _J-Alves: https://github.com/J-Alves
+.. _jason-ch-chen: https://github.com/jason-ch-chen
+.. _javieralso-arm: https://github.com/javieralso-arm
+.. _jayanthchidanand-arm: https://github.com/jayanthchidanand-arm
 .. _jcorbier: https://github.com/jcorbier
 .. _jenswi-linaro: https://github.com/jenswi-linaro
+.. _JiafeiPan: https://github.com/JiafeiPan
+.. _jimmy-brisson: https://github.com/theotherjimmy
+.. _joannafarley-arm: https://github.com/joannafarley-arm
 .. _jslater8: https://github.com/jslater8
 .. _jwerner-chromium: https://github.com/jwerner-chromium
 .. _kostapr: https://github.com/kostapr
 .. _lachitp: https://github.com/lachitp
+.. _laurenw-arm: https://github.com/laurenw-arm
+.. _leon-chen-mtk: https://github.com/leon-chen-mtk
+.. _linyidi: https://github.com/linyidi
+.. _madhukar-Arm: https://github.com/madhukar-Arm
+.. _manish-pandey-arm: https://github.com/manish-pandey-arm
+.. _ManishVB-Arm: https://github.com/ManishVB-Arm
+.. _marcbonnici: https://github.com/marcbonnici
+.. _marcone: https://github.com/marcone
+.. _mardyk01: https://github.com/mardyk01
 .. _marex: https://github.com/marex
 .. _masahir0y: https://github.com/masahir0y
 .. _masahisak: https://github.com/masahisak
+.. _max-shvetsov: https://github.com/max-shvetsov
+.. _meremST: https://github.com/meremST
 .. _michalsimek: https://github.com/michalsimek
 .. _mmind: https://github.com/mmind
 .. _MrVan: https://github.com/MrVan
 .. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen
-.. _leon-chen-mtk: https://github.com/leon-chen-mtk
-.. _jason-ch-chen: https://github.com/jason-ch-chen
-.. _linyidi: https://github.com/linyidi
+.. _Neal-liu: https://github.com/neal-liu
 .. _niej: https://github.com/niej
+.. _nmenon: https://github.com/nmenon
 .. _npoushin: https://github.com/npoushin
+.. _odeprez: https://github.com/odeprez
+.. _pangupta: https://github.com/pangupta
 .. _prabhakarlad: https://github.com/prabhakarlad
 .. _quic_mkf: https://github.com/quicmkf
+.. _raghuncstate: https://github.com/raghuncstate
+.. _raymo200915: https://github.com/raymo200915
 .. _remi-triplefault: https://github.com/repk
 .. _rockchip-linux: https://github.com/rockchip-linux
+.. _rohit-arm: https://github.com/rohit-arm
+.. _rupsin01: https://github.com/rupsin01
+.. _rutigl: https://github.com/rutigl
 .. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
 .. _sgorecha: https://github.com/sgorecha
 .. _shawnguo2: https://github.com/shawnguo2
+.. _sieumunt: https://github.com/sieumunt
 .. _smaeul: https://github.com/smaeul
 .. _soby-mathew: https://github.com/soby-mathew
 .. _sreekare: https://github.com/sreekare
 .. _stefanasimion: https://github.com/stefanasimion
 .. _stephan-gh: https://github.com/stephan-gh
-.. _sieumunt: https://github.com/sieumunt
-.. _BenjaminLimJL: https://github.com/BenjaminLimJL
 .. _thomas-arm: https://github.com/thomas-arm
 .. _TonyXie06: https://github.com/TonyXie06
 .. _TravMurav: https://github.com/TravMurav
-.. _vwadekar: https://github.com/vwadekar
-.. _Yann-lms: https://github.com/Yann-lms
-.. _manish-pandey-arm: https://github.com/manish-pandey-arm
-.. _mardyk01: https://github.com/mardyk01
-.. _odeprez: https://github.com/odeprez
-.. _bipinravi-arm: https://github.com/bipinravi-arm
-.. _joannafarley-arm: https://github.com/joannafarley-arm
-.. _ManishVB-Arm: https://github.com/ManishVB-Arm
-.. _max-shvetsov: https://github.com/max-shvetsov
-.. _javieralso-arm: https://github.com/javieralso-arm
-.. _laurenw-arm: https://github.com/laurenw-arm
-.. _J-Alves: https://github.com/J-Alves
-.. _madhukar-Arm: https://github.com/madhukar-Arm
-.. _raghuncstate: https://github.com/raghuncstate
-.. _CJKay: https://github.com/cjkay
-.. _nmenon: https://github.com/nmenon
-.. _anukou: https://github.com/anukou
-.. _chandnich: https://github.com/chandnich
-.. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
-.. _vishnu-banavath: https://github.com/vishnu-banavath
-.. _vijayenthiran-arm: https://github.com/vijayenthiran-arm
-.. _arugan02: https://github.com/arugan02
 .. _uarif1: https://github.com/uarif1
-.. _pangupta: https://github.com/pangupta
-.. _JiafeiPan: https://github.com/JiafeiPan
-.. _arve-android: https://github.com/arve-android
-.. _marcone: https://github.com/marcone
-.. _marcbonnici: https://github.com/marcbonnici
-.. _jayanthchidanand-arm: https://github.com/jayanthchidanand-arm
-.. _bytefire: https://github.com/bytefire
-.. _rupsin01: https://github.com/rupsin01
-.. _jimmy-brisson: https://github.com/theotherjimmy
-.. _ChiaweiW: https://github.com/chiaweiw
-.. _Neal-liu: https://github.com/neal-liu
-.. _amit-nagal: https://github.com/amit-nagal
-.. _Akshay-Belsare: https://github.com/Akshay-Belsare
-.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
-.. _rutigl: https://github.com/rutigl
-.. _avifishman: https://github.com/avifishman
+.. _vijayenthiran-arm: https://github.com/vijayenthiran-arm
+.. _vishnu-banavath: https://github.com/vishnu-banavath
+.. _vwadekar: https://github.com/vwadekar
 .. _xueliang-zhong-arm: https://github.com/xueliang-zhong-arm
-.. _raymo200915: https://github.com/raymo200915
-.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
+.. _Yann-lms: https://github.com/Yann-lms

diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index ab0bc6f..a5fd1d6 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst

@@ -101,6 +101,19 @@
 | None at this time.             |             |         |                                                         |
 +--------------------------------+-------------+---------+---------------------------------------------------------+
 
+Build Options deprecated/removed
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Populated table provides details about build options that were removed or deprecated.
+
++-----------------------+--------------------------------+
+| Build Option          | Deprecated from TF-A Version   |
++=======================+================================+
+| CTX_INCLUDE_MTE_REGS  | 2.11                           |
++-----------------------+--------------------------------+
+| ENABLE_FEAT_MTE       | 2.11                           |
++-----------------------+--------------------------------+
+
 --------------
 
 *Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.*

diff --git a/docs/components/fconf/index.rst b/docs/components/fconf/index.rst
index 029f324..b8b4519 100644
--- a/docs/components/fconf/index.rst
+++ b/docs/components/fconf/index.rst

@@ -147,3 +147,4 @@
   fconf_properties
   amu-bindings
   mpmm-bindings
+  tb_fw_bindings

diff --git a/docs/components/fconf/tb_fw_bindings.rst b/docs/components/fconf/tb_fw_bindings.rst
new file mode 100644
index 0000000..aee3b8d
--- /dev/null
+++ b/docs/components/fconf/tb_fw_bindings.rst

@@ -0,0 +1,159 @@
+Trusted Boot Firmware Configuration bindings
+============================================
+
+This document defines the nodes and properties used to define the Trusted-Boot
+firmware configuration. Platform owners are advised to define shared bindings
+here. If a binding does not generalize, they should be documented
+alongside platform documentation. There is no guarantee of backward
+compatibility with the nodes and properties outlined in this context.
+
+Trusted Boot Firmware Configuration
+-----------------------------------
+
+- compatible [mandatory]
+   - value type: <string>
+   - Should be the string ``"<plat>,tb_fw"``, where ``<plat>`` is the name of the
+     platform (i.e. ``"arm,tb_fw"``).
+
+- disable_auth [mandatory]
+   - value type: <u32>
+   - Flag used to dynamically disable authentication for development purposes.
+     Has two possible values: 0 or 1. Setting the flag to 1 disables
+     authentication.
+
+- mbedtls_heap_addr [mandatory]
+   - value type: <u64>
+   - Base address of the dynamically allocated Mbed TLS heap. This is given as a placeholder.
+
+- mbedtls_heap_size [mandatory]
+   - value type: <u32>
+   - Size of the Mbed TLS heap.
+
+IO FIP Handles
+--------------
+
+- compatible [mandatory]
+   - value type: <string>
+   - Should be the string ``"<plat>,io-fip-handle"``, where ``<plat>`` is the name of the
+     platform (i.e. ``"arm,io-fip-handle"``).
+
+- scp_bl2_uuid [mandatory]
+   - value type: <string>
+   - SCP Firmware SCP_BL2 UUID
+
+- bl31_uuid [mandatory]
+   - value type: <string>
+   - EL3 Runtime Firmware BL31 UUID
+
+- bl32_uuid [mandatory]
+   - value type: <string>
+   - Secure Payload BL32 (Trusted OS) UUID
+
+- bl32_extra1_uuid [mandatory]
+   - value type: <string>
+   - Secure Payload BL32_EXTRA1 (Trusted OS Extra1) UUID
+
+- bl32_extra2_uuid [mandatory]
+   - value type: <string>
+   - Secure Payload BL32_EXTRA2 (Trusted OS Extra2) UUID
+
+- bl33_uuid [mandatory]
+   - value type: <string>
+   - Non-Trusted Firmware BL33 UUID
+
+- hw_cfg_uuid [mandatory]
+   - value type: <string>
+   - HW_CONFIG (e.g. Kernel DT) UUID
+
+- soc_fw_cfg_uuid [mandatory]
+   - value type: <string>
+   - SOC Firmware Configuration SOC_FW_CONFIG UUID
+
+- tos_fw_cfg_uuid [mandatory]
+   - value type: <string>
+   - Trusted OS Firmware Configuration TOS_FW_CONFIG UUID
+
+- nt_fw_cfg_uuid [mandatory]
+   - value type: <string>
+   - Non-Trusted Firmware Configuration NT_FW_CONFIG UUID
+
+- cca_cert_uuid [optional]
+   - value type: <string>
+   - CCA Content Certificate UUID
+
+- core_swd_cert_uuid [optional]
+   - value type: <string>
+   - Core SWD Key Certificate UUID
+
+- plat_cert_uuid [optional]
+   - value type: <string>
+   - Core SWD Key Certificate UUID
+
+- t_key_cert_uuid [optional]
+   - value type: <string>
+   - Trusted Key Certificate UUID
+
+- scp_fw_key_uuid [optional]
+   - value type: <string>
+   - SCP Firmware Key UUID
+
+- soc_fw_key_uuid [optional]
+   - value type: <string>
+   - SOC Firmware Key UUID
+
+- tos_fw_key_cert_uuid [optional]
+   - value type: <string>
+   - TOS Firmware Key UUID
+
+- nt_fw_key_cert_uuid [optional]
+   - value type: <string>
+   - Non-Trusted Firmware Key UUID
+
+- scp_fw_content_cert_uuid [optional]
+   - value type: <string>
+   - SCP Firmware Content Certificate UUID
+
+- soc_fw_content_cert_uuid [optional]
+   - value type: <string>
+   - SOC Firmware Content Certificate UUID
+
+- tos_fw_content_cert_uuid [optional]
+   - value type: <string>
+   - TOS Firmware Content Certificate UUID
+
+- nt_fw_content_cert_uuid [optional]
+   - value type: <string>
+   - Non-Trusted Firmware Content Certificate UUID
+
+- plat_sp_content_cert_uuid [optional]
+   - value type: <string>
+   - Platform Secure Partition Content Certificate UUID
+
+
+Secure Partitions
+-----------------
+
+- compatible [mandatory]
+   - value type: <string>
+   - Should be the string ``"<plat>,sp"``, where ``<plat>`` is the name of the
+     platform (i.e. ``"arm,sp"``).
+
+- uuid [mandatory]
+   - value type: <string>
+   - A string identifying the UUID of the service implemented by this partition.
+     The UUID format is described in RFC 4122.
+
+- load-address [mandatory]
+   - value type: <u32>
+   - Physical base address of the partition in memory. Absence of this field
+     indicates that the partition is position independent and can be loaded at
+     any address chosen at boot time.
+
+- owner [optional]
+   - value type: <string>
+   - A string property representing the name of the owner of the secure
+     partition, which may be the silicon or platform provider.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 5733214..6147c1f 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst

@@ -826,6 +826,13 @@
   feature is enabled and can assist the Kernel in the process of
   mitigation of the erratum.
 
+-  ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4
+   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed
+   in r0p2.
+
+- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4
+  CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
@@ -916,6 +923,10 @@
    Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
    It is fixed in r1p1.
 
+-  ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to
+   Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0
+   and r1p1. It is fixed in r1p2.
+
 For Cortex-A720, the following errata build flags are defined :
 
 -  ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to

diff --git a/docs/design_documents/index.rst b/docs/design_documents/index.rst
index ecc68b2..ac982e0 100644
--- a/docs/design_documents/index.rst
+++ b/docs/design_documents/index.rst

@@ -9,7 +9,7 @@
    context_mgmt_rework
    measured_boot_poc
    drtm_poc
-   rss
+   rse
    psci_osi_mode
    measured_boot
 

diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 8a2ab2d..9dfe494 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst

@@ -91,10 +91,10 @@
    and the variable length crypto agile structure called TCG_PCR_EVENT2. Event
    Log driver implemented in TF-A covers later part.
 
-#. RSS
+#. RSE
 
    It is one of physical backend to extend the measurements. Please refer this
-   document :ref:`Runtime Security Subsystem (RSS)` for more details.
+   document :ref:`Runtime Security Engine (RSE)` for more details.
 
 Platform Interface
 ------------------
@@ -121,7 +121,7 @@
       void bl2_plat_mboot_init(void);
 
    Initialise all Measured Boot backends supported by the platform
-   (e.g. Event Log buffer, RSS). As these functions do not return any value,
+   (e.g. Event Log buffer, RSE). As these functions do not return any value,
    the platform should deal with error management, such as logging the error
    somewhere, or panicking the system if this is considered a fatal error.
 
@@ -147,7 +147,7 @@
 
      - If it is Event Log backend, then record the measurement in TCG Event Log
        format.
-     - If it is a secure crypto-processor (like RSS), then extend the designated
+     - If it is a secure crypto-processor (like RSE), then extend the designated
        PCR (or slot) with the given measurement.
    - This function must return 0 on success, a signed integer error code
      otherwise.
@@ -223,7 +223,7 @@
    - This function must return 0 on success, a signed integer error code
      otherwise.
    - In TC2 platform, this function is used to calculate the hash of the given
-     key and forward this hash to RSS alongside the measurement of the image
+     key and forward this hash to RSE alongside the measurement of the image
      which the key signs.
 
 --------------

diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rse.rst
similarity index 88%
rename from docs/design_documents/rss.rst
rename to docs/design_documents/rse.rst
index 18d5436..7296a45 100644
--- a/docs/design_documents/rss.rst
+++ b/docs/design_documents/rse.rst

@@ -1,45 +1,45 @@
-Runtime Security Subsystem (RSS)
-================================
+Runtime Security Engine (RSE)
+=============================
 
-This document focuses on the relationship between the Runtime Security Subsystem
-(RSS) and the application processor (AP). According to the ARM reference design
-the RSS is an independent core next to the AP and the SCP on the same die. It
+This document focuses on the relationship between the Runtime Security Engine
+(RSE) and the application processor (AP). According to the ARM reference design
+the RSE is an independent core next to the AP and the SCP on the same die. It
 provides fundamental security guarantees and runtime services for the rest of
 the system (e.g.: trusted boot, measured boot, platform attestation,
 key management, and key derivation).
 
-At power up RSS boots first from its private ROM code. It validates and loads
+At power up RSE boots first from its private ROM code. It validates and loads
 its own images and the initial images of SCP and AP. When AP and SCP are
 released from reset and their initial code is loaded then they continue their
-own boot process, which is the same as on non-RSS systems. Please refer to the
-``RSS documentation`` [1]_ for more details about the RSS boot flow.
+own boot process, which is the same as on non-RSE systems. Please refer to the
+``RSE documentation`` [1]_ for more details about the RSE boot flow.
 
-The last stage of the RSS firmware is a persistent, runtime component. Much
+The last stage of the RSE firmware is a persistent, runtime component. Much
 like AP_BL31, this is a passive entity which has no periodical task to do and
-just waits for external requests from other subsystems. RSS and other
-subsystems can communicate with each other over message exchange. RSS waits
+just waits for external requests from other subsystems. RSE and other
+subsystems can communicate with each other over message exchange. RSE waits
 in idle for the incoming request, handles them, and sends a response then goes
 back to idle.
 
-RSS communication layer
+RSE communication layer
 -----------------------
 
-The communication between RSS and other subsystems are primarily relying on the
-Message Handling Unit (MHU) module. The number of MHU interfaces between RSS
+The communication between RSE and other subsystems are primarily relying on the
+Message Handling Unit (MHU) module. The number of MHU interfaces between RSE
 and other cores is IMPDEF. Besides MHU other modules also could take part in
-the communication. RSS is capable of mapping the AP memory to its address space.
-Thereby either RSS core itself or a DMA engine if it is present, can move the
-data between memory belonging to RSS or AP. In this way, a bigger amount of data
+the communication. RSE is capable of mapping the AP memory to its address space.
+Thereby either RSE core itself or a DMA engine if it is present, can move the
+data between memory belonging to RSE or AP. In this way, a bigger amount of data
 can be transferred in a short time.
 
 The MHU comes in pairs. There is a sender and receiver side. They are connected
 to each other. An MHU interface consists of two pairs of MHUs, one sender and
 one receiver on both sides. Bidirectional communication is possible over an
-interface. One pair provides message sending from AP to RSS and the other pair
-from RSS to AP. The sender and receiver are connected via channels. There is an
+interface. One pair provides message sending from AP to RSE and the other pair
+from RSE to AP. The sender and receiver are connected via channels. There is an
 IMPDEF number of channels (e.g: 4-16) between a sender and a receiver module.
 
-The RSS communication layer provides two ways for message exchange:
+The RSE communication layer provides two ways for message exchange:
 
 - ``Embedded messaging``: The full message, including header and payload, are
   exchanged over the MHU channels. A channel is capable of delivering a single
@@ -55,16 +55,16 @@
 - ``Pointer-access messaging``: The message header and the payload are
   separated and they are conveyed in different ways. The header is sent
   over the channels, similar to the embedded messaging but the payload is
-  copied over by RSS core (or by DMA) between the sender and the receiver. This
+  copied over by RSE core (or by DMA) between the sender and the receiver. This
   could be useful in the case of long messages because transaction time is less
-  compared to the embedded messaging mode. Small payloads are copied by the RSS
+  compared to the embedded messaging mode. Small payloads are copied by the RSE
   core because setting up DMA would require more CPU cycles. The payload is
-  either copied into an internal buffer or directly read-written by RSS. Actual
-  behavior depends on RSS setup, whether the partition supports memory-mapped
+  either copied into an internal buffer or directly read-written by RSE. Actual
+  behavior depends on RSE setup, whether the partition supports memory-mapped
   ``iovec``. Therefore, the sender must handle both cases and prevent access to
-  the memory, where payload data lives, while the RSS handles the request.
+  the memory, where payload data lives, while the RSE handles the request.
 
-The RSS communication layer supports both ways of messaging in parallel. It is
+The RSE communication layer supports both ways of messaging in parallel. It is
 decided at runtime based on the message size which way to transfer the message.
 
 .. code-block:: bash
@@ -93,25 +93,25 @@
              V                           |            | |      V           V
     +----------------------------------------------+  | |  +-------------------+
     |                                              |--+-+  |                   |
-    |                  RSS                         |       |      SRAM         |
+    |                  RSE                         |       |      SRAM         |
     |                                              |       |                   |
     +----------------------------------------------+       +-------------------+
 
 .. Note::
 
-    The RSS communication layer is not prepared for concurrent execution. The
+    The RSE communication layer is not prepared for concurrent execution. The
     current use case only requires message exchange during the boot phase. In
     the boot phase, only a single core is running and the rest of the cores are
     in reset.
 
 Message structure
 ^^^^^^^^^^^^^^^^^
-A description of the message format can be found in the ``RSS communication
+A description of the message format can be found in the ``RSE communication
 design`` [2]_ document.
 
 Source files
 ^^^^^^^^^^^^
-- RSS comms:  ``drivers/arm/rss``
+- RSE comms:  ``drivers/arm/rse``
 - MHU driver: ``drivers/arm/mhu``
 
 
@@ -119,29 +119,29 @@
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 The API is defined in these header files:
 
-- ``include/drivers/arm/rss_comms.h``
+- ``include/drivers/arm/rse_comms.h``
 - ``include/drivers/arm/mhu.h``
 
-RSS provided runtime services
+RSE provided runtime services
 -----------------------------
 
-RSS provides the following runtime services:
+RSE provides the following runtime services:
 
 - ``Measured boot``: Securely store the firmware measurements which were
   computed during the boot process and the associated metadata (image
   description, measurement algorithm, etc.). More info on measured boot service
-  in RSS can be found in the ``measured_boot_integration_guide`` [3]_ .
+  in RSE can be found in the ``measured_boot_integration_guide`` [3]_ .
 - ``Delegated attestation``: Query the platform attestation token and derive a
   delegated attestation key. More info on the delegated attestation service
-  in RSS can be found in the ``delegated_attestation_integration_guide`` [4]_ .
+  in RSE can be found in the ``delegated_attestation_integration_guide`` [4]_ .
 - ``OTP assets management``: Public keys used by AP during the trusted boot
-  process can be requested from RSS. Furthermore, AP can request RSS to
+  process can be requested from RSE. Furthermore, AP can request RSE to
   increase a non-volatile counter. Please refer to the
-  ``RSS key management`` [5]_ document for more details.
+  ``RSE key management`` [5]_ document for more details.
 
 Runtime service API
 ^^^^^^^^^^^^^^^^^^^
-The RSS provided runtime services implement a PSA aligned API. The parameter
+The RSE provided runtime services implement a PSA aligned API. The parameter
 encoding follows the PSA client protocol described in the
 ``Firmware Framework for M`` [6]_ document in chapter 4.4. The implementation is
 restricted to the static handle use case therefore only the ``psa_call`` API is
@@ -168,7 +168,7 @@
          |                               |
          V                               V
     +------------------------------------------------+
-    |         RSS communication protocol             |
+    |         RSE communication protocol             |
     +------------------------------------------------+
          |                     ^
          | mhu_send_data()     | mhu_receive_data()
@@ -188,7 +188,7 @@
                          |
                          V
     +------------------------------------------------+
-    |             MHU HW on RSS side                 |
+    |             MHU HW on RSE side                 |
     +------------------------------------------------+
              |                        ^
              | IRQ                    | Register access
@@ -204,17 +204,17 @@
     +---------------+       +------------------------+
 
 
-RSS based Measured Boot
+RSE based Measured Boot
 -----------------------
 
 Measured Boot is the process of cryptographically measuring (computing the hash
 value of a binary) the code and critical data used at boot time. The
 measurement must be stored in a tamper-resistant way, so the security state
-of the device can be attested later to an external party. RSS provides a runtime
+of the device can be attested later to an external party. RSE provides a runtime
 service which is meant to store measurements and associated metadata alongside.
 
 Data is stored in internal SRAM which is only accessible by the secure runtime
-firmware of RSS. Data is stored in so-called measurement slots. A platform has
+firmware of RSE. Data is stored in so-called measurement slots. A platform has
 IMPDEF number of measurement slots. The measurement storage follows extend
 semantics. This means that measurements are not stored directly (as it was
 taken) instead they contribute to the current value of the measurement slot.
@@ -236,7 +236,7 @@
 .. code-block:: c
 
     psa_status_t
-    rss_measured_boot_extend_measurement(uint8_t        index,
+    rse_measured_boot_extend_measurement(uint8_t        index,
                                          const uint8_t *signer_id,
                                          size_t         signer_id_size,
                                          const uint8_t *version,
@@ -291,27 +291,27 @@
 .. Note::
 
     Extending multiple measurements in the same slot leads to some metadata
-    information loss. Since RSS is not constrained on special HW resources to
+    information loss. Since RSE is not constrained on special HW resources to
     store the measurements and metadata, therefore it is worth considering to
     store all of them one by one in distinct slots. However, they are one-by-one
     included in the platform attestation token. So, the number of distinct
     firmware image measurements has an impact on the size of the attestation
     token.
 
-The allocation of the measurement slot among RSS, Root and Realm worlds is
+The allocation of the measurement slot among RSE, Root and Realm worlds is
 platform dependent. The platform must provide an allocation of the measurement
 slot at build time. An example can be found in
 ``tf-a/plat/arm/board/tc/tc_bl1_measured_boot.c``
 Furthermore, the memory, which holds the metadata is also statically allocated
-in RSS memory. Some of the fields have a static value (measurement algorithm),
+in RSE memory. Some of the fields have a static value (measurement algorithm),
 and some of the values have a dynamic value (measurement value) which is updated
 by the bootloaders when the firmware image is loaded and measured. The metadata
 structure is defined in
-``include/drivers/measured_boot/rss/rss_measured_boot.h``.
+``include/drivers/measured_boot/rse/rse_measured_boot.h``.
 
 .. code-block:: c
 
-    struct rss_mboot_metadata {
+    struct rse_mboot_metadata {
             unsigned int id;
             uint8_t slot;
             uint8_t signer_id[SIGNER_ID_MAX_SIZE];
@@ -328,24 +328,24 @@
 ^^^^^^^^^^^^^
 
 This function calculates the hash of a public key (signer-ID) using the
-``Measurement algorithm`` and stores it in the ``rss_mboot_metadata`` field
+``Measurement algorithm`` and stores it in the ``rse_mboot_metadata`` field
 named ``signer_id``.
 Prior to calling this function, the caller must ensure that the ``signer_id``
 field points to the zero-filled buffer.
 
 Defined here:
 
-- ``include/drivers/measured_boot/rss/rss_measured_boot.h``
+- ``include/drivers/measured_boot/rse/rse_measured_boot.h``
 
 .. code-block:: c
 
-   int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+   int rse_mboot_set_signer_id(struct rse_mboot_metadata *metadata_ptr,
                                const void *pk_oid,
                                const void *pk_ptr,
                                size_t pk_len)
 
 
-- First parameter is the pointer to the ``rss_mboot_metadata`` structure.
+- First parameter is the pointer to the ``rse_mboot_metadata`` structure.
 - Second parameter is the pointer to the key-OID of the public key.
 - Third parameter is the pointer to the public key buffer.
 - Fourth parameter is the size of public key buffer.
@@ -356,15 +356,15 @@
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 
 - ``MEASURED_BOOT``: Enable measured boot. It depends on the platform
-  implementation whether RSS or TPM (or both) backend based measured boot is
+  implementation whether RSE or TPM (or both) backend based measured boot is
   enabled.
-- ``MBOOT_RSS_HASH_ALG``: Determine the hash algorithm to measure the images.
+- ``MBOOT_RSE_HASH_ALG``: Determine the hash algorithm to measure the images.
   The default value is sha-256.
 
 Measured boot flow
 ^^^^^^^^^^^^^^^^^^
 
-.. figure:: ../resources/diagrams/rss_measured_boot_flow.svg
+.. figure:: ../resources/diagrams/rse_measured_boot_flow.svg
   :align: center
 
 Sample console log
@@ -425,15 +425,15 @@
 the ``Delegated Attestation Service Integration Guide`` [4]_ document.
 
 In the CCA use case, the Realm Management Monitor (RMM) relies on the delegated
-attestation service of the RSS to get a realm attestation key and the CCA
+attestation service of the RSE to get a realm attestation key and the CCA
 platform token. BL31 does not use the service for its own purpose, only calls
-it on behalf of RMM. The access to MHU interface and thereby to RSS is
+it on behalf of RMM. The access to MHU interface and thereby to RSE is
 restricted to BL31 only. Therefore, RMM does not have direct access, all calls
 need to go through BL31. The RMM dispatcher module of the BL31 is responsible
 for delivering the calls between the two parties.
 
 .. Note::
-     Currently the connection between the RMM dispatcher and the PSA/RSS layer
+     Currently the connection between the RMM dispatcher and the PSA/RSE layer
      is not yet implemented. RMM dispatcher just returns hard coded data.
 
 Delegated Attestation API
@@ -445,7 +445,7 @@
 .. code-block:: c
 
     psa_status_t
-    rss_delegated_attest_get_delegated_key(uint8_t   ecc_curve,
+    rse_delegated_attest_get_delegated_key(uint8_t   ecc_curve,
                                            uint32_t  key_bits,
                                            uint8_t  *key_buf,
                                            size_t    key_buf_size,
@@ -453,7 +453,7 @@
                                            uint32_t  hash_algo);
 
     psa_status_t
-    rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+    rse_delegated_attest_get_token(const uint8_t *dak_pub_hash,
                                    size_t         dak_pub_hash_size,
                                    uint8_t       *token_buf,
                                    size_t         token_buf_size,
@@ -462,7 +462,7 @@
 Attestation flow
 ^^^^^^^^^^^^^^^^
 
-.. figure:: ../resources/diagrams/rss_attestation_flow.svg
+.. figure:: ../resources/diagrams/rse_attestation_flow.svg
   :align: center
 
 Sample attestation token
@@ -623,27 +623,27 @@
         "CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org"
     }
 
-RSS OTP Assets Management
+RSE OTP Assets Management
 -------------------------
 
-RSS provides access for AP to assets in OTP, which include keys for image
+RSE provides access for AP to assets in OTP, which include keys for image
 signature verification and non-volatile counters for anti-rollback protection.
 
 Non-Volatile Counter API
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
-AP/RSS interface for retrieving and incrementing non-volatile counters API is
+AP/RSE interface for retrieving and incrementing non-volatile counters API is
 as follows.
 
 Defined here:
 
-- ``include/lib/psa/rss_platform_api.h``
+- ``include/lib/psa/rse_platform_api.h``
 
 .. code-block:: c
 
-    psa_status_t rss_platform_nv_counter_increment(uint32_t counter_id)
+    psa_status_t rse_platform_nv_counter_increment(uint32_t counter_id)
 
-    psa_status_t rss_platform_nv_counter_read(uint32_t counter_id,
+    psa_status_t rse_platform_nv_counter_read(uint32_t counter_id,
             uint32_t size, uint8_t *val)
 
 Through this service, we can read/increment any of the 3 non-volatile
@@ -656,15 +656,15 @@
 Public Key API
 ^^^^^^^^^^^^^^
 
-AP/RSS interface for reading the ROTPK is as follows.
+AP/RSE interface for reading the ROTPK is as follows.
 
 Defined here:
 
-- ``include/lib/psa/rss_platform_api.h``
+- ``include/lib/psa/rse_platform_api.h``
 
 .. code-block:: c
 
-    psa_status_t rss_platform_key_read(enum rss_key_id_builtin_t key,
+    psa_status_t rse_platform_key_read(enum rse_key_id_builtin_t key,
             uint8_t *data, size_t data_size, size_t *data_length)
 
 Through this service, we can read any of the 3 ROTPKs used on an
@@ -677,11 +677,11 @@
 References
 ----------
 
-.. [1] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rss/readme.html
-.. [2] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rss/rss_comms.html
+.. [1] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rse/readme.html
+.. [2] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rse/rse_comms.html
 .. [3] https://git.trustedfirmware.org/TF-M/tf-m-extras.git/tree/partitions/measured_boot/measured_boot_integration_guide.rst
 .. [4] https://git.trustedfirmware.org/TF-M/tf-m-extras.git/tree/partitions/delegated_attestation/delegated_attest_integration_guide.rst
-.. [5] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rss/rss_key_management.html
+.. [5] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rse/rse_key_management.html
 .. [6] https://developer.arm.com/-/media/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf?revision=2d1429fa-4b5b-461a-a60e-4ef3d8f7f4b4&hash=3BFD6F3E687F324672F18E5BE9F08EDC48087C93
 .. [7] https://developer.arm.com/documentation/DEN0096/A_a/?lang=en
 

diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 3498ac5..0d4331f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst

@@ -8,32 +8,53 @@
 different from those listed below, however only the software described in this
 document can be officially supported.
 
-Build Host
-----------
+Getting the TF-A Source
+-----------------------
 
-|TF-A| can be compiled on both Linux and Windows-based machines.
-However, we strongly recommend using a UNIX-compatible build environment.
+Source code for |TF-A| is maintained in a Git repository hosted on
+`TrustedFirmware.org`_. To clone this repository from the server, run the following
+in your shell:
 
-Testing is performed using Ubuntu 22.04 LTS (64-bit), but other distributions
-should also work, provided the necessary tools and libraries are installed.
+.. code:: shell
+
+    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
 
-.. _prerequisites_toolchain:
 
-Toolchain
----------
+Requirements
+------------
 
-|TF-A| can be built with any of the following *cross-compiler* toolchains that
-target the Armv7-A or Armv8-A architectures:
+======================== =====================
+        Program          Min supported version
+======================== =====================
+Arm Compiler             6.18
+Arm GNU Compiler         13.2
+Clang/LLVM               11.0.0
+Device Tree Compiler     1.4.7
+GNU make                 3.81
+mbed TLS\ [#f1]_         3.4.1
+Node.js [#f2]_           16
+OpenSSL                  1.0.0
+Poetry [#f2]_            1.3.2
+QCBOR\ [#f3]_            1.2
+Sphinx\ [#f2]_           2.4.4
+======================== =====================
 
-- TF-A has been tested with version 13.2.Rel1 (gcc 13.2) from the `Arm Developer website`_
+.. [#f1] Required for Trusted Board Boot and Measured Boot.
+.. [#f2] Required only for building TF-A documentation.
+.. [#f3] Required only when enabling DICE Protection Environment support.
 
-   You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for
-   AArch32 and AArch64 builds respectively.
+Toolchain
+^^^^^^^^^
 
-- Clang == 14.0.0
-- Arm Compiler == 6.18
+|TF-A| can be compiled using any cross-compiler toolchain specified in the
+preceding table that target Armv7-A or Armv8-A. For AArch32 and
+AArch64 builds, the respective targets required are ``arm-none-eabi`` and
+``aarch64-none-elf``.
 
-In addition, a native compiler is required to build the supporting tools.
+Testing has been performed with version 13.2.Rel1 (gcc 13.2) of the Arm
+GNU compiler, which can be installed from the `Arm Developer website`_.
+
+In addition, a native compiler is required to build supporting tools.
 
 .. note::
    Versions greater than the ones specified are likely but not guaranteed to
@@ -45,74 +66,63 @@
    For instructions on how to select the cross compiler refer to
    :ref:`Performing an Initial Build`.
 
-.. _prerequisites_software_and_libraries:
-
-Software and Libraries
-----------------------
-
-The following tools are required to obtain and build |TF-A|:
-
-- An appropriate toolchain (see :ref:`prerequisites_toolchain`)
-- GNU Make
-- Git
-
-The following libraries must be available to build one or more components or
-supporting tools:
-
-- OpenSSL >= 1.0.0 (1.0.x, v3.0.0 to v3.0.6 highly discouraged due to security issues)
+OpenSSL
+^^^^^^^
 
-   Required to build the cert_create, encrypt_fw, and fiptool tools.
+OpenSSL is required to build the cert_create, encrypt_fw, and fiptool tools.
 
-   .. note::
+If using OpenSSL 3, older Linux versions may require it to be built from
+source code, as it may not be available in the default package repositories.
+Please refer to the OpenSSL project documentation for more information.
 
-    If using OpenSSL 3, older Linux versions may require it to be built from
-    source code, as it may not be available in the default package repositories.
-    Please refer to the OpenSSL project documentation for more information.
+.. warning::
+    Versions 1.0.x and from v3.0.0 up to v3.0.6 are strongly advised against due
+    to concerns regarding security vulnerabilities!
 
-The following libraries are required for Trusted Board Boot and Measured Boot
-support:
+Device Tree Compiler (DTC)
+^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-- mbed TLS == 3.4.1 (tag: ``mbedtls-3.4.1``)
+Needed if you want to rebuild the provided Flattened Device Tree (FDT)
+source files (``.dts`` files). DTC is available for Linux through the package
+repositories of most distributions.
 
-The following libraries are required for DICE Protection Environment support:
+Arm Development Studio (`Arm-DS`_)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-- QCBOR == 1.2 (tag: ``v1.2``)
+The standard software package used for debugging software on Arm development
+platforms and |FVP| models.
 
-These tools are optional:
+Node.js
+^^^^^^^
 
-- Device Tree Compiler (DTC) >= 1.4.7
+Highly recommended, and necessary in order to install and use the packaged
+Git hooks and helper tools. Without these tools you will need to rely on the
+CI for feedback on commit message conformance.
 
-   Needed if you want to rebuild the provided Flattened Device Tree (FDT)
-   source files (``.dts`` files). DTC is available for Linux through the package
-   repositories of most distributions.
+Poetry
+^^^^^^
 
-- Arm `Development Studio (Arm-DS)`_
+Required for managing Python dependencies, this will allow you to reliably
+reproduce a Python environment to build documentation and run analysis tools.
+Most importantly, it ensures your system environment will not be affected by
+dependencies in the Python scripts.
 
-   The standard software package used for debugging software on Arm development
-   platforms and |FVP| models.
-
-- Node.js >= 16
-
-   Highly recommended, and necessary in order to install and use the packaged
-   Git hooks and helper tools. Without these tools you will need to rely on the
-   CI for feedback on commit message conformance.
+.. _prerequisites_software_and_libraries:
 
-- Poetry >= 1.3.2
+Package Installation (Linux)
+----------------------------
 
-   Required for managing Python dependencies, this will allow you to reliably
-   reproduce a Python environment to build documentation and run analysis tools.
-   Most importantly, it ensures your system environment will not be affected by
-   dependencies in the Python scripts.
+|TF-A| can be compiled on both Linux and Windows-based machines.
+However, we strongly recommend using a UNIX-compatible build environment.
 
-Package Installation (Linux)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Testing is performed using Ubuntu 22.04 LTS (64-bit), but other distributions
+should also work, provided the necessary tools and libraries are installed.
 
-If you are using the recommended Ubuntu distribution then you can install the
-required packages with the following command:
+The following are steps to install the required packages:
 
 .. code:: shell
 
-    sudo apt install build-essential git
+    sudo apt install build-essential
 
 The optional packages can be installed using:
 
@@ -141,17 +151,6 @@
 
 .. _prerequisites_get_source:
 
-Getting the TF-A Source
------------------------
-
-Source code for |TF-A| is maintained in a Git repository hosted on
-TrustedFirmware.org. To clone this repository from the server, run the following
-in your shell:
-
-.. code:: shell
-
-    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
-
 Additional Steps for Contributors
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -189,5 +188,6 @@
 .. _Gerrit Code Review: https://www.gerritcodereview.com/
 .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
 .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
-.. _Development Studio (Arm-DS): https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
+.. _Arm-DS: https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
 .. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
+.. _TrustedFirmware.org: https://www.trustedfirmware.org/

diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index f5c1566..702726e 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst

@@ -70,11 +70,8 @@
 +----------------+----------------+--------------------+--------------------+
 |    Platform    |     Vendor     | Deprecated version |  Deleted version   |
 +================+================+====================+====================+
-|    sgi575      |      Arm       |        2.8         |       TBD          |
-+----------------+----------------+--------------------+--------------------+
-|    rdn1edge    |      Arm       |        2.8         |       TBD          |
-+----------------+----------------+--------------------+--------------------+
-|    tc1         |      Arm       |        2.10        |       TBD          |
+| None at this   |                |                    |                    |
+| time.          |                |                    |                    |
 +----------------+----------------+--------------------+--------------------+
 
 --------------

diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 7c66d11..c25c8cb 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst

@@ -256,10 +256,10 @@
 
    Defines the maximum address in secure RAM that the BL31 image can occupy.
 
--  **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE**
+-  **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE**
 
-   Defines the maximum message size between AP and RSS. Need to define if
-   platform supports RSS.
+   Defines the maximum message size between AP and RSE. Need to define if
+   platform supports RSE.
 
 For every image, the platform must define individual identifiers that will be
 used by BL1 or BL2 to load the corresponding image into memory from non-volatile
@@ -1712,6 +1712,18 @@
 corresponding to ``image_id``. This function is invoked in BL1, both in cold
 boot and FWU code path, before loading the image.
 
+Function : bl1_plat_calc_bl2_layout() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout
+    Return   : void
+
+This utility function calculates the memory layout of BL2, representing it in a
+`meminfo_t` structure. The default implementation derives this layout from the
+positioning of BL1’s RW data at the top of the memory layout.
+
 Function : bl1_plat_handle_post_image_load() [optional]
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

diff --git a/docs/resources/diagrams/plantuml/rss_attestation_flow.puml b/docs/resources/diagrams/plantuml/rse_attestation_flow.puml
similarity index 99%
rename from docs/resources/diagrams/plantuml/rss_attestation_flow.puml
rename to docs/resources/diagrams/plantuml/rse_attestation_flow.puml
index aca5c01..9d7d780 100644
--- a/docs/resources/diagrams/plantuml/rss_attestation_flow.puml
+++ b/docs/resources/diagrams/plantuml/rse_attestation_flow.puml

@@ -5,7 +5,7 @@
 participant RMM
 participant BL31
 endbox
-box RSS
+box RSE
 participant DelegAttest
 participant InitAttest
 participant MeasuredBoot

diff --git a/docs/resources/diagrams/plantuml/rse_measured_boot_flow.puml b/docs/resources/diagrams/plantuml/rse_measured_boot_flow.puml
new file mode 100644
index 0000000..97af562
--- /dev/null
+++ b/docs/resources/diagrams/plantuml/rse_measured_boot_flow.puml

@@ -0,0 +1,79 @@
+@startuml
+skinparam ParticipantPadding 10
+skinparam BoxPadding 10
+box RSE
+participant RSE_BL1_1
+participant RSE_BL1_2
+participant RSE_BL2
+participant RSE_S
+endbox
+box SCP
+participant SCP_BL1
+endbox
+box AP
+participant AP_BL1
+participant AP_BL2
+participant AP_BL31
+endbox
+
+== RSE Boot phase ==
+-> RSE_BL1_1: Reset
+Rnote over RSE_BL1_1: ROM code, XIP
+Rnote over RSE_BL1_2: OTP code, XIP
+Rnote over RSE_BL2, AP_BL31: Stored in flash, loaded and executed in RAM
+activate RSE_BL1_1 #Green
+RSE_BL1_1 -->> RSE_BL1_2: Validate, measure
+Rnote over RSE_BL1_1: BL1_2 measurement\n\ saved to a shared buffer
+RSE_BL1_1 -> RSE_BL1_2: Pass execution
+deactivate RSE_BL1_1
+activate RSE_BL1_2 #Green
+RSE_BL1_2 -->> RSE_BL2: Validate, measure, load
+Rnote over RSE_BL1_2: RSE_BL2 measurement\n\ saved to a shared buffer
+RSE_BL1_2 -> RSE_BL2: Pass execution
+deactivate RSE_BL1_2
+activate RSE_BL2 #Green
+RSE_BL2 -->> RSE_S: Validate, measure, load
+RSE_BL2 -->> SCP_BL1: Validate, measure, load
+Rnote over RSE_BL2: RSE_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer
+RSE_BL2 -> SCP_BL1: Release from reset
+activate SCP_BL1 #Green
+Rnote over RSE_BL2, SCP_BL1: MHU init between RSE and SCP
+Rnote over SCP_BL1: Configure memory
+Rnote over RSE_BL2: Waits for SCP
+SCP_BL1 --> RSE_BL2: Done
+RSE_BL2 -->> AP_BL1: Validate, measure, load
+Rnote over RSE_BL2: AP_BL1 measurement\n\ saved to a shared buffer
+RSE_BL2 -> AP_BL1: Release from reset
+activate AP_BL1 #Green
+RSE_BL2 -> RSE_S: Pass execution
+deactivate RSE_BL2
+activate RSE_S #Green
+Rnote over RSE_S: Measurements read from\n\ shared buffer and saved by\n\
+Measured Boot service to\n\ measurement slots.
+
+== RSE Runtime / AP Boot phase ==
+Rnote over RSE_S, AP_BL1: MHU init between RSE and AP
+Rnote over AP_BL1: Measure and load:\n\ FW_CONFIG\n\ TB_FW_CONFIG
+AP_BL1 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL1 -->> AP_BL2: Validate, measure,load
+AP_BL1 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL1 -> AP_BL2: Pass execution
+deactivate AP_BL1
+activate AP_BL2 #Green
+Rnote over AP_BL2: Measure and load:\n\ HW_CONFIG
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL2 -->> AP_BL31: Validate, measure,load
+Rnote over AP_BL2: Measure and load:\n\ BL31
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+Rnote over AP_BL2: Measure and load:\n\ RMM
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL2 -> AP_BL31: Pass execution
+deactivate AP_BL2
+activate AP_BL31 #Green
+== RSE / AP Runtime ==
+@enduml

diff --git a/docs/resources/diagrams/plantuml/rss_measured_boot_flow.puml b/docs/resources/diagrams/plantuml/rss_measured_boot_flow.puml
deleted file mode 100644
index 1aeb1a9..0000000
--- a/docs/resources/diagrams/plantuml/rss_measured_boot_flow.puml
+++ /dev/null

@@ -1,79 +0,0 @@
-@startuml
-skinparam ParticipantPadding 10
-skinparam BoxPadding 10
-box RSS
-participant RSS_BL1_1
-participant RSS_BL1_2
-participant RSS_BL2
-participant RSS_S
-endbox
-box SCP
-participant SCP_BL1
-endbox
-box AP
-participant AP_BL1
-participant AP_BL2
-participant AP_BL31
-endbox
-
-== RSS Boot phase ==
--> RSS_BL1_1: Reset
-Rnote over RSS_BL1_1: ROM code, XIP
-Rnote over RSS_BL1_2: OTP code, XIP
-Rnote over RSS_BL2, AP_BL31: Stored in flash, loaded and executed in RAM
-activate RSS_BL1_1 #Green
-RSS_BL1_1 -->> RSS_BL1_2: Validate, measure
-Rnote over RSS_BL1_1: BL1_2 measurement\n\ saved to a shared buffer
-RSS_BL1_1 -> RSS_BL1_2: Pass execution
-deactivate RSS_BL1_1
-activate RSS_BL1_2 #Green
-RSS_BL1_2 -->> RSS_BL2: Validate, measure, load
-Rnote over RSS_BL1_2: RSS_BL2 measurement\n\ saved to a shared buffer
-RSS_BL1_2 -> RSS_BL2: Pass execution
-deactivate RSS_BL1_2
-activate RSS_BL2 #Green
-RSS_BL2 -->> RSS_S: Validate, measure, load
-RSS_BL2 -->> SCP_BL1: Validate, measure, load
-Rnote over RSS_BL2: RSS_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer
-RSS_BL2 -> SCP_BL1: Release from reset
-activate SCP_BL1 #Green
-Rnote over RSS_BL2, SCP_BL1: MHU init between RSS and SCP
-Rnote over SCP_BL1: Configure memory
-Rnote over RSS_BL2: Waits for SCP
-SCP_BL1 --> RSS_BL2: Done
-RSS_BL2 -->> AP_BL1: Validate, measure, load
-Rnote over RSS_BL2: AP_BL1 measurement\n\ saved to a shared buffer
-RSS_BL2 -> AP_BL1: Release from reset
-activate AP_BL1 #Green
-RSS_BL2 -> RSS_S: Pass execution
-deactivate RSS_BL2
-activate RSS_S #Green
-Rnote over RSS_S: Measurements read from\n\ shared buffer and saved by\n\
-Measured Boot service to\n\ measurement slots.
-
-== RSS Runtime / AP Boot phase ==
-Rnote over RSS_S, AP_BL1: MHU init between RSS and AP
-Rnote over AP_BL1: Measure and load:\n\ FW_CONFIG\n\ TB_FW_CONFIG
-AP_BL1 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL1 -->> AP_BL2: Validate, measure,load
-AP_BL1 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL1 -> AP_BL2: Pass execution
-deactivate AP_BL1
-activate AP_BL2 #Green
-Rnote over AP_BL2: Measure and load:\n\ HW_CONFIG
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL2 -->> AP_BL31: Validate, measure,load
-Rnote over AP_BL2: Measure and load:\n\ BL31
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-Rnote over AP_BL2: Measure and load:\n\ RMM
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL2 -> AP_BL31: Pass execution
-deactivate AP_BL2
-activate AP_BL31 #Green
-== RSS / AP Runtime ==
-@enduml

diff --git a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml b/docs/resources/diagrams/plantuml/tfa_rse_dfd.puml
similarity index 89%
rename from docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
rename to docs/resources/diagrams/plantuml/tfa_rse_dfd.puml
index a7e0ce5..68a80bf 100644
--- a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
+++ b/docs/resources/diagrams/plantuml/tfa_rse_dfd.puml

@@ -5,7 +5,7 @@
  '/
 
 /'
-TF-A Data Flow Diagram including RSS
+TF-A Data Flow Diagram including RSE
 '/
 
 @startuml
@@ -54,12 +54,12 @@
             bl31 [label="TF-A Runtime\n(BL31)" fillcolor="#ddffb3"]
         }
 
-        # RSS cluster
-        subgraph cluster_rss{
-            label ="RSS";
+        # RSE cluster
+        subgraph cluster_rse{
+            label ="RSE";
             graph [style=filled color="#000000" fillcolor="#faf9cd"]
 
-            rss [label="Runtime Security\n\ Subsystem\n\ (RSS)" fillcolor="#ddffb3"]
+            rse [label="Runtime Security\n\ Subsystem\n\ (RSE)" fillcolor="#ddffb3"]
         }
     }
 
@@ -70,7 +70,7 @@
     sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"]
     nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
     bl2 ->  tzc [dir="both" ltail=cluster_tfa lhead=cluster_ip label="DF6" minlen=1]
-    bl31 -> rss [dir="both" ltail=cluster_tfa lhead=cluster_rss label="DF7" minlen=1]
+    bl31 -> rse [dir="both" ltail=cluster_tfa lhead=cluster_rse label="DF7" minlen=1]
 
 }
 

diff --git a/docs/resources/diagrams/rss_attestation_flow.svg b/docs/resources/diagrams/rse_attestation_flow.svg
similarity index 99%
rename from docs/resources/diagrams/rss_attestation_flow.svg
rename to docs/resources/diagrams/rse_attestation_flow.svg
index 3728c6f..7257576 100644
--- a/docs/resources/diagrams/rss_attestation_flow.svg
+++ b/docs/resources/diagrams/rse_attestation_flow.svg

@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentStyleType="text/css" height="1087px" preserveAspectRatio="none" style="width:900px;height:1087px;background:#FFFFFF;" version="1.1" viewBox="0 0 900 1087" width="900px" zoomAndPan="magnify"><defs/><g><rect fill="#DDDDDD" height="1075.1719" style="stroke:#181818;stroke-width:0.5;" width="261.5" x="44" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="20" x="164.75" y="18.0669">AP</text><rect fill="#DDDDDD" height="1075.1719" style="stroke:#181818;stroke-width:0.5;" width="502" x="364" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="28" x="601" y="18.0669">RSS</text><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="82" x2="82" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="266.5" x2="266.5" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="426" x2="426" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="553.5" x2="553.5" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="705" x2="705" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="822" x2="822" y1="56.4297" y2="1046.875"/><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="48" x="58" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="34" x="65" y="45.1279">RMM</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="48" x="58" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="34" x="65" y="1065.8701">RMM</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="49" x="242.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="35" x="249.5" y="45.1279">BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="49" x="242.5" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="35" x="249.5" y="1065.8701">BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="96" x="378" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="82" x="385" y="45.1279">DelegAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="96" x="378" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="82" x="385" y="1065.8701">DelegAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="516.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="523.5" y="45.1279">InitAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="516.5" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="523.5" y="1065.8701">InitAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="116" x="647" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="102" x="654" y="45.1279">MeasuredBoot</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="116" x="647" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="102" x="654" y="1065.8701">MeasuredBoot</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="59" x="793" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="45" x="800" y="45.1279">Crypto</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="59" x="793" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="45" x="800" y="1065.8701">Crypto</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="893" x="0" y="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="893" y1="86.9961" y2="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="893" y1="89.9961" y2="89.9961"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="144" x="374.5" y="76.4297"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="125" x="380.5" y="92.4966">RMM Boot phase</text><polygon fill="#181818" points="255,141.8281,265,145.8281,255,149.8281,259,145.8281" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="82" x2="261" y1="145.8281" y2="145.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="89" y="125.6294">get_realm_key(</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="74" x="121" y="140.7622">hash_algo</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="25" x="195" y="140.7622">, ...)</text><polygon fill="#181818" points="414,170.9609,424,174.9609,414,178.9609,418,174.9609" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="267" x2="420" y1="174.9609" y2="174.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="274" y="169.895">get_delegated_key</text><polygon fill="#181818" points="693,200.0938,703,204.0938,693,208.0938,697,204.0938" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="699" y1="204.0938" y2="204.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="127" x="433" y="199.0278">read_measurement</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="167" x="342" y="217.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="95" x="346" y="233.1606">Compute input</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="110" x="346" y="248.2935">for key derivation</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="159" x="346" y="263.4263">(hash of measurements)</text><polygon fill="#181818" points="810.5,292.625,820.5,296.625,810.5,300.625,814.5,296.625" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="816.5" y1="296.625" y2="296.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="68" x="433" y="291.5591">derive_key</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="150" x="351" y="309.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="126" x="355" y="325.6919">Compute public key</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="60" x="355" y="340.8247">hash with</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="74" x="419" y="340.8247">hash_algo</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="4" x="493" y="340.8247">.</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="132" x="756" y="357.8906"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="124" x="760" y="373.9575">Seed is provisioned</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="88" x="760" y="389.0903">in the factory.</text><polygon fill="#181818" points="278,418.2891,268,422.2891,278,426.2891,274,422.2891" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="272" x2="425" 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style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="82" x2="261" y1="634.75" y2="634.75"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="130" x="89" y="614.5513">get_platform_token(</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="121" y="629.6841">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="25" x="225" y="629.6841">, ...)</text><polygon fill="#181818" points="414,659.8828,424,663.8828,414,667.8828,418,663.8828" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="267" x2="420" y1="663.8828" y2="663.8828"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="135" x="274" y="658.8169">get_delegated_token</text><rect fill="#FEFFDD" height="38" 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fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="168" x="467" y="770.3481">Create the token including</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="21" x="467" y="785.481">the</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="492" y="785.481">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="40" x="600" y="785.481">as the</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="467" y="800.6138">challenge claim</text><polygon fill="#181818" points="693,829.8125,703,833.8125,693,837.8125,697,833.8125" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="554" x2="699" y1="833.8125" y2="833.8125"/><text fill="#000000" font-family="sans-serif" font-size="13" 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x="28" y="994.5435">cached. It is not</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="98" x="28" y="1009.6763">changing within</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="90" x="28" y="1024.8091">a power cycle.</text><!--MD5=[84fabec568a656165bea957fac178b53]
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Public</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="9" y="510.7544">key and its hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="126" x="9" y="525.8872">must be computed.</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="134" x="9" y="541.02">Public key is included</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="9" y="556.1528">in the realm token.</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="125" x="9" y="571.2856">Its hash is the input</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="146" x="9" y="586.4185">for get_platform_token</text><polygon fill="#181818" points="255,630.75,265,634.75,255,638.75,259,634.75" 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style="stroke:#181818;stroke-width:0.5;" width="155" x="348" y="676.8828"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="39" x="352" y="692.9497">Check</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="395" y="692.9497">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="352" y="708.0825">against derived key.</text><polygon fill="#181818" points="542,737.2813,552,741.2813,542,745.2813,546,741.2813" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="548" y1="741.2813" y2="741.2813"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="433" y="736.2153">get_initial_token</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="181" x="463" y="754.2813"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="168" x="467" y="770.3481">Create the token including</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="21" x="467" y="785.481">the</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="492" y="785.481">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="40" x="600" y="785.481">as the</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="467" y="800.6138">challenge claim</text><polygon fill="#181818" points="693,829.8125,703,833.8125,693,837.8125,697,833.8125" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="554" x2="699" y1="833.8125" y2="833.8125"/><text fill="#000000" font-family="sans-serif" font-size="13" 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x="28" y="994.5435">cached. It is not</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="98" x="28" y="1009.6763">changing within</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="90" x="28" y="1024.8091">a power cycle.</text><!--MD5=[84fabec568a656165bea957fac178b53]
 @startuml

 skinparam ParticipantPadding 10

 skinparam BoxPadding 10

@@ -6,7 +6,7 @@
 participant RMM

 participant BL31

 endbox

-box RSS

+box RSE

 participant DelegAttest

 participant InitAttest

 participant MeasuredBoot


diff --git a/docs/resources/diagrams/rss_measured_boot_flow.svg b/docs/resources/diagrams/rse_measured_boot_flow.svg
similarity index 90%
rename from docs/resources/diagrams/rss_measured_boot_flow.svg
rename to docs/resources/diagrams/rse_measured_boot_flow.svg
index f5bf311..0ccfbc2 100644
--- a/docs/resources/diagrams/rss_measured_boot_flow.svg
+++ b/docs/resources/diagrams/rse_measured_boot_flow.svg

@@ -1,12 +1,12 @@
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style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="0" x2="75.5" y1="130.6953" y2="130.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="36" x="7" y="125.6294">Reset</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="99" x="37" y="143.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="91" x="41" y="159.7622">ROM code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="95" x="185" y="176.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="87" x="189" y="192.895">OTP code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="861" x="368" y="209.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="281" x="658" y="226.0278">Stored in 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measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="154" y="409.9575">saved to a shared buffer</text><polygon fill="#181818" points="396.5,439.1563,406.5,443.1563,396.5,447.1563,400.5,443.1563" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="232.5" x2="402.5" y1="443.1563" y2="443.1563"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="239.5" y="438.0903">Pass execution</text><line style="stroke:#181818;stroke-width:1.0;" x1="592.5" x2="582.5" y1="472.2891" y2="468.2891"/><line style="stroke:#181818;stroke-width:1.0;" x1="592.5" x2="582.5" y1="472.2891" y2="476.2891"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="593.5" y1="472.2891" y2="472.2891"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="467.2231">Validate, measure, load</text><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="497.4219"/><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="505.4219"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="710" y1="501.4219" y2="501.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="496.356">Validate, measure, load</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="148" x="339" y="514.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="131" x="343" y="530.4888">RSS_S and SCP_BL1</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="140" x="343" y="545.6216">measurements saved</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="114" x="343" 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y="45.1279">AP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="798.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="805.5" y="1804.792">AP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="975.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="982.5" y="45.1279">AP_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="975.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="982.5" y="1804.792">AP_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="74" x="1148" y="25.1328"/><text fill="#000000" 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style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="0" x2="75.5" y1="130.6953" y2="130.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="36" x="7" y="125.6294">Reset</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="99" x="37" y="143.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="91" x="41" y="159.7622">ROM code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="95" x="185" y="176.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="87" x="189" y="192.895">OTP code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="861" x="368" y="209.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="281" x="658" y="226.0278">Stored in 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style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="86.5" x2="221.5" y1="336.625" y2="336.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="93.5" y="331.5591">Pass execution</text><line style="stroke:#181818;stroke-width:1.0;" x1="411.5" x2="401.5" y1="365.7578" y2="361.7578"/><line style="stroke:#181818;stroke-width:1.0;" x1="411.5" x2="401.5" y1="365.7578" y2="369.7578"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="237.5" x2="412.5" y1="365.7578" y2="365.7578"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="244.5" y="360.6919">Validate, measure, load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="150" y="378.7578"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="154" y="394.8247">RSE_BL2 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measure, load</text><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="497.4219"/><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="505.4219"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="710" y1="501.4219" y2="501.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="496.356">Validate, measure, load</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="148" x="339" y="514.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="131" x="343" y="530.4888">RSE_S and SCP_BL1</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="140" x="343" y="545.6216">measurements saved</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="114" x="343" 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Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1149.6763">store measurement</text><line style="stroke:#181818;stroke-width:1.0;" x1="1006" x2="996" y1="1182.875" y2="1178.875"/><line style="stroke:#181818;stroke-width:1.0;" x1="1006" x2="996" y1="1182.875" y2="1186.875"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="836" x2="1007" y1="1182.875" y2="1182.875"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="148" x="843" y="1177.8091">Validate, measure,load</text><polygon fill="#181818" points="610.5,1208.0078,600.5,1212.0078,610.5,1216.0078,606.5,1212.0078" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="825" y1="1212.0078" y2="1212.0078"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1206.9419">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1225.0078"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1241.0747">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1256.2075">store measurement</text><polygon fill="#181818" points="991,1285.4063,1001,1289.4063,991,1293.4063,995,1289.4063" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="831" x2="997" y1="1289.4063" y2="1289.4063"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="838" y="1284.3403">Pass execution</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1302.4063"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1318.4731">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="77" x="949" y="1333.606">HW_CONFIG</text><polygon fill="#181818" points="610.5,1362.8047,600.5,1366.8047,610.5,1370.8047,606.5,1366.8047" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1366.8047" y2="1366.8047"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1361.7388">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1379.8047"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1395.8716">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1411.0044">store measurement</text><line style="stroke:#181818;stroke-width:1.0;" x1="1183" x2="1173" y1="1444.2031" y2="1440.2031"/><line style="stroke:#181818;stroke-width:1.0;" x1="1183" x2="1173" y1="1444.2031" y2="1448.2031"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="1013" x2="1184" y1="1444.2031" y2="1444.2031"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="148" x="1020" y="1439.1372">Validate, measure,load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1457.2031"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1473.27">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="32" x="949" y="1488.4028">BL31</text><polygon fill="#181818" points="610.5,1517.6016,600.5,1521.6016,610.5,1525.6016,606.5,1521.6016" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1521.6016" y2="1521.6016"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1516.5356">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1534.6016"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1550.6685">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1565.8013">store measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1582.8672"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1598.9341">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="30" x="949" y="1614.0669">RMM</text><polygon fill="#181818" points="610.5,1643.2656,600.5,1647.2656,610.5,1651.2656,606.5,1647.2656" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1647.2656" y2="1647.2656"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1642.1997">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1660.2656"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1676.3325">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1691.4653">store measurement</text><polygon fill="#181818" points="1168,1720.6641,1178,1724.6641,1168,1728.6641,1172,1724.6641" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="1008" x2="1174" y1="1724.6641" y2="1724.6641"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="1015" y="1719.5981">Pass execution</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="1753.2305"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="1753.2305" y2="1753.2305"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="1756.2305" y2="1756.2305"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="148" x="549.5" y="1742.6641"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="129" x="555.5" y="1758.731">RSE / AP Runtime</text><!--MD5=[e3f0ee259d2a4aa9c2a97ff856de0312]
 @startuml

 skinparam ParticipantPadding 10

 skinparam BoxPadding 10

-box RSS

-participant RSS_BL1_1

-participant RSS_BL1_2

-participant RSS_BL2

-participant RSS_S

+box RSE

+participant RSE_BL1_1

+participant RSE_BL1_2

+participant RSE_BL2

+participant RSE_S

 endbox

 box SCP

 participant SCP_BL1

@@ -17,65 +17,65 @@
 participant AP_BL31

 endbox

 

-== RSS Boot phase ==

--> RSS_BL1_1: Reset

-Rnote over RSS_BL1_1: ROM code, XIP

-Rnote over RSS_BL1_2: OTP code, XIP

-Rnote over RSS_BL2, AP_BL31: Stored in flash, loaded and executed in RAM

-activate RSS_BL1_1 #Green

-RSS_BL1_1 - ->> RSS_BL1_2: Validate, measure

-Rnote over RSS_BL1_1: BL1_2 measurement\n\ saved to a shared buffer

-RSS_BL1_1 -> RSS_BL1_2: Pass execution

-deactivate RSS_BL1_1

-activate RSS_BL1_2 #Green

-RSS_BL1_2 - ->> RSS_BL2: Validate, measure, load

-Rnote over RSS_BL1_2: RSS_BL2 measurement\n\ saved to a shared buffer

-RSS_BL1_2 -> RSS_BL2: Pass execution

-deactivate RSS_BL1_2

-activate RSS_BL2 #Green

-RSS_BL2 - ->> RSS_S: Validate, measure, load

-RSS_BL2 - ->> SCP_BL1: Validate, measure, load

-Rnote over RSS_BL2: RSS_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer

-RSS_BL2 -> SCP_BL1: Release from reset

+== RSE Boot phase ==

+-> RSE_BL1_1: Reset

+Rnote over RSE_BL1_1: ROM code, XIP

+Rnote over RSE_BL1_2: OTP code, XIP

+Rnote over RSE_BL2, AP_BL31: Stored in flash, loaded and executed in RAM

+activate RSE_BL1_1 #Green

+RSE_BL1_1 - ->> RSE_BL1_2: Validate, measure

+Rnote over RSE_BL1_1: BL1_2 measurement\n\ saved to a shared buffer

+RSE_BL1_1 -> RSE_BL1_2: Pass execution

+deactivate RSE_BL1_1

+activate RSE_BL1_2 #Green

+RSE_BL1_2 - ->> RSE_BL2: Validate, measure, load

+Rnote over RSE_BL1_2: RSE_BL2 measurement\n\ saved to a shared buffer

+RSE_BL1_2 -> RSE_BL2: Pass execution

+deactivate RSE_BL1_2

+activate RSE_BL2 #Green

+RSE_BL2 - ->> RSE_S: Validate, measure, load

+RSE_BL2 - ->> SCP_BL1: Validate, measure, load

+Rnote over RSE_BL2: RSE_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer

+RSE_BL2 -> SCP_BL1: Release from reset

 activate SCP_BL1 #Green

-Rnote over RSS_BL2, SCP_BL1: MHU init between RSS and SCP

+Rnote over RSE_BL2, SCP_BL1: MHU init between RSE and SCP

 Rnote over SCP_BL1: Configure memory

-Rnote over RSS_BL2: Waits for SCP

-SCP_BL1 - -> RSS_BL2: Done

-RSS_BL2 - ->> AP_BL1: Validate, measure, load

-Rnote over RSS_BL2: AP_BL1 measurement\n\ saved to a shared buffer

-RSS_BL2 -> AP_BL1: Release from reset

+Rnote over RSE_BL2: Waits for SCP

+SCP_BL1 - -> RSE_BL2: Done

+RSE_BL2 - ->> AP_BL1: Validate, measure, load

+Rnote over RSE_BL2: AP_BL1 measurement\n\ saved to a shared buffer

+RSE_BL2 -> AP_BL1: Release from reset

 activate AP_BL1 #Green

-RSS_BL2 -> RSS_S: Pass execution

-deactivate RSS_BL2

-activate RSS_S #Green

-Rnote over RSS_S: Measurements read from\n\ shared buffer and saved by\nMeasured Boot service to\n\ measurement slots.

+RSE_BL2 -> RSE_S: Pass execution

+deactivate RSE_BL2

+activate RSE_S #Green

+Rnote over RSE_S: Measurements read from\n\ shared buffer and saved by\nMeasured Boot service to\n\ measurement slots.

 

-== RSS Runtime / AP Boot phase ==

-Rnote over RSS_S, AP_BL1: MHU init between RSS and AP

+== RSE Runtime / AP Boot phase ==

+Rnote over RSE_S, AP_BL1: MHU init between RSE and AP

 Rnote over AP_BL1: Measure and load:\n\ FW_CONFIG\n\ TB_FW_CONFIG

-AP_BL1 -> RSS_S: Extend measurement

-Rnote over RSS_S: Measured Boot:\n\ store measurement

+AP_BL1 -> RSE_S: Extend measurement

+Rnote over RSE_S: Measured Boot:\n\ store measurement

 AP_BL1 - ->> AP_BL2: Validate, measure,load

-AP_BL1 -> RSS_S: Extend measurement

-Rnote over RSS_S: Measured Boot:\n\ store measurement

+AP_BL1 -> RSE_S: Extend measurement

+Rnote over RSE_S: Measured Boot:\n\ store measurement

 AP_BL1 -> AP_BL2: Pass execution

 deactivate AP_BL1

 activate AP_BL2 #Green

 Rnote over AP_BL2: Measure and load:\n\ HW_CONFIG

-AP_BL2 -> RSS_S: Extend measurement

-Rnote over RSS_S: Measured Boot:\n\ store measurement

+AP_BL2 -> RSE_S: Extend measurement

+Rnote over RSE_S: Measured Boot:\n\ store measurement

 AP_BL2 - ->> AP_BL31: Validate, measure,load

 Rnote over AP_BL2: Measure and load:\n\ BL31

-AP_BL2 -> RSS_S: Extend measurement

-Rnote over RSS_S: Measured Boot:\n\ store measurement

+AP_BL2 -> RSE_S: Extend measurement

+Rnote over RSE_S: Measured Boot:\n\ store measurement

 Rnote over AP_BL2: Measure and load:\n\ RMM

-AP_BL2 -> RSS_S: Extend measurement

-Rnote over RSS_S: Measured Boot:\n\ store measurement

+AP_BL2 -> RSE_S: Extend measurement

+Rnote over RSE_S: Measured Boot:\n\ store measurement

 AP_BL2 -> AP_BL31: Pass execution

 deactivate AP_BL2

 activate AP_BL31 #Green

-== RSS / AP Runtime ==

+== RSE / AP Runtime ==

 @enduml

 
 PlantUML version 1.2022.7(Mon Aug 22 19:01:30 CEST 2022)

diff --git a/docs/threat_model/firmware_threat_model/index.rst b/docs/threat_model/firmware_threat_model/index.rst
index 05b6710..ce1752f 100644
--- a/docs/threat_model/firmware_threat_model/index.rst
+++ b/docs/threat_model/firmware_threat_model/index.rst

@@ -30,7 +30,7 @@
    threat_model
    threat_model_el3_spm
    threat_model_fvp_r
-   threat_model_rss_interface
+   threat_model_rse_interface
    threat_model_arm_cca
    threat_model_fw_update_and_recovery
 

diff --git a/docs/threat_model/firmware_threat_model/threat_model_rss_interface.rst b/docs/threat_model/firmware_threat_model/threat_model_rse_interface.rst
similarity index 74%
rename from docs/threat_model/firmware_threat_model/threat_model_rss_interface.rst
rename to docs/threat_model/firmware_threat_model/threat_model_rse_interface.rst
index 025d2d9..3b391c1 100644
--- a/docs/threat_model/firmware_threat_model/threat_model_rss_interface.rst
+++ b/docs/threat_model/firmware_threat_model/threat_model_rse_interface.rst

@@ -1,41 +1,41 @@
-Threat Model for RSS - AP interface
+Threat Model for RSE - AP interface
 ***********************************
 
 ************
 Introduction
 ************
 This document is an extension for the general TF-A threat-model. It considers
-those platforms where a Runtime Security Subsystem (RSS) is included in the SoC
+those platforms where a Runtime Security Engine (RSE) is included in the SoC
 next to the Application Processor (AP).
 
 ********************
 Target of Evaluation
 ********************
-The scope of this threat model only includes the interface between the RSS and
+The scope of this threat model only includes the interface between the RSE and
 AP. Otherwise, the TF-A :ref:`Generic Threat Model` document is applicable for
-the AP core. The threat model for the RSS firmware will be provided by the RSS
+the AP core. The threat model for the RSE firmware will be provided by the RSE
 firmware project in the future.
 
 
 Data Flow Diagram
 =================
 This diagram is different only from the general TF-A data flow diagram in that
-it includes the RSS and highlights the interface between the AP and the RSS
-cores. The interface description only focuses on the AP-RSS interface the rest
+it includes the RSE and highlights the interface between the AP and the RSE
+cores. The interface description only focuses on the AP-RSE interface the rest
 is the same as in the general TF-A threat-model document.
 
-.. uml:: ../../resources/diagrams/plantuml/tfa_rss_dfd.puml
-  :caption: Figure 1: TF-A Data Flow Diagram including RSS
+.. uml:: ../../resources/diagrams/plantuml/tfa_rse_dfd.puml
+  :caption: Figure 1: TF-A Data Flow Diagram including RSE
 
-.. table:: Table 1: TF-A - RSS data flow diagram
+.. table:: Table 1: TF-A - RSE data flow diagram
 
   +-----------------+--------------------------------------------------------+
   | Diagram Element | Description                                            |
   +=================+========================================================+
-  |       DF7       | | Boot images interact with RSS over a communication   |
+  |       DF7       | | Boot images interact with RSE over a communication   |
   |                 |   channel to record boot measurements and get image    |
   |                 |   verification keys. At runtime, BL31 obtains the      |
-  |                 |   realm world attestation signing key from RSS.        |
+  |                 |   realm world attestation signing key from RSE.        |
   +-----------------+--------------------------------------------------------+
 
 Threat Assessment
@@ -44,12 +44,12 @@
 threat-model document, :ref:`Generic Threat Model`. All the threats listed there
 are applicable for the AP core, here only the differences are highlighted.
 
-    - ID 11: The access to the communication interface between AP and RSS is
+    - ID 11: The access to the communication interface between AP and RSE is
       allowed only for firmware running at EL3. Accidentally exposing this
-      interface to NSCode can allow malicious code to interact with RSS and
+      interface to NSCode can allow malicious code to interact with RSE and
       gain access to sensitive data.
     - ID 13: Relevant in the context of the realm attestation key, which can be
-      retrieved by BL31 through DF7. The RSS communication protocol layer
+      retrieved by BL31 through DF7. The RSE communication protocol layer
       mitigates against this by clearing its internal buffer when reply is
       received. The caller of the API must do the same if data is not needed
       anymore.

diff --git a/docs/threat_model/supply_chain_threat_model.rst b/docs/threat_model/supply_chain_threat_model.rst
index 386a4b0..a0fed5c 100644
--- a/docs/threat_model/supply_chain_threat_model.rst
+++ b/docs/threat_model/supply_chain_threat_model.rst

@@ -115,7 +115,7 @@
 - *EDK2 UEFI*: Normal world bootloader from the EDK2 project [7]_. We use EDK2
   UEFI binaries hosted on tf.org servers for testing [8]_.
 
-Other software components used to test TF-A include U-Boot, Linux kernel, RSS,
+Other software components used to test TF-A include U-Boot, Linux kernel, RSE,
 MCP, and file systems, all sourced from the Arm Reference Platforms teams.
 
 TF-A Toolchain

diff --git a/drivers/arm/rss/rss_comms.c b/drivers/arm/rse/rse_comms.c
similarity index 77%
rename from drivers/arm/rss/rss_comms.c
rename to drivers/arm/rse/rse_comms.c
index 332105f..cfc5a83 100644
--- a/drivers/arm/rss/rss_comms.c
+++ b/drivers/arm/rse/rse_comms.c

@@ -9,16 +9,16 @@
 
 #include <common/debug.h>
 #include <drivers/arm/mhu.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <psa/client.h>
-#include <rss_comms_protocol.h>
+#include <rse_comms_protocol.h>
 
 /* Union as message space and reply space are never used at the same time, and this saves space as
  * we can overlap them.
  */
-union __packed __attribute__((aligned(4))) rss_comms_io_buffer_t {
-	struct serialized_rss_comms_msg_t msg;
-	struct serialized_rss_comms_reply_t reply;
+union __packed __attribute__((aligned(4))) rse_comms_io_buffer_t {
+	struct serialized_rse_comms_msg_t msg;
+	struct serialized_rse_comms_reply_t reply;
 };
 
 static uint8_t select_protocol_version(const psa_invec *in_vec, size_t in_len,
@@ -40,13 +40,13 @@
 
 	comms_mhu_msg_size = mhu_get_max_message_size();
 
-	comms_embed_msg_min_size = sizeof(struct serialized_rss_comms_header_t) +
-				   sizeof(struct rss_embed_msg_t) -
-				   PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE;
+	comms_embed_msg_min_size = sizeof(struct serialized_rse_comms_header_t) +
+				   sizeof(struct rse_embed_msg_t) -
+				   PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE;
 
-	comms_embed_reply_min_size = sizeof(struct serialized_rss_comms_header_t) +
-				     sizeof(struct rss_embed_reply_t) -
-				     PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE;
+	comms_embed_reply_min_size = sizeof(struct serialized_rse_comms_header_t) +
+				     sizeof(struct rse_embed_reply_t) -
+				     PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE;
 
 	/* Use embed if we can pack into one message and reply, else use
 	 * pointer_access. The underlying MHU transport protocol uses a
@@ -63,9 +63,9 @@
 	     comms_mhu_msg_size - sizeof(uint32_t)) ||
 	    (comms_embed_reply_min_size + out_size_total >
 	     comms_mhu_msg_size - sizeof(uint32_t))) {
-		return RSS_COMMS_PROTOCOL_POINTER_ACCESS;
+		return RSE_COMMS_PROTOCOL_POINTER_ACCESS;
 	} else {
-		return RSS_COMMS_PROTOCOL_EMBED;
+		return RSE_COMMS_PROTOCOL_EMBED;
 	}
 }
 
@@ -75,7 +75,7 @@
 	/* Declared statically to avoid using huge amounts of stack space. Maybe revisit if
 	 * functions not being reentrant becomes a problem.
 	 */
-	static union rss_comms_io_buffer_t io_buf;
+	static union rse_comms_io_buffer_t io_buf;
 	enum mhu_error_t err;
 	psa_status_t status;
 	static uint8_t seq_num = 1U;
@@ -94,13 +94,13 @@
 	io_buf.msg.header.client_id = 1U,
 	io_buf.msg.header.protocol_ver = select_protocol_version(in_vec, in_len, out_vec, out_len);
 
-	status = rss_protocol_serialize_msg(handle, type, in_vec, in_len, out_vec,
+	status = rse_protocol_serialize_msg(handle, type, in_vec, in_len, out_vec,
 					    out_len, &io_buf.msg, &msg_size);
 	if (status != PSA_SUCCESS) {
 		return status;
 	}
 
-	VERBOSE("[RSS-COMMS] Sending message\n");
+	VERBOSE("[RSE-COMMS] Sending message\n");
 	VERBOSE("protocol_ver=%u\n", io_buf.msg.header.protocol_ver);
 	VERBOSE("seq_num=%u\n", io_buf.msg.header.seq_num);
 	VERBOSE("client_id=%u\n", io_buf.msg.header.client_id);
@@ -117,7 +117,7 @@
 #if DEBUG
 	/*
 	 * Poisoning the message buffer (with a known pattern).
-	 * Helps in detecting hypothetical RSS communication bugs.
+	 * Helps in detecting hypothetical RSE communication bugs.
 	 */
 	memset(&io_buf.msg, 0xA5, msg_size);
 #endif
@@ -127,12 +127,12 @@
 		return PSA_ERROR_COMMUNICATION_FAILURE;
 	}
 
-	VERBOSE("[RSS-COMMS] Received reply\n");
+	VERBOSE("[RSE-COMMS] Received reply\n");
 	VERBOSE("protocol_ver=%u\n", io_buf.reply.header.protocol_ver);
 	VERBOSE("seq_num=%u\n", io_buf.reply.header.seq_num);
 	VERBOSE("client_id=%u\n", io_buf.reply.header.client_id);
 
-	status = rss_protocol_deserialize_reply(out_vec, out_len, &return_val,
+	status = rse_protocol_deserialize_reply(out_vec, out_len, &return_val,
 						&io_buf.reply, reply_size);
 	if (status != PSA_SUCCESS) {
 		return status;
@@ -152,16 +152,16 @@
 	return return_val;
 }
 
-int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base)
+int rse_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base)
 {
 	enum mhu_error_t err;
 
 	err = mhu_init_sender(mhu_sender_base);
 	if (err != MHU_ERR_NONE) {
 		if (err == MHU_ERR_ALREADY_INIT) {
-			INFO("[RSS-COMMS] Host to RSS MHU driver already initialized\n");
+			INFO("[RSE-COMMS] Host to RSE MHU driver already initialized\n");
 		} else {
-			ERROR("[RSS-COMMS] Host to RSS MHU driver initialization failed: %d\n", err);
+			ERROR("[RSE-COMMS] Host to RSE MHU driver initialization failed: %d\n", err);
 			return -1;
 		}
 	}
@@ -169,9 +169,9 @@
 	err = mhu_init_receiver(mhu_receiver_base);
 	if (err != MHU_ERR_NONE) {
 		if (err == MHU_ERR_ALREADY_INIT) {
-			INFO("[RSS-COMMS] RSS to Host MHU driver already initialized\n");
+			INFO("[RSE-COMMS] RSE to Host MHU driver already initialized\n");
 		} else {
-			ERROR("[RSS-COMMS] RSS to Host MHU driver initialization failed: %d\n", err);
+			ERROR("[RSE-COMMS] RSE to Host MHU driver initialization failed: %d\n", err);
 			return -1;
 		}
 	}

diff --git a/drivers/arm/rse/rse_comms.mk b/drivers/arm/rse/rse_comms.mk
new file mode 100644
index 0000000..a1abc6a
--- /dev/null
+++ b/drivers/arm/rse/rse_comms.mk

@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+$(warning "RSE driver is an experimental feature")
+
+RSE_COMMS_SOURCES	:=	$(addprefix drivers/arm/rse/,			\
+					rse_comms.c				\
+					rse_comms_protocol.c			\
+					rse_comms_protocol_embed.c		\
+					rse_comms_protocol_pointer_access.c	\
+				)
+
+# Default to MHUv2 if PLAT_MHU_VERSION undefined
+PLAT_MHU_VERSION ?= 2
+
+ifeq (${PLAT_MHU_VERSION}, 3)
+RSE_COMMS_SOURCES	+=	$(addprefix drivers/arm/mhu/,			\
+					mhu_v3_x.c				\
+					mhu_wrapper_v3_x.c			\
+				)
+else ifeq (${PLAT_MHU_VERSION}, 2)
+RSE_COMMS_SOURCES	+=	$(addprefix drivers/arm/mhu/,			\
+					mhu_v2_x.c				\
+					mhu_wrapper_v2_x.c			\
+				)
+else
+$(error Unsupported MHU version)
+endif
+
+PLAT_INCLUDES		+=	-Idrivers/arm/rse		\
+				-Idrivers/arm/mhu

diff --git a/drivers/arm/rss/rss_comms_protocol.c b/drivers/arm/rse/rse_comms_protocol.c
similarity index 62%
rename from drivers/arm/rss/rss_comms_protocol.c
rename to drivers/arm/rse/rse_comms_protocol.c
index a1b1b58..3eb7eaa 100644
--- a/drivers/arm/rss/rss_comms_protocol.c
+++ b/drivers/arm/rse/rse_comms_protocol.c

@@ -7,15 +7,15 @@
 #include <assert.h>
 
 #include <common/debug.h>
-#include "rss_comms_protocol.h"
+#include "rse_comms_protocol.h"
 
-psa_status_t rss_protocol_serialize_msg(psa_handle_t handle,
+psa_status_t rse_protocol_serialize_msg(psa_handle_t handle,
 					int16_t type,
 					const psa_invec *in_vec,
 					uint8_t in_len,
 					const psa_outvec *out_vec,
 					uint8_t out_len,
-					struct serialized_rss_comms_msg_t *msg,
+					struct serialized_rse_comms_msg_t *msg,
 					size_t *msg_len)
 {
 	psa_status_t status;
@@ -25,15 +25,15 @@
 	assert(in_vec != NULL);
 
 	switch (msg->header.protocol_ver) {
-	case RSS_COMMS_PROTOCOL_EMBED:
-		status = rss_protocol_embed_serialize_msg(handle, type, in_vec, in_len, out_vec,
+	case RSE_COMMS_PROTOCOL_EMBED:
+		status = rse_protocol_embed_serialize_msg(handle, type, in_vec, in_len, out_vec,
 							  out_len, &msg->msg.embed, msg_len);
 		if (status != PSA_SUCCESS) {
 			return status;
 		}
 		break;
-	case RSS_COMMS_PROTOCOL_POINTER_ACCESS:
-		status = rss_protocol_pointer_access_serialize_msg(handle, type, in_vec, in_len,
+	case RSE_COMMS_PROTOCOL_POINTER_ACCESS:
+		status = rse_protocol_pointer_access_serialize_msg(handle, type, in_vec, in_len,
 								   out_vec, out_len,
 								   &msg->msg.pointer_access,
 								   msg_len);
@@ -45,26 +45,26 @@
 		return PSA_ERROR_NOT_SUPPORTED;
 	}
 
-	*msg_len += sizeof(struct serialized_rss_comms_header_t);
+	*msg_len += sizeof(struct serialized_rse_comms_header_t);
 
 	return PSA_SUCCESS;
 }
 
-psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec,
+psa_status_t rse_protocol_deserialize_reply(psa_outvec *out_vec,
 					    uint8_t out_len,
 					    psa_status_t *return_val,
-					    const struct serialized_rss_comms_reply_t *reply,
+					    const struct serialized_rse_comms_reply_t *reply,
 					    size_t reply_size)
 {
 	assert(reply != NULL);
 	assert(return_val != NULL);
 
 	switch (reply->header.protocol_ver) {
-	case RSS_COMMS_PROTOCOL_EMBED:
-		return rss_protocol_embed_deserialize_reply(out_vec, out_len, return_val,
+	case RSE_COMMS_PROTOCOL_EMBED:
+		return rse_protocol_embed_deserialize_reply(out_vec, out_len, return_val,
 							    &reply->reply.embed, reply_size);
-	case RSS_COMMS_PROTOCOL_POINTER_ACCESS:
-		return rss_protocol_pointer_access_deserialize_reply(out_vec, out_len, return_val,
+	case RSE_COMMS_PROTOCOL_POINTER_ACCESS:
+		return rse_protocol_pointer_access_deserialize_reply(out_vec, out_len, return_val,
 								     &reply->reply.pointer_access,
 								     reply_size);
 	default:

diff --git a/drivers/arm/rse/rse_comms_protocol.h b/drivers/arm/rse/rse_comms_protocol.h
new file mode 100644
index 0000000..24f3965
--- /dev/null
+++ b/drivers/arm/rse/rse_comms_protocol.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSE_COMMS_PROTOCOL_H__
+#define __RSE_COMMS_PROTOCOL_H__
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <psa/client.h>
+#include "rse_comms_protocol_embed.h"
+#include "rse_comms_protocol_pointer_access.h"
+
+enum rse_comms_protocol_version_t {
+	RSE_COMMS_PROTOCOL_EMBED = 0,
+	RSE_COMMS_PROTOCOL_POINTER_ACCESS = 1,
+};
+
+struct __packed serialized_rse_comms_header_t {
+	uint8_t protocol_ver;
+	uint8_t seq_num;
+	uint16_t client_id;
+};
+
+/* MHU message passed from Host to RSE to deliver a PSA client call */
+struct __packed serialized_rse_comms_msg_t {
+	struct serialized_rse_comms_header_t header;
+	union __packed {
+		struct rse_embed_msg_t embed;
+		struct rse_pointer_access_msg_t pointer_access;
+	} msg;
+};
+
+/* MHU reply message to hold the PSA client reply result returned by RSE */
+struct __packed serialized_rse_comms_reply_t {
+	struct serialized_rse_comms_header_t header;
+	union __packed {
+		struct rse_embed_reply_t embed;
+		struct rse_pointer_access_reply_t pointer_access;
+	} reply;
+};
+
+/* in_len and out_len are uint8_ts, therefore if there are more than 255 iovecs
+ * an error may occur.
+ */
+CASSERT(PSA_MAX_IOVEC <= UINT8_MAX, assert_rse_comms_max_iovec_too_large);
+
+psa_status_t rse_protocol_serialize_msg(psa_handle_t handle,
+					int16_t type,
+					const psa_invec *in_vec,
+					uint8_t in_len,
+					const psa_outvec *out_vec,
+					uint8_t out_len,
+					struct serialized_rse_comms_msg_t *msg,
+					size_t *msg_len);
+
+psa_status_t rse_protocol_deserialize_reply(psa_outvec *out_vec,
+					    uint8_t out_len,
+					    psa_status_t *return_val,
+					    const struct serialized_rse_comms_reply_t *reply,
+					    size_t reply_size);
+
+#endif /* __RSE_COMMS_PROTOCOL_H__ */

diff --git a/drivers/arm/rss/rss_comms_protocol_common.h b/drivers/arm/rse/rse_comms_protocol_common.h
similarity index 89%
rename from drivers/arm/rss/rss_comms_protocol_common.h
rename to drivers/arm/rse/rse_comms_protocol_common.h
index 177d636..235ea92 100644
--- a/drivers/arm/rss/rss_comms_protocol_common.h
+++ b/drivers/arm/rse/rse_comms_protocol_common.h

@@ -17,8 +17,8 @@
  * Res: Reserved.
  */
 
-#ifndef RSS_COMMS_PROTOCOL_COMMON
-#define RSS_COMMS_PROTOCOL_COMMON
+#ifndef RSE_COMMS_PROTOCOL_COMMON
+#define RSE_COMMS_PROTOCOL_COMMON
 
 #define TYPE_OFFSET	(0U)
 #define TYPE_MASK	(0xFFFFUL << TYPE_OFFSET)
@@ -32,4 +32,4 @@
 	 ((((uint32_t)(in_len)) << IN_LEN_OFFSET) & IN_LEN_MASK) | \
 	 ((((uint32_t)(out_len)) << OUT_LEN_OFFSET) & OUT_LEN_MASK))
 
-#endif /* RSS_COMMS_PROTOCOL_COMMON */
+#endif /* RSE_COMMS_PROTOCOL_COMMON */

diff --git a/drivers/arm/rss/rss_comms_protocol_embed.c b/drivers/arm/rse/rse_comms_protocol_embed.c
similarity index 85%
rename from drivers/arm/rss/rss_comms_protocol_embed.c
rename to drivers/arm/rse/rse_comms_protocol_embed.c
index 05628cc..d425257 100644
--- a/drivers/arm/rss/rss_comms_protocol_embed.c
+++ b/drivers/arm/rse/rse_comms_protocol_embed.c

@@ -9,16 +9,16 @@
 #include <string.h>
 
 #include <common/debug.h>
-#include "rss_comms_protocol_common.h"
-#include "rss_comms_protocol_embed.h"
+#include "rse_comms_protocol_common.h"
+#include "rse_comms_protocol_embed.h"
 
-psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle,
+psa_status_t rse_protocol_embed_serialize_msg(psa_handle_t handle,
 					      int16_t type,
 					      const psa_invec *in_vec,
 					      uint8_t in_len,
 					      const psa_outvec *out_vec,
 					      uint8_t out_len,
-					      struct rss_embed_msg_t *msg,
+					      struct rse_embed_msg_t *msg,
 					      size_t *msg_len)
 {
 	uint32_t payload_size = 0;
@@ -55,10 +55,10 @@
 	return PSA_SUCCESS;
 }
 
-psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec,
+psa_status_t rse_protocol_embed_deserialize_reply(psa_outvec *out_vec,
 						  uint8_t out_len,
 						  psa_status_t *return_val,
-						  const struct rss_embed_reply_t *reply,
+						  const struct rse_embed_reply_t *reply,
 						  size_t reply_size)
 {
 	uint32_t payload_offset = 0;

diff --git a/drivers/arm/rse/rse_comms_protocol_embed.h b/drivers/arm/rse/rse_comms_protocol_embed.h
new file mode 100644
index 0000000..165978d
--- /dev/null
+++ b/drivers/arm/rse/rse_comms_protocol_embed.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSE_COMMS_PROTOCOL_EMBED_H__
+#define __RSE_COMMS_PROTOCOL_EMBED_H__
+
+#include <cdefs.h>
+
+#include <psa/client.h>
+
+#include <platform_def.h>
+
+
+
+struct __packed rse_embed_msg_t {
+	psa_handle_t handle;
+	uint32_t ctrl_param; /* type, in_len, out_len */
+	uint16_t io_size[PSA_MAX_IOVEC];
+	uint8_t trailer[PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE];
+};
+
+struct __packed rse_embed_reply_t {
+	int32_t return_val;
+	uint16_t out_size[PSA_MAX_IOVEC];
+	uint8_t trailer[PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE];
+};
+
+psa_status_t rse_protocol_embed_serialize_msg(psa_handle_t handle,
+					      int16_t type,
+					      const psa_invec *in_vec,
+					      uint8_t in_len,
+					      const psa_outvec *out_vec,
+					      uint8_t out_len,
+					      struct rse_embed_msg_t *msg,
+					      size_t *msg_len);
+
+psa_status_t rse_protocol_embed_deserialize_reply(psa_outvec *out_vec,
+						  uint8_t out_len,
+						  psa_status_t *return_val,
+						  const struct rse_embed_reply_t *reply,
+						  size_t reply_size);
+
+#endif /* __RSE_COMMS_PROTOCOL_EMBED_H__ */

diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.c b/drivers/arm/rse/rse_comms_protocol_pointer_access.c
similarity index 78%
rename from drivers/arm/rss/rss_comms_protocol_pointer_access.c
rename to drivers/arm/rse/rse_comms_protocol_pointer_access.c
index 3a10a98..63524eb 100644
--- a/drivers/arm/rss/rss_comms_protocol_pointer_access.c
+++ b/drivers/arm/rse/rse_comms_protocol_pointer_access.c

@@ -6,16 +6,16 @@
  */
 #include <assert.h>
 
-#include "rss_comms_protocol_common.h"
-#include "rss_comms_protocol_pointer_access.h"
+#include "rse_comms_protocol_common.h"
+#include "rse_comms_protocol_pointer_access.h"
 
-psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle,
+psa_status_t rse_protocol_pointer_access_serialize_msg(psa_handle_t handle,
 						       int16_t type,
 						       const psa_invec *in_vec,
 						       uint8_t in_len,
 						       const psa_outvec *out_vec,
 						       uint8_t out_len,
-						       struct rss_pointer_access_msg_t *msg,
+						       struct rse_pointer_access_msg_t *msg,
 						       size_t *msg_len)
 {
 	unsigned int i;
@@ -42,10 +42,10 @@
 	return PSA_SUCCESS;
 }
 
-psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
+psa_status_t rse_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
 							   uint8_t out_len,
 							   psa_status_t *return_val,
-							   const struct rss_pointer_access_reply_t *reply,
+							   const struct rse_pointer_access_reply_t *reply,
 							   size_t reply_size)
 {
 	unsigned int i;

diff --git a/drivers/arm/rse/rse_comms_protocol_pointer_access.h b/drivers/arm/rse/rse_comms_protocol_pointer_access.h
new file mode 100644
index 0000000..e5935f3
--- /dev/null
+++ b/drivers/arm/rse/rse_comms_protocol_pointer_access.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSE_COMMS_PROTOCOL_POINTER_ACCESS_H__
+#define __RSE_COMMS_PROTOCOL_POINTER_ACCESS_H__
+
+#include <cdefs.h>
+
+#include <psa/client.h>
+
+struct __packed rse_pointer_access_msg_t {
+	psa_handle_t handle;
+	uint32_t ctrl_param;
+	uint32_t io_sizes[PSA_MAX_IOVEC];
+	uint64_t host_ptrs[PSA_MAX_IOVEC];
+};
+
+struct __packed rse_pointer_access_reply_t {
+	int32_t return_val;
+	uint32_t out_sizes[PSA_MAX_IOVEC];
+};
+
+psa_status_t rse_protocol_pointer_access_serialize_msg(psa_handle_t handle,
+						       int16_t type,
+						       const psa_invec *in_vec,
+						       uint8_t in_len,
+						       const psa_outvec *out_vec,
+						       uint8_t out_len,
+						       struct rse_pointer_access_msg_t *msg,
+						       size_t *msg_len);
+
+psa_status_t rse_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
+							   uint8_t out_len,
+							   psa_status_t *return_val,
+							   const struct rse_pointer_access_reply_t *reply,
+							   size_t reply_size);
+
+#endif /* __RSE_COMMS_PROTOCOL_POINTER_ACCESS_H__ */

diff --git a/drivers/arm/rss/rss_comms.mk b/drivers/arm/rss/rss_comms.mk
deleted file mode 100644
index 0d1e308..0000000
--- a/drivers/arm/rss/rss_comms.mk
+++ /dev/null

@@ -1,34 +0,0 @@
-#
-# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-$(warning "RSS driver is an experimental feature")
-
-RSS_COMMS_SOURCES	:=	$(addprefix drivers/arm/rss/,			\
-					rss_comms.c				\
-					rss_comms_protocol.c			\
-					rss_comms_protocol_embed.c		\
-					rss_comms_protocol_pointer_access.c	\
-				)
-
-# Default to MHUv2 if PLAT_MHU_VERSION undefined
-PLAT_MHU_VERSION ?= 2
-
-ifeq (${PLAT_MHU_VERSION}, 3)
-RSS_COMMS_SOURCES	+=	$(addprefix drivers/arm/mhu/,			\
-					mhu_v3_x.c				\
-					mhu_wrapper_v3_x.c			\
-				)
-else ifeq (${PLAT_MHU_VERSION}, 2)
-RSS_COMMS_SOURCES	+=	$(addprefix drivers/arm/mhu/,			\
-					mhu_v2_x.c				\
-					mhu_wrapper_v2_x.c			\
-				)
-else
-$(error Unsupported MHU version)
-endif
-
-PLAT_INCLUDES		+=	-Idrivers/arm/rss		\
-				-Idrivers/arm/mhu

diff --git a/drivers/arm/rss/rss_comms_protocol.h b/drivers/arm/rss/rss_comms_protocol.h
deleted file mode 100644
index 9a38057..0000000
--- a/drivers/arm/rss/rss_comms_protocol.h
+++ /dev/null

@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __RSS_COMMS_PROTOCOL_H__
-#define __RSS_COMMS_PROTOCOL_H__
-
-#include <cdefs.h>
-#include <stdint.h>
-
-#include <psa/client.h>
-#include "rss_comms_protocol_embed.h"
-#include "rss_comms_protocol_pointer_access.h"
-
-enum rss_comms_protocol_version_t {
-	RSS_COMMS_PROTOCOL_EMBED = 0,
-	RSS_COMMS_PROTOCOL_POINTER_ACCESS = 1,
-};
-
-struct __packed serialized_rss_comms_header_t {
-	uint8_t protocol_ver;
-	uint8_t seq_num;
-	uint16_t client_id;
-};
-
-/* MHU message passed from Host to RSS to deliver a PSA client call */
-struct __packed serialized_rss_comms_msg_t {
-	struct serialized_rss_comms_header_t header;
-	union __packed {
-		struct rss_embed_msg_t embed;
-		struct rss_pointer_access_msg_t pointer_access;
-	} msg;
-};
-
-/* MHU reply message to hold the PSA client reply result returned by RSS */
-struct __packed serialized_rss_comms_reply_t {
-	struct serialized_rss_comms_header_t header;
-	union __packed {
-		struct rss_embed_reply_t embed;
-		struct rss_pointer_access_reply_t pointer_access;
-	} reply;
-};
-
-/* in_len and out_len are uint8_ts, therefore if there are more than 255 iovecs
- * an error may occur.
- */
-CASSERT(PSA_MAX_IOVEC <= UINT8_MAX, assert_rss_comms_max_iovec_too_large);
-
-psa_status_t rss_protocol_serialize_msg(psa_handle_t handle,
-					int16_t type,
-					const psa_invec *in_vec,
-					uint8_t in_len,
-					const psa_outvec *out_vec,
-					uint8_t out_len,
-					struct serialized_rss_comms_msg_t *msg,
-					size_t *msg_len);
-
-psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec,
-					    uint8_t out_len,
-					    psa_status_t *return_val,
-					    const struct serialized_rss_comms_reply_t *reply,
-					    size_t reply_size);
-
-#endif /* __RSS_COMMS_PROTOCOL_H__ */

diff --git a/drivers/arm/rss/rss_comms_protocol_embed.h b/drivers/arm/rss/rss_comms_protocol_embed.h
deleted file mode 100644
index c81c795..0000000
--- a/drivers/arm/rss/rss_comms_protocol_embed.h
+++ /dev/null

@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __RSS_COMMS_PROTOCOL_EMBED_H__
-#define __RSS_COMMS_PROTOCOL_EMBED_H__
-
-#include <cdefs.h>
-
-#include <psa/client.h>
-
-#include <platform_def.h>
-
-
-
-struct __packed rss_embed_msg_t {
-	psa_handle_t handle;
-	uint32_t ctrl_param; /* type, in_len, out_len */
-	uint16_t io_size[PSA_MAX_IOVEC];
-	uint8_t trailer[PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE];
-};
-
-struct __packed rss_embed_reply_t {
-	int32_t return_val;
-	uint16_t out_size[PSA_MAX_IOVEC];
-	uint8_t trailer[PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE];
-};
-
-psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle,
-					      int16_t type,
-					      const psa_invec *in_vec,
-					      uint8_t in_len,
-					      const psa_outvec *out_vec,
-					      uint8_t out_len,
-					      struct rss_embed_msg_t *msg,
-					      size_t *msg_len);
-
-psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec,
-						  uint8_t out_len,
-						  psa_status_t *return_val,
-						  const struct rss_embed_reply_t *reply,
-						  size_t reply_size);
-
-#endif /* __RSS_COMMS_PROTOCOL_EMBED_H__ */

diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.h b/drivers/arm/rss/rss_comms_protocol_pointer_access.h
deleted file mode 100644
index a4d054b..0000000
--- a/drivers/arm/rss/rss_comms_protocol_pointer_access.h
+++ /dev/null

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__
-#define __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__
-
-#include <cdefs.h>
-
-#include <psa/client.h>
-
-struct __packed rss_pointer_access_msg_t {
-	psa_handle_t handle;
-	uint32_t ctrl_param;
-	uint32_t io_sizes[PSA_MAX_IOVEC];
-	uint64_t host_ptrs[PSA_MAX_IOVEC];
-};
-
-struct __packed rss_pointer_access_reply_t {
-	int32_t return_val;
-	uint32_t out_sizes[PSA_MAX_IOVEC];
-};
-
-psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle,
-						       int16_t type,
-						       const psa_invec *in_vec,
-						       uint8_t in_len,
-						       const psa_outvec *out_vec,
-						       uint8_t out_len,
-						       struct rss_pointer_access_msg_t *msg,
-						       size_t *msg_len);
-
-psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
-							   uint8_t out_len,
-							   psa_status_t *return_val,
-							   const struct rss_pointer_access_reply_t *reply,
-							   size_t reply_size);
-
-#endif /* __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__ */

diff --git a/drivers/measured_boot/rss/dice_prot_env.c b/drivers/measured_boot/rse/dice_prot_env.c
similarity index 98%
rename from drivers/measured_boot/rss/dice_prot_env.c
rename to drivers/measured_boot/rse/dice_prot_env.c
index 81a21d1..8e9185a 100644
--- a/drivers/measured_boot/rss/dice_prot_env.c
+++ b/drivers/measured_boot/rse/dice_prot_env.c

@@ -13,7 +13,7 @@
 
 #include <common/debug.h>
 #include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
 #include <lib/cassert.h>
 #include <lib/psa/dice_protection_environment.h>
 

diff --git a/drivers/measured_boot/rss/dice_prot_env.mk b/drivers/measured_boot/rse/dice_prot_env.mk
similarity index 91%
rename from drivers/measured_boot/rss/dice_prot_env.mk
rename to drivers/measured_boot/rse/dice_prot_env.mk
index c5a35e0..7c83307 100644
--- a/drivers/measured_boot/rss/dice_prot_env.mk
+++ b/drivers/measured_boot/rse/dice_prot_env.mk

@@ -26,4 +26,4 @@
         DPE_DIGEST_SIZE \
 )))
 
-DPE_SOURCES	+=	drivers/measured_boot/rss/dice_prot_env.c
+DPE_SOURCES	+=	drivers/measured_boot/rse/dice_prot_env.c

diff --git a/drivers/measured_boot/rss/qcbor.mk b/drivers/measured_boot/rse/qcbor.mk
similarity index 100%
rename from drivers/measured_boot/rss/qcbor.mk
rename to drivers/measured_boot/rse/qcbor.mk


diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rse/rse_measured_boot.c
similarity index 87%
rename from drivers/measured_boot/rss/rss_measured_boot.c
rename to drivers/measured_boot/rse/rse_measured_boot.c
index c44ec73..5337c3d 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.c
+++ b/drivers/measured_boot/rse/rse_measured_boot.c

@@ -9,7 +9,7 @@
 
 #include <common/debug.h>
 #include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
 #include <lib/psa/measured_boot.h>
 #include <psa/crypto_types.h>
 #include <psa/crypto_values.h>
@@ -46,12 +46,12 @@
 #endif /* ENABLE_ASSERTIONS */
 
 /* Functions' declarations */
-void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr)
+void rse_measured_boot_init(struct rse_mboot_metadata *metadata_ptr)
 {
 	assert(metadata_ptr != NULL);
 
 	/* Init the non-const members of the metadata structure */
-	while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+	while (metadata_ptr->id != RSE_MBOOT_INVALID_ID) {
 		assert(null_arr(metadata_ptr->signer_id, MBOOT_DIGEST_SIZE));
 		metadata_ptr->sw_type_size =
 			strlen((const char *)&metadata_ptr->sw_type) + 1;
@@ -59,7 +59,7 @@
 	}
 }
 
-int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr,
+int rse_mboot_measure_and_record(struct rse_mboot_metadata *metadata_ptr,
 				 uintptr_t data_base, uint32_t data_size,
 				 uint32_t data_id)
 {
@@ -70,13 +70,13 @@
 	assert(metadata_ptr != NULL);
 
 	/* Get the metadata associated with this image. */
-	while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) &&
+	while ((metadata_ptr->id != RSE_MBOOT_INVALID_ID) &&
 		(metadata_ptr->id != data_id)) {
 		metadata_ptr++;
 	}
 
 	/* If image is not present in metadata array then skip */
-	if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) {
+	if (metadata_ptr->id == RSE_MBOOT_INVALID_ID) {
 		return 0;
 	}
 
@@ -87,7 +87,7 @@
 		return rc;
 	}
 
-	ret = rss_measured_boot_extend_measurement(
+	ret = rse_measured_boot_extend_measurement(
 						metadata_ptr->slot,
 						metadata_ptr->signer_id,
 						metadata_ptr->signer_id_size,
@@ -106,7 +106,7 @@
 	return 0;
 }
 
-int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+int rse_mboot_set_signer_id(struct rse_mboot_metadata *metadata_ptr,
 			    const void *pk_oid,
 			    const void *pk_ptr,
 			    size_t pk_len)
@@ -125,7 +125,7 @@
 	 * The platform may decide not to measure all of the images
 	 * in the system.
 	 */
-	while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+	while (metadata_ptr->id != RSE_MBOOT_INVALID_ID) {
 		/* Get the metadata associated with this key-oid */
 		if (metadata_ptr->pk_oid == pk_oid) {
 			if (hash_calc_done == false) {

diff --git a/drivers/measured_boot/rss/rss_measured_boot.mk b/drivers/measured_boot/rse/rse_measured_boot.mk
similarity index 65%
rename from drivers/measured_boot/rss/rss_measured_boot.mk
rename to drivers/measured_boot/rse/rse_measured_boot.mk
index 18ee836..1bd971f 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.mk
+++ b/drivers/measured_boot/rse/rse_measured_boot.mk

@@ -6,27 +6,27 @@
 
 # Hash algorithm for measured boot
 # SHA-256 (or stronger) is required.
-MBOOT_RSS_HASH_ALG		:=	sha256
+MBOOT_RSE_HASH_ALG		:=	sha256
 
-ifeq (${MBOOT_RSS_HASH_ALG}, sha512)
+ifeq (${MBOOT_RSE_HASH_ALG}, sha512)
     MBOOT_ALG_ID		:=	MBOOT_ALG_SHA512
     MBOOT_DIGEST_SIZE		:=	64U
-else ifeq (${MBOOT_RSS_HASH_ALG}, sha384)
+else ifeq (${MBOOT_RSE_HASH_ALG}, sha384)
     MBOOT_ALG_ID		:=	MBOOT_ALG_SHA384
     MBOOT_DIGEST_SIZE		:=	48U
 else
     MBOOT_ALG_ID		:=	MBOOT_ALG_SHA256
     MBOOT_DIGEST_SIZE		:=	32U
-endif #MBOOT_RSS_HASH_ALG
+endif #MBOOT_RSE_HASH_ALG
 
 # Set definitions for Measured Boot driver.
 $(eval $(call add_defines,\
     $(sort \
         MBOOT_ALG_ID \
         MBOOT_DIGEST_SIZE \
-        MBOOT_RSS_BACKEND \
+        MBOOT_RSE_BACKEND \
 )))
 
-MEASURED_BOOT_SRC_DIR	:= drivers/measured_boot/rss/
+MEASURED_BOOT_SRC_DIR	:= drivers/measured_boot/rse/
 
-MEASURED_BOOT_SOURCES	+= ${MEASURED_BOOT_SRC_DIR}rss_measured_boot.c
+MEASURED_BOOT_SOURCES	+= ${MEASURED_BOOT_SRC_DIR}rse_measured_boot.c

diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 6c31d9d..5508ebb 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h

@@ -131,7 +131,6 @@
 #define MPAMVPM6_EL2		S3_4_C10_C6_6
 #define MPAMVPM7_EL2		S3_4_C10_C6_7
 #define MPAMVPMV_EL2		S3_4_C10_C4_1
-#define TRFCR_EL2		S3_4_C1_C2_1
 #define VNCR_EL2		S3_4_C2_C2_0
 #define PMSCR_EL2		S3_4_C9_C9_0
 #define TFSR_EL2		S3_4_C5_C6_0
@@ -1337,6 +1336,8 @@
 #define GPTBR_EL3			S3_6_C2_C1_4
 
 #define SCXTNUM_EL2			S3_4_C13_C0_7
+#define SCXTNUM_EL1			S3_0_C13_C0_7
+#define SCXTNUM_EL0			S3_3_C13_C0_7
 
 /*******************************************************************************
  * RAS system registers
@@ -1459,10 +1460,19 @@
 #define GCSCR_EL2		S3_4_C2_C5_0
 #define GCSPR_EL2		S3_4_C2_C5_1
 #define GCSCR_EL1		S3_0_C2_C5_0
+#define GCSCRE0_EL1		S3_0_C2_C5_2
+#define GCSPR_EL1		S3_0_C2_C5_1
+#define GCSPR_EL0		S3_3_C2_C5_1
 
 #define GCSCR_EXLOCK_EN_BIT	(UL(1) << 6)
 
 /*******************************************************************************
+ * FEAT_TRF - Trace Filter Control Registers
+ ******************************************************************************/
+#define TRFCR_EL2		S3_4_C1_C2_1
+#define TRFCR_EL1		S3_0_C1_C2_1
+
+/*******************************************************************************
  * Definitions for DynamicIQ Shared Unit registers
  ******************************************************************************/
 #define CLUSTERPWRDN_EL1	S3_0_c15_c3_6

diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index da7b162..57dbc06 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h

@@ -569,6 +569,8 @@
 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
 
 /* Armv8.1 VHE Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
@@ -606,6 +608,7 @@
 
 /* Armv8.4 FEAT_TRF Register */
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
 
 /* Armv8.5 MTE Registers */
@@ -656,6 +659,9 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
 
 /* DynamIQ Shared Unit power management */
 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
@@ -712,16 +718,88 @@
 }
 
 /*
- * TLBIPAALLOS instruction
- * (TLB Inivalidate GPT Information by PA,
- * All Entries, Outer Shareable)
+ * TLBI PAALLOS instruction
+ * (TLB Invalidate GPT Information by PA, All Entries, Outer Shareable)
  */
 static inline void tlbipaallos(void)
 {
-	__asm__("SYS #6,c8,c1,#4");
+	__asm__("sys #6, c8, c1, #4");
 }
 
 /*
+ * TLBI RPALOS instructions
+ * (TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable)
+ *
+ * command SIZE, bits [47:44] field:
+ * 0b0000	4KB
+ * 0b0001	16KB
+ * 0b0010	64KB
+ * 0b0011	2MB
+ * 0b0100	32MB
+ * 0b0101	512MB
+ * 0b0110	1GB
+ * 0b0111	16GB
+ * 0b1000	64GB
+ * 0b1001	512GB
+ */
+#define TLBI_SZ_4K		0UL
+#define TLBI_SZ_16K		1UL
+#define TLBI_SZ_64K		2UL
+#define TLBI_SZ_2M		3UL
+#define TLBI_SZ_32M		4UL
+#define TLBI_SZ_512M		5UL
+#define TLBI_SZ_1G		6UL
+#define TLBI_SZ_16G		7UL
+#define TLBI_SZ_64G		8UL
+#define TLBI_SZ_512G		9UL
+
+#define	TLBI_ADDR_SHIFT		U(12)
+#define	TLBI_SIZE_SHIFT		U(44)
+
+#define TLBIRPALOS(_addr, _size)				\
+{								\
+	u_register_t arg = ((_addr) >> TLBI_ADDR_SHIFT) |	\
+			   ((_size) << TLBI_SIZE_SHIFT);	\
+	__asm__("sys #6, c8, c4, #7, %0" : : "r" (arg));	\
+}
+
+/* Note: addr must be aligned to 4KB */
+static inline void tlbirpalos_4k(uintptr_t addr)
+{
+	TLBIRPALOS(addr, TLBI_SZ_4K);
+}
+
+/* Note: addr must be aligned to 16KB */
+static inline void tlbirpalos_16k(uintptr_t addr)
+{
+	TLBIRPALOS(addr, TLBI_SZ_16K);
+}
+
+/* Note: addr must be aligned to 64KB */
+static inline void tlbirpalos_64k(uintptr_t addr)
+{
+	TLBIRPALOS(addr, TLBI_SZ_64K);
+}
+
+/* Note: addr must be aligned to 2MB */
+static inline void tlbirpalos_2m(uintptr_t addr)
+{
+	TLBIRPALOS(addr, TLBI_SZ_2M);
+}
+
+/* Note: addr must be aligned to 32MB */
+static inline void tlbirpalos_32m(uintptr_t addr)
+{
+	TLBIRPALOS(addr, TLBI_SZ_32M);
+}
+
+/* Note: addr must be aligned to 512MB */
+static inline void tlbirpalos_512m(uintptr_t addr)
+{
+	TLBIRPALOS(addr, TLBI_SZ_512M);
+}
+
+/*
  * Invalidate TLBs of GPT entries by Physical address, last level.
  *
  * @pa: the starting address for the range
@@ -730,7 +808,6 @@
  */
 void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
 
-
 /* Previously defined accessor functions with incomplete register names  */
 
 #define read_current_el()	read_CurrentEl()

diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h
index 7cd7e72..3ab88de 100644
--- a/include/bl1/bl1.h
+++ b/include/bl1/bl1.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -94,9 +94,5 @@
 		(FWU_SMC_FID_END - FWU_SMC_FID_START + 1),
 		assert_FWU_NUM_SMC_CALLS_mismatch);
 
-/* Utility functions */
-void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
-			meminfo_t *bl2_mem_layout);
-
 #endif /* __ASSEMBLER__ */
 #endif /* BL1_H */

diff --git a/include/drivers/arm/rse_comms.h b/include/drivers/arm/rse_comms.h
new file mode 100644
index 0000000..e4169a5
--- /dev/null
+++ b/include/drivers/arm/rse_comms.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef RSE_COMMS_H
+#define RSE_COMMS_H
+
+#include <stdint.h>
+
+int rse_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base);
+
+#endif /* RSE_COMMS_H */

diff --git a/include/drivers/arm/rss_comms.h b/include/drivers/arm/rss_comms.h
deleted file mode 100644
index b96c79f..0000000
--- a/include/drivers/arm/rss_comms.h
+++ /dev/null

@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef RSS_COMMS_H
-#define RSS_COMMS_H
-
-#include <stdint.h>
-
-int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base);
-
-#endif /* RSS_COMMS_H */

diff --git a/include/drivers/measured_boot/rss/dice_prot_env.h b/include/drivers/measured_boot/rse/dice_prot_env.h
similarity index 100%
rename from include/drivers/measured_boot/rss/dice_prot_env.h
rename to include/drivers/measured_boot/rse/dice_prot_env.h


diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rse/rse_measured_boot.h
similarity index 65%
rename from include/drivers/measured_boot/rss/rss_measured_boot.h
rename to include/drivers/measured_boot/rse/rse_measured_boot.h
index 38f7d4e..2f605d7 100644
--- a/include/drivers/measured_boot/rss/rss_measured_boot.h
+++ b/include/drivers/measured_boot/rse/rse_measured_boot.h

@@ -4,17 +4,17 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef RSS_MEASURED_BOOT_H
-#define RSS_MEASURED_BOOT_H
+#ifndef RSE_MEASURED_BOOT_H
+#define RSE_MEASURED_BOOT_H
 
 #include <stdint.h>
 
 #include <common/debug.h>
 #include <drivers/measured_boot/metadata.h>
 
-#define RSS_MBOOT_INVALID_ID	UINT32_MAX
+#define RSE_MBOOT_INVALID_ID	UINT32_MAX
 
-struct rss_mboot_metadata {
+struct rse_mboot_metadata {
 	unsigned int id;
 	uint8_t slot;
 	uint8_t signer_id[SIGNER_ID_MAX_SIZE];
@@ -28,13 +28,13 @@
 };
 
 /* Functions' declarations */
-void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr);
-int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr,
+void rse_measured_boot_init(struct rse_mboot_metadata *metadata_ptr);
+int rse_mboot_measure_and_record(struct rse_mboot_metadata *metadata_ptr,
 				 uintptr_t data_base, uint32_t data_size,
 				 uint32_t data_id);
 
-int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+int rse_mboot_set_signer_id(struct rse_mboot_metadata *metadata_ptr,
 			    const void *pk_oid, const void *pk_ptr,
 			    size_t pk_len);
 
-#endif /* RSS_MEASURED_BOOT_H */
+#endif /* RSE_MEASURED_BOOT_H */

diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
index 17d07c8..433687b 100644
--- a/include/lib/cpus/aarch64/cortex_x4.h
+++ b/include/lib/cpus/aarch64/cortex_x4.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,4 +23,9 @@
 #define CORTEX_X4_CPUPWRCTLR_EL1			S3_0_C15_C2_7
 #define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
+/*******************************************************************************
+ * CPU Auxiliary control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X4_CPUACTLR3_EL1				S3_0_C15_C1_2
+
 #endif /* CORTEX_X4_H */

diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 74790d1..4f11ad2 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h

@@ -191,10 +191,35 @@
 #define CTX_TCR2_REGS_END       CTX_S2POE_REGS_END
 #endif /* ENABLE_FEAT_TCR2 */
 
+#if ENABLE_TRF_FOR_NS
+#define CTX_TRFCR_EL1		(CTX_TCR2_REGS_END + U(0x0))
+#define CTX_TRF_REGS_END	(CTX_TCR2_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_TRF_REGS_END	CTX_TCR2_REGS_END
+#endif /* ENABLE_TRF_FOR_NS */
+
+#if ENABLE_FEAT_CSV2_2
+#define CTX_SCXTNUM_EL0		(CTX_TRF_REGS_END + U(0x0))
+#define CTX_SCXTNUM_EL1		(CTX_TRF_REGS_END + U(0x8))
+#define CTX_CSV2_2_REGS_END	(CTX_TRF_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_CSV2_2_REGS_END	CTX_TRF_REGS_END
+#endif /* ENABLE_FEAT_CSV2_2 */
+
+#if ENABLE_FEAT_GCS
+#define CTX_GCSCR_EL1		(CTX_CSV2_2_REGS_END + U(0x0))
+#define CTX_GCSCRE0_EL1		(CTX_CSV2_2_REGS_END + U(0x8))
+#define CTX_GCSPR_EL1		(CTX_CSV2_2_REGS_END + U(0x10))
+#define CTX_GCSPR_EL0		(CTX_CSV2_2_REGS_END + U(0x18))
+#define CTX_GCS_REGS_END	(CTX_CSV2_2_REGS_END + U(0x20)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_GCS_REGS_END	CTX_CSV2_2_REGS_END
+#endif /* ENABLE_FEAT_GCS */
+
 /*
- * End of system registers.
+ * End of EL1 system registers.
  */
-#define CTX_EL1_SYSREGS_END	CTX_TCR2_REGS_END
+#define CTX_EL1_SYSREGS_END	CTX_GCS_REGS_END
 
 /*******************************************************************************
  * Constants that allow assembler code to access members of and the 'fp_regs'

diff --git a/include/lib/psa/delegated_attestation.h b/include/lib/psa/delegated_attestation.h
index 7aaceb3..ec49f5d 100644
--- a/include/lib/psa/delegated_attestation.h
+++ b/include/lib/psa/delegated_attestation.h

@@ -15,9 +15,9 @@
 
 #include "psa/error.h"
 
-/* RSS Delegated Attestation message types that distinguish its services. */
-#define RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY      1001U
-#define RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN     1002U
+/* RSE Delegated Attestation message types that distinguish its services. */
+#define RSE_DELEGATED_ATTEST_GET_DELEGATED_KEY      1001U
+#define RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN     1002U
 
 /**
  * The aim of these APIs to get a derived signing key (private only) for the
@@ -28,13 +28,13 @@
  * key is bind to the platform token (details below).
  *
  * Expected usage model:
- *  - First rss_delegated_attest_get_delegated_key() API need to be called to
+ *  - First rse_delegated_attest_get_delegated_key() API need to be called to
  *    obtain the private part of the delegated attestation key. The public part
  *    of key is computed by the cryptographic library when the key is
  *    registered.
- *  - Secondly the rss_delegated_attest_get_token() must be called to obtain
+ *  - Secondly the rse_delegated_attest_get_token() must be called to obtain
  *    platform attestation token. The hash of the public key (computed by
- *    the hash_algo indicated in the rss_delegated_attest_get_delegated_key()
+ *    the hash_algo indicated in the rse_delegated_attest_get_delegated_key()
  *    call) must be the input of this call. This ensures that nothing but the
  *    previously derived delegated key is bindable to the platform token.
  */
@@ -74,7 +74,7 @@
  *     platform attestation token as they are cryptographically linked together.
  */
 psa_status_t
-rss_delegated_attest_get_delegated_key(uint8_t   ecc_curve,
+rse_delegated_attest_get_delegated_key(uint8_t   ecc_curve,
 				       uint32_t  key_bits,
 				       uint8_t  *key_buf,
 				       size_t    key_buf_size,
@@ -100,7 +100,7 @@
  * code will be returned.
  */
 psa_status_t
-rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+rse_delegated_attest_get_token(const uint8_t *dak_pub_hash,
 			       size_t         dak_pub_hash_size,
 			       uint8_t       *token_buf,
 			       size_t         token_buf_size,

diff --git a/include/lib/psa/dice_protection_environment.h b/include/lib/psa/dice_protection_environment.h
index 61b6482..5351451 100644
--- a/include/lib/psa/dice_protection_environment.h
+++ b/include/lib/psa/dice_protection_environment.h

@@ -14,7 +14,7 @@
 
 #include <dice.h>
 
-/* Additional defines for max size limit. These limits are set by DPE in RSS. */
+/* Additional defines for max size limit. These limits are set by DPE in RSE. */
 #define DICE_AUTHORITY_DESCRIPTOR_MAX_SIZE	64
 #define DICE_CONFIG_DESCRIPTOR_MAX_SIZE		64
 #define DICE_CODE_DESCRIPTOR_MAX_SIZE		32
@@ -28,7 +28,7 @@
 #define DPE_ARGUMENT_NOT_SUPPORTED	((dpe_error_t)4)
 #define DPE_SESSION_EXHAUSTED		((dpe_error_t)5)
 
-/* Custom values in RSS based DPE implementation */
+/* Custom values in RSE based DPE implementation */
 #define DPE_INSUFFICIENT_MEMORY		((dpe_error_t)128)
 #define DPE_ERR_CBOR_FORMATTING		((dpe_error_t)129)
 

diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h
index 79cdfa0..3cc6c95 100644
--- a/include/lib/psa/measured_boot.h
+++ b/include/lib/psa/measured_boot.h

@@ -43,11 +43,11 @@
  *	- When the requested slot is not accessible to the caller.
  */
 
-/* Not a standard PSA API, just an extension therefore use the 'rss_' prefix
+/* Not a standard PSA API, just an extension therefore use the 'rse_' prefix
  * rather than the usual 'psa_'.
  */
 psa_status_t
-rss_measured_boot_extend_measurement(uint8_t index,
+rse_measured_boot_extend_measurement(uint8_t index,
 				     const uint8_t *signer_id,
 				     size_t signer_id_size,
 				     const uint8_t *version,
@@ -92,7 +92,7 @@
  * PSA_ERROR_DOES_NOT_EXIST
  *	- The requested slot is empty, does not contain a measurement.
  */
-psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+psa_status_t rse_measured_boot_read_measurement(uint8_t index,
 					uint8_t *signer_id,
 					size_t signer_id_size,
 					size_t *signer_id_len,

diff --git a/include/lib/psa/psa_manifest/sid.h b/include/lib/psa/psa_manifest/sid.h
index 6c15656..bb8abe4 100644
--- a/include/lib/psa/psa_manifest/sid.h
+++ b/include/lib/psa/psa_manifest/sid.h

@@ -8,19 +8,19 @@
 #ifndef PSA_MANIFEST_SID_H
 #define PSA_MANIFEST_SID_H
 
-/******** RSS_SP_CRYPTO ********/
-#define RSS_CRYPTO_HANDLE				(0x40000100U)
+/******** RSE_SP_CRYPTO ********/
+#define RSE_CRYPTO_HANDLE				(0x40000100U)
 
-/******** RSS_SP_PLATFORM ********/
-#define RSS_PLATFORM_SERVICE_HANDLE			(0x40000105U)
+/******** RSE_SP_PLATFORM ********/
+#define RSE_PLATFORM_SERVICE_HANDLE			(0x40000105U)
 
 /******** PSA_SP_MEASURED_BOOT ********/
-#define RSS_MEASURED_BOOT_HANDLE			(0x40000110U)
+#define RSE_MEASURED_BOOT_HANDLE			(0x40000110U)
 
 /******** PSA_SP_DELEGATED_ATTESTATION ********/
-#define RSS_DELEGATED_SERVICE_HANDLE			(0x40000111U)
+#define RSE_DELEGATED_SERVICE_HANDLE			(0x40000111U)
 
 /******** PSA_SP_DICE_PROTECTION_ENVIRONMENT ********/
-#define RSS_DPE_SERVICE_HANDLE				(0x40000112U)
+#define RSE_DPE_SERVICE_HANDLE				(0x40000112U)
 
 #endif /* PSA_MANIFEST_SID_H */

diff --git a/include/lib/psa/rss_crypto_defs.h b/include/lib/psa/rse_crypto_defs.h
similarity index 68%
rename from include/lib/psa/rss_crypto_defs.h
rename to include/lib/psa/rse_crypto_defs.h
index 301dc05..44936b8 100644
--- a/include/lib/psa/rss_crypto_defs.h
+++ b/include/lib/psa/rse_crypto_defs.h

@@ -5,8 +5,8 @@
  *
  */
 
-#ifndef RSS_CRYPTO_DEFS_H
-#define RSS_CRYPTO_DEFS_H
+#ifndef RSE_CRYPTO_DEFS_H
+#define RSE_CRYPTO_DEFS_H
 
 /* Declares types that encode errors, algorithms, key types, policies, etc. */
 #include "psa/crypto_types.h"
@@ -16,31 +16,31 @@
  * to the corresponding API implementation in the Crypto service backend.
  *
  */
-#define RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID	(uint16_t)(0x701)
+#define RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID	(uint16_t)(0x701)
 
 /*
- * The persistent key identifiers for RSS builtin keys.
+ * The persistent key identifiers for RSE builtin keys.
  */
-enum rss_key_id_builtin_t {
-	RSS_BUILTIN_KEY_ID_HOST_S_ROTPK = 0x7FFF816Cu,
-	RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK,
-	RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK,
+enum rse_key_id_builtin_t {
+	RSE_BUILTIN_KEY_ID_HOST_S_ROTPK = 0x7FFF816Cu,
+	RSE_BUILTIN_KEY_ID_HOST_NS_ROTPK,
+	RSE_BUILTIN_KEY_ID_HOST_CCA_ROTPK,
 };
 
 /*
- * This type is used to overcome a limitation within RSS firmware in the number of maximum
+ * This type is used to overcome a limitation within RSE firmware in the number of maximum
  * IOVECs it can use especially in psa_aead_encrypt and psa_aead_decrypt.
  */
-#define RSS_CRYPTO_MAX_NONCE_LENGTH (16u)
-struct rss_crypto_aead_pack_input {
-	uint8_t nonce[RSS_CRYPTO_MAX_NONCE_LENGTH];
+#define RSE_CRYPTO_MAX_NONCE_LENGTH (16u)
+struct rse_crypto_aead_pack_input {
+	uint8_t nonce[RSE_CRYPTO_MAX_NONCE_LENGTH];
 	uint32_t nonce_length;
 };
 
 /*
  * Structure used to pack non-pointer types in a call to PSA Crypto APIs
  */
-struct rss_crypto_pack_iovec {
+struct rse_crypto_pack_iovec {
 	psa_key_id_t key_id;		/* !< Key id */
 	psa_algorithm_t alg;		/* !< Algorithm */
 	uint32_t op_handle;		/*
@@ -56,7 +56,7 @@
 					 *    AEAD
 					 */
 
-	struct rss_crypto_aead_pack_input aead_in; /*
+	struct rse_crypto_aead_pack_input aead_in; /*
 						    * !< Packs AEAD-related
 						    *    inputs
 						    */
@@ -64,7 +64,7 @@
 	uint16_t function_id;	/*
 				 * !< Used to identify the function in the
 				 *    API dispatcher to the service backend
-				 *    See rss_crypto_func_sid for detail
+				 *    See rse_crypto_func_sid for detail
 				 */
 	uint16_t step;		/* !< Key derivation step */
 	union {
@@ -76,4 +76,4 @@
 	};
 };
 
-#endif /* RSS_CRYPTO_DEFS_H */
+#endif /* RSE_CRYPTO_DEFS_H */

diff --git a/include/lib/psa/rss_platform_api.h b/include/lib/psa/rse_platform_api.h
similarity index 75%
rename from include/lib/psa/rss_platform_api.h
rename to include/lib/psa/rse_platform_api.h
index 8f74a51..535001b 100644
--- a/include/lib/psa/rss_platform_api.h
+++ b/include/lib/psa/rse_platform_api.h

@@ -5,16 +5,16 @@
  *
  */
 
-#ifndef RSS_PLATFORM_API_H
-#define RSS_PLATFORM_API_H
+#ifndef RSE_PLATFORM_API_H
+#define RSE_PLATFORM_API_H
 
 #include <stdint.h>
 
 #include "psa/error.h"
-#include <rss_crypto_defs.h>
+#include <rse_crypto_defs.h>
 
-#define RSS_PLATFORM_API_ID_NV_READ       (1010)
-#define RSS_PLATFORM_API_ID_NV_INCREMENT  (1011)
+#define RSE_PLATFORM_API_ID_NV_READ       (1010)
+#define RSE_PLATFORM_API_ID_NV_INCREMENT  (1011)
 
 /*
  * Increments the given non-volatile (NV) counter by one
@@ -25,7 +25,7 @@
  *	it returns a PSA_ERROR.
  */
 psa_status_t
-rss_platform_nv_counter_increment(uint32_t counter_id);
+rse_platform_nv_counter_increment(uint32_t counter_id);
 
 /*
  * Reads the given non-volatile (NV) counter
@@ -39,7 +39,7 @@
  *	it returns a PSA_ERROR.
  */
 psa_status_t
-rss_platform_nv_counter_read(uint32_t counter_id,
+rse_platform_nv_counter_read(uint32_t counter_id,
 		uint32_t size, uint8_t *val);
 
 /*
@@ -54,7 +54,7 @@
  *	it returns a PSA_ERROR.
  */
 psa_status_t
-rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data,
+rse_platform_key_read(enum rse_key_id_builtin_t key, uint8_t *data,
 		size_t data_size, size_t *data_length);
 
-#endif /* RSS_PLATFORM_API_H */
+#endif /* RSE_PLATFORM_API_H */

diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 9fd3fc6..055a911 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,15 +15,21 @@
 	volatile uint32_t lock;
 } spinlock_t;
 
+typedef struct bitlock {
+	volatile uint8_t lock;
+} bitlock_t;
+
 void spin_lock(spinlock_t *lock);
 void spin_unlock(spinlock_t *lock);
 
+void bit_lock(bitlock_t *lock, uint8_t mask);
+void bit_unlock(bitlock_t *lock, uint8_t mask);
+
 #else
 
 /* Spin lock definitions for use in assembly */
 #define SPINLOCK_ASM_ALIGN	2
 #define SPINLOCK_ASM_SIZE	4
 
-#endif
-
+#endif /* __ASSEMBLER__ */
 #endif /* SPINLOCK_H */

diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
index c5df22b..5bea270 100644
--- a/include/lib/transfer_list.h
+++ b/include/lib/transfer_list.h

@@ -44,6 +44,8 @@
 	TL_TAG_OPTEE_PAGABLE_PART = 0x100,
 	TL_TAG_DT_SPMC_MANIFEST = 0x101,
 	TL_TAG_EXEC_EP_INFO64 = 0x102,
+	TL_TAG_TB_FW_CONFIG = 0x103,
+	TL_TAG_SRAM_LAYOUT64 = 0x104,
 };
 
 enum transfer_list_ops {

diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index c3a88e7..ec5f90b 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h

@@ -411,6 +411,8 @@
 #define ARM_V2M_MAP_MEM_PROTECT		MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR,	\
 						V2M_FLASH_BLOCK_SIZE,		\
 						MT_DEVICE | MT_RW | MT_SECURE)
+
+#if !TRANSFER_LIST
 /*
  * Map the region for device tree configuration with read and write permissions
  */
@@ -418,6 +420,8 @@
 						(ARM_FW_CONFIGS_LIMIT		\
 							- ARM_BL_RAM_BASE),	\
 						MT_MEMORY | MT_RW | EL3_PAS)
+#endif
+
 /*
  * Map L0_GPT with read and write permissions
  */
@@ -505,6 +509,14 @@
  */
 #define CACHE_WRITEBACK_GRANULE		(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
 
+/* Define memory configuration for trusted boot device tree files. */
+#ifdef PLAT_ARM_TB_FW_CONFIG_SIZE
+#define ARM_TB_FW_CONFIG_MAX_SIZE	PLAT_ARM_TB_FW_CONFIG_SIZE
+#else
+#define ARM_TB_FW_CONFIG_MAX_SIZE	U(0x400)
+#endif
+
+#if !TRANSFER_LIST
 /*
  * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
  * and limit. Leave enough space of BL2 meminfo.
@@ -526,6 +538,7 @@
  */
 #define ARM_FW_CONFIGS_SIZE		(PAGE_SIZE * 2)
 #define ARM_FW_CONFIGS_LIMIT		(ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+#endif
 
 #if ENABLE_RME
 /*

diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index a43e13c..48d7068 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h

@@ -9,12 +9,14 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include <common/desc_image_load.h>
 #include <drivers/arm/tzc_common.h>
 #include <lib/bakery_lock.h>
 #include <lib/cassert.h>
 #include <lib/el3_runtime/cpu_data.h>
 #include <lib/gpt_rme/gpt_rme.h>
 #include <lib/spinlock.h>
+#include <lib/transfer_list.h>
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_compat.h>
 
@@ -254,6 +256,7 @@
 int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
 int arm_bl2_handle_post_image_load(unsigned int image_id);
 struct bl_params *arm_get_next_bl_params(void);
+void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node);
 
 /* BL2 at EL3 functions */
 void arm_bl2_el3_early_platform_setup(void);
@@ -266,12 +269,25 @@
 void arm_bl2u_plat_arch_setup(void);
 
 /* BL31 utility functions */
+#if TRANSFER_LIST
+void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
+				   u_register_t arg2, u_register_t arg3);
+#else
 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
 				uintptr_t hw_config, void *plat_params_from_bl2);
+#endif
 void arm_bl31_platform_setup(void);
 void arm_bl31_plat_runtime_setup(void);
 void arm_bl31_plat_arch_setup(void);
 
+/* Firmware Handoff utility functions */
+void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl);
+void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
+					struct transfer_list_header *secure_tl,
+					struct transfer_list_header *ns_tl);
+void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl,
+				      struct transfer_list_header *ns_tl);
+
 /* TSP utility functions */
 void arm_tsp_early_platform_setup(void);
 

diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 0aea548..6203937 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h

@@ -58,12 +58,12 @@
 	INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL)
 
 #define CSS_G1S_IRQ_PROPS(grp) \
 	CSS_G1S_INT_PROPS(grp), \
+	INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL)
 

diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 4fe3620..2af49a9 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h

@@ -243,7 +243,11 @@
 int bl1_plat_handle_pre_image_load(unsigned int image_id);
 int bl1_plat_handle_post_image_load(unsigned int image_id);
 
-#if (MEASURED_BOOT || DICE_PROTECTION_ENVIRONMENT)
+/* Utility functions */
+void bl1_plat_calc_bl2_layout(const meminfo_t *bl1_mem_layout,
+			      meminfo_t *bl2_mem_layout);
+
+#if MEASURED_BOOT
 void bl1_plat_mboot_init(void);
 void bl1_plat_mboot_finish(void);
 #else

diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index a5be22d..16be161 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S

@@ -94,6 +94,27 @@
 
 check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
 
+workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106
+	mov x0, #3
+	msr CORTEX_A715_CPUPSELR_EL3, x0
+	isb
+	ldr x0, =0xd503339f
+	msr CORTEX_A715_CPUPOR_EL3, x0
+	ldr x0, =0xfffff3ff
+	msr CORTEX_A715_CPUPMR_EL3, x0
+	mov x0, #1
+	orr x0, x0, #(3<<4)
+	orr x0, x0, #(0xf<<6)
+	orr x0, x0, #(1<<13)
+	orr x0, x0, #(1<<20)
+	orr x0, x0, #(1<<22)
+	orr x0, x0, #(1<<31)
+	orr x0, x0, #(1<<50)
+	msr CORTEX_A715_CPUPCR_EL3, x0
+workaround_reset_end cortex_a715, ERRATUM(2728106)
+
+check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1)
+
 workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*

diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 7619f9c..20f1ae1 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,6 +26,19 @@
         wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
 #endif /* WORKAROUND_CVE_2022_23960 */
 
+workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
+	/* dsb before isb of power down sequence */
+	dsb	sy
+workaround_runtime_end cortex_x4, ERRATUM(2740089)
+
+check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
+
+workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018
+	sysreg_bit_set	CORTEX_X4_CPUACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_x4, ERRATUM(2763018)
+
+check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
+
 workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -53,6 +66,9 @@
 	 * ---------------------------------------------------
 	 */
 	sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
+	apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
+
 	isb
 	ret
 endfunc cortex_x4_core_pwr_dwn

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 872f6c7..f736b5a 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk

@@ -823,6 +823,14 @@
 # cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_X4_2701112
 
+# Flag to apply erratum 2740089 workaround during powerdown. This erratum
+# applies to all revisions <= r0p1 of the Cortex-X4 cpu, it is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_2740089
+
+# Flag to apply erratum 2763018 workaround on reset. This erratum applies
+# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_2763018
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_A510_1922240
@@ -940,6 +948,10 @@
 # only to revision r1p0. It is fixed in r1p1.
 CPU_FLAG_LIST += ERRATA_A715_2561034
 
+# Flag to apply erratum 2728106 workaround during reset. This erratum applies
+# only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_A715_2728106
+
 # Flag to apply erratum 2926083 workaround during reset. This erratum applies
 # to revisions r0p0 and r0p1. It is fixed in r0p2.
 CPU_FLAG_LIST += ERRATA_A720_2926083

diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index e96156d..301c60c 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c

@@ -149,11 +149,9 @@
 		trf_init_el3();
 	}
 
-	/*
-	 * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure
-	 * state execution. This does not affect lower NS ELs.
-	 */
-	pmuv3_init_el3();
+	if (read_feat_pmuv3_id_field() >= 3U) {
+		pmuv3_init_el3();
+	}
 #endif /*  IMAGE_BL32 */
 }
 

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index be75e53..35c98f5 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c

@@ -1549,6 +1549,28 @@
 		write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1());
 	}
 #endif
+
+#if ENABLE_TRF_FOR_NS
+	if (is_feat_trf_supported()) {
+		write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1());
+	}
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+	if (is_feat_csv2_2_supported()) {
+		write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0());
+		write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1());
+	}
+#endif
+
+#if ENABLE_FEAT_GCS
+	if (is_feat_gcs_supported()) {
+		write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1());
+		write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1());
+		write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1());
+		write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0());
+	}
+#endif
 }
 
 static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@@ -1636,6 +1658,28 @@
 		write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1));
 	}
 #endif
+
+#if ENABLE_TRF_FOR_NS
+	if (is_feat_trf_supported()) {
+		write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1));
+	}
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+	if (is_feat_csv2_2_supported()) {
+		write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0));
+		write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1));
+	}
+#endif
+
+#if ENABLE_FEAT_GCS
+	if (is_feat_gcs_supported()) {
+		write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1));
+		write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1));
+		write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1));
+		write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0));
+	}
+#endif
 }
 
 /*******************************************************************************

diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c
index effb7e0..456a48e 100644
--- a/lib/extensions/pmuv3/aarch32/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch32/pmuv3.c

@@ -25,10 +25,6 @@
 	return sdcr;
 }
 
-/*
- * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and
- * to not clash with platforms which reuse the PMU name
- */
 void pmuv3_init_el3(void)
 {
 	u_register_t sdcr = read_sdcr();

diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index 36f7a51..72e905e 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,7 +21,7 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 
 #if !ENABLE_RME
-#error "ENABLE_RME must be enabled to use the GPT library."
+#error "ENABLE_RME must be enabled to use the GPT library"
 #endif
 
 /*
@@ -58,7 +58,7 @@
 static const gpt_p_val_e gpt_p_lookup[] = {PGS_4KB_P, PGS_64KB_P, PGS_16KB_P};
 
 /*
- * This structure contains GPT configuration data.
+ * This structure contains GPT configuration data
  */
 typedef struct {
 	uintptr_t plat_gpt_l0_base;
@@ -70,7 +70,7 @@
 
 static gpt_config_t gpt_config;
 
-/* These variables are used during initialization of the L1 tables. */
+/* These variables are used during initialization of the L1 tables */
 static unsigned int gpt_next_l1_tbl_idx;
 static uintptr_t gpt_l1_tbl;
 
@@ -91,7 +91,7 @@
  * Return
  *   true for a valid GPI, false for an invalid one.
  */
-static bool gpt_is_gpi_valid(unsigned int gpi)
+static bool is_gpi_valid(unsigned int gpi)
 {
 	if ((gpi == GPT_GPI_NO_ACCESS) || (gpi == GPT_GPI_ANY) ||
 	    ((gpi >= GPT_GPI_SECURE) && (gpi <= GPT_GPI_REALM))) {
@@ -112,8 +112,8 @@
  * Return
  *   True if PAS regions overlap, false if they do not.
  */
-static bool gpt_check_pas_overlap(uintptr_t base_1, size_t size_1,
-				  uintptr_t base_2, size_t size_2)
+static bool check_pas_overlap(uintptr_t base_1, size_t size_1,
+			      uintptr_t base_2, size_t size_2)
 {
 	if (((base_1 + size_1) > base_2) && ((base_2 + size_2) > base_1)) {
 		return true;
@@ -133,13 +133,13 @@
  * Return
  *   True if a PAS region occupies the L0 region in question, false if not.
  */
-static bool gpt_does_previous_pas_exist_here(unsigned int l0_idx,
-					     pas_region_t *pas_regions,
-					     unsigned int pas_idx)
+static bool does_previous_pas_exist_here(unsigned int l0_idx,
+					 pas_region_t *pas_regions,
+					 unsigned int pas_idx)
 {
-	/* Iterate over PAS regions up to pas_idx. */
+	/* Iterate over PAS regions up to pas_idx */
 	for (unsigned int i = 0U; i < pas_idx; i++) {
-		if (gpt_check_pas_overlap((GPT_L0GPTSZ_ACTUAL_SIZE * l0_idx),
+		if (check_pas_overlap((GPT_L0GPTSZ_ACTUAL_SIZE * l0_idx),
 		    GPT_L0GPTSZ_ACTUAL_SIZE,
 		    pas_regions[i].base_pa, pas_regions[i].size)) {
 			return true;
@@ -164,8 +164,8 @@
  *   Negative Linux error code in the event of a failure, number of L1 regions
  *   required when successful.
  */
-static int gpt_validate_pas_mappings(pas_region_t *pas_regions,
-				     unsigned int pas_region_cnt)
+static int validate_pas_mappings(pas_region_t *pas_regions,
+				 unsigned int pas_region_cnt)
 {
 	unsigned int idx;
 	unsigned int l1_cnt = 0U;
@@ -176,18 +176,18 @@
 	assert(pas_region_cnt != 0U);
 
 	for (idx = 0U; idx < pas_region_cnt; idx++) {
-		/* Check for arithmetic overflow in region. */
+		/* Check for arithmetic overflow in region */
 		if ((ULONG_MAX - pas_regions[idx].base_pa) <
 		    pas_regions[idx].size) {
-			ERROR("[GPT] Address overflow in PAS[%u]!\n", idx);
+			ERROR("GPT: Address overflow in PAS[%u]!\n", idx);
 			return -EOVERFLOW;
 		}
 
-		/* Initial checks for PAS validity. */
+		/* Initial checks for PAS validity */
 		if (((pas_regions[idx].base_pa + pas_regions[idx].size) >
 		    GPT_PPS_ACTUAL_SIZE(gpt_config.t)) ||
-		    !gpt_is_gpi_valid(GPT_PAS_ATTR_GPI(pas_regions[idx].attrs))) {
-			ERROR("[GPT] PAS[%u] is invalid!\n", idx);
+		    !is_gpi_valid(GPT_PAS_ATTR_GPI(pas_regions[idx].attrs))) {
+			ERROR("GPT: PAS[%u] is invalid!\n", idx);
 			return -EFAULT;
 		}
 
@@ -196,12 +196,12 @@
 		 * start from idx + 1 instead of 0 since prior PAS mappings will
 		 * have already checked themselves against this one.
 		 */
-		for (unsigned int i = idx + 1; i < pas_region_cnt; i++) {
-			if (gpt_check_pas_overlap(pas_regions[idx].base_pa,
+		for (unsigned int i = idx + 1U; i < pas_region_cnt; i++) {
+			if (check_pas_overlap(pas_regions[idx].base_pa,
 			    pas_regions[idx].size,
 			    pas_regions[i].base_pa,
 			    pas_regions[i].size)) {
-				ERROR("[GPT] PAS[%u] overlaps with PAS[%u]\n",
+				ERROR("GPT: PAS[%u] overlaps with PAS[%u]\n",
 					i, idx);
 				return -EFAULT;
 			}
@@ -214,11 +214,12 @@
 		 * initialized.
 		 */
 		for (unsigned int i = GPT_L0_IDX(pas_regions[idx].base_pa);
-		     i <= GPT_L0_IDX(pas_regions[idx].base_pa + pas_regions[idx].size - 1);
+		     i <= GPT_L0_IDX(pas_regions[idx].base_pa +
+						pas_regions[idx].size - 1UL);
 		     i++) {
 			if ((GPT_L0_TYPE(l0_desc[i]) == GPT_L0_TYPE_BLK_DESC) &&
 			    (GPT_L0_BLKD_GPI(l0_desc[i]) == GPT_GPI_ANY)) {
-				/* This descriptor is unused so continue. */
+				/* This descriptor is unused so continue */
 				continue;
 			}
 
@@ -226,18 +227,18 @@
 			 * This descriptor has been initialized in a previous
 			 * call to this function so cannot be initialized again.
 			 */
-			ERROR("[GPT] PAS[%u] overlaps with previous L0[%d]!\n",
+			ERROR("GPT: PAS[%u] overlaps with previous L0[%d]!\n",
 			      idx, i);
 			return -EFAULT;
 		}
 
-		/* Check for block mapping (L0) type. */
+		/* Check for block mapping (L0) type */
 		if (GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs) ==
 		    GPT_PAS_ATTR_MAP_TYPE_BLOCK) {
-			/* Make sure base and size are block-aligned. */
+			/* Make sure base and size are block-aligned */
 			if (!GPT_IS_L0_ALIGNED(pas_regions[idx].base_pa) ||
 			    !GPT_IS_L0_ALIGNED(pas_regions[idx].size)) {
-				ERROR("[GPT] PAS[%u] is not block-aligned!\n",
+				ERROR("GPT: PAS[%u] is not block-aligned!\n",
 				      idx);
 				return -EFAULT;
 			}
@@ -245,21 +246,21 @@
 			continue;
 		}
 
-		/* Check for granule mapping (L1) type. */
+		/* Check for granule mapping (L1) type */
 		if (GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs) ==
 		    GPT_PAS_ATTR_MAP_TYPE_GRANULE) {
-			/* Make sure base and size are granule-aligned. */
+			/* Make sure base and size are granule-aligned */
 			if (!GPT_IS_L1_ALIGNED(gpt_config.p, pas_regions[idx].base_pa) ||
 			    !GPT_IS_L1_ALIGNED(gpt_config.p, pas_regions[idx].size)) {
-				ERROR("[GPT] PAS[%u] is not granule-aligned!\n",
+				ERROR("GPT: PAS[%u] is not granule-aligned!\n",
 				      idx);
 				return -EFAULT;
 			}
 
-			/* Find how many L1 tables this PAS occupies. */
+			/* Find how many L1 tables this PAS occupies */
 			pas_l1_cnt = (GPT_L0_IDX(pas_regions[idx].base_pa +
-				     pas_regions[idx].size - 1) -
-				     GPT_L0_IDX(pas_regions[idx].base_pa) + 1);
+				     pas_regions[idx].size - 1UL) -
+				     GPT_L0_IDX(pas_regions[idx].base_pa) + 1U);
 
 			/*
 			 * This creates a situation where, if multiple PAS
@@ -277,26 +278,26 @@
 			 * both for overlap against other PAS.
 			 */
 			if (pas_l1_cnt > 1) {
-				if (gpt_does_previous_pas_exist_here(
+				if (does_previous_pas_exist_here(
 				    GPT_L0_IDX(pas_regions[idx].base_pa +
-				    pas_regions[idx].size - 1),
+				    pas_regions[idx].size - 1UL),
 				    pas_regions, idx)) {
-					pas_l1_cnt = pas_l1_cnt - 1;
+					pas_l1_cnt--;
 				}
 			}
 
-			if (gpt_does_previous_pas_exist_here(
+			if (does_previous_pas_exist_here(
 			    GPT_L0_IDX(pas_regions[idx].base_pa),
 			    pas_regions, idx)) {
-				pas_l1_cnt = pas_l1_cnt - 1;
+				pas_l1_cnt--;
 			}
 
 			l1_cnt += pas_l1_cnt;
 			continue;
 		}
 
-		/* If execution reaches this point, mapping type is invalid. */
-		ERROR("[GPT] PAS[%u] has invalid mapping type 0x%x.\n", idx,
+		/* If execution reaches this point, mapping type is invalid */
+		ERROR("GPT: PAS[%u] has invalid mapping type 0x%x.\n", idx,
 		      GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs));
 		return -EINVAL;
 	}
@@ -314,8 +315,8 @@
  * Return
  *   Negative Linux error code in the event of a failure, 0 for success.
  */
-static int gpt_validate_l0_params(gpccr_pps_e pps, uintptr_t l0_mem_base,
-				  size_t l0_mem_size)
+static int validate_l0_params(gpccr_pps_e pps, uintptr_t l0_mem_base,
+				size_t l0_mem_size)
 {
 	size_t l0_alignment;
 
@@ -324,27 +325,29 @@
 	 * to work.
 	 */
 	if (pps > GPT_PPS_MAX) {
-		ERROR("[GPT] Invalid PPS: 0x%x\n", pps);
+		ERROR("GPT: Invalid PPS: 0x%x\n", pps);
 		return -EINVAL;
 	}
 	gpt_config.pps = pps;
 	gpt_config.t = gpt_t_lookup[pps];
 
-	/* Alignment must be the greater of 4k or l0 table size. */
+	/* Alignment must be the greater of 4KB or l0 table size */
 	l0_alignment = PAGE_SIZE_4KB;
 	if (l0_alignment < GPT_L0_TABLE_SIZE(gpt_config.t)) {
 		l0_alignment = GPT_L0_TABLE_SIZE(gpt_config.t);
 	}
 
-	/* Check base address. */
-	if ((l0_mem_base == 0U) || ((l0_mem_base & (l0_alignment - 1)) != 0U)) {
-		ERROR("[GPT] Invalid L0 base address: 0x%lx\n", l0_mem_base);
+	/* Check base address */
+	if ((l0_mem_base == 0UL) ||
+	   ((l0_mem_base & (l0_alignment - 1UL)) != 0UL)) {
+		ERROR("GPT: Invalid L0 base address: 0x%lx\n", l0_mem_base);
 		return -EFAULT;
 	}
 
-	/* Check size. */
+	/* Check size */
 	if (l0_mem_size < GPT_L0_TABLE_SIZE(gpt_config.t)) {
-		ERROR("[GPT] Inadequate L0 memory: need 0x%lx, have 0x%lx)\n",
+		ERROR("%sL0%s\n", "GPT: Inadequate ", " memory\n");
+		ERROR("      Expected 0x%lx bytes, got 0x%lx bytes\n",
 		      GPT_L0_TABLE_SIZE(gpt_config.t),
 		      l0_mem_size);
 		return -ENOMEM;
@@ -365,8 +368,8 @@
  * Return
  *   Negative Linux error code in the event of a failure, 0 for success.
  */
-static int gpt_validate_l1_params(uintptr_t l1_mem_base, size_t l1_mem_size,
-				  unsigned int l1_gpt_cnt)
+static int validate_l1_params(uintptr_t l1_mem_base, size_t l1_mem_size,
+				unsigned int l1_gpt_cnt)
 {
 	size_t l1_gpt_mem_sz;
 
@@ -376,31 +379,31 @@
 		return -EPERM;
 	}
 
-	/* Make sure L1 tables are aligned to their size. */
-	if ((l1_mem_base & (GPT_L1_TABLE_SIZE(gpt_config.p) - 1)) != 0U) {
-		ERROR("[GPT] Unaligned L1 GPT base address: 0x%lx\n",
+	/* Make sure L1 tables are aligned to their size */
+	if ((l1_mem_base & (GPT_L1_TABLE_SIZE(gpt_config.p) - 1UL)) != 0UL) {
+		ERROR("GPT: Unaligned L1 GPT base address: 0x%"PRIxPTR"\n",
 		      l1_mem_base);
 		return -EFAULT;
 	}
 
-	/* Get total memory needed for L1 tables. */
+	/* Get total memory needed for L1 tables */
 	l1_gpt_mem_sz = l1_gpt_cnt * GPT_L1_TABLE_SIZE(gpt_config.p);
 
-	/* Check for overflow. */
+	/* Check for overflow */
 	if ((l1_gpt_mem_sz / GPT_L1_TABLE_SIZE(gpt_config.p)) != l1_gpt_cnt) {
-		ERROR("[GPT] Overflow calculating L1 memory size.\n");
+		ERROR("GPT: Overflow calculating L1 memory size\n");
 		return -ENOMEM;
 	}
 
-	/* Make sure enough space was supplied. */
+	/* Make sure enough space was supplied */
 	if (l1_mem_size < l1_gpt_mem_sz) {
-		ERROR("[GPT] Inadequate memory for L1 GPTs. ");
-		ERROR("      Expected 0x%lx bytes. Got 0x%lx bytes\n",
+		ERROR("%sL1 GPTs%s", "GPT: Inadequate ", " memory\n");
+		ERROR("      Expected 0x%lx bytes, got 0x%lx bytes\n",
 		      l1_gpt_mem_sz, l1_mem_size);
 		return -ENOMEM;
 	}
 
-	VERBOSE("[GPT] Requested 0x%lx bytes for L1 GPTs.\n", l1_gpt_mem_sz);
+	VERBOSE("GPT: Requested 0x%lx bytes for L1 GPTs\n", l1_gpt_mem_sz);
 	return 0;
 }
 
@@ -412,7 +415,7 @@
  *   *pas		Pointer to the structure defining the PAS region to
  *			initialize.
  */
-static void gpt_generate_l0_blk_desc(pas_region_t *pas)
+static void generate_l0_blk_desc(pas_region_t *pas)
 {
 	uint64_t gpt_desc;
 	unsigned int end_idx;
@@ -424,7 +427,7 @@
 
 	/*
 	 * Checking of PAS parameters has already been done in
-	 * gpt_validate_pas_mappings so no need to check the same things again.
+	 * validate_pas_mappings so no need to check the same things again.
 	 */
 
 	l0_gpt_arr = (uint64_t *)gpt_config.plat_gpt_l0_base;
@@ -442,10 +445,10 @@
 	 */
 	end_idx = GPT_L0_IDX(pas->base_pa + pas->size);
 
-	/* Generate the needed block descriptors. */
+	/* Generate the needed block descriptors */
 	for (; idx < end_idx; idx++) {
 		l0_gpt_arr[idx] = gpt_desc;
-		VERBOSE("[GPT] L0 entry (BLOCK) index %u [%p]: GPI = 0x%" PRIx64 " (0x%" PRIx64 ")\n",
+		VERBOSE("GPT: L0 entry (BLOCK) index %u [%p]: GPI = 0x%"PRIx64" (0x%"PRIx64")\n",
 			idx, &l0_gpt_arr[idx],
 			(gpt_desc >> GPT_L0_BLK_DESC_GPI_SHIFT) &
 			GPT_L0_BLK_DESC_GPI_MASK, l0_gpt_arr[idx]);
@@ -465,7 +468,7 @@
  * Return
  *   The PA of the end of the current range.
  */
-static uintptr_t gpt_get_l1_end_pa(uintptr_t cur_pa, uintptr_t end_pa)
+static uintptr_t get_l1_end_pa(uintptr_t cur_pa, uintptr_t end_pa)
 {
 	uintptr_t cur_idx;
 	uintptr_t end_idx;
@@ -492,11 +495,11 @@
  *   first		Address of first granule in range.
  *   last		Address of last granule in range (inclusive).
  */
-static void gpt_fill_l1_tbl(uint64_t gpi, uint64_t *l1, uintptr_t first,
+static void fill_l1_tbl(uint64_t gpi, uint64_t *l1, uintptr_t first,
 			    uintptr_t last)
 {
 	uint64_t gpi_field = GPT_BUILD_L1_DESC(gpi);
-	uint64_t gpi_mask = 0xFFFFFFFFFFFFFFFF;
+	uint64_t gpi_mask = ULONG_MAX;
 
 	assert(first <= last);
 	assert((first & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) == 0U);
@@ -504,25 +507,25 @@
 	assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
 	assert(l1 != NULL);
 
-	/* Shift the mask if we're starting in the middle of an L1 entry. */
+	/* Shift the mask if we're starting in the middle of an L1 entry */
 	gpi_mask = gpi_mask << (GPT_L1_GPI_IDX(gpt_config.p, first) << 2);
 
-	/* Fill out each L1 entry for this region. */
+	/* Fill out each L1 entry for this region */
 	for (unsigned int i = GPT_L1_IDX(gpt_config.p, first);
 	     i <= GPT_L1_IDX(gpt_config.p, last); i++) {
-		/* Account for stopping in the middle of an L1 entry. */
+		/* Account for stopping in the middle of an L1 entry */
 		if (i == GPT_L1_IDX(gpt_config.p, last)) {
-			gpi_mask &= (gpi_mask >> ((15 -
+			gpi_mask &= (gpi_mask >> ((15U -
 				    GPT_L1_GPI_IDX(gpt_config.p, last)) << 2));
 		}
 
-		/* Write GPI values. */
+		/* Write GPI values */
 		assert((l1[i] & gpi_mask) ==
 		       (GPT_BUILD_L1_DESC(GPT_GPI_ANY) & gpi_mask));
 		l1[i] = (l1[i] & ~gpi_mask) | (gpi_mask & gpi_field);
 
-		/* Reset mask. */
-		gpi_mask = 0xFFFFFFFFFFFFFFFF;
+		/* Reset mask */
+		gpi_mask = ULONG_MAX;
 	}
 }
 
@@ -537,14 +540,14 @@
  * Return
  *   Pointer to the next available L1 table.
  */
-static uint64_t *gpt_get_new_l1_tbl(void)
+static uint64_t *get_new_l1_tbl(void)
 {
-	/* Retrieve the next L1 table. */
+	/* Retrieve the next L1 table */
 	uint64_t *l1 = (uint64_t *)((uint64_t)(gpt_l1_tbl) +
 		       (GPT_L1_TABLE_SIZE(gpt_config.p) *
 		       gpt_next_l1_tbl_idx));
 
-	/* Increment L1 counter. */
+	/* Increment L1 counter */
 	gpt_next_l1_tbl_idx++;
 
 	/* Initialize all GPIs to GPT_GPI_ANY */
@@ -563,7 +566,7 @@
  * Parameters
  *   *pas		Pointer to the structure defining the PAS region.
  */
-static void gpt_generate_l0_tbl_desc(pas_region_t *pas)
+static void generate_l0_tbl_desc(pas_region_t *pas)
 {
 	uintptr_t end_pa;
 	uintptr_t cur_pa;
@@ -577,7 +580,7 @@
 
 	/*
 	 * Checking of PAS parameters has already been done in
-	 * gpt_validate_pas_mappings so no need to check the same things again.
+	 * validate_pas_mappings so no need to check the same things again.
 	 */
 
 	end_pa = pas->base_pa + pas->size;
@@ -586,7 +589,7 @@
 	/* We start working from the granule at base PA */
 	cur_pa = pas->base_pa;
 
-	/* Iterate over each L0 region in this memory range. */
+	/* Iterate over each L0 region in this memory range */
 	for (l0_idx = GPT_L0_IDX(pas->base_pa);
 	     l0_idx <= GPT_L0_IDX(end_pa - 1U);
 	     l0_idx++) {
@@ -596,25 +599,23 @@
 		 * need to create one.
 		 */
 		if (GPT_L0_TYPE(l0_gpt_base[l0_idx]) == GPT_L0_TYPE_TBL_DESC) {
-			/* Get the L1 array from the L0 entry. */
+			/* Get the L1 array from the L0 entry */
 			l1_gpt_arr = GPT_L0_TBLD_ADDR(l0_gpt_base[l0_idx]);
 		} else {
-			/* Get a new L1 table from the L1 memory space. */
-			l1_gpt_arr = gpt_get_new_l1_tbl();
+			/* Get a new L1 table from the L1 memory space */
+			l1_gpt_arr = get_new_l1_tbl();
 
-			/* Fill out the L0 descriptor and flush it. */
+			/* Fill out the L0 descriptor and flush it */
 			l0_gpt_base[l0_idx] = GPT_L0_TBL_DESC(l1_gpt_arr);
 		}
 
-		VERBOSE("[GPT] L0 entry (TABLE) index %u [%p] ==> L1 Addr 0x%llx (0x%" PRIx64 ")\n",
-			l0_idx, &l0_gpt_base[l0_idx],
-			(unsigned long long)(l1_gpt_arr),
-			l0_gpt_base[l0_idx]);
+		VERBOSE("GPT: L0 entry (TABLE) index %u [%p] ==> L1 Addr %p (0x%"PRIx64")\n",
+			l0_idx, &l0_gpt_base[l0_idx], l1_gpt_arr, l0_gpt_base[l0_idx]);
 
 		/*
 		 * Determine the PA of the last granule in this L0 descriptor.
 		 */
-		last_gran_pa = gpt_get_l1_end_pa(cur_pa, end_pa) -
+		last_gran_pa = get_l1_end_pa(cur_pa, end_pa) -
 			       GPT_PGS_ACTUAL_SIZE(gpt_config.p);
 
 		/*
@@ -622,11 +623,11 @@
 		 * function needs the addresses of the first granule and last
 		 * granule in the range.
 		 */
-		gpt_fill_l1_tbl(GPT_PAS_ATTR_GPI(pas->attrs), l1_gpt_arr,
+		fill_l1_tbl(GPT_PAS_ATTR_GPI(pas->attrs), l1_gpt_arr,
 				cur_pa, last_gran_pa);
 
-		/* Advance cur_pa to first granule in next L0 region. */
-		cur_pa = gpt_get_l1_end_pa(cur_pa, end_pa);
+		/* Advance cur_pa to first granule in next L0 region */
+		cur_pa = get_l1_end_pa(cur_pa, end_pa);
 	}
 }
 
@@ -649,19 +650,19 @@
 	uint64_t *l0 = (uint64_t *)gpt_config.plat_gpt_l0_base;
 
 	assert(pas != NULL);
-	assert(pas_count > 0);
+	assert(pas_count != 0U);
 
-	/* Initial start and end values. */
+	/* Initial start and end values */
 	start_idx = GPT_L0_IDX(pas[0].base_pa);
-	end_idx = GPT_L0_IDX(pas[0].base_pa + pas[0].size - 1);
+	end_idx = GPT_L0_IDX(pas[0].base_pa + pas[0].size - 1UL);
 
-	/* Find lowest and highest L0 indices used in this PAS array. */
-	for (idx = 1; idx < pas_count; idx++) {
+	/* Find lowest and highest L0 indices used in this PAS array */
+	for (idx = 1U; idx < pas_count; idx++) {
 		if (GPT_L0_IDX(pas[idx].base_pa) < start_idx) {
 			start_idx = GPT_L0_IDX(pas[idx].base_pa);
 		}
-		if (GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1) > end_idx) {
-			end_idx = GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1);
+		if (GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1UL) > end_idx) {
+			end_idx = GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1UL);
 		}
 	}
 
@@ -670,7 +671,7 @@
 	 * the end index value.
 	 */
 	flush_dcache_range((uintptr_t)&l0[start_idx],
-			   ((end_idx + 1) - start_idx) * sizeof(uint64_t));
+			   ((end_idx + 1U) - start_idx) * sizeof(uint64_t));
 }
 
 /*
@@ -689,8 +690,8 @@
 	 * Granule tables must be initialised before enabling
 	 * granule protection.
 	 */
-	if (gpt_config.plat_gpt_l0_base == 0U) {
-		ERROR("[GPT] Tables have not been initialized!\n");
+	if (gpt_config.plat_gpt_l0_base == 0UL) {
+		ERROR("GPT: Tables have not been initialized!\n");
 		return -EPERM;
 	}
 
@@ -711,7 +712,7 @@
 	 */
 	gpccr_el3 |= SET_GPCCR_SH(GPCCR_SH_IS);
 
-	/* Outer and Inner cacheability set to Normal memory, WB, RA, WA. */
+	/* Outer and Inner cacheability set to Normal memory, WB, RA, WA */
 	gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA);
 	gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA);
 
@@ -727,7 +728,7 @@
 	/* Enable GPT */
 	gpccr_el3 |= GPCCR_GPC_BIT;
 
-	/* TODO: Configure GPCCR_EL3_GPCP for Fault control. */
+	/* TODO: Configure GPCCR_EL3_GPCP for Fault control */
 	write_gpccr_el3(gpccr_el3);
 	isb();
 	tlbipaallos();
@@ -769,16 +770,16 @@
 	int ret;
 	uint64_t gpt_desc;
 
-	/* Ensure that MMU and Data caches are enabled. */
+	/* Ensure that MMU and Data caches are enabled */
 	assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
 
-	/* Validate other parameters. */
-	ret = gpt_validate_l0_params(pps, l0_mem_base, l0_mem_size);
+	/* Validate other parameters */
+	ret = validate_l0_params(pps, l0_mem_base, l0_mem_size);
 	if (ret != 0) {
 		return ret;
 	}
 
-	/* Create the descriptor to initialize L0 entries with. */
+	/* Create the descriptor to initialize L0 entries with */
 	gpt_desc = GPT_L0_BLK_DESC(GPT_GPI_ANY);
 
 	/* Iterate through all L0 entries */
@@ -786,11 +787,11 @@
 		((uint64_t *)l0_mem_base)[i] = gpt_desc;
 	}
 
-	/* Flush updated L0 tables to memory. */
+	/* Flush updated L0 tables to memory */
 	flush_dcache_range((uintptr_t)l0_mem_base,
 			   (size_t)GPT_L0_TABLE_SIZE(gpt_config.t));
 
-	/* Stash the L0 base address once initial setup is complete. */
+	/* Stash the L0 base address once initial setup is complete */
 	gpt_config.plat_gpt_l0_base = l0_mem_base;
 
 	return 0;
@@ -824,79 +825,79 @@
 	int ret;
 	int l1_gpt_cnt;
 
-	/* Ensure that MMU and Data caches are enabled. */
+	/* Ensure that MMU and Data caches are enabled */
 	assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
 
-	/* PGS is needed for gpt_validate_pas_mappings so check it now. */
+	/* PGS is needed for validate_pas_mappings so check it now */
 	if (pgs > GPT_PGS_MAX) {
-		ERROR("[GPT] Invalid PGS: 0x%x\n", pgs);
+		ERROR("GPT: Invalid PGS: 0x%x\n", pgs);
 		return -EINVAL;
 	}
 	gpt_config.pgs = pgs;
 	gpt_config.p = gpt_p_lookup[pgs];
 
-	/* Make sure L0 tables have been initialized. */
+	/* Make sure L0 tables have been initialized */
 	if (gpt_config.plat_gpt_l0_base == 0U) {
-		ERROR("[GPT] L0 tables must be initialized first!\n");
+		ERROR("GPT: L0 tables must be initialized first!\n");
 		return -EPERM;
 	}
 
-	/* Check if L1 GPTs are required and how many. */
-	l1_gpt_cnt = gpt_validate_pas_mappings(pas_regions, pas_count);
+	/* Check if L1 GPTs are required and how many */
+	l1_gpt_cnt = validate_pas_mappings(pas_regions, pas_count);
 	if (l1_gpt_cnt < 0) {
 		return l1_gpt_cnt;
 	}
 
-	VERBOSE("[GPT] %u L1 GPTs requested.\n", l1_gpt_cnt);
+	VERBOSE("GPT: %i L1 GPTs requested\n", l1_gpt_cnt);
 
-	/* If L1 tables are needed then validate the L1 parameters. */
+	/* If L1 tables are needed then validate the L1 parameters */
 	if (l1_gpt_cnt > 0) {
-		ret = gpt_validate_l1_params(l1_mem_base, l1_mem_size,
-		      l1_gpt_cnt);
+		ret = validate_l1_params(l1_mem_base, l1_mem_size,
+					(unsigned int)l1_gpt_cnt);
 		if (ret != 0) {
 			return ret;
 		}
 
-		/* Set up parameters for L1 table generation. */
+		/* Set up parameters for L1 table generation */
 		gpt_l1_tbl = l1_mem_base;
 		gpt_next_l1_tbl_idx = 0U;
 	}
 
-	INFO("[GPT] Boot Configuration\n");
+	INFO("GPT: Boot Configuration\n");
 	INFO("  PPS/T:     0x%x/%u\n", gpt_config.pps, gpt_config.t);
 	INFO("  PGS/P:     0x%x/%u\n", gpt_config.pgs, gpt_config.p);
 	INFO("  L0GPTSZ/S: 0x%x/%u\n", GPT_L0GPTSZ, GPT_S_VAL);
-	INFO("  PAS count: 0x%x\n", pas_count);
-	INFO("  L0 base:   0x%lx\n", gpt_config.plat_gpt_l0_base);
+	INFO("  PAS count: %u\n", pas_count);
+	INFO("  L0 base:   0x%"PRIxPTR"\n", gpt_config.plat_gpt_l0_base);
 
-	/* Generate the tables in memory. */
+	/* Generate the tables in memory */
 	for (unsigned int idx = 0U; idx < pas_count; idx++) {
-		INFO("[GPT] PAS[%u]: base 0x%lx, size 0x%lx, GPI 0x%x, type 0x%x\n",
-		     idx, pas_regions[idx].base_pa, pas_regions[idx].size,
-		     GPT_PAS_ATTR_GPI(pas_regions[idx].attrs),
-		     GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs));
+		VERBOSE("GPT: PAS[%u]: base 0x%"PRIxPTR"\tsize 0x%lx\tGPI 0x%x\ttype 0x%x\n",
+			idx, pas_regions[idx].base_pa, pas_regions[idx].size,
+			GPT_PAS_ATTR_GPI(pas_regions[idx].attrs),
+			GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs));
 
 		/* Check if a block or table descriptor is required */
 		if (GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs) ==
 		    GPT_PAS_ATTR_MAP_TYPE_BLOCK) {
-			gpt_generate_l0_blk_desc(&pas_regions[idx]);
+			generate_l0_blk_desc(&pas_regions[idx]);
 
 		} else {
-			gpt_generate_l0_tbl_desc(&pas_regions[idx]);
+			generate_l0_tbl_desc(&pas_regions[idx]);
 		}
 	}
 
-	/* Flush modified L0 tables. */
+	/* Flush modified L0 tables */
 	flush_l0_for_pas_array(pas_regions, pas_count);
 
-	/* Flush L1 tables if needed. */
+	/* Flush L1 tables if needed */
 	if (l1_gpt_cnt > 0) {
 		flush_dcache_range(l1_mem_base,
 				   GPT_L1_TABLE_SIZE(gpt_config.p) *
 				   l1_gpt_cnt);
 	}
 
-	/* Make sure that all the entries are written to the memory. */
+	/* Make sure that all the entries are written to the memory */
 	dsbishst();
 	tlbipaallos();
 	dsb();
@@ -920,12 +921,12 @@
 {
 	u_register_t reg;
 
-	/* Ensure that MMU and Data caches are enabled. */
+	/* Ensure that MMU and Data caches are enabled */
 	assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
 
-	/* Ensure GPC are already enabled. */
+	/* Ensure GPC are already enabled */
 	if ((read_gpccr_el3() & GPCCR_GPC_BIT) == 0U) {
-		ERROR("[GPT] Granule protection checks are not enabled!\n");
+		ERROR("GPT: Granule protection checks are not enabled!\n");
 		return -EPERM;
 	}
 
@@ -938,18 +939,18 @@
 				      GPTBR_BADDR_MASK) <<
 				      GPTBR_BADDR_VAL_SHIFT;
 
-	/* Read GPCCR to get PGS and PPS values. */
+	/* Read GPCCR to get PGS and PPS values */
 	reg = read_gpccr_el3();
 	gpt_config.pps = (reg >> GPCCR_PPS_SHIFT) & GPCCR_PPS_MASK;
 	gpt_config.t = gpt_t_lookup[gpt_config.pps];
 	gpt_config.pgs = (reg >> GPCCR_PGS_SHIFT) & GPCCR_PGS_MASK;
 	gpt_config.p = gpt_p_lookup[gpt_config.pgs];
 
-	VERBOSE("[GPT] Runtime Configuration\n");
+	VERBOSE("GPT: Runtime Configuration\n");
 	VERBOSE("  PPS/T:     0x%x/%u\n", gpt_config.pps, gpt_config.t);
 	VERBOSE("  PGS/P:     0x%x/%u\n", gpt_config.pgs, gpt_config.p);
 	VERBOSE("  L0GPTSZ/S: 0x%x/%u\n", GPT_L0GPTSZ, GPT_S_VAL);
-	VERBOSE("  L0 base:   0x%lx\n", gpt_config.plat_gpt_l0_base);
+	VERBOSE("  L0 base:   0x%"PRIxPTR"\n", gpt_config.plat_gpt_l0_base);
 
 	return 0;
 }
@@ -963,7 +964,7 @@
 
 /*
  * A helper to write the value (target_pas << gpi_shift) to the index of
- * the gpt_l1_addr
+ * the gpt_l1_addr.
  */
 static inline void write_gpt(uint64_t *gpt_l1_desc, uint64_t *gpt_l1_addr,
 			     unsigned int gpi_shift, unsigned int idx,
@@ -976,7 +977,7 @@
 
 /*
  * Helper to retrieve the gpt_l1_* information from the base address
- * returned in gpi_info
+ * returned in gpi_info.
  */
 static int get_gpi_params(uint64_t base, gpi_info_t *gpi_info)
 {
@@ -985,12 +986,12 @@
 	gpt_l0_base = (uint64_t *)gpt_config.plat_gpt_l0_base;
 	gpt_l0_desc = gpt_l0_base[GPT_L0_IDX(base)];
 	if (GPT_L0_TYPE(gpt_l0_desc) != GPT_L0_TYPE_TBL_DESC) {
-		VERBOSE("[GPT] Granule is not covered by a table descriptor!\n");
-		VERBOSE("      Base=0x%" PRIx64 "\n", base);
+		VERBOSE("GPT: Granule is not covered by a table descriptor!\n");
+		VERBOSE("      Base=0x%"PRIx64"\n", base);
 		return -EINVAL;
 	}
 
-	/* Get the table index and GPI shift from PA. */
+	/* Get the table index and GPI shift from PA */
 	gpi_info->gpt_l1_addr = GPT_L0_TBLD_ADDR(gpt_l0_desc);
 	gpi_info->idx = GPT_L1_IDX(gpt_config.p, base);
 	gpi_info->gpi_shift = GPT_L1_GPI_IDX(gpt_config.p, base) << 2;
@@ -1025,36 +1026,36 @@
 	int res;
 	unsigned int target_pas;
 
-	/* Ensure that the tables have been set up before taking requests. */
+	/* Ensure that the tables have been set up before taking requests */
 	assert(gpt_config.plat_gpt_l0_base != 0UL);
 
-	/* Ensure that caches are enabled. */
+	/* Ensure that caches are enabled */
 	assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
 
 	/* Delegate request can only come from REALM or SECURE */
 	assert(src_sec_state == SMC_FROM_REALM ||
 	       src_sec_state == SMC_FROM_SECURE);
 
-	/* See if this is a single or a range of granule transition. */
+	/* See if this is a single or a range of granule transition */
 	if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
 		return -EINVAL;
 	}
 
 	/* Check that base and size are valid */
 	if ((ULONG_MAX - base) < size) {
-		VERBOSE("[GPT] Transition request address overflow!\n");
-		VERBOSE("      Base=0x%" PRIx64 "\n", base);
+		VERBOSE("GPT: Transition request address overflow!\n");
+		VERBOSE("      Base=0x%"PRIx64"\n", base);
 		VERBOSE("      Size=0x%lx\n", size);
 		return -EINVAL;
 	}
 
-	/* Make sure base and size are valid. */
-	if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
-	    ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
+	/* Make sure base and size are valid */
+	if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
+	    ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
 	    (size == 0UL) ||
 	    ((base + size) >= GPT_PPS_ACTUAL_SIZE(gpt_config.t))) {
-		VERBOSE("[GPT] Invalid granule transition address range!\n");
-		VERBOSE("      Base=0x%" PRIx64 "\n", base);
+		VERBOSE("GPT: Invalid granule transition address range!\n");
+		VERBOSE("      Base=0x%"PRIx64"\n", base);
 		VERBOSE("      Size=0x%lx\n", size);
 		return -EINVAL;
 	}
@@ -1078,7 +1079,7 @@
 
 	/* Check that the current address is in NS state */
 	if (gpi_info.gpi != GPT_GPI_NS) {
-		VERBOSE("[GPT] Only Granule in NS state can be delegated.\n");
+		VERBOSE("GPT: Only Granule in NS state can be delegated.\n");
 		VERBOSE("      Caller: %u, Current GPI: %u\n", src_sec_state,
 			gpi_info.gpi);
 		spin_unlock(&gpt_lock);
@@ -1094,7 +1095,7 @@
 	/*
 	 * In order to maintain mutual distrust between Realm and Secure
 	 * states, remove any data speculatively fetched into the target
-	 * physical address space. Issue DC CIPAPA over address range
+	 * physical address space. Issue DC CIPAPA over address range.
 	 */
 	if (is_feat_mte2_supported()) {
 		flush_dcache_to_popa_range_mte2(nse | base,
@@ -1121,14 +1122,14 @@
 					   GPT_PGS_ACTUAL_SIZE(gpt_config.p));
 	}
 
-	/* Unlock access to the L1 tables. */
+	/* Unlock access to the L1 tables */
 	spin_unlock(&gpt_lock);
 
 	/*
 	 * The isb() will be done as part of context
-	 * synchronization when returning to lower EL
+	 * synchronization when returning to lower EL.
 	 */
-	VERBOSE("[GPT] Granule 0x%" PRIx64 ", GPI 0x%x->0x%x\n",
+	VERBOSE("GPT: Granule 0x%"PRIx64" GPI 0x%x->0x%x\n",
 		base, gpi_info.gpi, target_pas);
 
 	return 0;
@@ -1157,36 +1158,36 @@
 	uint64_t nse;
 	int res;
 
-	/* Ensure that the tables have been set up before taking requests. */
+	/* Ensure that the tables have been set up before taking requests */
 	assert(gpt_config.plat_gpt_l0_base != 0UL);
 
-	/* Ensure that MMU and caches are enabled. */
+	/* Ensure that MMU and caches are enabled */
 	assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
 
 	/* Delegate request can only come from REALM or SECURE */
 	assert(src_sec_state == SMC_FROM_REALM ||
 	       src_sec_state == SMC_FROM_SECURE);
 
-	/* See if this is a single or a range of granule transition. */
+	/* See if this is a single or a range of granule transition */
 	if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
 		return -EINVAL;
 	}
 
 	/* Check that base and size are valid */
 	if ((ULONG_MAX - base) < size) {
-		VERBOSE("[GPT] Transition request address overflow!\n");
-		VERBOSE("      Base=0x%" PRIx64 "\n", base);
+		VERBOSE("GPT: Transition request address overflow!\n");
+		VERBOSE("      Base=0x%"PRIx64"\n", base);
 		VERBOSE("      Size=0x%lx\n", size);
 		return -EINVAL;
 	}
 
-	/* Make sure base and size are valid. */
-	if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
-	    ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
+	/* Make sure base and size are valid */
+	if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
+	    ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
 	    (size == 0UL) ||
 	    ((base + size) >= GPT_PPS_ACTUAL_SIZE(gpt_config.t))) {
-		VERBOSE("[GPT] Invalid granule transition address range!\n");
-		VERBOSE("      Base=0x%" PRIx64 "\n", base);
+		VERBOSE("GPT: Invalid granule transition address range!\n");
+		VERBOSE("      Base=0x%"PRIx64"\n", base);
 		VERBOSE("      Size=0x%lx\n", size);
 		return -EINVAL;
 	}
@@ -1209,8 +1210,8 @@
 	     gpi_info.gpi != GPT_GPI_REALM) ||
 	    (src_sec_state == SMC_FROM_SECURE &&
 	     gpi_info.gpi != GPT_GPI_SECURE)) {
-		VERBOSE("[GPT] Only Granule in REALM or SECURE state can be undelegated.\n");
-		VERBOSE("      Caller: %u, Current GPI: %u\n", src_sec_state,
+		VERBOSE("GPT: Only Granule in REALM or SECURE state can be undelegated.\n");
+		VERBOSE("      Caller: %u Current GPI: %u\n", src_sec_state,
 			gpi_info.gpi);
 		spin_unlock(&gpt_lock);
 		return -EPERM;
@@ -1272,9 +1273,9 @@
 
 	/*
 	 * The isb() will be done as part of context
-	 * synchronization when returning to lower EL
+	 * synchronization when returning to lower EL.
 	 */
-	VERBOSE("[GPT] Granule 0x%" PRIx64 ", GPI 0x%x->0x%x\n",
+	VERBOSE("GPT: Granule 0x%"PRIx64" GPI 0x%x->0x%x\n",
 		base, gpi_info.gpi, GPT_GPI_NS);
 
 	return 0;

diff --git a/lib/gpt_rme/gpt_rme_private.h b/lib/gpt_rme/gpt_rme_private.h
index 3c817f3..b2a5dae 100644
--- a/lib/gpt_rme/gpt_rme_private.h
+++ b/lib/gpt_rme/gpt_rme_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,13 +15,13 @@
 /* GPT descriptor definitions                                                 */
 /******************************************************************************/
 
-/* GPT level 0 descriptor bit definitions. */
+/* GPT level 0 descriptor bit definitions */
 #define GPT_L0_TYPE_MASK		UL(0xF)
 #define GPT_L0_TYPE_SHIFT		U(0)
 
-/* For now, we don't support contiguous descriptors, only table and block. */
-#define GPT_L0_TYPE_TBL_DESC		UL(0x3)
-#define GPT_L0_TYPE_BLK_DESC		UL(0x1)
+/* For now, we don't support contiguous descriptors, only table and block */
+#define GPT_L0_TYPE_TBL_DESC		UL(3)
+#define GPT_L0_TYPE_BLK_DESC		UL(1)
 
 #define GPT_L0_TBL_DESC_L1ADDR_MASK	UL(0xFFFFFFFFFF)
 #define GPT_L0_TBL_DESC_L1ADDR_SHIFT	U(12)
@@ -57,7 +57,7 @@
 /* GPT platform configuration                                                 */
 /******************************************************************************/
 
-/* This value comes from GPCCR_EL3 so no externally supplied definition. */
+/* This value comes from GPCCR_EL3 so no externally supplied definition */
 #define GPT_L0GPTSZ		((unsigned int)((read_gpccr_el3() >> \
 				GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK))
 
@@ -117,10 +117,10 @@
 	unsigned int gpi;
 } gpi_info_t;
 
-/* Max valid value for PGS. */
+/* Max valid value for PGS */
 #define GPT_PGS_MAX			(2U)
 
-/* Max valid value for PPS. */
+/* Max valid value for PPS */
 #define GPT_PPS_MAX			(6U)
 
 /******************************************************************************/
@@ -139,7 +139,7 @@
 #define GPT_L0_IDX_WIDTH(_t)		(((_t) > GPT_S_VAL) ? \
 					((_t) - GPT_S_VAL) : (0U))
 
-/* Bit shift for the L0 index field in a PA. */
+/* Bit shift for the L0 index field in a PA */
 #define GPT_L0_IDX_SHIFT		(GPT_S_VAL)
 
 /*
@@ -153,13 +153,13 @@
 #define GPT_L0_IDX_MASK(_t)		(0x3FFFFFUL >> (22U - \
 					(GPT_L0_IDX_WIDTH(_t))))
 
-/* Total number of L0 regions. */
+/* Total number of L0 regions */
 #define GPT_L0_REGION_COUNT(_t)		((GPT_L0_IDX_MASK(_t)) + 1U)
 
-/* Total size of each GPT L0 region in bytes. */
+/* Total size of each GPT L0 region in bytes */
 #define GPT_L0_REGION_SIZE		(1UL << (GPT_L0_IDX_SHIFT))
 
-/* Total size in bytes of the whole L0 table. */
+/* Total size in bytes of the whole L0 table */
 #define GPT_L0_TABLE_SIZE(_t)		((GPT_L0_REGION_COUNT(_t)) << 3U)
 
 /******************************************************************************/
@@ -175,7 +175,7 @@
  */
 #define GPT_L1_IDX_WIDTH(_p)		((GPT_S_VAL - 1U) - ((_p) + 3U))
 
-/* Bit shift for the L1 index field. */
+/* Bit shift for the L1 index field */
 #define GPT_L1_IDX_SHIFT(_p)		((_p) + 4U)
 
 /*
@@ -183,38 +183,38 @@
  *
  * The value 0x7FFFFF is 23 bits wide and is the maximum possible width of the
  * L1 index within a physical address. It is calculated by
- * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512gb, the largest
+ * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512GB, the largest
  * L0GPTSZ, and p_min is 12 for 4KB granules, the smallest PGS.
  */
 #define GPT_L1_IDX_MASK(_p)		(0x7FFFFFUL >> (23U - \
 					(GPT_L1_IDX_WIDTH(_p))))
 
-/* Bit shift for the index of the L1 GPI in a PA. */
+/* Bit shift for the index of the L1 GPI in a PA */
 #define GPT_L1_GPI_IDX_SHIFT(_p)	(_p)
 
-/* Mask for the index of the L1 GPI in a PA. */
+/* Mask for the index of the L1 GPI in a PA */
 #define GPT_L1_GPI_IDX_MASK		(0xF)
 
-/* Total number of entries in each L1 table. */
+/* Total number of entries in each L1 table */
 #define GPT_L1_ENTRY_COUNT(_p)		((GPT_L1_IDX_MASK(_p)) + 1U)
 
-/* Total size in bytes of each L1 table. */
+/* Total size in bytes of each L1 table */
 #define GPT_L1_TABLE_SIZE(_p)		((GPT_L1_ENTRY_COUNT(_p)) << 3U)
 
 /******************************************************************************/
 /* General helper macros                                                      */
 /******************************************************************************/
 
-/* Protected space actual size in bytes. */
+/* Protected space actual size in bytes */
 #define GPT_PPS_ACTUAL_SIZE(_t)	(1UL << (_t))
 
-/* Granule actual size in bytes. */
+/* Granule actual size in bytes */
 #define GPT_PGS_ACTUAL_SIZE(_p)	(1UL << (_p))
 
-/* L0 GPT region size in bytes. */
+/* L0 GPT region size in bytes */
 #define GPT_L0GPTSZ_ACTUAL_SIZE	(1UL << GPT_S_VAL)
 
-/* Get the index of the L0 entry from a physical address. */
+/* Get the index of the L0 entry from a physical address */
 #define GPT_L0_IDX(_pa)		((_pa) >> GPT_L0_IDX_SHIFT)
 
 /*
@@ -223,38 +223,38 @@
  */
 #define GPT_IS_L0_ALIGNED(_pa)	(((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
 
-/* Get the type field from an L0 descriptor. */
+/* Get the type field from an L0 descriptor */
 #define GPT_L0_TYPE(_desc)	(((_desc) >> GPT_L0_TYPE_SHIFT) & \
 				GPT_L0_TYPE_MASK)
 
-/* Create an L0 block descriptor. */
+/* Create an L0 block descriptor */
 #define GPT_L0_BLK_DESC(_gpi)	(GPT_L0_TYPE_BLK_DESC | \
 				(((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \
 				GPT_L0_BLK_DESC_GPI_SHIFT))
 
-/* Create an L0 table descriptor with an L1 table address. */
+/* Create an L0 table descriptor with an L1 table address */
 #define GPT_L0_TBL_DESC(_pa)	(GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \
 				(GPT_L0_TBL_DESC_L1ADDR_MASK << \
 				GPT_L0_TBL_DESC_L1ADDR_SHIFT)))
 
-/* Get the GPI from an L0 block descriptor. */
+/* Get the GPI from an L0 block descriptor */
 #define GPT_L0_BLKD_GPI(_desc)	(((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \
 				GPT_L0_BLK_DESC_GPI_MASK)
 
-/* Get the L1 address from an L0 table descriptor. */
+/* Get the L1 address from an L0 table descriptor */
 #define GPT_L0_TBLD_ADDR(_desc)	((uint64_t *)(((_desc) & \
 				(GPT_L0_TBL_DESC_L1ADDR_MASK << \
 				GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
 
-/* Get the index into the L1 table from a physical address. */
+/* Get the index into the L1 table from a physical address */
 #define GPT_L1_IDX(_p, _pa)	(((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
 				GPT_L1_IDX_MASK(_p))
 
-/* Get the index of the GPI within an L1 table entry from a physical address. */
+/* Get the index of the GPI within an L1 table entry from a physical address */
 #define GPT_L1_GPI_IDX(_p, _pa)	(((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
 				GPT_L1_GPI_IDX_MASK)
 
-/* Determine if an address is granule-aligned. */
+/* Determine if an address is granule-aligned */
 #define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
 				   == U(0))
 

diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index 5144bf7..77bb7fe 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,8 @@
 
 	.globl	spin_lock
 	.globl	spin_unlock
+	.globl	bit_lock
+	.globl	bit_unlock
 
 #if USE_SPINLOCK_CAS
 #if !ARM_ARCH_AT_LEAST(8, 1)
@@ -73,3 +75,43 @@
 	stlr	wzr, [x0]
 	ret
 endfunc spin_unlock
+
+/*
+ * Atomic bit clear and set instructions require FEAT_LSE which is
+ * mandatory from Armv8.1.
+ */
+#if ARM_ARCH_AT_LEAST(8, 1)
+
+/*
+ * Acquire bitlock using atomic bit set on byte. If the original read value
+ * has the bit set, use load exclusive semantics to monitor the address and
+ * enter WFE.
+ *
+ * void bit_lock(bitlock_t *lock, uint8_t mask);
+ */
+func bit_lock
+1:	ldsetab	w1, w2, [x0]
+	tst	w2, w1
+	b.eq	2f
+	ldxrb	w2, [x0]
+	tst	w2, w1
+	b.eq	1b
+	wfe
+	b	1b
+2:
+	ret
+endfunc bit_lock
+
+/*
+ * Use atomic bit clear store-release to unconditionally clear bitlock variable.
+ * Store operation generates an event to all cores waiting in WFE when address
+ * is monitored by the global monitor.
+ *
+ * void bit_unlock(bitlock_t *lock, uint8_t mask);
+ */
+func bit_unlock
+	stclrlb	w1, [x0]
+	ret
+endfunc bit_unlock
+
+#endif /* ARM_ARCH_AT_LEAST(8, 1) */

diff --git a/lib/psa/delegated_attestation.c b/lib/psa/delegated_attestation.c
index 81e2621..805a941 100644
--- a/lib/psa/delegated_attestation.c
+++ b/lib/psa/delegated_attestation.c

@@ -10,7 +10,7 @@
 #include <psa_manifest/sid.h>
 
 psa_status_t
-rss_delegated_attest_get_delegated_key(uint8_t   ecc_curve,
+rse_delegated_attest_get_delegated_key(uint8_t   ecc_curve,
 				       uint32_t  key_bits,
 				       uint8_t  *key_buf,
 				       size_t    key_buf_size,
@@ -31,8 +31,8 @@
 		return PSA_ERROR_INVALID_ARGUMENT;
 	}
 
-	status = psa_call(RSS_DELEGATED_SERVICE_HANDLE,
-			  RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY,
+	status = psa_call(RSE_DELEGATED_SERVICE_HANDLE,
+			  RSE_DELEGATED_ATTEST_GET_DELEGATED_KEY,
 			  in_vec,  IOVEC_LEN(in_vec),
 			  out_vec, IOVEC_LEN(out_vec));
 	if (status == PSA_SUCCESS) {
@@ -43,7 +43,7 @@
 }
 
 psa_status_t
-rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+rse_delegated_attest_get_token(const uint8_t *dak_pub_hash,
 			       size_t         dak_pub_hash_size,
 			       uint8_t       *token_buf,
 			       size_t         token_buf_size,
@@ -61,8 +61,8 @@
 		return PSA_ERROR_INVALID_ARGUMENT;
 	}
 
-	status = psa_call(RSS_DELEGATED_SERVICE_HANDLE,
-			  RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN,
+	status = psa_call(RSE_DELEGATED_SERVICE_HANDLE,
+			  RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN,
 			  in_vec, IOVEC_LEN(in_vec),
 			  out_vec, IOVEC_LEN(out_vec));
 	if (status == PSA_SUCCESS) {

diff --git a/lib/psa/dice_protection_environment.c b/lib/psa/dice_protection_environment.c
index 44a5848..2145611 100644
--- a/lib/psa/dice_protection_environment.c
+++ b/lib/psa/dice_protection_environment.c

@@ -258,7 +258,7 @@
 		{ cmd_output, *cmd_output_size },
 	};
 
-	err = psa_call(RSS_DPE_SERVICE_HANDLE, 0,
+	err = psa_call(RSE_DPE_SERVICE_HANDLE, 0,
 			in_vec, IOVEC_LEN(in_vec), out_vec, IOVEC_LEN(out_vec));
 
 	if (err == PSA_SUCCESS) {

diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c
index ff1f45d..c66b8da 100644
--- a/lib/psa/measured_boot.c
+++ b/lib/psa/measured_boot.c

@@ -63,7 +63,7 @@
 }
 
 psa_status_t
-rss_measured_boot_extend_measurement(uint8_t index,
+rse_measured_boot_extend_measurement(uint8_t index,
 				     const uint8_t *signer_id,
 				     size_t signer_id_size,
 				     const uint8_t *version,
@@ -115,13 +115,13 @@
 			measurement_algo, measurement_value,
 			measurement_value_size, lock_measurement);
 
-	return psa_call(RSS_MEASURED_BOOT_HANDLE,
-			RSS_MEASURED_BOOT_EXTEND,
+	return psa_call(RSE_MEASURED_BOOT_HANDLE,
+			RSE_MEASURED_BOOT_EXTEND,
 			in_vec, IOVEC_LEN(in_vec),
 			NULL, 0);
 }
 
-psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+psa_status_t rse_measured_boot_read_measurement(uint8_t index,
 					uint8_t *signer_id,
 					size_t signer_id_size,
 					size_t *signer_id_len,
@@ -158,7 +158,7 @@
 		{.base = measurement_value, .len = measurement_value_size}
 	};
 
-	status = psa_call(RSS_MEASURED_BOOT_HANDLE, RSS_MEASURED_BOOT_READ,
+	status = psa_call(RSE_MEASURED_BOOT_HANDLE, RSE_MEASURED_BOOT_READ,
 					  in_vec, IOVEC_LEN(in_vec),
 					  out_vec, IOVEC_LEN(out_vec));
 

diff --git a/lib/psa/measured_boot_private.h b/lib/psa/measured_boot_private.h
index b8ca31d..bf2ae48 100644
--- a/lib/psa/measured_boot_private.h
+++ b/lib/psa/measured_boot_private.h

@@ -13,8 +13,8 @@
 #include <drivers/measured_boot/metadata.h>
 
 /* Measured boot message types that distinguish its services */
-#define RSS_MEASURED_BOOT_READ		1001U
-#define RSS_MEASURED_BOOT_EXTEND	1002U
+#define RSE_MEASURED_BOOT_READ		1001U
+#define RSE_MEASURED_BOOT_EXTEND	1002U
 
 struct measured_boot_read_iovec_in_t {
     uint8_t index;

diff --git a/lib/psa/rse_platform.c b/lib/psa/rse_platform.c
new file mode 100644
index 0000000..7fc2382
--- /dev/null
+++ b/lib/psa/rse_platform.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <psa/client.h>
+#include <psa_manifest/sid.h>
+#include <rse_crypto_defs.h>
+#include <rse_platform_api.h>
+
+psa_status_t
+rse_platform_nv_counter_increment(uint32_t counter_id)
+{
+	struct psa_invec in_vec[1];
+
+	in_vec[0].base = &counter_id;
+	in_vec[0].len = sizeof(counter_id);
+
+	return psa_call(RSE_PLATFORM_SERVICE_HANDLE,
+			RSE_PLATFORM_API_ID_NV_INCREMENT,
+			in_vec, 1, NULL, 0);
+}
+
+psa_status_t
+rse_platform_nv_counter_read(uint32_t counter_id,
+		uint32_t size, uint8_t *val)
+{
+	struct psa_invec in_vec[1];
+	struct psa_outvec out_vec[1];
+
+	in_vec[0].base = &counter_id;
+	in_vec[0].len = sizeof(counter_id);
+
+	out_vec[0].base = val;
+	out_vec[0].len = size;
+
+	return psa_call(RSE_PLATFORM_SERVICE_HANDLE,
+			RSE_PLATFORM_API_ID_NV_READ,
+			in_vec, 1, out_vec, 1);
+}
+
+psa_status_t
+rse_platform_key_read(enum rse_key_id_builtin_t key, uint8_t *data,
+		size_t data_size, size_t *data_length)
+{
+	psa_status_t status;
+
+	struct rse_crypto_pack_iovec iov = {
+		.function_id = RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID,
+		.key_id = key,
+	};
+
+	psa_invec in_vec[] = {
+		{.base = &iov, .len = sizeof(struct rse_crypto_pack_iovec)},
+	};
+	psa_outvec out_vec[] = {
+		{.base = data, .len = data_size}
+	};
+
+	status = psa_call(RSE_CRYPTO_HANDLE, PSA_IPC_CALL,
+			in_vec, IOVEC_LEN(in_vec),
+			out_vec, IOVEC_LEN(out_vec));
+
+	*data_length = out_vec[0].len;
+
+	return status;
+}

diff --git a/lib/psa/rss_platform.c b/lib/psa/rss_platform.c
deleted file mode 100644
index 7d90bfc..0000000
--- a/lib/psa/rss_platform.c
+++ /dev/null

@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#include <psa/client.h>
-#include <psa_manifest/sid.h>
-#include <rss_crypto_defs.h>
-#include <rss_platform_api.h>
-
-psa_status_t
-rss_platform_nv_counter_increment(uint32_t counter_id)
-{
-	struct psa_invec in_vec[1];
-
-	in_vec[0].base = &counter_id;
-	in_vec[0].len = sizeof(counter_id);
-
-	return psa_call(RSS_PLATFORM_SERVICE_HANDLE,
-			RSS_PLATFORM_API_ID_NV_INCREMENT,
-			in_vec, 1, NULL, 0);
-}
-
-psa_status_t
-rss_platform_nv_counter_read(uint32_t counter_id,
-		uint32_t size, uint8_t *val)
-{
-	struct psa_invec in_vec[1];
-	struct psa_outvec out_vec[1];
-
-	in_vec[0].base = &counter_id;
-	in_vec[0].len = sizeof(counter_id);
-
-	out_vec[0].base = val;
-	out_vec[0].len = size;
-
-	return psa_call(RSS_PLATFORM_SERVICE_HANDLE,
-			RSS_PLATFORM_API_ID_NV_READ,
-			in_vec, 1, out_vec, 1);
-}
-
-psa_status_t
-rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data,
-		size_t data_size, size_t *data_length)
-{
-	psa_status_t status;
-
-	struct rss_crypto_pack_iovec iov = {
-		.function_id = RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID,
-		.key_id = key,
-	};
-
-	psa_invec in_vec[] = {
-		{.base = &iov, .len = sizeof(struct rss_crypto_pack_iovec)},
-	};
-	psa_outvec out_vec[] = {
-		{.base = data, .len = data_size}
-	};
-
-	status = psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL,
-			in_vec, IOVEC_LEN(in_vec),
-			out_vec, IOVEC_LEN(out_vec));
-
-	*data_length = out_vec[0].len;
-
-	return status;
-}

diff --git a/lib/transfer_list/transfer_list.mk b/lib/transfer_list/transfer_list.mk
index 42574e8..3ec4df2 100644
--- a/lib/transfer_list/transfer_list.mk
+++ b/lib/transfer_list/transfer_list.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -15,6 +15,7 @@
 
 BL31_SOURCES	+=	$(TRANSFER_LIST_SOURCES)
 BL2_SOURCES	+=	$(TRANSFER_LIST_SOURCES)
+BL1_SOURCES	+=	$(TRANSFER_LIST_SOURCES)
 
 endif	# TRANSFER_LIST
 

diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index ee6c260..30f1760 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -96,6 +96,15 @@
 		      <0x0 0x88000000 0x0 0x10000000>;
 	};
 
+	memory@2 {
+		device_type = "device-memory";
+		reg = <0x0 0x1c090000 0x0 0x40000>, /* UART */
+		      <0x0 0x2bfe0000 0x0 0x20000>, /* SMMUv3TestEngine */
+		      <0x0 0x2a490000 0x0 0x20000>, /* SP805 Trusted Watchdog */
+		      <0x0 0x1c130000 0x0 0x10000>; /* Virtio block device */
+	};
+
+
 #if MEASURED_BOOT
 #include "event_log.dtsi"
 #endif

diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index f29ea45..d90544b 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts

@@ -68,4 +68,9 @@
 		reg = <0x00008800 0x80000000 0x0 0x7f000000>,
 		      <0x0 0x88000000 0x0 0x10000000>;
 	};
+
+	memory@0 {
+		device_type = "device-memory";
+		reg = <0x0 0x1c090000 0x0 0x40000>; /* UART */
+	};
 };

diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 97d000e..ebdd80d 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c

@@ -20,8 +20,6 @@
 
 #include "fvp_private.h"
 
-static struct transfer_list_header *ns_tl __unused;
-
 #if ENABLE_RME
 /*
  * The GPT library might modify the gpt regions structure to optimize
@@ -50,6 +48,11 @@
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
 {
+	struct transfer_list_entry *te __unused;
+
+#if TRANSFER_LIST
+	arg0 = arg3;
+#endif
 	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
 
 	/* Initialize the platform config for future decision making */
@@ -60,10 +63,6 @@
 {
 	arm_bl2_platform_setup();
 
-#if TRANSFER_LIST
-	ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE);
-	assert(ns_tl != NULL);
-#endif
 	/* Initialize System level generic or SP804 timer */
 	fvp_timer_init();
 }
@@ -81,16 +80,15 @@
 struct bl_params *plat_get_next_bl_params(void)
 {
 	struct bl_params *arm_bl_params;
-	const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
-	struct transfer_list_entry *te __unused;
 	bl_mem_params_node_t *param_node __unused;
+	const struct dyn_cfg_dtb_info_t *fw_config_info __unused;
+	const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
+	entry_point_info_t *ep __unused;
+	uint32_t next_exe_img_id __unused;
+	uintptr_t fw_config_base __unused;
 
 	arm_bl_params = arm_get_next_bl_params();
 
-#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
-	const struct dyn_cfg_dtb_info_t *fw_config_info;
-	uintptr_t fw_config_base = 0UL;
-
 #if __aarch64__
 	/* Get BL31 image node */
 	param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
@@ -100,6 +98,15 @@
 #endif /* __aarch64__ */
 	assert(param_node != NULL);
 
+#if TRANSFER_LIST
+	arm_bl_params->head = &param_node->params_node_mem;
+	arm_bl_params->head->ep_info = &param_node->ep_info;
+	arm_bl_params->head->image_id = param_node->image_id;
+
+	arm_bl2_setup_next_ep_info(param_node);
+#elif !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
+	fw_config_base = 0UL;
+
 	/* Update the next image's ep info with the FW config address */
 	fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
 	assert(fw_config_info != NULL);
@@ -113,49 +120,29 @@
 	param_node = get_bl_mem_params_node(BL33_IMAGE_ID);
 	assert(param_node != NULL);
 
-#if TRANSFER_LIST
-	/* Update BL33's ep info with NS HW config address  */
-	te = transfer_list_find(ns_tl, TL_TAG_FDT);
-	assert(te != NULL);
-
-	param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE |
-					REGISTER_CONVENTION_VERSION_MASK;
-	param_node->ep_info.args.arg2 = 0;
-	param_node->ep_info.args.arg3 = (uintptr_t)ns_tl;
-	param_node->ep_info.args.arg0 =
-		te ? (uintptr_t)transfer_list_entry_data(te) : 0;
-#else
 	hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
 	assert(hw_config_info != NULL);
 
 	param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr;
 #endif /* TRANSFER_LIST */
-#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
 
 	return arm_bl_params;
 }
 
 int bl2_plat_handle_post_image_load(unsigned int image_id)
 {
-#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
+#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST
 	if (image_id == HW_CONFIG_ID) {
-		const struct dyn_cfg_dtb_info_t *hw_config_info;
+		const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
 		struct transfer_list_entry *te __unused;
+		bl_mem_params_node_t *param_node __unused;
 
-		const bl_mem_params_node_t *param_node =
-			get_bl_mem_params_node(image_id);
+		param_node = get_bl_mem_params_node(image_id);
 		assert(param_node != NULL);
 
 		hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
 		assert(hw_config_info != NULL);
 
-#if TRANSFER_LIST
-		/* Update BL33's ep info with NS HW config address  */
-		te = transfer_list_add(ns_tl, TL_TAG_FDT,
-				       param_node->image_info.image_size,
-				       (void *)hw_config_info->config_addr);
-		assert(te != NULL);
-#else
 		memcpy((void *)hw_config_info->secondary_config_addr,
 		       (void *)hw_config_info->config_addr,
 		       (size_t)param_node->image_info.image_size);
@@ -166,9 +153,8 @@
 		 */
 		flush_dcache_range(hw_config_info->secondary_config_addr,
 				   param_node->image_info.image_size);
-#endif /* TRANSFER_LIST */
 	}
-#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
+#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/
 
 	return arm_bl2_plat_handle_post_image_load(image_id);
 }

diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index 93289b6..e087565 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c

@@ -5,12 +5,15 @@
  */
 
 #include <assert.h>
+
+#include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/arm/smmu_v3.h>
 #include <fconf_hw_config_getter.h>
 #include <lib/fconf/fconf.h>
 #include <lib/fconf/fconf_dyn_cfg_getter.h>
 #include <lib/mmio.h>
+
 #include <plat/arm/common/arm_config.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
@@ -25,6 +28,9 @@
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();
 
+#if TRANSFER_LIST
+	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
+#else
 #if !RESET_TO_BL31 && !RESET_TO_BL2
 	const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
 
@@ -48,8 +54,8 @@
 	assert(hw_config_info->secondary_config_addr != 0UL);
 	arg2 = hw_config_info->secondary_config_addr;
 #endif /* !RESET_TO_BL31 && !RESET_TO_BL2 */
-
 	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+#endif /* TRANSFER_LIST */
 
 	/* Initialize the platform config for future decision making */
 	fvp_config_setup();
@@ -88,6 +94,7 @@
 	}
 }
 
+#if !TRANSFER_LIST
 void __init bl31_plat_arch_setup(void)
 {
 	int rc __unused;
@@ -142,6 +149,7 @@
 	}
 #endif /* !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 */
 }
+#endif /* TRANSFER_LIST */
 
 unsigned int plat_get_syscnt_freq2(void)
 {

diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 8cbf10e..5557d59 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c

@@ -81,10 +81,15 @@
 
 #if TRANSFER_LIST
 #ifdef FW_NS_HANDOFF_BASE
-#define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, \
-					  FW_HANDOFF_SIZE,    \
-					  MT_MEMORY | MT_RW | MT_NS)
+#define MAP_FW_NS_HANDOFF                                             \
+	MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
+			MT_MEMORY | MT_RW | MT_NS)
 #endif
+#ifdef PLAT_ARM_EL3_FW_HANDOFF_BASE
+#define MAP_EL3_FW_HANDOFF                            \
+	MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
+			PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
+#endif
 #endif
 
 /*
@@ -165,7 +170,10 @@
 	ARM_MAP_OPTEE_CORE_MEM,
 	ARM_OPTEE_PAGEABLE_LOAD_MEM,
 #endif
-	{0}
+#ifdef MAP_EL3_FW_HANDOFF
+	MAP_EL3_FW_HANDOFF,
+#endif
+	{ 0 }
 };
 #endif
 #ifdef IMAGE_BL2U
@@ -202,7 +210,10 @@
 #ifdef MAP_FW_NS_HANDOFF
 	MAP_FW_NS_HANDOFF,
 #endif
-	{0}
+#ifdef MAP_EL3_FW_HANDOFF
+	MAP_EL3_FW_HANDOFF,
+#endif
+	{ 0 }
 };
 
 #if defined(IMAGE_BL31) && SPM_MM

diff --git a/plat/arm/board/fvp/fvp_common_measured_boot.c b/plat/arm/board/fvp/fvp_common_measured_boot.c
index d56f510..605f0ff 100644
--- a/plat/arm/board/fvp/fvp_common_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_common_measured_boot.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,12 +9,10 @@
 
 #include <common/desc_image_load.h>
 #include <drivers/measured_boot/event_log/event_log.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
 extern event_log_metadata_t fvp_event_log_metadata[];
-extern struct rss_mboot_metadata fvp_rss_mboot_metadata[];
 
 int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
 {

diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index 5fb3141..f5bd722 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c

@@ -98,7 +98,7 @@
 
 /*
  * Get the hardcoded platform attestation token as FVP does not support
- * RSS.
+ * RSE.
  */
 int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
 				   uintptr_t hash, size_t hash_size)

diff --git a/plat/arm/board/fvp/fvp_realm_attest_key.c b/plat/arm/board/fvp/fvp_realm_attest_key.c
index fe0cde7..150608d 100644
--- a/plat/arm/board/fvp/fvp_realm_attest_key.c
+++ b/plat/arm/board/fvp/fvp_realm_attest_key.c

@@ -19,7 +19,7 @@
 
 /*
  * Get the hardcoded delegated realm attestation key as FVP
- * does not support RSS.
+ * does not support RSE.
  */
 int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
 				       unsigned int type)

diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index ab1b07f..56de8b8 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h

@@ -143,8 +143,14 @@
 #define PLAT_ARM_NS_IMAGE_BASE		(ARM_DRAM1_BASE + UL(0x8000000))
 
 #if TRANSFER_LIST
-#define FW_HANDOFF_SIZE			0x4000
-#define FW_NS_HANDOFF_BASE		(PLAT_ARM_NS_IMAGE_BASE - FW_HANDOFF_SIZE)
+#define PLAT_ARM_FW_HANDOFF_SIZE	U(0x5000)
+
+#define FW_NS_HANDOFF_BASE		(PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE)
+#define PLAT_ARM_EL3_FW_HANDOFF_BASE	ARM_BL_RAM_BASE
+#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT	PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+
+#else
+#define PLAT_ARM_FW_HANDOFF_SIZE	U(0)
 #endif
 
 /*
@@ -269,9 +275,15 @@
  * BL2 and BL1-RW.
  * Size of the BL31 PROGBITS increases as the SRAM size increases.
  */
+#if TRANSFER_LIST
+#define PLAT_ARM_MAX_BL31_SIZE                              \
+	(PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \
+	 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE)
+#else
 #define PLAT_ARM_MAX_BL31_SIZE		(PLAT_ARM_TRUSTED_SRAM_SIZE - \
 					 ARM_SHARED_RAM_SIZE - \
 					 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE)
+#endif /* TRANSFER_LIST */
 #endif /* RESET_TO_BL31 */
 
 #ifndef __aarch64__

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 8fa01ff..07e69e6 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk

@@ -330,9 +330,23 @@
 BL31_SOURCES		+=	drivers/delay_timer/generic_delay_timer.c
 endif
 
+ifeq (${TRANSFER_LIST}, 1)
+include lib/transfer_list/transfer_list.mk
+endif
+
 # Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
 ifdef UNIX_MK
+FVP_TB_FW_CONFIG	:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
 FVP_HW_CONFIG_DTS	:=	fdts/${FVP_DT_PREFIX}.dts
+
+FDT_SOURCES		+=	${FVP_HW_CONFIG_DTS}
+$(eval FVP_HW_CONFIG	:=	${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
+
+ifeq (${TRANSFER_LIST}, 1)
+FDT_SOURCES		+=	$(addprefix plat/arm/board/fvp/fdts/,	\
+					${PLAT}_tb_fw_config.dts	\
+				)
+else
 FDT_SOURCES		+=	$(addprefix plat/arm/board/fvp/fdts/,	\
 					${PLAT}_fw_config.dts		\
 					${PLAT}_tb_fw_config.dts	\
@@ -341,7 +355,6 @@
 				)
 
 FVP_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-FVP_TB_FW_CONFIG	:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
 FVP_SOC_FW_CONFIG	:=	${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb
 FVP_NT_FW_CONFIG	:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
 
@@ -353,10 +366,6 @@
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
 endif
 
-ifeq (${TRANSFER_LIST}, 1)
-include lib/transfer_list/transfer_list.mk
-endif
-
 ifeq (${SPD},spmd)
 
 ifeq ($(ARM_SPMC_MANIFEST_DTS),)
@@ -372,16 +381,14 @@
 
 # Add the FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
 # Add the SOC_FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG}))
 # Add the NT_FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG}))
-
-FDT_SOURCES		+=	${FVP_HW_CONFIG_DTS}
-$(eval FVP_HW_CONFIG	:=	${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
+endif
 
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
 # Add the HW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
 endif

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_main.c b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
index 252fc31..29495cf 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_main.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_main.c

@@ -92,27 +92,6 @@
 }
 
 /*******************************************************************************
- * Helper utility to calculate the BL2 memory layout taking into consideration
- * the BL1 RW data assuming that it is at the top of the memory layout.
- ******************************************************************************/
-void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
-			meminfo_t *bl2_mem_layout)
-{
-	assert(bl1_mem_layout != NULL);
-	assert(bl2_mem_layout != NULL);
-
-	/*
-	 * Remove BL1 RW data from the scope of memory visible to BL2.
-	 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
-	 */
-	assert(bl1_mem_layout->total_base < BL1_RW_BASE);
-	bl2_mem_layout->total_base = bl1_mem_layout->total_base;
-	bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
-
-	flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
-}
-
-/*******************************************************************************
  * This function prepares for entry to BL33
  ******************************************************************************/
 void bl1_prepare_next_image(unsigned int image_id)

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
index 6a7c0c8..dcf5e04 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -235,7 +235,7 @@
 	 */
 	bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
 
-	bl1_calc_bl2_mem_layout(bl1_secram_layout, bl33_secram_layout);
+	bl1_plat_calc_bl2_layout(bl1_secram_layout, bl33_secram_layout);
 
 	ep_info->args.arg1 = (uintptr_t)bl33_secram_layout;
 

diff --git a/plat/arm/board/fvp_r/include/platform_def.h b/plat/arm/board/fvp_r/include/platform_def.h
index 548825c..1fdec15 100644
--- a/plat/arm/board/fvp_r/include/platform_def.h
+++ b/plat/arm/board/fvp_r/include/platform_def.h

@@ -75,13 +75,6 @@
 #define PLAT_BL1_RO_LIMIT               (BL1_RO_BASE \
 					+ PLAT_ARM_TRUSTED_ROM_SIZE)
 
-#define PLAT_ARM_SYS_CNTCTL_BASE	UL(0xaa430000)
-#define PLAT_ARM_SYS_CNTREAD_BASE	UL(0xaa800000)
-#define PLAT_ARM_SYS_TIMCTL_BASE	UL(0xaa810000)
-#define PLAT_ARM_SYS_CNT_BASE_S		UL(0xaa820000)
-#define PLAT_ARM_SYS_CNT_BASE_NS	UL(0xaa830000)
-#define PLAT_ARM_SP805_TWDG_BASE	UL(0xaa490000)
-
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
new file mode 100644
index 0000000..74835f6
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the CSS specific memory and interrupt map
+ * definitions for the first generation platforms based on the A75, N1 and V1
+ * CPUs. There are minor differences in the memory map of these platforms and
+ * those differences are not in the scope of this file.
+ */
+
+#ifndef NRD_CSS_DEF1_H
+#define NRD_CSS_DEF1_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* On-Chip ROM */
+#define NRD_CSS_TRUSTED_ROM_BASE	UL(0x00000000)
+#define NRD_CSS_TRUSTED_ROM_SIZE	UL(0x00080000)	/* 512KB */
+
+/* On-Chip RAM */
+#define	NRD_CSS_TRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
+#define NRD_CSS_NONTRUSTED_SRAM_BASE	UL(0x06000000)
+#define NRD_CSS_NONTRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
+
+/* PL011 UART */
+#define NRD_CSS_SEC_UART_BASE		UL(0x2A410000)
+#define NRD_CSS_UART_SIZE		UL(0x10000)
+
+/* CSS peripherals */
+#define NRD_CSS_PERIPH_BASE		UL(0x20000000)
+#define NRD_CSS_PERIPH_SIZE		UL(0x40000000)
+
+/* Secure Watchdog */
+#define NRD_CSS_WDOG_BASE		UL(0x2A480000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_BASE		ULL(0x8080000000)
+#define NRD_CSS_DRAM2_SIZE		ULL(0x180000000)
+
+#endif /* NRD_CSS_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
new file mode 100644
index 0000000..70a7d49
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the CSS firmware specific definitions for
+ * the first generation platforms based on the A75, N1 and V1 CPUs.
+ */
+
+#ifndef NRD1_CSS_FW_DEF1_H
+#define NRD1_CSS_FW_DEF1_H
+
+#include <nrd_css_def1.h>
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define NRD_CSS_BL1_RW_SIZE		UL(64 * 1024)	/* 64KB */
+
+#if TRUSTED_BOARD_BOOT
+# define NRD_CSS_BL2_SIZE		UL(0x28000)
+#else
+# define NRD_CSS_BL2_SIZE		UL(0x14000)
+#endif
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
+ * and BL1-RW.
+ */
+#define NRD_CSS_BL31_SIZE		UL(116 * 1024)	/* 116 KB */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define NRD_CSS_UART_CLK_IN_HZ		UL(7372800)
+
+/*******************************************************************************
+ * Watchdog config
+ ******************************************************************************/
+
+#define NRD_CSS_WDOG_TIMEOUT		UL(100)
+
+/*******************************************************************************
+ * Platform ID
+ ******************************************************************************/
+
+/* Platform ID address */
+#define SSC_VERSION		(SSC_REG_BASE + SSC_VERSION_OFFSET)
+#ifndef __ASSEMBLER__
+/* SSC_VERSION related accessors */
+/* Returns the part number of the platform */
+#define GET_NRD_PART_NUM						\
+			GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
+/* Returns the configuration number of the platform */
+#define GET_NRD_CONFIG_NUM						\
+			GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
+#endif /* __ASSEMBLER__ */
+
+/*******************************************************************************
+ * MMU mappings
+ ******************************************************************************/
+
+#define NRD_CSS_PERIPH_MMAP(n)						\
+		MAP_REGION_FLAT(					\
+			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
+			NRD_CSS_PERIPH_BASE,				\
+			NRD_CSS_PERIPH_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_CSS_SHARED_RAM_MMAP(n)					\
+		MAP_REGION_FLAT(					\
+			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
+			ARM_SHARED_RAM_BASE,				\
+			ARM_SHARED_RAM_SIZE,				\
+			MT_NON_CACHEABLE | MT_RW | MT_SECURE)
+
+#if SPM_MM
+/*
+ * Stand-alone MM logs would be routed via secure UART. Define page table
+ * entry for secure UART which would be common to all platforms.
+ */
+#define NRD_CSS_SECURE_UART_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_CSS_SEC_UART_BASE,				\
+			NRD_CSS_UART_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
+#endif /* NRD_CSS_FW_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
new file mode 100644
index 0000000..bca095c
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h

@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the platform port definitions for the
+ * first generation platforms based on the A75, N1 and V1 CPUs.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF1_H
+#define NRD_PLAT_ARM_DEF1_H
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+#include <plat/common/common_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_ros_fw_def1.h>
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT	(NRD_CHIP_COUNT *			\
+				PLAT_ARM_CLUSTER_COUNT *		\
+				NRD_MAX_CPUS_PER_CLUSTER *		\
+				NRD_MAX_PE_PER_CPU)
+
+/*******************************************************************************
+ * PA/VA config
+ ******************************************************************************/
+
+#ifdef __aarch64__
+#define PLAT_PHY_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
+						NRD_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
+						NRD_CHIP_COUNT)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+#if defined(IMAGE_BL31)
+# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
+#  define PLAT_ARM_MMAP_ENTRIES		(10 + ((NRD_CHIP_COUNT - 1) * 3))
+#  define MAX_XLAT_TABLES		(11 + ((NRD_CHIP_COUNT - 1) * 3))
+#  define PLAT_SP_IMAGE_MMAP_REGIONS	U(12)
+#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	U(14)
+# else
+#  define PLAT_ARM_MMAP_ENTRIES		(5 + ((NRD_CHIP_COUNT - 1) * 3))
+#  define MAX_XLAT_TABLES		(6 + ((NRD_CHIP_COUNT - 1) * 3))
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES		U(8)
+# define MAX_XLAT_TABLES		U(5)
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES		(11 + (NRD_CHIP_COUNT - 1))
+
+/*
+ * MAX_XLAT_TABLES entries need to be doubled because when the address width
+ * exceeds 40 bits an additional level of translation is required. In case of
+ * multichip platforms peripherals also fall into address space with width
+ * > 40 bits.
+ */
+# define MAX_XLAT_TABLES		(11  + ((NRD_CHIP_COUNT - 1) * 2))
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES		U(11)
+# define MAX_XLAT_TABLES		U(7)
+#else
+# define PLAT_ARM_MMAP_ENTRIES		U(12)
+# define MAX_XLAT_TABLES		U(6)
+#endif
+
+/*******************************************************************************
+ * Stack size
+ ******************************************************************************/
+
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE		U(0x1000)
+# else
+#  define PLATFORM_STACK_SIZE		U(0x440)
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE		U(0x1000)
+# else
+#  define PLATFORM_STACK_SIZE		U(0x400)
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE		U(0x400)
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+#  define PLATFORM_STACK_SIZE		U(0x500)
+# else
+#  define PLATFORM_STACK_SIZE		U(0x400)
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE		U(0x440)
+#endif
+
+#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
+/*
+ * Secure partition stack follows right after the memory region that is shared
+ * between EL3 and S-EL0.
+ */
+#define PLAT_ARM_SP_IMAGE_STACK_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +	\
+					 PLAT_SP_IMAGE_NS_BUF_SIZE)
+#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	U(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	U(0xe000)
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	U(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	U(0)
+#endif
+
+#define PLAT_ARM_MAX_BL1_RW_SIZE	NRD_CSS_BL1_RW_SIZE
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
+ */
+#define PLAT_ARM_MAX_BL2_SIZE		(NRD_CSS_BL2_SIZE +		\
+						((NRD_CHIP_COUNT - 1) * 0x2000))
+
+#define PLAT_ARM_MAX_BL31_SIZE		(NRD_CSS_BL31_SIZE +		\
+						PLAT_ARM_MAX_BL2_SIZE +	\
+						PLAT_ARM_MAX_BL1_RW_SIZE)
+
+/*******************************************************************************
+ * ROM, SRAM and DRAM config
+ ******************************************************************************/
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	NRD_CSS_TRUSTED_SRAM_SIZE
+
+#define PLAT_ARM_TRUSTED_ROM_BASE	NRD_CSS_TRUSTED_ROM_BASE
+#define PLAT_ARM_TRUSTED_ROM_SIZE	NRD_CSS_TRUSTED_ROM_SIZE
+
+#define PLAT_ARM_NSRAM_BASE		NRD_CSS_NONTRUSTED_SRAM_BASE
+#define PLAT_ARM_NSRAM_SIZE		NRD_CSS_NONTRUSTED_SRAM_SIZE
+
+#define PLAT_ARM_DRAM2_BASE		NRD_CSS_DRAM2_BASE
+#define PLAT_ARM_DRAM2_SIZE		NRD_CSS_DRAM2_SIZE
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define PLAT_ARM_BOOT_UART_BASE		NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE		NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE	NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * Timer config
+ ******************************************************************************/
+
+#define PLAT_ARM_NSTIMER_FRAME_ID	(0)
+
+/*******************************************************************************
+ * Power config
+ ******************************************************************************/
+
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
+
+/*******************************************************************************
+ * Flash config
+ ******************************************************************************/
+
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
+					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+/* IO storage framework */
+#define MAX_IO_DEVICES			U(3)
+#define MAX_IO_HANDLES			U(4)
+
+/*******************************************************************************
+ * SCMI config
+ ******************************************************************************/
+
+/* Number of SCMI channels on the platform */
+#define PLAT_ARM_SCMI_CHANNEL_COUNT	NRD_CHIP_COUNT
+
+/*******************************************************************************
+ * SDS config
+ ******************************************************************************/
+
+/* Index of SDS region used in the communication with SCP */
+#define SDS_SCP_AP_REGION_ID		U(0)
+/* SDS ID for unusable CPU MPID list structure */
+#define SDS_ISOLATED_CPU_LIST_ID	U(128)
+
+/*******************************************************************************
+ * GIC/EHF config
+ ******************************************************************************/
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp)	CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
+#define PLAT_SP_PRI			U(0x10)
+
+/*******************************************************************************
+ * Platform type identification macro
+ ******************************************************************************/
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK		U(0x0f)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		U(0x0)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR		U(0x02)
+
+#ifndef __ASSEMBLER__
+#define BOARD_CSS_GET_PLAT_TYPE(addr)					\
+		((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK)	\
+		>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+#endif /* __ASSEMBLER__ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR		NRD_ROS_PLATFORM_BASE +	\
+						UL(0x00fe00e0)
+
+#endif /* NRD_PLAT_ARM_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
new file mode 100644
index 0000000..b86ab21
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS specific definitions for the first
+ * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
+ * is used to refer to the part of the reference design platform that excludes
+ * CSS.
+ */
+
+#ifndef NRD_ROS_DEF1_H
+#define NRD_ROS_DEF1_H
+
+/*******************************************************************************
+ * ROS configs
+ ******************************************************************************/
+
+/* RoS Peripherals */
+#define NRD_ROS_PERIPH_BASE		UL(0x60000000)
+#define NRD_ROS_PERIPH_SIZE		UL(0x20000000)
+
+/* System Reg */
+#define NRD_ROS_SYSTEMREG_BASE		UL(0x1C010000)
+#define NRD_ROS_SYSTEMREG_SIZE		UL(0x00010000)
+
+/* NOR Flash 2 */
+#define NRD_ROS_NOR2_FLASH_BASE		UL(0x10000000)
+#define NRD_ROS_NOR2_FLASH_SIZE		UL(0x04000000)
+
+/* RoS Platform */
+#define NRD_ROS_PLATFORM_BASE		UL(0x7F000000)
+#define NRD_ROS_PLATFORM_SIZE		UL(0x20000000)
+
+#endif /* NRD_ROS_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
new file mode 100644
index 0000000..c521043
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS firmware specific definitions for the
+ * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
+ * System) is used to refer to the part of the reference design platform that
+ * excludes CSS.
+ */
+
+#ifndef NRD_ROS_FW_DEF1_H
+#define NRD_ROS_FW_DEF1_H
+
+#include <nrd_ros_def1.h>
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_ROS_PERIPH_MMAP(n)						\
+		MAP_REGION_FLAT(					\
+			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
+			NRD_ROS_PERIPH_BASE,				\
+			NRD_ROS_PERIPH_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP				\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_SYSTEMREG_BASE,				\
+			NRD_ROS_SYSTEMREG_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define NRD_ROS_SECURE_NOR2_USER_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_NOR2_FLASH_BASE,			\
+			NRD_ROS_NOR2_FLASH_SIZE,			\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define NRD_MAP_FLASH0_RO						\
+		MAP_REGION_FLAT(					\
+			V2M_FLASH0_BASE,				\
+			V2M_FLASH0_SIZE,				\
+			MT_DEVICE | MT_RO | MT_SECURE)
+
+/*******************************************************************************
+ * TZ config
+ ******************************************************************************/
+
+/*
+ * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
+ * where both the DRAM regions are marked for non-secure access. This applies
+ * to multi-chip platforms.
+ */
+#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n)				\
+	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE,		\
+		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END,		\
+		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},	\
+	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE,		\
+		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END,		\
+		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
+
+#endif  /* NRD_ROS_FW_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h
new file mode 100644
index 0000000..6cf57d4
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS specific definitions for the second generation
+ * platforms based on the N2/V2 CPU.
+ */
+
+#ifndef NRD_CSS_DEF2_H
+#define NRD_CSS_DEF2_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* Boot ROM */
+#define NRD_CSS_SECURE_ROM_BASE			UL(0x00000000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_BASE			ULL(0x8080000000)
+
+/* NS SRAM */
+#define NRD_CSS_NS_SRAM_BASE			UL(0x06000000)
+
+/* PL011 UART */
+#define NRD_CSS_SEC_UART_BASE			UL(0x2A410000)
+#define NRD_CSS_NSEC_UART_BASE			UL(0x2A400000)
+#define NRD_CSS_UART_SIZE			UL(0x10000)
+
+/* General Peripherals */
+#define NRD_CSS_PERIPH_BASE			UL(0x20000000)
+#define NRD_CSS_PERIPH_SIZE			UL(0x20000000)
+
+/* NS RAM Error record */
+#define NRD_CSS_NS_RAM_ERR_REC_BASE		UL(0x2A4C0000)
+
+/*Secure Watchdog */
+#define NRD_CSS_SECURE_WDOG_BASE		UL(0x2A480000)
+
+/* MHU */
+#define NRD_CSS_AP_SCP_S_MHU_BASE		UL(0x2A920000)
+
+/* GIC */
+#define NRD_CSS_GIC_BASE			UL(0x30000000)
+
+#endif /* NRD_CSS_DEF2_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h
new file mode 100644
index 0000000..481632b
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS-firmware specific definitions for the second
+ * generation platforms based on the N2/V2 CPU.
+ */
+
+#ifndef NRD_CSS_FW_DEF2_H
+#define NRD_CSS_FW_DEF2_H
+
+#include <nrd_css_def2.h>
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define NRD_CSS_BL1_RW_SIZE		UL(64 * 1024)	/* 64KB */
+
+#if TRUSTED_BOARD_BOOT
+# define NRD_CSS_BL2_SIZE		UL(0x20000)
+#else
+# define NRD_CSS_BL2_SIZE		UL(0x14000)
+#endif
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
+ * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31
+ * PROGBITS size which is around 64-68KB at the time this change is being made.
+ * A buffer of ~35KB is added to account for future expansion of the image,
+ * making it a total of 100KB.
+ */
+#define NRD_CSS_BL31_SIZE		UL(116 * 1024)	/* 116 KB */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define NRD_CSS_UART_CLK_IN_HZ		UL(7372800)
+
+/*******************************************************************************
+ * Watchdog config
+ ******************************************************************************/
+
+#define NRD_CSS_SECURE_WDOG_TIMEOUT	UL(100)
+
+/*******************************************************************************
+ * RAS config
+ ******************************************************************************/
+
+#define NRD_CSS_NS_RAM_ECC_CE_INT		U(87)
+#define NRD_CSS_NS_RAM_ECC_UE_INT		U(88)
+
+#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))			\
+	&& ENABLE_FEAT_RAS && FFH_SUPPORT
+/*
+ * CPER buffer memory of 128KB is reserved and it is placed adjacent to the
+ * memory shared between EL3 and S-EL0.
+ */
+#define NRD_CSS_SP_CPER_BUF_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +	\
+					 PLAT_SP_IMAGE_NS_BUF_SIZE)
+#define NRD_CSS_SP_CPER_BUF_SIZE	UL(0x10000)
+#endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_CSS_SHARED_RAM_MMAP(n)					\
+		MAP_REGION_FLAT(					\
+			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
+			ARM_SHARED_RAM_BASE,				\
+			ARM_SHARED_RAM_SIZE,				\
+			MT_NON_CACHEABLE | MT_RW | MT_SECURE)
+
+#define NRD_CSS_PERIPH_MMAP(n)						\
+		MAP_REGION_FLAT(					\
+			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
+			NRD_CSS_PERIPH_BASE,				\
+			NRD_CSS_PERIPH_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) &&			\
+ENABLE_FEAT_RAS && FFH_SUPPORT
+/*
+ * CPER buffer memory of 128KB is reserved and it is placed adjacent to the
+ * memory shared between EL3 and S-EL0.
+ */
+#define NRD_CSS_SP_CPER_BUF_MMAP					\
+		MAP_REGION2(						\
+			NRD_CSS_SP_CPER_BUF_BASE,			\
+			NRD_CSS_SP_CPER_BUF_BASE,			\
+			NRD_CSS_SP_CPER_BUF_SIZE,			\
+			MT_RW_DATA | MT_NS | MT_USER,			\
+			PAGE_SIZE)
+#endif
+
+#if SPM_MM
+#define NRD_CSS_SECURE_UART_USER_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_CSS_SEC_UART_BASE,				\
+			NRD_CSS_UART_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
+#endif /* NRD_CSS_FW_DEF2_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
new file mode 100644
index 0000000..3ee413f
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h

@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the trusted firmware required platform port
+ * definitions for the second generation platforms based on the N2/V2 CPUs. The
+ * common platform support for Arm platforms expect platforms to define certain
+ * definitions and those definitions are referred to as the platform port
+ * definitions.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF2_H
+#define NRD_PLAT_ARM_DEF2_H
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <nrd_css_fw_def2.h>
+#include <nrd_ros_fw_def2.h>
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT		(NRD_CHIP_COUNT *		\
+					PLAT_ARM_CLUSTER_COUNT *	\
+					NRD_MAX_CPUS_PER_CLUSTER *	\
+					NRD_MAX_PE_PER_CPU)
+
+#if (NRD_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT		U(8)
+#elif (NRD_PLATFORM_VARIANT == 2)
+#define PLAT_ARM_CLUSTER_COUNT		U(4)
+#else
+#define PLAT_ARM_CLUSTER_COUNT		U(16)
+#endif
+
+/*******************************************************************************
+ * PA/VA config
+ ******************************************************************************/
+
+#ifdef __aarch64__
+#define PLAT_PHY_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
+						NRD_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
+						NRD_CHIP_COUNT)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#endif
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+#if defined(IMAGE_BL31)
+# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
+#  define PLAT_ARM_MMAP_ENTRIES		(10  + ((NRD_CHIP_COUNT - 1) * 3))
+#  define MAX_XLAT_TABLES		(8  + ((NRD_CHIP_COUNT - 1) * 3))
+#  define PLAT_SP_IMAGE_MMAP_REGIONS	U(12)
+#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	U(14)
+# else
+#  define PLAT_ARM_MMAP_ENTRIES		(5 + ((NRD_CHIP_COUNT - 1) * 3))
+#  define MAX_XLAT_TABLES		(6 + ((NRD_CHIP_COUNT - 1) * 3))
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES		U(8)
+# define MAX_XLAT_TABLES		U(5)
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES		(11 + (NRD_CHIP_COUNT - 1))
+
+/*
+ * MAX_XLAT_TABLES entries need to be doubled because when the address width
+ * exceeds 40 bits an additional level of translation is required. In case of
+ * multichip platforms peripherals also fall into address space with width
+ * > 40 bits
+ *
+ */
+# define MAX_XLAT_TABLES		(7  + ((NRD_CHIP_COUNT - 1) * 2))
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES		U(11)
+# define MAX_XLAT_TABLES		U(7)
+#else
+# define PLAT_ARM_MMAP_ENTRIES		U(12)
+# define MAX_XLAT_TABLES		U(6)
+#endif
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+/*
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+ */
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0xe000)
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0)
+#endif
+
+#define PLAT_ARM_MAX_BL1_RW_SIZE	NRD_CSS_BL1_RW_SIZE
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
+ */
+#define PLAT_ARM_MAX_BL2_SIZE		(NRD_CSS_BL2_SIZE +		\
+						((NRD_CHIP_COUNT - 1) * 0x2000))
+
+#define PLAT_ARM_MAX_BL31_SIZE		(NRD_CSS_BL31_SIZE +		\
+						PLAT_ARM_MAX_BL2_SIZE +	\
+						PLAT_ARM_MAX_BL1_RW_SIZE)
+
+/*******************************************************************************
+ * Stack sizes
+ ******************************************************************************/
+
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
+# else
+#  define PLATFORM_STACK_SIZE		UL(0x440)
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
+# else
+#  define PLATFORM_STACK_SIZE		UL(0x400)
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE		UL(0x400)
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+#  define PLATFORM_STACK_SIZE		UL(0x500)
+# else
+#  define PLATFORM_STACK_SIZE		UL(0x400)
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE		UL(0x440)
+#endif
+
+#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) &&			\
+ENABLE_FEAT_RAS && FFH_SUPPORT
+/*
+ * Secure partition stack follows right after the memory space reserved for
+ * CPER buffer memory.
+ */
+#define PLAT_ARM_SP_IMAGE_STACK_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +   \
+					 PLAT_SP_IMAGE_NS_BUF_SIZE +   \
+					 NRD_CSS_SP_CPER_BUF_SIZE)
+#elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
+/*
+ * Secure partition stack follows right after the memory region that is shared
+ * between EL3 and S-EL0.
+ */
+#define PLAT_ARM_SP_IMAGE_STACK_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +	\
+					 PLAT_SP_IMAGE_NS_BUF_SIZE)
+#endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define PLAT_ARM_BOOT_UART_BASE		NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE		NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE	NRD_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * SCMI config
+ ******************************************************************************/
+
+/* Number of SCMI channels on the platform */
+#define PLAT_ARM_SCMI_CHANNEL_COUNT	NRD_CHIP_COUNT
+
+/*******************************************************************************
+ * ROM, SRAM and DRAM config
+ ******************************************************************************/
+
+#define PLAT_ARM_TRUSTED_ROM_BASE	NRD_CSS_SECURE_ROM_BASE
+#define PLAT_ARM_TRUSTED_ROM_SIZE	NRD_CSS_SECURE_ROM_SIZE
+
+#define PLAT_ARM_DRAM2_BASE		NRD_CSS_DRAM2_BASE
+#define PLAT_ARM_DRAM2_SIZE		NRD_CSS_DRAM2_SIZE
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	NRD_CSS_SECURE_SRAM_SIZE
+
+#define PLAT_ARM_NSTIMER_FRAME_ID	0
+
+#define PLAT_ARM_NSRAM_BASE		NRD_CSS_NS_SRAM_BASE
+#define PLAT_ARM_NSRAM_SIZE		NRD_CSS_NS_SRAM_SIZE
+/*
+ * Required platform porting definitions common to all ARM CSS SoCs
+ */
+/* 2MB used for SCP DDR retraining */
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x00200000)
+
+/*******************************************************************************
+ * GIC/EHF config
+ ******************************************************************************/
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE		NRD_CSS_GIC_BASE
+
+#if (NRD_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE		NRD_CSS_GIC_BASE + UL(0x00100000)
+#elif (NRD_PLATFORM_VARIANT == 3)
+#define PLAT_ARM_GICR_BASE		NRD_CSS_GIC_BASE + UL(0x00300000)
+#else
+#define PLAT_ARM_GICR_BASE		NRD_CSS_GIC_BASE + UL(0x001C0000)
+#endif
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp)	CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
+
+#if ENABLE_FEAT_RAS && FFH_SUPPORT
+#define PLAT_SP_PRI			PLAT_RAS_PRI
+#else
+#define PLAT_SP_PRI			(0x10)
+#endif
+
+/* Interrupt priority level for shutdown/reboot */
+#define PLAT_REBOOT_PRI		GIC_HIGHEST_SEC_PRIORITY
+#define PLAT_EHF_DESC		EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
+
+/*******************************************************************************
+ * Secure world config
+ ******************************************************************************/
+
+#define SECURE_PARTITION_COUNT		1
+#define NS_PARTITION_COUNT		1
+#define MAX_EL3_LP_DESCS_COUNT		1
+
+/*******************************************************************************
+ * MHU config
+ ******************************************************************************/
+
+#define PLAT_CSS_MHU_BASE		NRD_CSS_AP_SCP_S_MHU_BASE
+#define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
+
+/*******************************************************************************
+ * Power config
+ ******************************************************************************/
+
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
+
+/*******************************************************************************
+ * TZ config
+ ******************************************************************************/
+
+#define PLAT_ARM_TZC_BASE		NRD_ROS_MEMCNTRL_BASE + UL(0x00720000)
+#define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
+
+/*******************************************************************************
+ * SDS config
+ ******************************************************************************/
+
+/* SDS ID for unusable CPU MPID list structure */
+#define SDS_ISOLATED_CPU_LIST_ID	U(128)
+
+/* Index of SDS region used in the communication with SCP */
+#define SDS_SCP_AP_REGION_ID		U(0)
+
+/*******************************************************************************
+ * Flash config
+ ******************************************************************************/
+
+#define MAX_IO_DEVICES			U(3)
+#define MAX_IO_HANDLES			U(4)
+
+#define V2M_SYS_LED			U(0x8)
+
+#define V2M_SYS_LED_SS_SHIFT		U(0)
+#define V2M_SYS_LED_EL_SHIFT		U(1)
+#define V2M_SYS_LED_EC_SHIFT		U(3)
+
+#define V2M_SYS_LED_SS_MASK		U(0x01)
+#define V2M_SYS_LED_EL_MASK		U(0x03)
+#define V2M_SYS_LED_EC_MASK		U(0x1f)
+
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xC0000000)
+
+#define V2M_SYSREGS_BASE		NRD_ROS_SYSTEM_PERIPH_BASE +	\
+						UL(0x00010000)
+#define V2M_FLASH0_BASE			NRD_ROS_SMC0_BASE
+#define V2M_FLASH0_SIZE			NRD_ROS_SMC0_SIZE
+#define V2M_FLASH_BLOCK_SIZE		UL(0x00040000)	/* 256 KB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE +	\
+					V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*******************************************************************************
+ * Platform type identification macro
+ ******************************************************************************/
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK		U(0x0F)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		U(0x00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK	U(0xF00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT	U(0x08)
+#define BOARD_CSS_PLAT_TYPE_RTL			U(0x00)
+#define BOARD_CSS_PLAT_TYPE_FPGA		U(0x01)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR		U(0x02)
+#define BOARD_CSS_PLAT_TYPE_FVP			U(0x03)
+
+#ifndef __ASSEMBLER__
+#define BOARD_CSS_GET_PLAT_TYPE(addr)					\
+	((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK)		\
+	>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+#endif /* __ASSEMBLER__ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR	NRD_ROS_PLATFORM_PERIPH_BASE +	\
+						UL(0x00FE00E0)
+
+/*******************************************************************************
+ * ROS peripheral config
+ ******************************************************************************/
+
+/* Non-volatile counters */
+#define SOC_TRUSTED_NVCTR_BASE		NRD_ROS_PLATFORM_PERIPH_BASE +	\
+						UL(0x00E70000)
+#define TFW_NVCTR_BASE			(SOC_TRUSTED_NVCTR_BASE	+ 0x0000)
+#define TFW_NVCTR_SIZE			U(4)
+#define NTFW_CTR_BASE			(SOC_TRUSTED_NVCTR_BASE + 0x0004)
+#define NTFW_CTR_SIZE			U(4)
+
+/*******************************************************************************
+ * MMU config
+ ******************************************************************************/
+
+#define V2M_MAP_FLASH0_RW						\
+		MAP_REGION_FLAT(					\
+			V2M_FLASH0_BASE,				\
+			V2M_FLASH0_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#define V2M_MAP_FLASH0_RO						\
+		MAP_REGION_FLAT(					\
+			V2M_FLASH0_BASE,				\
+			V2M_FLASH0_SIZE,				\
+			MT_RO_DATA | MT_SECURE)
+
+#endif /* NRD_PLAT_ARM_DEF2_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h
new file mode 100644
index 0000000..3558cfc
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the RoS specific definitions for the second generation
+ * platforms based on the N2/V2 CPU.
+ */
+
+#ifndef NRD_ROS_DEF2_H
+#define NRD_ROS_DEF2_H
+
+/*******************************************************************************
+ * SoC memory map related defines
+ ******************************************************************************/
+
+/* System Reg */
+#define NRD_ROS_SYSTEMREG_BASE			UL(0x0C010000)
+#define NRD_ROS_SYSTEMREG_SIZE			UL(0x00010000)
+
+/* NOR flash 2 */
+#define NRD_ROS_NOR2_FLASH_BASE			ULL(0x001054000000)
+#define NRD_ROS_NOR2_FLASH_SIZE			UL(0x000004000000)
+
+/* Memory controller */
+#define NRD_ROS_MEMCNTRL_BASE			UL(0x10000000)
+#define NRD_ROS_MEMCNTRL_SIZE			UL(0x10000000)
+
+/* System peripherals */
+#define NRD_ROS_SYSTEM_PERIPH_BASE		UL(0x0C000000)
+#define NRD_ROS_SYSTEM_PERIPH_SIZE		UL(0x02000000)
+
+/* Platform peripherals */
+#define NRD_ROS_PLATFORM_PERIPH_BASE		UL(0x0E000000)
+#define NRD_ROS_PLATFORM_PERIPH_SIZE		UL(0x02000000)
+
+/* SMC0 */
+#define NRD_ROS_SMC0_BASE			UL(0x08000000)
+#define NRD_ROS_SMC0_SIZE			UL(0x04000000)
+
+#endif /* NRD_ROS_DEF2_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h
new file mode 100644
index 0000000..6091672
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS firmware specific definitions for the
+ * second generation platforms based on the N2/V2 CPUs. RoS (Rest Of System) is
+ * used to refer to the part of the reference design platform that excludes CSS.
+ */
+
+#ifndef NRD_ROS_FW_DEF2_H
+#define NRD_ROS_FW_DEF2_H
+
+#include <nrd_ros_def2.h>
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_ROS_PLATFORM_PERIPH_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_PLATFORM_PERIPH_BASE,			\
+			NRD_ROS_PLATFORM_PERIPH_SIZE,			\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#if SPM_MM
+
+#define NRD_ROS_PLATFORM_PERIPH_USER_MMAP				\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_PLATFORM_PERIPH_BASE,			\
+			NRD_ROS_PLATFORM_PERIPH_SIZE,			\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
+#define NRD_ROS_SYSTEM_PERIPH_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_SYSTEM_PERIPH_BASE,			\
+			NRD_ROS_SYSTEM_PERIPH_SIZE,			\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_MEMCNTRL_MMAP(n)					\
+		MAP_REGION_FLAT(					\
+			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
+			NRD_ROS_MEMCNTRL_BASE,				\
+			NRD_ROS_MEMCNTRL_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP				\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_SYSTEMREG_BASE,				\
+			NRD_ROS_SYSTEMREG_SIZE,				\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define NRD_ROS_SECURE_NOR2_USER_MMAP					\
+		MAP_REGION_FLAT(					\
+			NRD_ROS_NOR2_FLASH_BASE,			\
+			NRD_ROS_NOR2_FLASH_SIZE,			\
+			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+
+#define NRD_ROS_FLASH0_RO_MMAP						\
+		MAP_REGION_FLAT(					\
+			V2M_FLASH0_BASE,				\
+			V2M_FLASH0_SIZE,				\
+			MT_DEVICE | MT_RO | MT_SECURE)
+
+/*******************************************************************************
+ * TZ config
+ ******************************************************************************/
+
+/*
+ * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
+ * where both the DRAM regions are marked for non-secure access. This applies
+ * to multi-chip platforms.
+ */
+#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n)				\
+	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE,		\
+		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END,		\
+		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},	\
+	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE,		\
+		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END,		\
+		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
+
+#endif /* NRD_ROS_FW_DEF2_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h b/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h
deleted file mode 100644
index 89fa924..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h
+++ /dev/null

@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_BASE_PLATFORM_DEF_H
-#define NRD_BASE_PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/common/arm_def.h>
-#include <plat/arm/common/arm_spm_def.h>
-#include <plat/arm/css/common/css_def.h>
-#include <plat/common/common_def.h>
-
-#define PLATFORM_CORE_COUNT		(NRD_CHIP_COUNT *		\
-					PLAT_ARM_CLUSTER_COUNT *	\
-					NRD_MAX_CPUS_PER_CLUSTER *	\
-					NRD_MAX_PE_PER_CPU)
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00080000	/* 512 KB */
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
-		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-/*
- * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
- * plat_arm_mmap array defined for each BL stage. In addition to that, on
- * multi-chip platforms, address regions on each of the remote chips are
- * also mapped. In BL31, for instance, three address regions on the remote
- * chips are accessed - secure ram, css device and soc device regions.
- */
-#if defined(IMAGE_BL31)
-# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
-#  define PLAT_ARM_MMAP_ENTRIES		(10  + ((NRD_CHIP_COUNT - 1) * 3))
-#  define MAX_XLAT_TABLES		(8  + ((NRD_CHIP_COUNT - 1) * 3))
-#  define PLAT_SP_IMAGE_MMAP_REGIONS	12
-#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	14
-# else
-#  define PLAT_ARM_MMAP_ENTRIES		(5 + ((NRD_CHIP_COUNT - 1) * 3))
-#  define MAX_XLAT_TABLES		(6 + ((NRD_CHIP_COUNT - 1) * 3))
-# endif
-#elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES		8
-# define MAX_XLAT_TABLES		5
-#elif defined(IMAGE_BL2)
-# define PLAT_ARM_MMAP_ENTRIES		(11 + (NRD_CHIP_COUNT - 1))
-
-/*
- * MAX_XLAT_TABLES entries need to be doubled because when the address width
- * exceeds 40 bits an additional level of translation is required. In case of
- * multichip platforms peripherals also fall into address space with width
- * > 40 bits
- *
- */
-# define MAX_XLAT_TABLES		(7  + ((NRD_CHIP_COUNT - 1) * 2))
-#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES		11
-# define MAX_XLAT_TABLES		7
-#else
-# define PLAT_ARM_MMAP_ENTRIES		12
-# define MAX_XLAT_TABLES		6
-#endif
-
-/*
- * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
- * plus a little space for growth.
- */
-#define PLAT_ARM_MAX_BL1_RW_SIZE	(64 * 1024)	/* 64 KB */
-
-/*
- * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
- */
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0xe000
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
-#endif
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth. Additional 8KiB space is added per chip in
- * order to accommodate the additional level of translation required for "TZC"
- * peripheral access which lies in >4TB address space.
- *
- */
-#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE		(0x20000 + ((NRD_CHIP_COUNT - 1) * \
-							0x2000))
-#else
-# define PLAT_ARM_MAX_BL2_SIZE		(0x14000 + ((NRD_CHIP_COUNT - 1) * \
-							0x2000))
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
- * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31
- * PROGBITS size which is around 64-68KB at the time this change is being made.
- * A buffer of ~35KB is added to account for future expansion of the image,
- * making it a total of 100KB.
- */
-#define NRD_BL31_SIZE			(116 * 1024)	/* 116 KB */
-#define PLAT_ARM_MAX_BL31_SIZE		(NRD_BL31_SIZE +		\
-						PLAT_ARM_MAX_BL2_SIZE +	\
-						PLAT_ARM_MAX_BL1_RW_SIZE)
-
-/*
- * Size of cacheable stacks
- */
-#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
-# else
-#  define PLATFORM_STACK_SIZE 0x440
-# endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
-# else
-#  define PLATFORM_STACK_SIZE 0x400
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
-#elif defined(IMAGE_BL31)
-# if SPM_MM
-#  define PLATFORM_STACK_SIZE 0x500
-# else
-#  define PLATFORM_STACK_SIZE 0x400
-# endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
-#endif
-
-/* PL011 UART related constants */
-#define SOC_CSS_SEC_UART_BASE			UL(0x2A410000)
-#define SOC_CSS_NSEC_UART_BASE			UL(0x2A400000)
-#define SOC_CSS_UART_SIZE			UL(0x10000)
-#define SOC_CSS_UART_CLK_IN_HZ			UL(7372800)
-
-/* UART related constants */
-#define PLAT_ARM_BOOT_UART_BASE			SOC_CSS_SEC_UART_BASE
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ		SOC_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_RUN_UART_BASE			SOC_CSS_SEC_UART_BASE
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ		SOC_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_CRASH_UART_BASE		SOC_CSS_SEC_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ		SOC_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_NSTIMER_FRAME_ID	0
-
-#define PLAT_ARM_TRUSTED_ROM_BASE	0x0
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00080000	/* 512KB */
-
-#define PLAT_ARM_NSRAM_BASE		0x06000000
-#define PLAT_ARM_NSRAM_SIZE		0x00080000	/* 512KB */
-
-#define PLAT_ARM_DRAM2_BASE		ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE		ULL(0x180000000)
-
-#define PLAT_ARM_G1S_IRQ_PROPS(grp)	CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
-
-#define NRD_DEVICE_BASE	(0x20000000)
-#define NRD_DEVICE_SIZE	(0x20000000)
-#define NRD_MAP_DEVICE	MAP_REGION_FLAT(		\
-					NRD_DEVICE_BASE,	\
-					NRD_DEVICE_SIZE,	\
-					MT_DEVICE | MT_RW | MT_SECURE)
-
-#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n)					\
-			MAP_REGION_FLAT(					\
-				NRD_REMOTE_CHIP_MEM_OFFSET(n) +		\
-				ARM_SHARED_RAM_BASE,				\
-				ARM_SHARED_RAM_SIZE,				\
-				MT_NON_CACHEABLE | MT_RW | MT_SECURE		\
-			)
-
-#define NRD_MAP_DEVICE_REMOTE_CHIP(n)					\
-			MAP_REGION_FLAT(					\
-				NRD_REMOTE_CHIP_MEM_OFFSET(n) +		\
-				NRD_DEVICE_BASE,				\
-				NRD_DEVICE_SIZE,				\
-				MT_DEVICE | MT_RW | MT_SECURE			\
-			)
-
-#define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n)					\
-			MAP_REGION_FLAT(					\
-				NRD_REMOTE_CHIP_MEM_OFFSET(n) +		\
-				SOC_CSS_DEVICE_BASE,				\
-				SOC_CSS_DEVICE_SIZE,				\
-				MT_DEVICE | MT_RW | MT_SECURE			\
-			)
-
-/* Map the secure region for access from S-EL0 */
-#define PLAT_ARM_SECURE_MAP_DEVICE	MAP_REGION_FLAT(	\
-					SOC_CSS_DEVICE_BASE,	\
-					SOC_CSS_DEVICE_SIZE,	\
-					MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#if ENABLE_FEAT_RAS && FFH_SUPPORT
-#define PLAT_SP_PRI				PLAT_RAS_PRI
-#else
-#define PLAT_SP_PRI				0x10
-#endif
-
-#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && ENABLE_FEAT_RAS && FFH_SUPPORT
-/*
- * CPER buffer memory of 128KB is reserved and it is placed adjacent to the
- * memory shared between EL3 and S-EL0.
- */
-#define NRD_SP_CPER_BUF_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE + \
-					 PLAT_SP_IMAGE_NS_BUF_SIZE)
-#define NRD_SP_CPER_BUF_SIZE	ULL(0x10000)
-#define NRD_SP_CPER_BUF_MMAP	MAP_REGION2(			       \
-						NRD_SP_CPER_BUF_BASE,      \
-						NRD_SP_CPER_BUF_BASE,      \
-						NRD_SP_CPER_BUF_SIZE,      \
-						MT_RW_DATA | MT_NS | MT_USER,  \
-						PAGE_SIZE)
-
-/*
- * Secure partition stack follows right after the memory space reserved for
- * CPER buffer memory.
- */
-#define PLAT_ARM_SP_IMAGE_STACK_BASE		(PLAT_SP_IMAGE_NS_BUF_BASE +   \
-						 PLAT_SP_IMAGE_NS_BUF_SIZE +   \
-						 NRD_SP_CPER_BUF_SIZE)
-#elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
-/*
- * Secure partition stack follows right after the memory region that is shared
- * between EL3 and S-EL0.
- */
-#define PLAT_ARM_SP_IMAGE_STACK_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +	\
-					 PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */
-
-/* Platform ID address */
-#define SSC_VERSION                     (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLER__
-/* SSC_VERSION related accessors */
-/* Returns the part number of the platform */
-#define GET_NRD_PART_NUM                                       \
-		GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
-/* Returns the configuration number of the platform */
-#define GET_NRD_CONFIG_NUM                                     \
-		GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLER__ */
-
-/*******************************************************************************
- * Memprotect definitions
- ******************************************************************************/
-/* PSCI memory protect definitions:
- * This variable is stored in a non-secure flash because some ARM reference
- * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
- * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
- */
-#define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
-					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-/*Secure Watchdog Constants */
-#define SBSA_SECURE_WDOG_BASE		UL(0x2A480000)
-#define SBSA_SECURE_WDOG_TIMEOUT	UL(100)
-
-/* Number of SCMI channels on the platform */
-#define PLAT_ARM_SCMI_CHANNEL_COUNT	NRD_CHIP_COUNT
-
-/*
- * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
- * where both the DRAM regions are marked for non-secure access. This applies
- * to multi-chip platforms.
- */
-#define NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n)				\
-	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE,		\
-		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END,	\
-		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},	\
-	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE,		\
-		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END,	\
-		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-
-#if SPM_MM
-
-/*
- * Stand-alone MM logs would be routed via secure UART. Define page table
- * entry for secure UART which would be common to all platforms.
- */
-#define SOC_PLATFORM_SECURE_UART	MAP_REGION_FLAT(		\
-					SOC_CSS_SEC_UART_BASE,		\
-					SOC_CSS_UART_SIZE,		\
-					MT_DEVICE | MT_RW | 		\
-					MT_SECURE | MT_USER)
-
-#endif
-
-/* Index of SDS region used in the communication with SCP */
-#define SDS_SCP_AP_REGION_ID			U(0)
-/* SDS ID for unusable CPU MPID list structure */
-#define SDS_ISOLATED_CPU_LIST_ID		U(128)
-
-#endif /* NRD_BASE_PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def.h
deleted file mode 100644
index 7c1f5ae..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def.h
+++ /dev/null

@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_CSS_DEF_H
-#define NRD_SOC_CSS_DEF_H
-
-#include <lib/utils_def.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-#include <plat/common/common_def.h>
-
-/*
- * Definitions common to all ARM CSSv1-based development platforms
- */
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR		UL(0x7ffe00e0)
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK		0x0f
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		0x0
-#define BOARD_CSS_PLAT_TYPE_EMULATOR		0x02
-
-#ifndef __ASSEMBLER__
-
-#include <lib/mmio.h>
-
-#define BOARD_CSS_GET_PLAT_TYPE(addr)					\
-	((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK)		\
-	>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-
-#endif /* __ASSEMBLER__ */
-
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
-
-/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#endif /* NRD_SOC_CSS_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h
deleted file mode 100644
index 33f9b4b..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_css_def_v2.h
+++ /dev/null

@@ -1,207 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_CSS_DEF_V2_H
-#define NRD_SOC_CSS_DEF_V2_H
-
-#include <lib/utils_def.h>
-#include <plat/common/common_def.h>
-
-/*
- * Definitions common to all ARM CSS SoCs
- */
-
-/* Following covers ARM CSS SoC Peripherals */
-
-#define SOC_SYSTEM_PERIPH_BASE		UL(0x0C000000)
-#define SOC_SYSTEM_PERIPH_SIZE		UL(0x02000000)
-
-#define SOC_PLATFORM_PERIPH_BASE	UL(0x0E000000)
-#define SOC_PLATFORM_PERIPH_SIZE	UL(0x02000000)
-
-#define SOC_CSS_PCIE_CONTROL_BASE	UL(0x0ef20000)
-
-/* Memory controller */
-#define SOC_MEMCNTRL_BASE		UL(0x10000000)
-#define SOC_MEMCNTRL_SIZE		UL(0x10000000)
-
-/* SoC NIC-400 Global Programmers View (GPV) */
-#define SOC_CSS_NIC400_BASE		UL(0x0ED00000)
-
-#define SOC_CSS_NIC400_USB_EHCI		U(0)
-#define SOC_CSS_NIC400_TLX_MASTER	U(1)
-#define SOC_CSS_NIC400_USB_OHCI		U(2)
-#define SOC_CSS_NIC400_PL354_SMC	U(3)
-/*
- * The apb4_bridge controls access to:
- *   - the PCIe configuration registers
- *   - the MMU units for USB, HDLCD and DMA
- */
-#define SOC_CSS_NIC400_APB4_BRIDGE	U(4)
-
-/* Non-volatile counters */
-#define SOC_TRUSTED_NVCTR_BASE		UL(0x0EE70000)
-#define TFW_NVCTR_BASE			(SOC_TRUSTED_NVCTR_BASE + 0x0000)
-#define TFW_NVCTR_SIZE			U(4)
-#define NTFW_CTR_BASE			(SOC_TRUSTED_NVCTR_BASE + 0x0004)
-#define NTFW_CTR_SIZE			U(4)
-
-/* Keys */
-#define SOC_KEYS_BASE			UL(0x0EE80000)
-#define TZ_PUB_KEY_HASH_BASE		(SOC_KEYS_BASE + 0x0000)
-#define TZ_PUB_KEY_HASH_SIZE		U(32)
-#define HU_KEY_BASE			(SOC_KEYS_BASE + 0x0020)
-#define HU_KEY_SIZE			U(16)
-#define END_KEY_BASE			(SOC_KEYS_BASE + 0x0044)
-#define END_KEY_SIZE			U(32)
-
-/* Base Element RAM error definitions */
-#define SOC_NS_RAM_ERR_REC_BASE		UL(0x2A4C0000)
-#define NS_RAM_ECC_CE_INT		U(87)
-#define NS_RAM_ECC_UE_INT		U(88)
-
-#define SOC_PLATFORM_PERIPH_MAP_DEVICE	MAP_REGION_FLAT(			\
-						SOC_PLATFORM_PERIPH_BASE, 	\
-						SOC_PLATFORM_PERIPH_SIZE, 	\
-						MT_DEVICE | MT_RW | MT_SECURE)
-
-#if SPM_MM
-/*
- * Memory map definition for the platform peripheral memory region that is
- * accessible from S-EL0 (with secure user mode access).
- */
-#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER				       \
-		MAP_REGION_FLAT(					       \
-			SOC_PLATFORM_PERIPH_BASE,			       \
-			SOC_PLATFORM_PERIPH_SIZE,			       \
-			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-#endif
-
-#define SOC_SYSTEM_PERIPH_MAP_DEVICE	MAP_REGION_FLAT(			\
-						SOC_SYSTEM_PERIPH_BASE,		\
-						SOC_SYSTEM_PERIPH_SIZE,		\
-						MT_DEVICE | MT_RW | MT_SECURE)
-
-#define SOC_MEMCNTRL_MAP_DEVICE		MAP_REGION_FLAT(			\
-						SOC_MEMCNTRL_BASE,		\
-						SOC_MEMCNTRL_SIZE,		\
-						MT_DEVICE | MT_RW | MT_SECURE)
-
-#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n)					\
-		MAP_REGION_FLAT(						\
-			NRD_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE,	\
-			SOC_MEMCNTRL_SIZE,					\
-			MT_DEVICE | MT_RW | MT_SECURE)
-
-/*
- * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
- */
-#define SOC_CSS_NIC400_BOOTSEC_BRIDGE		U(5)
-#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1	UL(1 << 12)
-
-/*
- * Required platform porting definitions common to all ARM CSS SoCs
- */
-/* 2MB used for SCP DDR retraining */
-#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x00200000)
-
-/* V2M motherboard system registers & offsets */
-#define V2M_SYSREGS_BASE		UL(0x0C010000)
-#define V2M_SYS_LED			U(0x8)
-
-/*
- * V2M sysled bit definitions. The values written to this
- * register are defined in arch.h & runtime_svc.h. Only
- * used by the primary cpu to diagnose any cold boot issues.
- *
- * SYS_LED[0]   - Security state (S=0/NS=1)
- * SYS_LED[2:1] - Exception Level (EL3-EL0)
- * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
- *
- */
-#define V2M_SYS_LED_SS_SHIFT		U(0)
-#define V2M_SYS_LED_EL_SHIFT		U(1)
-#define V2M_SYS_LED_EC_SHIFT		U(3)
-
-#define V2M_SYS_LED_SS_MASK		U(0x01)
-#define V2M_SYS_LED_EL_MASK		U(0x03)
-#define V2M_SYS_LED_EC_MASK		U(0x1f)
-
-/* NOR Flash */
-#define V2M_FLASH0_BASE			UL(0x08000000)
-#define V2M_FLASH0_SIZE			UL(0x04000000)
-#define V2M_FLASH_BLOCK_SIZE		UL(0x00040000)	/* 256 KB */
-
-/*
- * The flash can be mapped either as read-only or read-write.
- *
- * If it is read-write then it should also be mapped as device memory because
- * NOR flash programming involves sending a fixed, ordered sequence of commands.
- *
- * If it is read-only then it should also be mapped as:
- * - Normal memory, because reading from NOR flash is transparent, it is like
- *   reading from RAM.
- * - Non-executable by default. If some parts of the flash need to be executable
- *   then platform code is responsible for re-mapping the appropriate portion
- *   of it as executable.
- */
-#define V2M_MAP_FLASH0_RW		MAP_REGION_FLAT(V2M_FLASH0_BASE,\
-						V2M_FLASH0_SIZE,	\
-						MT_DEVICE | MT_RW | MT_SECURE)
-
-#define V2M_MAP_FLASH0_RO		MAP_REGION_FLAT(V2M_FLASH0_BASE,\
-						V2M_FLASH0_SIZE,	\
-						MT_RO_DATA | MT_SECURE)
-
-#define NRD_MAP_FLASH0_RO		MAP_REGION_FLAT(V2M_FLASH0_BASE,\
-						V2M_FLASH0_SIZE,	\
-						MT_DEVICE | MT_RO | MT_SECURE)
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR		UL(0x0EFE00E0)
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK		U(0x0F)
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		U(0x00)
-#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK	U(0xF00)
-#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT	U(0x08)
-#define BOARD_CSS_PLAT_TYPE_RTL			U(0x00)
-#define BOARD_CSS_PLAT_TYPE_FPGA		U(0x01)
-#define BOARD_CSS_PLAT_TYPE_EMULATOR		U(0x02)
-#define BOARD_CSS_PLAT_TYPE_FVP			U(0x03)
-
-#ifndef __ASSEMBLER__
-
-#include <lib/mmio.h>
-
-#define BOARD_CSS_GET_PLAT_TYPE(addr)					\
-	((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK)		\
-	>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-
-#endif /* __ASSEMBLER__ */
-
-
-#define MAX_IO_DEVICES			U(3)
-#define MAX_IO_HANDLES			U(4)
-
-/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#if ARM_GPT_SUPPORT
-/*
- * Offset of the FIP in the GPT image. BL1 component uses this option
- * as it does not load the partition table to get the FIP base
- * address. At sector 34 by default (i.e. after reserved sectors 0-33)
- * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
- */
-#define PLAT_ARM_FIP_OFFSET_IN_GPT		0x4400
-#endif /* ARM_GPT_SUPPORT */
-
-#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#endif /* NRD_SOC_CSS_DEF_V2_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def.h
deleted file mode 100644
index 0024e49..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def.h
+++ /dev/null

@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_PLATFORM_DEF_H
-#define NRD_SOC_PLATFORM_DEF_H
-
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-
-#include <nrd_base_platform_def.h>
-#include <nrd_soc_css_def.h>
-
-/* Map the System registers to access from S-EL0 */
-#define CSS_SYSTEMREG_DEVICE_BASE	(0x1C010000)
-#define CSS_SYSTEMREG_DEVICE_SIZE	(0x00010000)
-#define PLAT_ARM_SECURE_MAP_SYSTEMREG	MAP_REGION_FLAT(		    \
-						CSS_SYSTEMREG_DEVICE_BASE,  \
-						CSS_SYSTEMREG_DEVICE_SIZE,  \
-						(MT_DEVICE | MT_RW |	    \
-						 MT_SECURE | MT_USER))
-
-/* Map the NOR2 Flash to access from S-EL0 */
-#define CSS_NOR2_FLASH_DEVICE_BASE	(0x10000000)
-#define CSS_NOR2_FLASH_DEVICE_SIZE	(0x04000000)
-#define PLAT_ARM_SECURE_MAP_NOR2	MAP_REGION_FLAT(                    \
-						CSS_NOR2_FLASH_DEVICE_BASE, \
-						CSS_NOR2_FLASH_DEVICE_SIZE, \
-						(MT_DEVICE | MT_RW |	    \
-						 MT_SECURE | MT_USER))
-
-#endif /* NRD_SOC_PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def_v2.h b/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def_v2.h
deleted file mode 100644
index 2e6f354..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd_soc_platform_def_v2.h
+++ /dev/null

@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NRD_SOC_PLATFORM_DEF_V2_H
-#define NRD_SOC_PLATFORM_DEF_V2_H
-
-#include <nrd_base_platform_def.h>
-#include <nrd_soc_css_def_v2.h>
-
-/* Map the System registers to access from S-EL0 */
-#define CSS_SYSTEMREG_DEVICE_BASE	(0x0C010000)
-#define CSS_SYSTEMREG_DEVICE_SIZE	(0x00010000)
-#define PLAT_ARM_SECURE_MAP_SYSTEMREG	MAP_REGION_FLAT(                    \
-						CSS_SYSTEMREG_DEVICE_BASE,  \
-						CSS_SYSTEMREG_DEVICE_SIZE,  \
-						(MT_DEVICE | MT_RW |	    \
-						 MT_SECURE | MT_USER))
-
-/* Map the NOR2 Flash to access from S-EL0 */
-#define CSS_NOR2_FLASH_DEVICE_BASE	(0x001054000000)
-#define CSS_NOR2_FLASH_DEVICE_SIZE	(0x000004000000)
-#define PLAT_ARM_SECURE_MAP_NOR2	MAP_REGION_FLAT(                    \
-						CSS_NOR2_FLASH_DEVICE_BASE, \
-						CSS_NOR2_FLASH_DEVICE_SIZE, \
-						(MT_DEVICE | MT_RW |	    \
-						 MT_SECURE | MT_USER))
-
-#endif /* NRD_SOC_PLATFORM_DEF_V2_H */

diff --git a/plat/arm/board/neoverse_rd/common/nrd-common.mk b/plat/arm/board/neoverse_rd/common/nrd-common.mk
index 96e6f01..95a221f 100644
--- a/plat/arm/board/neoverse_rd/common/nrd-common.mk
+++ b/plat/arm/board/neoverse_rd/common/nrd-common.mk

@@ -42,6 +42,7 @@
 PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/arch/aarch64/nrd_helper.S
 
 BL1_SOURCES		+=	${INTERCONNECT_SOURCES}			\
+				${NRD_COMMON_BASE}/nrd_bl1_setup.c	\
 				drivers/arm/sbsa/sbsa.c
 
 BL2_SOURCES		+=	${NRD_COMMON_BASE}/nrd_image_load.c	\
@@ -77,5 +78,4 @@
 
 include plat/arm/common/arm_common.mk
 include plat/arm/css/common/css_common.mk
-include plat/arm/soc/common/soc_css.mk
 include plat/arm/board/common/board_common.mk

diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl1_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl1_setup.c
new file mode 100644
index 0000000..a0f656f
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl1_setup.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/soc/common/soc_css.h>
+
+/*******************************************************************************
+ * Perform any BL1 specific platform actions.
+ ******************************************************************************/
+
+void soc_css_init_nic400(void)
+{
+}
+
+void soc_css_init_pcie(void)
+{
+}

diff --git a/plat/arm/board/neoverse_rd/common/nrd_image_load.c b/plat/arm/board/neoverse_rd/common/nrd_image_load.c
index 39de0ab..15d90be 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_image_load.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_image_load.c

@@ -14,7 +14,6 @@
 #include <plat/common/platform.h>
 #include <platform_def.h>
 
-#include <nrd_base_platform_def.h>
 #include <nrd_variant.h>
 
 /*

diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat.c b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
similarity index 85%
rename from plat/arm/board/neoverse_rd/common/nrd_plat.c
rename to plat/arm/board/neoverse_rd/common/nrd_plat1.c
index 0c59271..32444f4 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat1.c

@@ -17,15 +17,10 @@
 #include <plat/common/platform.h>
 #include <drivers/arm/sbsa.h>
 
-#include <nrd_base_platform_def.h>
-
 #if SPM_MM
 #include <services/spm_mm_partition.h>
 #endif
 
-#define NRD_MAP_FLASH0_RO	MAP_REGION_FLAT(V2M_FLASH0_BASE,\
-						V2M_FLASH0_SIZE,	\
-						MT_DEVICE | MT_RO | MT_SECURE)
 /*
  * Table of regions for different BL stages to map using the MMU.
  * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
@@ -37,8 +32,8 @@
 const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
 	NRD_MAP_FLASH0_RO,
-	NRD_MAP_DEVICE,
-	SOC_CSS_MAP_DEVICE,
+	NRD_CSS_PERIPH_MMAP(0),
+	NRD_ROS_PERIPH_MMAP(0),
 	{0}
 };
 #endif
@@ -49,17 +44,17 @@
 #ifdef PLAT_ARM_MEM_PROT_ADDR
 	ARM_V2M_MAP_MEM_PROTECT,
 #endif
-	NRD_MAP_DEVICE,
-	SOC_CSS_MAP_DEVICE,
+	NRD_CSS_PERIPH_MMAP(0),
+	NRD_ROS_PERIPH_MMAP(0),
 	ARM_MAP_NS_DRAM1,
 #if NRD_CHIP_COUNT > 1
-	NRD_MAP_DEVICE_REMOTE_CHIP(1),
+	NRD_CSS_PERIPH_MMAP(1),
 #endif
 #if NRD_CHIP_COUNT > 2
-	NRD_MAP_DEVICE_REMOTE_CHIP(2),
+	NRD_CSS_PERIPH_MMAP(2),
 #endif
 #if NRD_CHIP_COUNT > 3
-	NRD_MAP_DEVICE_REMOTE_CHIP(3),
+	NRD_CSS_PERIPH_MMAP(3),
 #endif
 #if ARM_BL31_IN_DRAM
 	ARM_MAP_BL31_SEC_DRAM,
@@ -77,11 +72,11 @@
 const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
 	V2M_MAP_IOFPGA,
-	NRD_MAP_DEVICE,
+	NRD_CSS_PERIPH_MMAP(0),
 #ifdef PLAT_ARM_MEM_PROT_ADDR
 	ARM_V2M_MAP_MEM_PROTECT,
 #endif
-	SOC_CSS_MAP_DEVICE,
+	NRD_ROS_PERIPH_MMAP(0),
 #if SPM_MM
 	ARM_SPM_BUF_EL3_MMAP,
 #endif
@@ -90,15 +85,11 @@
 
 #if SPM_MM && defined(IMAGE_BL31)
 const mmap_region_t plat_arm_secure_partition_mmap[] = {
-	PLAT_ARM_SECURE_MAP_SYSTEMREG,
-	PLAT_ARM_SECURE_MAP_NOR2,
-	SOC_PLATFORM_SECURE_UART,
-	PLAT_ARM_SECURE_MAP_DEVICE,
+	NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
+	NRD_ROS_SECURE_NOR2_USER_MMAP,
+	NRD_CSS_SECURE_UART_MMAP,
 	ARM_SP_IMAGE_MMAP,
 	ARM_SP_IMAGE_NS_BUF_MMAP,
-#if ENABLE_FEAT_RAS && FFH_SUPPORT
-	NRD_SP_CPER_BUF_MMAP,
-#endif
 	ARM_SP_IMAGE_RW_MMAP,
 	ARM_SPM_BUF_EL0_MMAP,
 	{0}
@@ -170,12 +161,12 @@
 
 void plat_arm_secure_wdt_start(void)
 {
-	sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+	sbsa_wdog_start(NRD_CSS_WDOG_BASE, NRD_CSS_WDOG_TIMEOUT);
 }
 
 void plat_arm_secure_wdt_stop(void)
 {
-	sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+	sbsa_wdog_stop(NRD_CSS_WDOG_BASE);
 }
 
 static sds_region_desc_t nrd_sds_regions[] = {

diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat_v2.c b/plat/arm/board/neoverse_rd/common/nrd_plat2.c
similarity index 82%
rename from plat/arm/board/neoverse_rd/common/nrd_plat_v2.c
rename to plat/arm/board/neoverse_rd/common/nrd_plat2.c
index 67f486e..4a7b021 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat_v2.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat2.c

@@ -23,35 +23,35 @@
  */
 #if IMAGE_BL1
 const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	NRD_MAP_FLASH0_RO,
-	NRD_MAP_DEVICE,
-	SOC_PLATFORM_PERIPH_MAP_DEVICE,
-	SOC_SYSTEM_PERIPH_MAP_DEVICE,
+	NRD_CSS_SHARED_RAM_MMAP(0),
+	NRD_ROS_FLASH0_RO_MMAP,
+	NRD_CSS_PERIPH_MMAP(0),
+	NRD_ROS_PLATFORM_PERIPH_MMAP,
+	NRD_ROS_SYSTEM_PERIPH_MMAP,
 	{0}
 };
 #endif
 
 #if IMAGE_BL2
 const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	NRD_MAP_FLASH0_RO,
+	NRD_CSS_SHARED_RAM_MMAP(0),
+	NRD_ROS_FLASH0_RO_MMAP,
 #ifdef PLAT_ARM_MEM_PROT_ADDR
 	ARM_V2M_MAP_MEM_PROTECT,
 #endif
-	NRD_MAP_DEVICE,
-	SOC_MEMCNTRL_MAP_DEVICE,
-	SOC_PLATFORM_PERIPH_MAP_DEVICE,
-	SOC_SYSTEM_PERIPH_MAP_DEVICE,
+	NRD_CSS_PERIPH_MMAP(0),
+	NRD_ROS_MEMCNTRL_MMAP(0),
+	NRD_ROS_PLATFORM_PERIPH_MMAP,
+	NRD_ROS_SYSTEM_PERIPH_MMAP,
 	ARM_MAP_NS_DRAM1,
 #if NRD_CHIP_COUNT > 1
-	SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
+	NRD_ROS_MEMCNTRL_MMAP(1),
 #endif
 #if NRD_CHIP_COUNT > 2
-	SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
+	NRD_ROS_MEMCNTRL_MMAP(2),
 #endif
 #if NRD_CHIP_COUNT > 3
-	SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
+	NRD_ROS_MEMCNTRL_MMAP(3),
 #endif
 #if ARM_BL31_IN_DRAM
 	ARM_MAP_BL31_SEC_DRAM,
@@ -68,13 +68,13 @@
 
 #if IMAGE_BL31
 const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
+	NRD_CSS_SHARED_RAM_MMAP(0),
 #ifdef PLAT_ARM_MEM_PROT_ADDR
 	ARM_V2M_MAP_MEM_PROTECT,
 #endif
-	NRD_MAP_DEVICE,
-	SOC_PLATFORM_PERIPH_MAP_DEVICE,
-	SOC_SYSTEM_PERIPH_MAP_DEVICE,
+	NRD_CSS_PERIPH_MMAP(0),
+	NRD_ROS_PLATFORM_PERIPH_MMAP,
+	NRD_ROS_SYSTEM_PERIPH_MMAP,
 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
 	ARM_SPM_BUF_EL3_MMAP,
 #endif
@@ -83,14 +83,14 @@
 
 #if SPM_MM && defined(IMAGE_BL31)
 const mmap_region_t plat_arm_secure_partition_mmap[] = {
-	PLAT_ARM_SECURE_MAP_SYSTEMREG,
-	PLAT_ARM_SECURE_MAP_NOR2,
-	SOC_PLATFORM_SECURE_UART,
-	SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
+	NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
+	NRD_ROS_SECURE_NOR2_USER_MMAP,
+	NRD_CSS_SECURE_UART_USER_MMAP,
+	NRD_ROS_PLATFORM_PERIPH_USER_MMAP,
 	ARM_SP_IMAGE_MMAP,
 	ARM_SP_IMAGE_NS_BUF_MMAP,
 #if ENABLE_FEAT_RAS && FFH_SUPPORT
-	NRD_SP_CPER_BUF_MMAP,
+	NRD_CSS_SP_CPER_BUF_MMAP,
 #endif
 	ARM_SP_IMAGE_RW_MMAP,
 	ARM_SPM_BUF_EL0_MMAP,
@@ -171,12 +171,12 @@
 
 void plat_arm_secure_wdt_start(void)
 {
-	sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+	sbsa_wdog_start(NRD_CSS_SECURE_WDOG_BASE, NRD_CSS_SECURE_WDOG_TIMEOUT);
 }
 
 void plat_arm_secure_wdt_stop(void)
 {
-	sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+	sbsa_wdog_stop(NRD_CSS_SECURE_WDOG_BASE);
 }
 
 static sds_region_desc_t nrd_sds_regions[] = {

diff --git a/plat/arm/board/neoverse_rd/common/ras/nrd_ras_sram.c b/plat/arm/board/neoverse_rd/common/ras/nrd_ras_sram.c
index 521efdf..96aa864 100644
--- a/plat/arm/board/neoverse_rd/common/ras/nrd_ras_sram.c
+++ b/plat/arm/board/neoverse_rd/common/ras/nrd_ras_sram.c

@@ -56,8 +56,9 @@
 
 	/* Determine error record base address to read. */
 	base_addr = 0;
-	if (intr == NS_RAM_ECC_CE_INT || intr == NS_RAM_ECC_UE_INT) {
-		base_addr = SOC_NS_RAM_ERR_REC_BASE;
+	if (intr == NRD_CSS_NS_RAM_ECC_CE_INT ||
+		intr == NRD_CSS_NS_RAM_ECC_UE_INT) {
+		base_addr = NRD_CSS_NS_RAM_ERR_REC_BASE;
 	}
 	sram_info.err_status = mmio_read_32(base_addr + ERRSTATUS);
 	sram_info.err_code = mmio_read_32(base_addr + ERRCODE);

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
index 83590eb..5357c31 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h

@@ -8,9 +8,14 @@
 #define PLATFORM_DEF_H
 
 #include <lib/utils_def.h>
-
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
 #include <nrd_sdei.h>
-#include <nrd_soc_platform_def.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
+		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
 
 #define PLAT_ARM_CLUSTER_COUNT		U(2)
 #define NRD_MAX_CPUS_PER_CLUSTER	U(4)
@@ -22,36 +27,18 @@
 #define RDN1EDGE_DMC620_BASE0		UL(0x4e000000)
 #define RDN1EDGE_DMC620_BASE1		UL(0x4e100000)
 
-/* System power domain level */
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
-
 /* Virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
 /* Maximum number of address bits used per chip */
 #define NRD_ADDR_BITS_PER_CHIP	U(42)
 
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#endif
-
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
 #define PLAT_ARM_GICR_BASE		UL(0x300C0000)
 
-#define RDN1E1_CHIP0_SPI_START		U(32)
-#define RDN1E1_CHIP0_SPI_END		U(991)
+/* GIC SPI range for multichip */
+#define NRD_CHIP0_SPI_MIN		U(32)
+#define NRD_CHIP0_SPI_MAX		U(991)
 
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
index 8f21314..15fc9bb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk

@@ -4,8 +4,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
-
 # GIC-600 configuration
 GICV3_IMPL_GIC600_MULTICHIP	:=	1
 
@@ -13,11 +11,12 @@
 
 RDN1EDGE_BASE		=	plat/arm/board/neoverse_rd/platform/rdn1edge
 
-PLAT_INCLUDES		+=	-I${RDN1EDGE_BASE}/include/
+PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
+				-I${RDN1EDGE_BASE}/include/
 
 NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n1.S
 
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
 
 BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
 				${RDN1EDGE_BASE}/rdn1edge_err.c
@@ -73,6 +72,7 @@
 endif
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
+override SPMD_SPM_AT_SEL2		:= 0
 
 # Enable the flag since RD-N1-EDGE has a system level cache
 NEOVERSE_Nx_EXTERNAL_LLC		:=	1

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
index 0c6756c..ccabe22 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c

@@ -10,13 +10,12 @@
 #include <plat/common/platform.h>
 
 #include <nrd_plat.h>
-#include <nrd_soc_platform_def.h>
 
 #if defined(IMAGE_BL31)
 static const mmap_region_t rdn1edge_dynamic_mmap[] = {
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
-	NRD_MAP_DEVICE_REMOTE_CHIP(1),
-	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
+	NRD_CSS_SHARED_RAM_MMAP(1),
+	NRD_CSS_PERIPH_MMAP(1),
+	NRD_ROS_PERIPH_MMAP(1)
 };
 
 static struct gic600_multichip_data rdn1e1_multichip_data __init = {
@@ -28,8 +27,9 @@
 		(PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
 	},
 	.spi_ids = {
-		{PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START,
-			RDN1E1_CHIP0_SPI_END},
+		{PLAT_ARM_GICD_BASE,
+		NRD_CHIP0_SPI_MIN,
+		NRD_CHIP0_SPI_MAX},
 		{0, 0, 0}
 	}
 };

diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
index 840ea4a..f6f2b86 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h

@@ -8,29 +8,30 @@
 #define PLATFORM_DEF_H
 
 #include <lib/utils_def.h>
+
+#include <nrd_css_fw_def2.h>
+#include <nrd_plat_arm_def2.h>
+#include <nrd_ros_fw_def2.h>
 #include <nrd_sdei.h>
-#include <nrd_soc_platform_def_v2.h>
 
-#if (NRD_PLATFORM_VARIANT == 1)
-#define PLAT_ARM_CLUSTER_COUNT		U(8)
-#elif (NRD_PLATFORM_VARIANT == 2)
-#define PLAT_ARM_CLUSTER_COUNT		U(4)
-#else
-#define PLAT_ARM_CLUSTER_COUNT		U(16)
-#endif
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n)					\
+		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
 
 #define NRD_MAX_CPUS_PER_CLUSTER	U(1)
 #define NRD_MAX_PE_PER_CPU		U(1)
 
+/* Boot ROM */
+#define NRD_CSS_SECURE_ROM_SIZE		UL(0x00080000) /* 512KB */
+
-#define PLAT_CSS_MHU_BASE		UL(0x2A920000)
-#define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
+/* Secure SRAM */
+#define NRD_CSS_SECURE_SRAM_SIZE	UL(0x00080000) /* 512KB */
 
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
+/* NS SRAM */
+#define NRD_CSS_NS_SRAM_SIZE		UL(0x00080000) /* 512KB */
 
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE		UL(0x10720000)
-#define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
+/* DRAM2 */
+#define NRD_CSS_DRAM2_SIZE		ULL(0x180000000) /* 6GB */
 
 #define TZC400_OFFSET			UL(0x1000000)
 
@@ -67,60 +68,26 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifdef __aarch64__
 #if (NRD_PLATFORM_VARIANT == 2)
 #define NRD_ADDR_BITS_PER_CHIP	U(46)	/* 64TB */
 #else
 #define NRD_ADDR_BITS_PER_CHIP	U(42)	/* 4TB */
 #endif
 
-#define PLAT_PHY_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+/* GIC SPI range for multichip */
+#define NRD_CHIP0_SPI_MIN		U(32)
+#define NRD_CHIP0_SPI_MAX		U(511)
+#if NRD_CHIP_COUNT > 1
+#define NRD_CHIP1_SPI_MIN		U(512)
+#define NRD_CHIP1_SPI_MAX		U(991)
 #endif
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xC0000000)
-
-#if (NRD_PLATFORM_VARIANT == 1)
-#define PLAT_ARM_GICR_BASE		UL(0x30100000)
-#elif (NRD_PLATFORM_VARIANT == 3)
-#define PLAT_ARM_GICR_BASE		UL(0x30300000)
-#else
-#define PLAT_ARM_GICR_BASE		UL(0x301C0000)
+#if NRD_CHIP_COUNT > 2
+#define NRD_CHIP2_SPI_MIN		U(4096)
+#define NRD_CHIP2_SPI_MAX		U(4575)
 #endif
-
-/* Interrupt priority level for shutdown/reboot */
-#define PLAT_REBOOT_PRI		GIC_HIGHEST_SEC_PRIORITY
-#define PLAT_EHF_DESC		EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
-
-/*
- * Number of Secure Partitions supported.
- * SPMC at EL3, uses this count to configure the maximum number of supported
- * secure partitions.
- */
-#define SECURE_PARTITION_COUNT          1
-
-/*
- * Number of NWd Partitions supported.
- * SPMC at EL3, uses this count to configure the maximum number of supported
- * nwld partitions.
- */
-#define NS_PARTITION_COUNT              1
-
-/*
- * Number of Logical Partitions supported.
- * SPMC at EL3, uses this count to configure the maximum number of supported
- * logical partitions.
- */
-#define MAX_EL3_LP_DESCS_COUNT		1
+#if NRD_CHIP_COUNT > 3
+#define NRD_CHIP3_SPI_MIN		U(4576)
+#define NRD_CHIP3_SPI_MAX		U(5055)
+#endif
 
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index 12e7db4..c8f0899 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk

@@ -32,12 +32,13 @@
 
 RDN2_BASE		=	plat/arm/board/neoverse_rd/platform/rdn2
 
-PLAT_INCLUDES		+=	-I${RDN2_BASE}/include/
+PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd2/	\
+				-I${RDN2_BASE}/include/
 
 NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n2.S \
 				lib/cpus/aarch64/neoverse_v2.S
 
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat_v2.c
+PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat2.c
 
 BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
 				${RDN2_BASE}/rdn2_err.c
@@ -103,7 +104,9 @@
 endif
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
-override ENABLE_FEAT_AMU		:= 1
+override ENABLE_FEAT_AMU		:= 2
+override ENABLE_FEAT_MTE2       	:= 2
+override SPMD_SPM_AT_SEL2		:= 0
 
 # Enable the flag since RD-N2 has a system level cache
 NEOVERSE_Nx_EXTERNAL_LLC		:=	1

diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
index 0051049..b1046d6 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c

@@ -11,23 +11,22 @@
 #include <services/el3_spmc_ffa_memory.h>
 
 #include <nrd_plat.h>
-#include <nrd_soc_platform_def_v2.h>
 #include <rdn2_ras.h>
 
 #if defined(IMAGE_BL31)
 #if (NRD_PLATFORM_VARIANT == 2)
 static const mmap_region_t rdn2mc_dynamic_mmap[] = {
 #if NRD_CHIP_COUNT > 1
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
-	NRD_MAP_DEVICE_REMOTE_CHIP(1),
+	NRD_CSS_SHARED_RAM_MMAP(1),
+	NRD_CSS_PERIPH_MMAP(1),
 #endif
 #if NRD_CHIP_COUNT > 2
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
-	NRD_MAP_DEVICE_REMOTE_CHIP(2),
+	NRD_CSS_SHARED_RAM_MMAP(2),
+	NRD_CSS_PERIPH_MMAP(2),
 #endif
 #if NRD_CHIP_COUNT > 3
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
-	NRD_MAP_DEVICE_REMOTE_CHIP(3),
+	NRD_CSS_SHARED_RAM_MMAP(3),
+	NRD_CSS_PERIPH_MMAP(3),
 #endif
 };
 #endif
@@ -50,15 +49,23 @@
 #endif
 	},
 	.spi_ids = {
-		{PLAT_ARM_GICD_BASE, 32, 511},
+		{PLAT_ARM_GICD_BASE,
+		NRD_CHIP0_SPI_MIN,
+		NRD_CHIP0_SPI_MAX},
 	#if NRD_CHIP_COUNT > 1
-		{PLAT_ARM_GICD_BASE, 512, 991},
+		{PLAT_ARM_GICD_BASE,
+		NRD_CHIP1_SPI_MIN,
+		NRD_CHIP1_SPI_MAX},
 	#endif
 	#if NRD_CHIP_COUNT > 2
-		{PLAT_ARM_GICD_BASE, 4096, 4575},
+		{PLAT_ARM_GICD_BASE,
+		NRD_CHIP2_SPI_MIN,
+		NRD_CHIP2_SPI_MAX},
 	#endif
 	#if NRD_CHIP_COUNT > 3
-		{PLAT_ARM_GICD_BASE, 4576, 5055},
+		{PLAT_ARM_GICD_BASE,
+		NRD_CHIP3_SPI_MIN,
+		NRD_CHIP3_SPI_MAX},
 	#endif
 	}
 };

diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c
index d046a1f..e328764 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c

@@ -11,10 +11,10 @@
 
 struct nrd_ras_ev_map plat_ras_map[] = {
 	/* Non Secure base RAM ECC CE interrupt */
-	{NRD_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, NRD_RAS_INTR_TYPE_SPI},
+	{NRD_SDEI_DS_EVENT_0, NRD_CSS_NS_RAM_ECC_CE_INT, NRD_RAS_INTR_TYPE_SPI},
 
 	/* Non Secure base RAM ECC UE interrupt */
-	{NRD_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, NRD_RAS_INTR_TYPE_SPI},
+	{NRD_SDEI_DS_EVENT_0, NRD_CSS_NS_RAM_ECC_UE_INT, NRD_RAS_INTR_TYPE_SPI},
 
 	/* CPU 1-bit ECC CE error interrupt */
 	{NRD_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, NRD_RAS_INTR_TYPE_PPI}
@@ -23,7 +23,7 @@
 /* RAS error record list definition, used by the common RAS framework. */
 struct err_record_info plat_err_records[] = {
 	/* Base element RAM Non-secure error record. */
-	ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL,
+	ERR_RECORD_MEMMAP_V1(NRD_CSS_NS_RAM_ERR_REC_BASE, 4, NULL,
 				&nrd_ras_sram_intr_handler, 0),
 	ERR_RECORD_SYSREG_V1(0, 1, NULL, &nrd_ras_cpu_intr_handler, 0),
 };
@@ -34,10 +34,10 @@
 		.intr_number = PLAT_CORE_FAULT_IRQ,
 		.err_record = &plat_err_records[1],
 	}, {
-		.intr_number = NS_RAM_ECC_CE_INT,
+		.intr_number = NRD_CSS_NS_RAM_ECC_CE_INT,
 		.err_record = &plat_err_records[0],
 	}, {
-		.intr_number = NS_RAM_ECC_UE_INT,
+		.intr_number = NRD_CSS_NS_RAM_ECC_UE_INT,
 		.err_record = &plat_err_records[0],
 	},
 };

diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
index 41172ea..7319d1a 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c

@@ -9,8 +9,8 @@
 #include <platform_def.h>
 
 #define RDN2_TZC_CPER_REGION				\
-	{NRD_SP_CPER_BUF_BASE, (NRD_SP_CPER_BUF_BASE +	\
-	NRD_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE,	\
+	{NRD_CSS_SP_CPER_BUF_BASE, (NRD_CSS_SP_CPER_BUF_BASE +	\
+	NRD_CSS_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE,	\
 	PLAT_ARM_TZC_NS_DEV_ACCESS}
 
 static const arm_tzc_regions_info_t tzc_regions[] = {
@@ -25,20 +25,20 @@
 static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
 	{
 		/* TZC memory regions for second chip */
-		NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
+		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
 		{}
 	},
 #if NRD_CHIP_COUNT > 2
 	{
 		/* TZC memory regions for third chip */
-		NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
+		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
 		{}
 	},
 #endif
 #if NRD_CHIP_COUNT > 3
 	{
 		/* TZC memory regions for fourth chip */
-		NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
+		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
 		{}
 	},
 #endif

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
index f889561..cd40117 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h

@@ -8,8 +8,13 @@
 #define PLATFORM_DEF_H
 
 #include <lib/utils_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
 
-#include <nrd_soc_platform_def.h>
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
+		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
 
 #define PLAT_ARM_CLUSTER_COUNT		U(16)
 #define NRD_MAX_CPUS_PER_CLUSTER	U(1)
@@ -18,9 +23,6 @@
 #define PLAT_CSS_MHU_BASE		UL(0x45400000)
 #define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
 
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
-
 /* TZC Related Constants */
 #define PLAT_ARM_TZC_BASE		UL(0x21830000)
 #define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
@@ -49,20 +51,8 @@
 /* Maximum number of address bits used per chip */
 #define NRD_ADDR_BITS_PER_CHIP	U(42)
 
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << NRD_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << NRD_ADDR_BITS_PER_CHIP)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#endif
-
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
 #define PLAT_ARM_GICR_BASE		UL(0x30140000)
 
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
index 0950df2..fe87779 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk

@@ -10,11 +10,12 @@
 
 RDV1_BASE		=	plat/arm/board/neoverse_rd/platform/rdv1
 
-PLAT_INCLUDES		+=	-I${RDV1_BASE}/include/
+PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
+				-I${RDV1_BASE}/include/
 
 NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
 
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
 
 BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
 				${RDV1_BASE}/rdv1_err.c
@@ -57,7 +58,8 @@
 $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
-override ENABLE_FEAT_AMU		:= 1
+override ENABLE_FEAT_AMU		:= 2
+override SPMD_SPM_AT_SEL2		:= 0
 
 ifneq ($(NRD_PLATFORM_VARIANT),0)
  $(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
index 3e7c9b5..b4c5c0a 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h

@@ -8,7 +8,13 @@
 #define PLATFORM_DEF_H
 
 #include <lib/utils_def.h>
-#include <nrd_soc_platform_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
+		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
 
 #define PLAT_ARM_CLUSTER_COUNT		U(4)
 #define NRD_MAX_CPUS_PER_CLUSTER	U(1)
@@ -17,9 +23,6 @@
 #define PLAT_CSS_MHU_BASE		UL(0x45400000)
 #define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
 
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
-
 /* TZC Related Constants */
 #define PLAT_ARM_TZC_BASE		UL(0x21830000)
 #define TZC400_BASE(n)			(PLAT_ARM_TZC_BASE + \
@@ -49,18 +52,12 @@
 /* Remote chip address offset (4TB per chip) */
 #define NRD_ADDR_BITS_PER_CHIP	U(42)
 
-/* Physical and virtual address space limits for MMU in AARCH64 mode */
-#define PLAT_PHY_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
 #define PLAT_ARM_GICR_BASE		UL(0x30140000)
 
-#define RDV1MC_CHIP0_SPI_START		U(32)
-#define RDV1MC_CHIP0_SPI_END		U(991)
+/* GIC SPI range for multichip */
+#define NRD_CHIP0_SPI_MIN		U(32)
+#define NRD_CHIP0_SPI_MAX		U(991)
 
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
index 9d878c3..a0a1204 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk

@@ -11,11 +11,12 @@
 
 RDV1MC_BASE	=	plat/arm/board/neoverse_rd/platform/rdv1mc
 
-PLAT_INCLUDES		+=	-I${RDV1MC_BASE}/include/
+PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
+				-I${RDV1MC_BASE}/include/
 
 NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
 
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
 
 BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
 				${RDV1MC_BASE}/rdv1mc_err.c
@@ -68,7 +69,8 @@
 $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
 
 override CTX_INCLUDE_AARCH32_REGS	:= 0
-override ENABLE_FEAT_AMU		:= 1
+override ENABLE_FEAT_AMU		:= 2
+override SPMD_SPM_AT_SEL2		:= 0
 
 ifneq ($(NRD_PLATFORM_VARIANT),0)
  $(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
index 4455ec4..5713cb9 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c

@@ -10,22 +10,21 @@
 #include <plat/common/platform.h>
 
 #include <nrd_plat.h>
-#include <nrd_soc_platform_def.h>
 
 #if defined(IMAGE_BL31)
 static const mmap_region_t rdv1mc_dynamic_mmap[] = {
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
-	NRD_MAP_DEVICE_REMOTE_CHIP(1),
-	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
+	NRD_CSS_SHARED_RAM_MMAP(1),
+	NRD_CSS_PERIPH_MMAP(1),
+	NRD_ROS_PERIPH_MMAP(1),
 #if (NRD_CHIP_COUNT > 2)
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
-	NRD_MAP_DEVICE_REMOTE_CHIP(2),
-	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
+	NRD_CSS_SHARED_RAM_MMAP(2),
+	NRD_CSS_PERIPH_MMAP(2),
+	NRD_ROS_PERIPH_MMAP(2),
 #endif
 #if (NRD_CHIP_COUNT > 3)
-	ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
-	NRD_MAP_DEVICE_REMOTE_CHIP(3),
-	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
+	NRD_CSS_SHARED_RAM_MMAP(3),
+	NRD_CSS_PERIPH_MMAP(3),
+	NRD_ROS_PERIPH_MMAP(3)
 #endif
 };
 
@@ -44,8 +43,9 @@
 #endif
 	},
 	.spi_ids = {
-		{PLAT_ARM_GICD_BASE, RDV1MC_CHIP0_SPI_START,
-			RDV1MC_CHIP0_SPI_END},
+		{PLAT_ARM_GICD_BASE,
+		NRD_CHIP0_SPI_MIN,
+		NRD_CHIP0_SPI_MAX},
 		{0, 0, 0},
 #if (NRD_CHIP_COUNT > 2)
 		{0, 0, 0},

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
index 7fca31a..1e59831 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c

@@ -18,20 +18,20 @@
 static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
 	{
 		/* TZC memory regions for second chip */
-		NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
+		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
 		{}
 	},
 #if NRD_CHIP_COUNT > 2
 	{
 		/* TZC memory regions for third chip */
-		NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
+		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
 		{}
 	},
 #endif
 #if NRD_CHIP_COUNT > 3
 	{
 		/* TZC memory regions for fourth chip */
-		NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
+		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
 		{}
 	},
 #endif

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
index 9658ee1..0797017 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h

@@ -8,9 +8,14 @@
 #define PLATFORM_DEF_H
 
 #include <lib/utils_def.h>
-
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
 #include <nrd_sdei.h>
-#include <nrd_soc_platform_def.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
+		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
 
 #define PLAT_ARM_CLUSTER_COUNT		U(2)
 #define NRD_MAX_CPUS_PER_CLUSTER	U(4)
@@ -22,28 +27,11 @@
 #define SGI575_DMC620_BASE0		UL(0x4e000000)
 #define SGI575_DMC620_BASE1		UL(0x4e100000)
 
-/* System power domain level */
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
-
 /* Maximum number of address bits used per chip */
 #define NRD_ADDR_BITS_PER_CHIP	U(36)
 
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << NRD_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << NRD_ADDR_BITS_PER_CHIP)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#endif
-
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
 #define PLAT_ARM_GICR_BASE		UL(0x300C0000)
 
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
index d34e555..37306be 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk

@@ -4,17 +4,16 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
-
 include plat/arm/board/neoverse_rd/common/nrd-common.mk
 
 SGI575_BASE		=	plat/arm/board/neoverse_rd/platform/sgi575
 
-PLAT_INCLUDES		+=	-I${SGI575_BASE}/include/
+PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
+				-I${SGI575_BASE}/include/
 
 NRD_CPU_SOURCES		:=	lib/cpus/aarch64/cortex_a75.S
 
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat.c
+PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
 
 BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
 				${SGI575_BASE}/sgi575_err.c
@@ -65,3 +64,5 @@
  $(error "NRD_PLATFORM_VARIANT for SGI575 should always be 0,\
      currently set to ${NRD_PLATFORM_VARIANT}.")
 endif
+
+override SPMD_SPM_AT_SEL2		:= 0

diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
index 3bc0cbb..dc6c7d8 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi

@@ -107,4 +107,9 @@
 		      <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
 		       HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
 	};
+
+	memory@2 {
+		device_type = "device-memory";
+		reg = <0x0 0x25000000 0x0 0x10000>; /* For cactus tertiary dummy device. */
+	};
 };

diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 3897096..dcae95f 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h

@@ -168,17 +168,9 @@
  * Size of cacheable stacks
  */
 #if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
 #  define PLATFORM_STACK_SIZE		0x1000
-# else
-#  define PLATFORM_STACK_SIZE		0x440
-# endif
 #elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
 #  define PLATFORM_STACK_SIZE		0x1000
-# else
-#  define PLATFORM_STACK_SIZE		0x400
-# endif
 #elif defined(IMAGE_BL2U)
 # define PLATFORM_STACK_SIZE		0x400
 #elif defined(IMAGE_BL31)
@@ -193,11 +185,11 @@
 
 /*
  * In the current implementation the RoT Service request that requires the
- * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
+ * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
  * maximum required buffer size is calculated based on the platform-specific
  * needs of this request.
  */
-#define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE	0x500
+#define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE	0x500
 
 #define TC_DEVICE_BASE			0x21000000
 #define TC_DEVICE_SIZE			0x5f000000
@@ -279,13 +271,13 @@
 
 /* Index of SDS region used in the communication with SCP */
 #define SDS_SCP_AP_REGION_ID		U(0)
-/* Index of SDS region used in the communication with RSS */
-#define SDS_RSS_AP_REGION_ID		U(1)
+/* Index of SDS region used in the communication with RSE */
+#define SDS_RSE_AP_REGION_ID		U(1)
 /*
- * Memory region for RSS's shared data storage (SDS)
+ * Memory region for RSE's shared data storage (SDS)
  * It is placed right after the SCMI payload area.
  */
-#define PLAT_ARM_RSS_AP_SDS_MEM_BASE	(CSS_SCMI_PAYLOAD_BASE + \
+#define PLAT_ARM_RSE_AP_SDS_MEM_BASE	(CSS_SCMI_PAYLOAD_BASE + \
 					 CSS_SCMI_PAYLOAD_SIZE_MAX)
 
 #define PLAT_ARM_CLUSTER_COUNT		U(1)
@@ -306,9 +298,9 @@
 #endif /* TARGET_PLATFORM == 3 */
 #define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
 
-/* TC2: AP<->RSS MHUs */
-#define PLAT_RSS_AP_SND_MHU_BASE	UL(0x2A840000)
-#define PLAT_RSS_AP_RCV_MHU_BASE	UL(0x2A850000)
+/* TC2: AP<->RSE MHUs */
+#define PLAT_RSE_AP_SND_MHU_BASE	UL(0x2A840000)
+#define PLAT_RSE_AP_RCV_MHU_BASE	UL(0x2A850000)
 
 #define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
 #define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1

diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h
index a6b2b0d..6ba4694 100644
--- a/plat/arm/board/tc/include/tc_plat.h
+++ b/plat/arm/board/tc/include/tc_plat.h

@@ -8,7 +8,7 @@
 #define TC_PLAT_H
 
 #ifdef PLATFORM_TEST_ROTPK
-#include <rss_crypto_defs.h>
+#include <rse_crypto_defs.h>
 #endif
 
 void tc_bl31_common_platform_setup(void);
@@ -23,7 +23,7 @@
 
 #ifdef PLATFORM_TEST_ROTPK
 struct key_id_info {
-	enum rss_key_id_builtin_t key_id;
+	enum rse_key_id_builtin_t key_id;
 	const char *key_id_name;
 };
 

diff --git a/plat/arm/board/tc/nv_counter_test.c b/plat/arm/board/tc/nv_counter_test.c
index 179ec4b..9025569 100644
--- a/plat/arm/board/tc/nv_counter_test.c
+++ b/plat/arm/board/tc/nv_counter_test.c

@@ -7,9 +7,9 @@
 #include <stdint.h>
 #include <stdio.h>
 
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <plat/common/platform.h>
-#include "rss_platform_api.h"
+#include "rse_platform_api.h"
 
 #include <platform_def.h>
 
@@ -20,30 +20,30 @@
 	uint32_t new_val;
 	uint32_t id;
 
-	status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+	status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
 	if (status != PSA_SUCCESS) {
-		printf("Failed to initialize RSS communication channel - psa_status = %d\n", status);
+		printf("Failed to initialize RSE communication channel - psa_status = %d\n", status);
 		return -1;
 	}
 
 	for (id = 0; id < 3; id++) {
-		status = rss_platform_nv_counter_read(id, sizeof(old_val), (uint8_t *)&old_val);
+		status = rse_platform_nv_counter_read(id, sizeof(old_val), (uint8_t *)&old_val);
 		if (status != PSA_SUCCESS) {
-			printf("Failed during first id=(%d) rss_platform_nv_counter_read - psa_status = %d\n",
+			printf("Failed during first id=(%d) rse_platform_nv_counter_read - psa_status = %d\n",
 				       id, status);
 			return -1;
 		}
 
-		status = rss_platform_nv_counter_increment(id);
+		status = rse_platform_nv_counter_increment(id);
 		if (status != PSA_SUCCESS) {
-			printf("Failed during id=(%d) rss_platform_nv_counter_increment - psa_status = %d\n",
+			printf("Failed during id=(%d) rse_platform_nv_counter_increment - psa_status = %d\n",
 					id, status);
 			return -1;
 		}
 
-		status = rss_platform_nv_counter_read(id, sizeof(new_val), (uint8_t *)&new_val);
+		status = rse_platform_nv_counter_read(id, sizeof(new_val), (uint8_t *)&new_val);
 		if (status != PSA_SUCCESS) {
-			printf("Failed during second id=(%d) rss_platform_nv_counter_read - psa_status = %d\n",
+			printf("Failed during second id=(%d) rse_platform_nv_counter_read - psa_status = %d\n",
 					id, status);
 			return -1;
 		}

diff --git a/plat/arm/board/tc/plat_def_fip_uuid.h b/plat/arm/board/tc/plat_def_fip_uuid.h
index 631f7c9..46a455c 100644
--- a/plat/arm/board/tc/plat_def_fip_uuid.h
+++ b/plat/arm/board/tc/plat_def_fip_uuid.h

@@ -10,28 +10,28 @@
 
 #include "uuid.h"
 
-#define UUID_RSS_FIRMWARE_BL1_2 \
+#define UUID_RSE_FIRMWARE_BL1_2 \
 	{{0x0a, 0xa5, 0xb1, 0xbe}, {0xe7, 0x84}, {0x41, 0xc5}, 0x81, 0xb8, {0x4a, 0x41, 0xcb, 0x4a, 0xd2, 0xdf}}
 
-#define UUID_RSS_FIRMWARE_BL2 \
+#define UUID_RSE_FIRMWARE_BL2 \
 	{{0xa3, 0xb3, 0xb3, 0x0d}, {0xeb, 0xc9}, {0x40, 0x48}, 0xb4, 0x80, {0x15, 0x53, 0x61, 0xc1, 0x70, 0x48}}
 
-#define UUID_RSS_FIRMWARE_SCP_BL1 \
+#define UUID_RSE_FIRMWARE_SCP_BL1 \
 	{{0xbf, 0xd5, 0x09, 0x8d}, {0xa7, 0x07}, {0x4f, 0x15}, 0x89, 0x1c, {0x37, 0x22, 0x10, 0xcb, 0x51, 0xe2}}
 
-#define UUID_RSS_FIRMWARE_AP_BL1 \
+#define UUID_RSE_FIRMWARE_AP_BL1 \
 	{{0x12, 0x4c, 0x50, 0xe0}, {0xf2, 0xda}, {0x45, 0xe9}, 0x85, 0xc8, {0xda, 0xd9, 0x60, 0x9b, 0x7a, 0x11}}
 
-#define UUID_RSS_FIRMWARE_NS \
+#define UUID_RSE_FIRMWARE_NS \
 	{{0x8d, 0x95, 0x9f, 0x72}, {0xb8, 0xb1}, {0x42, 0x11}, 0x9a, 0xe6, {0x4b, 0x80, 0x97, 0x47, 0x5a, 0xd9}}
 
-#define UUID_RSS_FIRMWARE_S \
+#define UUID_RSE_FIRMWARE_S \
 	{{0x22, 0xea, 0x33, 0x85}, {0xf8, 0x6e}, {0x47, 0x93}, 0x96, 0x8a, {0x2f, 0xe3, 0xdd, 0x50, 0x33, 0xcc}}
 
-#define UUID_RSS_SIC_TABLES_NS \
+#define UUID_RSE_SIC_TABLES_NS \
 	{{0xd9, 0x10, 0x00, 0x72}, {0x6a, 0x28}, {0x4b, 0xec}, 0xb0, 0xd6, {0x8c, 0xed, 0xc4, 0x15, 0x7c, 0xe0}}
 
-#define UUID_RSS_SIC_TABLES_S \
+#define UUID_RSE_SIC_TABLES_S \
 	{{0xc7, 0x38, 0xd0, 0xde}, {0x8c, 0x26}, {0x48, 0x51}, 0x93, 0x36, {0xf3, 0xdb, 0xe2, 0x96, 0x65, 0x18}}
 
 #endif /* __PLAT_DEF_FIP_UUID__ */

diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index b30e40c..8756f31 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk

@@ -173,20 +173,20 @@
 # Include Measured Boot makefile before any Crypto library makefile.
 # Crypto library makefile may need default definitions of Measured Boot build
 # flags present in Measured Boot makefile.
-$(info Including rss_comms.mk)
+$(info Including rse_comms.mk)
 ifeq (${MEASURED_BOOT},1)
-        $(info Including rss_comms.mk)
-        include drivers/arm/rss/rss_comms.mk
+        $(info Including rse_comms.mk)
+        include drivers/arm/rse/rse_comms.mk
 
-	BL1_SOURCES	+=	${RSS_COMMS_SOURCES}
-	BL2_SOURCES	+=	${RSS_COMMS_SOURCES}
+	BL1_SOURCES	+=	${RSE_COMMS_SOURCES}
+	BL2_SOURCES	+=	${RSE_COMMS_SOURCES}
 	PLAT_INCLUDES	+=	-Iinclude/lib/psa
 
     ifeq (${DICE_PROTECTION_ENVIRONMENT},1)
         $(info Including qcbor.mk)
-        include drivers/measured_boot/rss/qcbor.mk
+        include drivers/measured_boot/rse/qcbor.mk
         $(info Including dice_prot_env.mk)
-        include drivers/measured_boot/rss/dice_prot_env.mk
+        include drivers/measured_boot/rse/dice_prot_env.mk
 
 	BL1_SOURCES	+=	${QCBOR_SOURCES} \
 				${DPE_SOURCES} \
@@ -206,8 +206,8 @@
 	PLAT_INCLUDES	+=	-I${QCBOR_INCLUDES} \
 				-Iinclude/lib/dice
     else
-        $(info Including rss_measured_boot.mk)
-        include drivers/measured_boot/rss/rss_measured_boot.mk
+        $(info Including rse_measured_boot.mk)
+        include drivers/measured_boot/rse/rse_measured_boot.mk
 
 	BL1_SOURCES	+=	${MEASURED_BOOT_SOURCES} \
 				plat/arm/board/tc/tc_common_measured_boot.c \

diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk
index 4e81b2c..8ef6f76 100644
--- a/plat/arm/board/tc/platform_test.mk
+++ b/plat/arm/board/tc/platform_test.mk

@@ -5,42 +5,42 @@
 
 $(eval $(call add_define,PLATFORM_TESTS))
 
-ifeq (${PLATFORM_TEST},rss-nv-counters)
-    include drivers/arm/rss/rss_comms.mk
+ifeq (${PLATFORM_TEST},rse-nv-counters)
+    include drivers/arm/rse/rse_comms.mk
 
     # Test code.
     BL31_SOURCES	+=	plat/arm/board/tc/nv_counter_test.c
 
     # Code under testing.
-    BL31_SOURCES	+=	lib/psa/rss_platform.c \
-				${RSS_COMMS_SOURCES}
+    BL31_SOURCES	+=	lib/psa/rse_platform.c \
+				${RSE_COMMS_SOURCES}
 
     PLAT_INCLUDES	+=	-Iinclude/lib/psa
 
     $(eval $(call add_define,PLATFORM_TEST_NV_COUNTERS))
-else ifeq (${PLATFORM_TEST},rss-rotpk)
-    include drivers/arm/rss/rss_comms.mk
+else ifeq (${PLATFORM_TEST},rse-rotpk)
+    include drivers/arm/rse/rse_comms.mk
 
     # Test code.
     BL31_SOURCES	+=	plat/arm/board/tc/rotpk_test.c
 
     # Code under testing.
-    BL31_SOURCES	+=	lib/psa/rss_platform.c \
-				${RSS_COMMS_SOURCES}
+    BL31_SOURCES	+=	lib/psa/rse_platform.c \
+				${RSE_COMMS_SOURCES}
 
     PLAT_INCLUDES	+=	-Iinclude/lib/psa
 
     $(eval $(call add_define,PLATFORM_TEST_ROTPK))
 else ifeq (${PLATFORM_TEST},tfm-testsuite)
-    include drivers/arm/rss/rss_comms.mk
+    include drivers/arm/rse/rse_comms.mk
 
     # The variables need to be set to compile the platform test:
     ifeq (${TF_M_TESTS_PATH},)
-        # Example: ../rss/tf-m-tests
+        # Example: ../rse/tf-m-tests
         $(error Error: TF_M_TESTS_PATH not set)
     endif
     ifeq (${TF_M_EXTRAS_PATH},)
-        # Example: ../rss/tf-m-extras
+        # Example: ../rse/tf-m-extras
         $(error Error: TF_M_EXTRAS_PATH not set)
     endif
     ifeq (${MEASUREMENT_VALUE_SIZE},)
@@ -68,11 +68,11 @@
 					psa_crypto_slot_management.c		\
 					)
 
-    BL31_SOURCES	+=	${RSS_COMMS_SOURCES}				\
+    BL31_SOURCES	+=	${RSE_COMMS_SOURCES}				\
 				plat/arm/common/arm_dyn_cfg.c			\
-				${TC_BASE}/rss_ap_tests.c			\
-				${TC_BASE}/rss_ap_testsuites.c			\
-				${TC_BASE}/rss_ap_test_stubs.c			\
+				${TC_BASE}/rse_ap_tests.c			\
+				${TC_BASE}/rse_ap_testsuites.c			\
+				${TC_BASE}/rse_ap_test_stubs.c			\
 				$(TF_M_TESTS_PATH)/tests_reg/test/framework/test_framework.c \
 				$(MEASURED_BOOT_TESTS_PATH)/measured_boot_common.c \
 				$(MEASURED_BOOT_TESTS_PATH)/measured_boot_tests_common.c \

diff --git a/plat/arm/board/tc/rotpk_test.c b/plat/arm/board/tc/rotpk_test.c
index ed56c31..2178f69 100644
--- a/plat/arm/board/tc/rotpk_test.c
+++ b/plat/arm/board/tc/rotpk_test.c

@@ -7,9 +7,9 @@
 #include <stdint.h>
 #include <stdio.h>
 
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <plat/common/platform.h>
-#include <rss_platform_api.h>
+#include <rse_platform_api.h>
 #include <tc_plat.h>
 
 static void print_hex(const char *key_id_name, size_t key_size, const uint8_t *key_buf)
@@ -28,19 +28,19 @@
 	size_t key_size;
 
 	struct key_id_info key_ids[3] = {
-	       {.key_id = RSS_BUILTIN_KEY_ID_HOST_S_ROTPK,  .key_id_name = "Secure-ROTPK"},
-	       {.key_id = RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK,  .key_id_name = "NS-ROTPK"},
-	       {.key_id = RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK,  .key_id_name = "CCA-ROTPK"}
+	       {.key_id = RSE_BUILTIN_KEY_ID_HOST_S_ROTPK,  .key_id_name = "Secure-ROTPK"},
+	       {.key_id = RSE_BUILTIN_KEY_ID_HOST_NS_ROTPK,  .key_id_name = "NS-ROTPK"},
+	       {.key_id = RSE_BUILTIN_KEY_ID_HOST_CCA_ROTPK,  .key_id_name = "CCA-ROTPK"}
 	};
 
-	status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+	status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
 	if (status != PSA_SUCCESS) {
-		printf("Failed to initialize RSS communication channel - psa_status = %d\n", status);
+		printf("Failed to initialize RSE communication channel - psa_status = %d\n", status);
 		return -1;
 	}
 
 	for (int i = 0; i < ARRAY_SIZE(key_ids); i++) {
-		status = rss_platform_key_read(key_ids[i].key_id, key_buf,
+		status = rse_platform_key_read(key_ids[i].key_id, key_buf,
 			       sizeof(key_buf), &key_size);
 		if (status != PSA_SUCCESS) {
 			printf("Failed to retrieve %s - psa_status = %d\n", key_ids[i].key_id_name, status);

diff --git a/plat/arm/board/tc/rss_ap_test_stubs.c b/plat/arm/board/tc/rse_ap_test_stubs.c
similarity index 92%
rename from plat/arm/board/tc/rss_ap_test_stubs.c
rename to plat/arm/board/tc/rse_ap_test_stubs.c
index aa97476..cf79181 100644
--- a/plat/arm/board/tc/rss_ap_test_stubs.c
+++ b/plat/arm/board/tc/rse_ap_test_stubs.c

@@ -26,7 +26,7 @@
 				     size_t measurement_value_size,
 				     bool lock_measurement)
 {
-	return rss_measured_boot_extend_measurement(index,
+	return rse_measured_boot_extend_measurement(index,
 						    signer_id,
 						    signer_id_size,
 						    version,
@@ -56,7 +56,7 @@
 				   size_t *measurement_value_len,
 				   bool *is_locked)
 {
-	return rss_measured_boot_read_measurement(index,
+	return rse_measured_boot_read_measurement(index,
 						  signer_id,
 						  signer_id_size,
 						  signer_id_len,
@@ -80,7 +80,7 @@
 			       size_t         token_buf_size,
 			       size_t        *token_size)
 {
-	return rss_delegated_attest_get_token(dak_pub_hash,
+	return rse_delegated_attest_get_token(dak_pub_hash,
 					      dak_pub_hash_size,
 					      token_buf,
 					      token_buf_size,
@@ -95,7 +95,7 @@
 				       size_t   *key_size,
 				       uint32_t  hash_algo)
 {
-	return rss_delegated_attest_get_delegated_key(ecc_curve,
+	return rse_delegated_attest_get_delegated_key(ecc_curve,
 						      key_bits,
 						      key_buf,
 						      key_buf_size,

diff --git a/plat/arm/board/tc/rss_ap_tests.c b/plat/arm/board/tc/rse_ap_tests.c
similarity index 94%
rename from plat/arm/board/tc/rss_ap_tests.c
rename to plat/arm/board/tc/rse_ap_tests.c
index ea90ac3..3ca628a 100644
--- a/plat/arm/board/tc/rss_ap_tests.c
+++ b/plat/arm/board/tc/rse_ap_tests.c

@@ -10,9 +10,9 @@
 #include <mbedtls_common.h>
 #include <plat/common/platform.h>
 #include <psa/crypto.h>
-#include <rss_comms.h>
+#include <rse_comms.h>
 
-#include "rss_ap_testsuites.h"
+#include "rse_ap_testsuites.h"
 
 static struct test_suite_t test_suites[] = {
 	{.freg = register_testsuite_delegated_attest},
@@ -32,7 +32,7 @@
 	size_t i;
 
 	/* Initialize test environment. */
-	rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+	rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
 	mbedtls_init();
 	status = psa_crypto_init();
 	if (status != PSA_SUCCESS) {

diff --git a/plat/arm/board/tc/rss_ap_testsuites.c b/plat/arm/board/tc/rse_ap_testsuites.c
similarity index 93%
rename from plat/arm/board/tc/rss_ap_testsuites.c
rename to plat/arm/board/tc/rse_ap_testsuites.c
index aa47d4c..5f4dc16 100644
--- a/plat/arm/board/tc/rss_ap_testsuites.c
+++ b/plat/arm/board/tc/rse_ap_testsuites.c

@@ -11,7 +11,7 @@
  * necessary because both files define the function `extra_tests_init`, so a
  * linker error occurs when both are linked to BL31. This file defines a macro
  * that renames the colliding function names to something unique.
- * `plat/arm/board/tc/rss_ap_tests.c` can call the test init functions with
+ * `plat/arm/board/tc/rse_ap_tests.c` can call the test init functions with
  * their new name.
  */
 

diff --git a/plat/arm/board/tc/rss_ap_testsuites.h b/plat/arm/board/tc/rse_ap_testsuites.h
similarity index 76%
rename from plat/arm/board/tc/rss_ap_testsuites.h
rename to plat/arm/board/tc/rse_ap_testsuites.h
index 58502ab..9bb42f5 100644
--- a/plat/arm/board/tc/rss_ap_testsuites.h
+++ b/plat/arm/board/tc/rse_ap_testsuites.h

@@ -5,12 +5,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef RSS_AP_TESTSUITES_H
-#define RSS_AP_TESTSUITES_H
+#ifndef RSE_AP_TESTSUITES_H
+#define RSE_AP_TESTSUITES_H
 
 #include <test_framework.h>
 
 void register_testsuite_measured_boot(struct test_suite_t *p_test_suite);
 void register_testsuite_delegated_attest(struct test_suite_t *p_test_suite);
 
-#endif /* RSS_AP_TESTSUITES_H */
+#endif /* RSE_AP_TESTSUITES_H */

diff --git a/plat/arm/board/tc/tc_bl1_dpe.c b/plat/arm/board/tc/tc_bl1_dpe.c
index dc60fb6..432a163 100644
--- a/plat/arm/board/tc/tc_bl1_dpe.c
+++ b/plat/arm/board/tc/tc_bl1_dpe.c

@@ -8,11 +8,11 @@
 
 #include <common/debug.h>
 #include <drivers/arm/css/sds.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <drivers/delay_timer.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
@@ -53,7 +53,7 @@
 };
 
 /* Effective timeout of 10000 ms */
-#define RSS_DPE_BOOT_10US_RETRIES		1000000
+#define RSE_DPE_BOOT_10US_RETRIES		1000000
 #define TC2_SDS_DPE_CTX_HANDLE_STRUCT_ID	0x0000000A
 
 /* Context handle is meant to be used by BL2. Sharing it via TB_FW_CONFIG */
@@ -66,20 +66,20 @@
 
 void plat_dpe_get_context_handle(int *ctx_handle)
 {
-	int retry = RSS_DPE_BOOT_10US_RETRIES;
+	int retry = RSE_DPE_BOOT_10US_RETRIES;
 	int ret;
 
 	/* Initialize System level generic or SP804 timer */
 	generic_delay_timer_init();
 
-	/* Check the initialization of the Shared Data Storage area between RSS
-	 * and AP. Since AP_BL1 is executed first then a bit later the RSS
+	/* Check the initialization of the Shared Data Storage area between RSE
+	 * and AP. Since AP_BL1 is executed first then a bit later the RSE
 	 * runtime, which initialize this area, therefore AP needs to check it
-	 * in a loop until it gets written by RSS Secure Runtime.
+	 * in a loop until it gets written by RSE Secure Runtime.
 	 */
-	VERBOSE("Waiting for DPE service initialization in RSS Secure Runtime\n");
+	VERBOSE("Waiting for DPE service initialization in RSE Secure Runtime\n");
 	while (retry > 0) {
-		ret = sds_init(SDS_RSS_AP_REGION_ID);
+		ret = sds_init(SDS_RSE_AP_REGION_ID);
 		if (ret != SDS_OK) {
 			udelay(10);
 			retry--;
@@ -93,11 +93,11 @@
 		plat_panic_handler();
 	} else {
 		VERBOSE("DPE init succeeded in %dms.\n",
-			(RSS_DPE_BOOT_10US_RETRIES - retry) / 100);
+			(RSE_DPE_BOOT_10US_RETRIES - retry) / 100);
 	}
 
 	/* TODO: call this in a loop to avoid reading unfinished data */
-	ret = sds_struct_read(SDS_RSS_AP_REGION_ID,
+	ret = sds_struct_read(SDS_RSE_AP_REGION_ID,
 			      TC2_SDS_DPE_CTX_HANDLE_STRUCT_ID,
 			      0,
 			      ctx_handle,
@@ -113,9 +113,9 @@
 
 void bl1_plat_mboot_init(void)
 {
-	/* Initialize the communication channel between AP and RSS */
-	(void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
-			     PLAT_RSS_AP_RCV_MHU_BASE);
+	/* Initialize the communication channel between AP and RSE */
+	(void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+			     PLAT_RSE_AP_RCV_MHU_BASE);
 
 	dpe_init(tc_dpe_metadata);
 }

diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c
index 2e58954..28a1e31 100644
--- a/plat/arm/board/tc/tc_bl1_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl1_measured_boot.c

@@ -6,9 +6,9 @@
 
 #include <stdint.h>
 
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
 #include <tools_share/zero_oid.h>
 
 #include <plat/arm/common/plat_arm.h>
@@ -17,7 +17,7 @@
 /* Table with platform specific image IDs and metadata. Intentionally not a
  * const struct, some members might set by bootloaders during trusted boot.
  */
-struct rss_mboot_metadata tc_rss_mboot_metadata[] = {
+struct rse_mboot_metadata tc_rse_mboot_metadata[] = {
 	{
 		.id = FW_CONFIG_ID,
 		.slot = U(6),
@@ -41,16 +41,16 @@
 		.lock_measurement = true },
 
 	{
-		.id = RSS_MBOOT_INVALID_ID }
+		.id = RSE_MBOOT_INVALID_ID }
 };
 
 void bl1_plat_mboot_init(void)
 {
-	/* Initialize the communication channel between AP and RSS */
-	(void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
-			     PLAT_RSS_AP_RCV_MHU_BASE);
+	/* Initialize the communication channel between AP and RSE */
+	(void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+			     PLAT_RSE_AP_RCV_MHU_BASE);
 
-	rss_measured_boot_init(tc_rss_mboot_metadata);
+	rse_measured_boot_init(tc_rse_mboot_metadata);
 }
 
 void bl1_plat_mboot_finish(void)

diff --git a/plat/arm/board/tc/tc_bl2_dpe.c b/plat/arm/board/tc/tc_bl2_dpe.c
index e50508f..50cdbf8 100644
--- a/plat/arm/board/tc/tc_bl2_dpe.c
+++ b/plat/arm/board/tc/tc_bl2_dpe.c

@@ -7,9 +7,9 @@
 #include <stdint.h>
 
 #include <common/debug.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
@@ -211,9 +211,9 @@
 
 void bl2_plat_mboot_init(void)
 {
-	/* Initialize the communication channel between AP and RSS */
-	(void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
-			     PLAT_RSS_AP_RCV_MHU_BASE);
+	/* Initialize the communication channel between AP and RSE */
+	(void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+			     PLAT_RSE_AP_RCV_MHU_BASE);
 
 	dpe_init(tc_dpe_metadata);
 }

diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c
index fd80fdc..add871c 100644
--- a/plat/arm/board/tc/tc_bl2_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl2_measured_boot.c

@@ -6,9 +6,9 @@
 
 #include <stdint.h>
 
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
 #include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
 #include <tools_share/tbbr_oid.h>
 
 #include <plat/common/common_def.h>
@@ -17,7 +17,7 @@
 /* TC specific table with image IDs and metadata. Intentionally not a
  * const struct, some members might set by bootloaders during trusted boot.
  */
-struct rss_mboot_metadata tc_rss_mboot_metadata[] = {
+struct rse_mboot_metadata tc_rse_mboot_metadata[] = {
 	{
 		.id = BL31_IMAGE_ID,
 		.slot = U(9),
@@ -40,16 +40,16 @@
 		.pk_oid = SOC_FW_CONFIG_KEY_OID,
 		.lock_measurement = true },
 	{
-		.id = RSS_MBOOT_INVALID_ID }
+		.id = RSE_MBOOT_INVALID_ID }
 };
 
 void bl2_plat_mboot_init(void)
 {
-	/* Initialize the communication channel between AP and RSS */
-	(void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
-			     PLAT_RSS_AP_RCV_MHU_BASE);
+	/* Initialize the communication channel between AP and RSE */
+	(void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+			     PLAT_RSE_AP_RCV_MHU_BASE);
 
-	rss_measured_boot_init(tc_rss_mboot_metadata);
+	rse_measured_boot_init(tc_rse_mboot_metadata);
 }
 
 void bl2_plat_mboot_finish(void)

diff --git a/plat/arm/board/tc/tc_common_dpe.c b/plat/arm/board/tc/tc_common_dpe.c
index 42b5468..72ac673 100644
--- a/plat/arm/board/tc/tc_common_dpe.c
+++ b/plat/arm/board/tc/tc_common_dpe.c

@@ -9,7 +9,7 @@
 #include <stdint.h>
 
 #include <common/desc_image_load.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
 
 extern struct dpe_metadata tc_dpe_metadata[];
 
@@ -17,7 +17,7 @@
 {
 	int err;
 
-	/* Calculate image hash and record it in the DPE service in RSS. */
+	/* Calculate image hash and record it in the DPE service in RSE. */
 	err = dpe_measure_and_record(tc_dpe_metadata,
 				     image_data->image_base,
 				     image_data->image_size,

diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c
index 925a411..6b8d41a 100644
--- a/plat/arm/board/tc/tc_common_measured_boot.c
+++ b/plat/arm/board/tc/tc_common_measured_boot.c

@@ -8,22 +8,22 @@
 #include <stdint.h>
 
 #include <common/desc_image_load.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
 
-extern struct rss_mboot_metadata tc_rss_mboot_metadata[];
+extern struct rse_mboot_metadata tc_rse_mboot_metadata[];
 
 int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
 {
 	int err;
 
-	/* Calculate image hash and record data in RSS */
-	err = rss_mboot_measure_and_record(tc_rss_mboot_metadata,
+	/* Calculate image hash and record data in RSE */
+	err = rse_mboot_measure_and_record(tc_rse_mboot_metadata,
 					   image_data->image_base,
 					   image_data->image_size,
 					   image_id);
 	if (err != 0) {
 		ERROR("%s%s image id %u (%i)\n",
-		      "Failed to ", "record in RSS", image_id, err);
+		      "Failed to ", "record in RSE", image_id, err);
 	}
 
 	return err;
@@ -31,6 +31,6 @@
 
 int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
 {
-	return rss_mboot_set_signer_id(tc_rss_mboot_metadata, pk_oid, pk_ptr,
+	return rse_mboot_set_signer_id(tc_rse_mboot_metadata, pk_oid, pk_ptr,
 				       pk_len);
 }

diff --git a/plat/arm/board/tc/tc_dpe_cert.h b/plat/arm/board/tc/tc_dpe_cert.h
index 25855ec..d0632e8 100644
--- a/plat/arm/board/tc/tc_dpe_cert.h
+++ b/plat/arm/board/tc/tc_dpe_cert.h

@@ -20,10 +20,10 @@
  *     RoT Cert.       |                          |     |                +->TOS_FW_CONF  |     |                    |
  *  +------------+     |      +->SCP_BL1    +-----+-----+-->FW_CONF      +->AP_BL32      |     |     +->PVMFW       |
  *  |            |     |      |             |     |     |                |               |     |     |              |
- *  | RSS_BL1_2--+-----+-->RSS_BL2------->AP_BL1--+-----+------------->AP_BL2------------+-----+-->AP_BL33          |
+ *  | RSE_BL1_2--+-----+-->RSE_BL2------->AP_BL1--+-----+------------->AP_BL2------------+-----+-->AP_BL33          |
  *  |            |     |      |             |     |     |                |               |     |     |              |
- *  +------------+     |      +->RSS_S      +-----+-----+-->TB_FW_CONF   +->AP_BL31      |     |     +->HYPERVISOR  |
- *                     |      +->RSS_NS           |     |                +->SCP_BL2      |     |                    |
+ *  +------------+     |      +->RSE_S      +-----+-----+-->TB_FW_CONF   +->AP_BL31      |     |     +->HYPERVISOR  |
+ *                     |      +->RSE_NS           |     |                +->SCP_BL2      |     |                    |
  *                     |                          |     |                +->HW_CONF      |     |                    |
  *                     +--------------------------+     |                +---------------+-----+-->NT_FW_CONF       |
  *                                                      |                                |     |                    |

diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index e5d05c4..fed14f7 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c

@@ -165,7 +165,7 @@
 
 static sds_region_desc_t tc_sds_regions[] = {
 	{ .base = PLAT_ARM_SDS_MEM_BASE },
-	{ .base = PLAT_ARM_RSS_AP_SDS_MEM_BASE },
+	{ .base = PLAT_ARM_RSE_AP_SDS_MEM_BASE },
 };
 
 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)

diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index feff691..f043f59 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,9 @@
 #include <common/debug.h>
 #include <lib/fconf/fconf.h>
 #include <lib/fconf/fconf_dyn_cfg_getter.h>
+#if TRANSFER_LIST
+#include <lib/transfer_list.h>
+#endif
 #include <lib/utils.h>
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/arm/common/plat_arm.h>
@@ -61,6 +64,10 @@
 /* Boolean variable to hold condition whether firmware update needed or not */
 static bool is_fwu_needed;
 
+#if TRANSFER_LIST
+static struct transfer_list_header *secure_tl;
+#endif
+
 struct meminfo *bl1_plat_sec_mem_layout(void)
 {
 	return &bl1_tzram_layout;
@@ -144,9 +151,13 @@
  */
 void arm_bl1_platform_setup(void)
 {
-	const struct dyn_cfg_dtb_info_t *fw_config_info;
+	const struct dyn_cfg_dtb_info_t *config_info __unused;
+	uint32_t fw_config_max_size __unused;
+	image_info_t config_image_info __unused;
+	struct transfer_list_entry *te __unused;
+
 	image_desc_t *desc;
-	uint32_t fw_config_max_size;
+
 	int err = -1;
 
 	/* Initialise the IO layer and register platform IO devices */
@@ -159,6 +170,37 @@
 		return;
 	}
 
+#if TRANSFER_LIST
+	secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
+				       PLAT_ARM_FW_HANDOFF_SIZE);
+
+	if (secure_tl == NULL) {
+		ERROR("Secure transfer list initialisation failed!\n");
+		panic();
+	}
+
+	te = transfer_list_add(secure_tl, TL_TAG_TB_FW_CONFIG,
+			       ARM_TB_FW_CONFIG_MAX_SIZE, NULL);
+	assert(te != NULL);
+
+	/*
+	 * Set the load address of TB_FW_CONFIG in the data section of the TE just
+	 * allocated in the secure transfer list.
+	 */
+	SET_PARAM_HEAD(&config_image_info, PARAM_IMAGE_BINARY, VERSION_2, 0);
+	config_image_info.image_base = (uintptr_t)transfer_list_entry_data(te);
+	config_image_info.image_max_size = te->data_size;
+
+	VERBOSE("FCONF: Loading config with image ID: %u\n", TB_FW_CONFIG_ID);
+	err = load_auth_image(TB_FW_CONFIG_ID, &config_image_info);
+	if (err != 0) {
+		VERBOSE("Failed to load config %u\n", TB_FW_CONFIG_ID);
+		plat_error_handler(err);
+	}
+
+	transfer_list_update_checksum(secure_tl);
+	fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te));
+#else
 	/* Set global DTB info for fixed fw_config information */
 	fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
 	set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
@@ -174,13 +216,14 @@
 	 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
 	 * is successful then load TB_FW_CONFIG device tree.
 	 */
-	fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
-	if (fw_config_info != NULL) {
-		err = fconf_populate_dtb_registry(fw_config_info->config_addr);
+	config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+	if (config_info != NULL) {
+		err = fconf_populate_dtb_registry(config_info->config_addr);
 		if (err < 0) {
 			ERROR("Parsing of FW_CONFIG failed %d\n", err);
 			plat_error_handler(err);
 		}
+
 		/* load TB_FW_CONFIG */
 		err = fconf_load_config(TB_FW_CONFIG_ID);
 		if (err < 0) {
@@ -191,11 +234,17 @@
 		ERROR("Invalid FW_CONFIG address\n");
 		plat_error_handler(err);
 	}
+#endif /* TRANSFER_LIST */
 
-	/* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
 	desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+
+#if TRANSFER_LIST
+	transfer_list_set_handoff_args(secure_tl, &desc->ep_info);
+#else
+	/* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
 	assert(desc != NULL);
-	desc->ep_info.args.arg0 = fw_config_info->config_addr;
+	desc->ep_info.args.arg0 = config_info->config_addr;
+#endif /* TRANSFER_LIST */
 
 #if CRYPTO_SUPPORT
 	/* Share the Mbed TLS heap info with other images */
@@ -250,3 +299,32 @@
 {
 	return  is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
 }
+
+// Use the default implementation of this function when Firmware Handoff is
+// disabled to avoid duplicating its logic.
+#if TRANSFER_LIST
+int bl1_plat_handle_post_image_load(unsigned int image_id)
+{
+	image_desc_t *image_desc __unused;
+
+	assert(image_id == BL2_IMAGE_ID);
+	struct transfer_list_entry *te;
+
+	/* Convey this information to BL2 via its TL. */
+	te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT64,
+			       sizeof(meminfo_t), NULL);
+	assert(te != NULL);
+
+	bl1_plat_calc_bl2_layout(&bl1_tzram_layout,
+				 (meminfo_t *)transfer_list_entry_data(te));
+
+	transfer_list_update_checksum(secure_tl);
+
+	/**
+	 * Before exiting make sure the contents of the TL are flushed in case there's no
+	 * support for hardware cache coherency.
+	 */
+	flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
+	return 0;
+}
+#endif /* TRANSFER_LIST*/

diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 30d0647..877ae8f 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c

@@ -19,6 +19,9 @@
 #include <lib/fconf/fconf.h>
 #include <lib/fconf/fconf_dyn_cfg_getter.h>
 #include <lib/gpt_rme/gpt_rme.h>
+#if TRANSFER_LIST
+#include <lib/transfer_list.h>
+#endif
 #ifdef SPD_opteed
 #include <lib/optee_utils.h>
 #endif
@@ -30,13 +33,18 @@
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
 
 /* Base address of fw_config received from BL1 */
-static uintptr_t config_base;
+static uintptr_t config_base __unused;
 
 /*
  * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
  * for `meminfo_t` data structure and fw_configs passed from BL1.
  */
+#if TRANSFER_LIST
+CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE,
+	assert_bl2_base_overflows);
+#else
 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
+#endif /* TRANSFER_LIST */
 
 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak bl2_early_platform_setup2
@@ -58,6 +66,9 @@
 
 #pragma weak arm_bl2_plat_handle_post_image_load
 
+static struct transfer_list_header *secure_tl __unused;
+static struct transfer_list_header *ns_tl __unused;
+
 /*******************************************************************************
  * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
  * in x0. This memory layout is sitting at the base of the free trusted SRAM.
@@ -66,16 +77,28 @@
 void arm_bl2_early_platform_setup(uintptr_t fw_config,
 				  struct meminfo *mem_layout)
 {
+	struct transfer_list_entry *te __unused;
 	int __maybe_unused ret;
 
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();
 
-	/* Setup the BL2 memory layout */
-	bl2_tzram_layout = *mem_layout;
+#if TRANSFER_LIST
+	// TODO: modify the prototype of this function fw_config != bl2_tl
+	secure_tl = (struct transfer_list_header *)fw_config;
 
+	te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64);
+	assert(te != NULL);
+
+	bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te);
+	transfer_list_rem(secure_tl, te);
+#else
 	config_base = fw_config;
 
+	/* Setup the BL2 memory layout */
+	bl2_tzram_layout = *mem_layout;
+#endif
+
 	/* Initialise the IO layer and register platform IO devices */
 	plat_arm_io_setup();
 
@@ -103,7 +126,22 @@
  */
 void bl2_plat_preload_setup(void)
 {
+#if TRANSFER_LIST
+/* Assume the secure TL hasn't been initialised if BL2 is running at EL3. */
+#if RESET_TO_BL2
+	secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
+				       PLAT_ARM_FW_HANDOFF_SIZE);
+
+	if (secure_tl == NULL) {
+		ERROR("Secure transfer list initialisation failed!\n");
+		panic();
+	}
+#endif
+
+	arm_transfer_list_dyn_cfg_init(secure_tl);
+#else
 	arm_bl2_dyn_cfg_init();
+#endif
 
 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
 	/* Always use the FIP from bank 0 */
@@ -124,6 +162,16 @@
 #if defined(PLAT_ARM_MEM_PROT_ADDR)
 	arm_nor_psci_do_static_mem_protect();
 #endif
+
+#if TRANSFER_LIST
+	ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE,
+				   PLAT_ARM_FW_HANDOFF_SIZE);
+
+	if (ns_tl == NULL) {
+		ERROR("Non-secure transfer list initialisation failed!");
+		panic();
+	}
+#endif
 }
 
 void bl2_platform_setup(void)
@@ -151,11 +199,13 @@
 		ARM_MAP_ROMLIB_CODE,
 		ARM_MAP_ROMLIB_DATA,
 #endif
+#if !TRANSFER_LIST
 		ARM_MAP_BL_CONFIG_REGION,
+#endif /* TRANSFER_LIST */
 #if ENABLE_RME
 		ARM_MAP_L0_GPT_REGION,
 #endif
-		{0}
+		{ 0 }
 	};
 
 #if ENABLE_RME
@@ -184,10 +234,17 @@
 
 void bl2_plat_arch_setup(void)
 {
-	const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
-
+	const struct dyn_cfg_dtb_info_t *tb_fw_config_info __unused;
+	struct transfer_list_entry *te __unused;
 	arm_bl2_plat_arch_setup();
 
+#if TRANSFER_LIST
+	te = transfer_list_find(secure_tl, TL_TAG_TB_FW_CONFIG);
+	assert(te != NULL);
+
+	fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te));
+	transfer_list_rem(secure_tl, te);
+#else
 	/* Fill the properties struct with the info from the config dtb */
 	fconf_populate("FW_CONFIG", config_base);
 
@@ -196,6 +253,7 @@
 	assert(tb_fw_config_info != NULL);
 
 	fconf_populate("TB_FW", tb_fw_config_info->config_addr);
+#endif
 }
 
 int arm_bl2_handle_post_image_load(unsigned int image_id)
@@ -265,5 +323,20 @@
 		return 0;
 	}
 #endif
+
+#if TRANSFER_LIST
+	if (image_id == HW_CONFIG_ID) {
+		arm_transfer_list_copy_hw_config(secure_tl, ns_tl);
+	}
+#endif /* TRANSFER_LIST */
+
 	return arm_bl2_handle_post_image_load(image_id);
 }
+
+void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node)
+{
+	assert(transfer_list_set_handoff_args(
+		       secure_tl, &next_param_node->ep_info) != NULL);
+
+	arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl);
+}

diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 33043b7..414ac40 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c

@@ -13,13 +13,18 @@
 #include <drivers/console.h>
 #include <lib/debugfs.h>
 #include <lib/extensions/ras.h>
+#include <lib/fconf/fconf.h>
 #include <lib/gpt_rme/gpt_rme.h>
 #include <lib/mmio.h>
+#if TRANSFER_LIST
+#include <lib/transfer_list.h>
+#endif
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
 
+static struct transfer_list_header *secure_tl __unused;
 /*
  * Placeholder variables for copying the arguments that have been passed to
  * BL31 from BL2.
@@ -35,8 +40,12 @@
  * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
  * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
  */
+#if TRANSFER_LIST
+CASSERT(BL31_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl31_base_overflows);
+#else
 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
-#endif
+#endif /* TRANSFER_LIST */
+#endif /* RESET_TO_BL31 */
 
 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak bl31_early_platform_setup2
@@ -115,6 +124,44 @@
  * while creating page tables. BL2 has flushed this information to memory, so
  * we are guaranteed to pick up good data.
  ******************************************************************************/
+#if TRANSFER_LIST
+void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
+					  u_register_t arg2, u_register_t arg3)
+{
+	struct transfer_list_entry *te = NULL;
+	struct entry_point_info *ep;
+
+	secure_tl = (struct transfer_list_header *)arg3;
+
+	/*
+	 * Populate the global entry point structures used to execute subsequent
+	 * images.
+	 */
+	while ((te = transfer_list_next(secure_tl, te)) != NULL) {
+		ep = transfer_list_entry_data(te);
+
+		if (te->tag_id == TL_TAG_EXEC_EP_INFO64) {
+			switch (GET_SECURITY_STATE(ep->h.attr)) {
+			case NON_SECURE:
+				bl33_image_ep_info = *ep;
+				break;
+#if ENABLE_RME
+			case REALM:
+				rmm_image_ep_info = *ep;
+				break;
+#endif
+			case SECURE:
+				bl32_image_ep_info = *ep;
+				break;
+			default:
+				ERROR("Unrecognized Image Security State %lu\n",
+				      GET_SECURITY_STATE(ep->h.attr));
+				panic();
+			}
+		}
+	}
+}
+#else
 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
 				uintptr_t hw_config, void *plat_params_from_bl2)
 {
@@ -258,11 +305,16 @@
 	bl33_image_ep_info.args.arg3 = 0U;
 # endif
 }
+#endif
 
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3)
 {
+#if TRANSFER_LIST
+	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
+#else
 	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+#endif
 
 	/*
 	 * Initialize Interconnect for this cluster during cold boot.
@@ -448,5 +500,15 @@
 
 void __init bl31_plat_arch_setup(void)
 {
+	struct transfer_list_entry *te __unused;
+
 	arm_bl31_plat_arch_setup();
+
+#if TRANSFER_LIST && !RESET_TO_BL2
+	te = transfer_list_find(secure_tl, TL_TAG_FDT);
+	assert(te != NULL);
+
+	/* Populate HW_CONFIG device tree with the mapped address */
+	fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te));
+#endif
 }

diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 5084ea9..7ab39eb 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -299,6 +299,10 @@
 				plat/arm/common/arm_topology.c			\
 				plat/common/plat_psci_common.c
 
+ifeq (${TRANSFER_LIST}, 1)
+	TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c
+endif
+
 ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
 ARM_SVC_HANDLER_SRCS :=
 

diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index c411c6c..2525266 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,10 @@
 #pragma weak plat_get_bl_image_load_info
 #pragma weak plat_get_next_bl_params
 
-static bl_params_t *next_bl_params_cpy_ptr;
+#if TRANSFER_LIST
+static bl_params_t next_bl_params_cpy;
+#endif
+bl_params_t *next_bl_params_cpy_ptr;
 
 /*******************************************************************************
  * This function flushes the data structures so that they are visible
@@ -96,9 +99,15 @@
  ******************************************************************************/
 struct bl_params *arm_get_next_bl_params(void)
 {
-	bl_mem_params_node_t *bl2_mem_params_descs_cpy
-			= (bl_mem_params_node_t *)ARM_BL2_MEM_DESC_BASE;
-	const bl_params_t *next_bl_params;
+	bl_mem_params_node_t *bl2_mem_params_descs_cpy __unused;
+	const bl_params_t *next_bl_params __unused;
+
+#if TRANSFER_LIST
+	next_bl_params_cpy_ptr = &next_bl_params_cpy;
+	SET_PARAM_HEAD(next_bl_params_cpy_ptr, PARAM_BL_PARAMS, VERSION_2, 0U);
+#else
+	bl2_mem_params_descs_cpy =
+		(bl_mem_params_node_t *)ARM_BL2_MEM_DESC_BASE;
 
 	next_bl_params_cpy_ptr =
 		(bl_params_t *)(ARM_BL2_MEM_DESC_BASE +
@@ -127,6 +136,7 @@
 						(sizeof(bl_params_t)));
 
 	populate_next_bl_params_config(next_bl_params_cpy_ptr);
+#endif /* TRANSFER_LIST */
 
 	return next_bl_params_cpy_ptr;
 }

diff --git a/plat/arm/common/arm_transfer_list.c b/plat/arm/common/arm_transfer_list.c
new file mode 100644
index 0000000..d144bbb
--- /dev/null
+++ b/plat/arm/common/arm_transfer_list.c

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl)
+{
+	struct transfer_list_entry *te;
+	bl_mem_params_node_t *next_param_node =
+		get_bl_mem_params_node(HW_CONFIG_ID);
+	assert(next_param_node != NULL);
+
+	/*
+	 * The HW_CONFIG needs to be authenticated via the normal loading
+	 * mechanism. Pre-allocate a TE for the configuration and update the
+	 * load information so the configuration is loaded directly into the TE.
+	 */
+	te = transfer_list_add(secure_tl, TL_TAG_FDT, PLAT_ARM_HW_CONFIG_SIZE,
+			       NULL);
+	assert(te != NULL);
+
+	next_param_node->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
+	next_param_node->image_info.image_max_size = PLAT_ARM_HW_CONFIG_SIZE;
+	next_param_node->image_info.image_base =
+		(uintptr_t)transfer_list_entry_data(te);
+}
+
+void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
+					struct transfer_list_header *secure_tl,
+					struct transfer_list_header *ns_tl)
+{
+	uint32_t next_exe_img_id;
+	entry_point_info_t *ep;
+	struct transfer_list_entry *te;
+
+	assert(next_param_node != NULL);
+
+	while ((next_exe_img_id = next_param_node->next_handoff_image_id) !=
+	       INVALID_IMAGE_ID) {
+		next_param_node =
+			&bl_mem_params_desc_ptr[get_bl_params_node_index(
+				next_exe_img_id)];
+		assert(next_param_node != NULL);
+
+		te = transfer_list_add(secure_tl, TL_TAG_EXEC_EP_INFO64,
+				       sizeof(entry_point_info_t),
+				       &next_param_node->ep_info);
+		assert(te != NULL);
+
+		ep = transfer_list_entry_data(te);
+
+		if (next_exe_img_id == BL33_IMAGE_ID) {
+			ep = transfer_list_set_handoff_args(ns_tl, ep);
+			assert(ep != NULL);
+		} else if ((next_exe_img_id == BL32_IMAGE_ID) && SPMC_AT_EL3) {
+			/*
+			 * Populate the BL32 image base, size and max limit in
+			 * the entry point information, since there is no
+			 * platform function to retrieve them in generic
+			 * code. We choose arg2, arg3 and arg4 since the generic
+			 * code uses arg1 for stashing the SP manifest size. The
+			 * SPMC setup uses these arguments to update SP manifest
+			 * with actual SP's base address and it size.
+			 */
+			ep->args.arg2 = next_param_node->image_info.image_base;
+			ep->args.arg3 = next_param_node->image_info.image_size;
+			ep->args.arg4 =
+				next_param_node->image_info.image_base +
+				next_param_node->image_info.image_max_size;
+		}
+
+		next_exe_img_id = next_param_node->next_handoff_image_id;
+	}
+
+	flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
+}
+
+void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl,
+				      struct transfer_list_header *ns_tl)
+{
+	struct transfer_list_entry *te =
+		transfer_list_find(secure_tl, TL_TAG_FDT);
+	assert(te != NULL);
+
+	/* Refresh the now stale checksum following loading of HW_CONFIG into the TL. */
+	transfer_list_update_checksum(secure_tl);
+
+	/* Copy the hardware configuration to the non-secure TL. */
+	te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
+			       transfer_list_entry_data(te));
+	assert(te != NULL);
+}

diff --git a/plat/common/plat_bl1_common.c b/plat/common/plat_bl1_common.c
index bcf9f89..ff0e082 100644
--- a/plat/common/plat_bl1_common.c
+++ b/plat/common/plat_bl1_common.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -80,10 +80,8 @@
  */
 int bl1_plat_handle_post_image_load(unsigned int image_id)
 {
-	meminfo_t *bl2_secram_layout;
-	meminfo_t *bl1_secram_layout;
+	meminfo_t *bl1_tzram_layout;
 	image_desc_t *image_desc;
-	entry_point_info_t *ep_info;
 
 	if (image_id != BL2_IMAGE_ID)
 		return 0;
@@ -92,26 +90,41 @@
 	image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
 	assert(image_desc != NULL);
 
-	/* Get the entry point info */
-	ep_info = &image_desc->ep_info;
-
 	/* Find out how much free trusted ram remains after BL1 load */
-	bl1_secram_layout = bl1_plat_sec_mem_layout();
+	bl1_tzram_layout = bl1_plat_sec_mem_layout();
 
 	/*
-	 * Create a new layout of memory for BL2 as seen by BL1 i.e.
-	 * tell it the amount of total and free memory available.
-	 * This layout is created at the first free address visible
-	 * to BL2. BL2 will read the memory layout before using its
-	 * memory for other purposes.
+	 * Convey this information to BL2 by storing the layout at the first free
+	 * address visible to BL2.
 	 */
-	bl2_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
+	bl1_plat_calc_bl2_layout(bl1_tzram_layout,
+				 (meminfo_t *)bl1_tzram_layout->total_base);
 
-	bl1_calc_bl2_mem_layout(bl1_secram_layout, bl2_secram_layout);
-
-	ep_info->args.arg1 = (uintptr_t)bl2_secram_layout;
+	image_desc->ep_info.args.arg1 = (uintptr_t)bl1_tzram_layout->total_base;
 
 	VERBOSE("BL1: BL2 memory layout address = %p\n",
-		(void *) bl2_secram_layout);
+		(void *)image_desc->ep_info.args.arg1);
+
 	return 0;
 }
+
+/*******************************************************************************
+ * Helper utility to calculate the BL2 memory layout taking into consideration
+ * the BL1 RW data assuming that it is at the top of the memory layout.
+ ******************************************************************************/
+void bl1_plat_calc_bl2_layout(const meminfo_t *bl1_mem_layout,
+			      meminfo_t *bl2_mem_layout)
+{
+	assert(bl1_mem_layout != NULL);
+	assert(bl2_mem_layout != NULL);
+
+	/*
+	 * Remove BL1 RW data from the scope of memory visible to BL2.
+	 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
+	 */
+	assert(BL1_RW_BASE > bl1_mem_layout->total_base);
+	bl2_mem_layout->total_base = bl1_mem_layout->total_base;
+	bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
+
+	flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
+}

diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
index 86c4b81..cb57668 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c

@@ -37,18 +37,8 @@
 
 int apusys_kernel_apusys_rv_setup_reviser(void)
 {
-	static bool apusys_rv_setup_reviser_called;
-
 	spin_lock(&apusys_rv_lock);
 
-	if (apusys_rv_setup_reviser_called) {
-		WARN(MODULE_TAG "%s: already initialized\n", __func__);
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	apusys_rv_setup_reviser_called = true;
-
 	mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
 	mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
 
@@ -74,18 +64,8 @@
 
 int apusys_kernel_apusys_rv_reset_mp(void)
 {
-	static bool apusys_rv_reset_mp_called;
-
 	spin_lock(&apusys_rv_lock);
 
-	if (apusys_rv_reset_mp_called) {
-		WARN(MODULE_TAG "%s: already initialized\n", __func__);
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	apusys_rv_reset_mp_called = true;
-
 	mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
 
 	dsb();
@@ -106,18 +86,8 @@
 
 int apusys_kernel_apusys_rv_setup_boot(void)
 {
-	static bool apusys_rv_setup_boot_called;
-
 	spin_lock(&apusys_rv_lock);
 
-	if (apusys_rv_setup_boot_called) {
-		WARN(MODULE_TAG "%s: already initialized\n", __func__);
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	apusys_rv_setup_boot_called = true;
-
 	mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
 
 	mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
@@ -130,55 +100,17 @@
 
 int apusys_kernel_apusys_rv_start_mp(void)
 {
-	static bool apusys_rv_start_mp_called;
-
 	spin_lock(&apusys_rv_lock);
-
-	if (apusys_rv_start_mp_called) {
-		WARN(MODULE_TAG "%s: already initialized\n", __func__);
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	apusys_rv_start_mp_called = true;
-
 	mmio_write_32(MD32_RUNSTALL, MD32_RUN);
-
 	spin_unlock(&apusys_rv_lock);
 
 	return 0;
 }
 
-static bool watch_dog_is_timeout(void)
-{
-	if (mmio_read_32(WDT_INT) != WDT_INT_W1C) {
-		ERROR(MODULE_TAG "%s: WDT does not timeout\n", __func__);
-		return false;
-	}
-	return true;
-}
-
 int apusys_kernel_apusys_rv_stop_mp(void)
 {
-	static bool apusys_rv_stop_mp_called;
-
 	spin_lock(&apusys_rv_lock);
-
-	if (apusys_rv_stop_mp_called) {
-		WARN(MODULE_TAG "%s: already initialized\n", __func__);
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	if (watch_dog_is_timeout() == false) {
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	apusys_rv_stop_mp_called = true;
-
 	mmio_write_32(MD32_RUNSTALL, MD32_STALL);
-
 	spin_unlock(&apusys_rv_lock);
 
 	return 0;
@@ -186,19 +118,10 @@
 
 int apusys_kernel_apusys_rv_setup_sec_mem(void)
 {
-	static bool apusys_rv_setup_sec_mem_called;
 	int ret;
 
 	spin_lock(&apusys_rv_lock);
 
-	if (apusys_rv_setup_sec_mem_called) {
-		WARN(MODULE_TAG "%s: already initialized\n", __func__);
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
-	apusys_rv_setup_sec_mem_called = true;
-
 	ret = set_apu_emi_mpu_region();
 	if (ret != 0) {
 		ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__);
@@ -230,12 +153,6 @@
 int apusys_kernel_apusys_rv_cg_gating(void)
 {
 	spin_lock(&apusys_rv_lock);
-
-	if (watch_dog_is_timeout() == false) {
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
 	mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
 	spin_unlock(&apusys_rv_lock);
 
@@ -245,12 +162,6 @@
 int apusys_kernel_apusys_rv_cg_ungating(void)
 {
 	spin_lock(&apusys_rv_lock);
-
-	if (watch_dog_is_timeout() == false) {
-		spin_unlock(&apusys_rv_lock);
-		return -1;
-	}
-
 	mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
 	spin_unlock(&apusys_rv_lock);
 

diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
index da5242a..f4ff763 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c

@@ -271,15 +271,8 @@
 
 int apusys_devapc_rcx_init(void)
 {
-	static bool apusys_devapc_rcx_init_called;
 	enum apusys_apc_err_status ret;
 
-	if (apusys_devapc_rcx_init_called == true) {
-		INFO(MODULE_TAG "%s: init more than once!\n", __func__);
-		return -1;
-	}
-	apusys_devapc_rcx_init_called = true;
-
 	apusys_devapc_init("APUAPC_CTRL_RCX", APU_CTRL_DAPC_RCX_BASE);
 	apusys_devapc_init("APUAPC_NOC_RCX", APU_NOC_DAPC_RCX_BASE);
 

diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index 16187ef..ed95bc6 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk

@@ -88,8 +88,8 @@
 #
 # We go v8.0 by default and will enable all features we want
 
-ARM_ARCH_MAJOR		:=	8
-ARM_ARCH_MINOR		:=	0
+ARM_ARCH_MAJOR		?=	8
+ARM_ARCH_MINOR		?=	0
 
 # 8.0
 ENABLE_FEAT_CSV2_2	:=	2
@@ -106,6 +106,7 @@
 # 8.4
 ENABLE_FEAT_SEL2	:=	2
 ENABLE_FEAT_DIT		:=	2
+ENABLE_TRF_FOR_NS	:=	2
 
 # 8.5
 ENABLE_FEAT_RNG		:=	2
@@ -114,6 +115,7 @@
 ENABLE_FEAT_SB		:=	0
 
 # 8.6
+ENABLE_FEAT_ECV		:=	2
 ENABLE_FEAT_FGT		:=	2
 
 # 8.7

diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index a627ed7..0a70cc2 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c

@@ -161,7 +161,7 @@
 
 unsigned int plat_get_syscnt_freq2(void)
 {
-	return SYS_COUNTER_FREQ_IN_TICKS;
+	return read_cntfrq_el0();
 }
 
 /*******************************************************************************

diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index cafee6f..068c69c 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c

@@ -5,6 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <string.h>
+
 #include <platform_def.h>
 
 #include <arch_helpers.h>
@@ -226,46 +228,76 @@
 	uint64_t checksum;
 	uintptr_t base;
 	uint64_t size;
+	size_t num_banks = 1;
+	size_t num_consoles = 1;
 	struct ns_dram_bank *bank_ptr;
+	struct console_info *console_ptr;
 
 	assert(manifest != NULL);
 
 	manifest->version = RMMD_MANIFEST_VERSION;
 	manifest->padding = 0U; /* RES0 */
 	manifest->plat_data = (uintptr_t)NULL;
-	manifest->plat_dram.num_banks = 1;
+	manifest->plat_dram.num_banks = num_banks;
+	manifest->plat_console.num_consoles = num_consoles;
 
 	/*
-	 * Array ns_dram_banks[] follows ns_dram_info structure:
+	 * Boot manifest structure illustration:
 	 *
-	 * +-----------------------------------+
-	 * |  offset  |   field   |  comment   |
-	 * +----------+-----------+------------+
-	 * |    0     |  version  | 0x00000002 |
-	 * +----------+-----------+------------+
-	 * |    4     |  padding  | 0x00000000 |
-	 * +----------+-----------+------------+
-	 * |    8     | plat_data |    NULL    |
-	 * +----------+-----------+------------+
-	 * |    16    | num_banks |            |
-	 * +----------+-----------+            |
-	 * |    24    |   banks   | plat_dram  |
-	 * +----------+-----------+            |
-	 * |    32    | checksum  |            |
-	 * +----------+-----------+------------+
-	 * |    40    |  base 0   |            |
-	 * +----------+-----------+   bank[0]  |
-	 * |    48    |  size 0   |            |
-	 * +----------+-----------+------------+
+	 * +----------------------------------------+
+	 * |  offset  |   field      |  comment     |
+	 * +----------+--------------+--------------+
+	 * |    0     |  version     | 0x00000003   |
+	 * +----------+--------------+--------------+
+	 * |    4     |  padding     | 0x00000000   |
+	 * +----------+--------------+--------------+
+	 * |    8     | plat_data    |    NULL      |
+	 * +----------+--------------+--------------+
+	 * |    16    | num_banks    |              |
+	 * +----------+--------------+              |
+	 * |    24    |   banks      | plat_dram    |
+	 * +----------+--------------+              |
+	 * |    32    | checksum     |              |
+	 * +----------+--------------+--------------+
+	 * |    40    | num_consoles |              |
+	 * +----------+--------------+              |
+	 * |    48    | consoles     | plat_console |
+	 * +----------+--------------+              |
+	 * |    56    | checksum     |              |
+	 * +----------+--------------+--------------+
+	 * |    64    |  base 0      |              |
+	 * +----------+--------------+   bank[0]    |
+	 * |    72    |  size 0      |              |
+	 * +----------+--------------+--------------+
+	 * |    80    |  base        |              |
+	 * +----------+--------------+              |
+	 * |    88    |  map_pages   |              |
+	 * +----------+--------------+              |
+	 * |    96    |  name        |              |
+	 * +----------+--------------+  consoles[0] |
+	 * |   104    |  clk_in_hz   |              |
+	 * +----------+--------------+              |
+	 * |   112    |  baud_rate   |              |
+	 * +----------+--------------+              |
+	 * |   120    |  flags       |              |
+	 * +----------+--------------+--------------+
 	 */
 	bank_ptr = (struct ns_dram_bank *)
-			((uintptr_t)&manifest->plat_dram.checksum +
-			sizeof(manifest->plat_dram.checksum));
+		(((uintptr_t)manifest) + sizeof(*manifest));
+
+	console_ptr = (struct console_info *)
+		((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
 
 	manifest->plat_dram.banks = bank_ptr;
+	manifest->plat_console.consoles = console_ptr;
+
+	/* Ensure the manifest is not larger than the shared buffer */
+	assert((sizeof(struct rmm_manifest) +
+		(sizeof(struct console_info) * num_consoles) +
+		(sizeof(struct ns_dram_bank) * num_banks)) <= RMM_SHARED_SIZE);
 
 	/* Calculate checksum of plat_dram structure */
-	checksum = 1 + (uint64_t)bank_ptr;
+	checksum = num_banks + (uint64_t)bank_ptr;
 
 	base = NS_DRAM0_BASE;
 	size = NS_DRAM0_SIZE;
@@ -276,6 +308,26 @@
 	/* Checksum must be 0 */
 	manifest->plat_dram.checksum = ~checksum + 1UL;
 
+	/* Calculate the checksum of the plat_consoles structure */
+	checksum = num_consoles + (uint64_t)console_ptr;
+
+	/* Zero out the console info struct */
+	memset((void *)console_ptr, 0, sizeof(struct console_info) * num_consoles);
+
+	console_ptr[0].map_pages = 1;
+	console_ptr[0].base = PLAT_QEMU_BOOT_UART_BASE;
+	console_ptr[0].clk_in_hz = PLAT_QEMU_BOOT_UART_CLK_IN_HZ;
+	console_ptr[0].baud_rate = PLAT_QEMU_CONSOLE_BAUDRATE;
+
+	strlcpy(console_ptr[0].name, "pl011", sizeof(console_ptr[0].name));
+
+	/* Update checksum */
+	checksum += console_ptr[0].base + console_ptr[0].map_pages +
+		console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+
+	/* Checksum must be 0 */
+	manifest->plat_console.checksum = ~checksum + 1UL;
+
 	return 0;
 }
 #endif  /* ENABLE_RME */

diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
index cf3376d..f7d7e90 100644
--- a/plat/qemu/common/qemu_plat_attest_token.c
+++ b/plat/qemu/common/qemu_plat_attest_token.c

@@ -98,7 +98,7 @@
 
 /*
  * Get the hardcoded platform attestation token as QEMU does not support
- * RSS.
+ * RSE.
  */
 int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
 				   uintptr_t hash, size_t hash_size)

diff --git a/plat/qemu/common/qemu_realm_attest_key.c b/plat/qemu/common/qemu_realm_attest_key.c
index abd569b..7da04d1 100644
--- a/plat/qemu/common/qemu_realm_attest_key.c
+++ b/plat/qemu/common/qemu_realm_attest_key.c

@@ -19,7 +19,7 @@
 
 /*
  * Get the hardcoded delegated realm attestation key as QEMU
- * does not support RSS.
+ * does not support RSE.
  */
 int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
 				       unsigned int type)

diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 4e0b50a..95620d3 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h

@@ -302,11 +302,6 @@
 #define PLAT_SDEI_SGI_PRIVATE		QEMU_IRQ_SEC_SGI_0
 
 /*
- * System counter
- */
-#define SYS_COUNTER_FREQ_IN_TICKS	((1000 * 1000 * 1000) / 16)
-
-/*
  * Maximum size of Event Log buffer used in Measured Boot Event Log driver
  */
 #define	PLAT_EVENT_LOG_MAX_SIZE		UL(0x400)

diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index e8f0344..d230095 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h

@@ -266,11 +266,6 @@
 #define PLAT_QEMU_DT_BASE		NS_DRAM0_BASE
 #define PLAT_QEMU_DT_MAX_SIZE		0x100000
 
-/*
- * System counter
- */
-#define SYS_COUNTER_FREQ_IN_TICKS	((1000 * 1000 * 1000) / 16)
-
 #if SPM_MM
 #define PLAT_QEMU_SP_IMAGE_BASE		BL_RAM_BASE
 #define PLAT_QEMU_SP_IMAGE_SIZE		ULL(0x300000)

diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index 83b001a..d6c0040 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c

@@ -87,6 +87,13 @@
 	uint32_t linear_id;
 	optee_context_t *optee_ctx;
 
+#if OPTEE_ALLOW_SMC_LOAD
+	if (optee_vector_table == NULL) {
+		/* OPTEE is not loaded yet, ignore this interrupt */
+		SMC_RET0(handle);
+	}
+#endif
+
 	/* Check the security state when the exception was generated */
 	assert(get_interrupt_src_ss(flags) == NON_SECURE);
 
@@ -115,6 +122,24 @@
 	SMC_RET1(&optee_ctx->cpu_ctx, read_elr_el3());
 }
 
+/*
+ * Registers an interrupt handler for S-EL1 interrupts when generated during
+ * code executing in the non-secure state. Panics if it fails to do so.
+ */
+static void register_opteed_interrupt_handler(void)
+{
+	u_register_t flags;
+	uint64_t rc;
+
+	flags = 0;
+	set_interrupt_rm_flag(flags, NON_SECURE);
+	rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
+			opteed_sel1_interrupt_handler,
+			flags);
+	if (rc)
+		panic();
+}
+
 /*******************************************************************************
  * OPTEE Dispatcher setup. The OPTEED finds out the OPTEE entrypoint and type
  * (aarch32/aarch64) if not already known and initialises the context for entry
@@ -125,6 +150,11 @@
 #if OPTEE_ALLOW_SMC_LOAD
 	opteed_allow_load = true;
 	INFO("Delaying OP-TEE setup until we receive an SMC call to load it\n");
+	/*
+	 * We must register the interrupt handler now so that the interrupt
+	 * priorities are not changed after starting the linux kernel.
+	 */
+	register_opteed_interrupt_handler();
 	return 0;
 #else
 	entry_point_info_t *optee_ep_info;
@@ -575,7 +605,6 @@
 	cpu_context_t *ns_cpu_context;
 	uint32_t linear_id = plat_my_core_pos();
 	optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
-	uint64_t rc;
 
 	/*
 	 * Determine which security state this SMC originated from
@@ -709,18 +738,9 @@
 			 */
 			psci_register_spd_pm_hook(&opteed_pm);
 
-			/*
-			 * Register an interrupt handler for S-EL1 interrupts
-			 * when generated during code executing in the
-			 * non-secure state.
-			 */
-			flags = 0;
-			set_interrupt_rm_flag(flags, NON_SECURE);
-			rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
-						opteed_sel1_interrupt_handler,
-						flags);
-			if (rc)
-				panic();
+#if !OPTEE_ALLOW_SMC_LOAD
+			register_opteed_interrupt_handler();
+#endif
 		}
 
 		/*

diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c
index 2513213..4a36ee8 100644
--- a/tools/cert_create/src/cert.c
+++ b/tools/cert_create/src/cert.c

@@ -22,7 +22,6 @@
 #include "sha.h"
 
 #define SERIAL_RAND_BITS	64
-#define RSA_SALT_LEN		32
 
 cert_t *certs;
 unsigned int num_certs;
@@ -152,7 +151,7 @@
 			goto END;
 		}
 
-		if (!EVP_PKEY_CTX_set_rsa_pss_saltlen(pKeyCtx, RSA_SALT_LEN)) {
+		if (!EVP_PKEY_CTX_set_rsa_pss_saltlen(pKeyCtx, EVP_MD_size(get_digest(md_alg)))) {
 			ERR_print_errors_fp(stdout);
 			goto END;
 		}

diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c
index 04214aa..f6ceeda 100644
--- a/tools/cert_create/src/key.c
+++ b/tools/cert_create/src/key.c

@@ -168,6 +168,7 @@
 	}
 }
 
+#if OPENSSL_VERSION_NUMBER >= 0x10100000L
 static int key_create_ecdsa_brainpool_r(key_t *key, int key_bits)
 {
 	return key_create_ecdsa(key, key_bits, NID_brainpoolP256r1);
@@ -177,6 +178,7 @@
 {
 	return key_create_ecdsa(key, key_bits, NID_brainpoolP256t1);
 }
+#endif
 #endif /* USING_OPENSSL3 */
 #endif /* OPENSSL_NO_EC */
 
@@ -185,8 +187,10 @@
 	[KEY_ALG_RSA] = key_create_rsa,
 #ifndef OPENSSL_NO_EC
 	[KEY_ALG_ECDSA_NIST] = key_create_ecdsa_nist,
+#if OPENSSL_VERSION_NUMBER >= 0x10100000L
 	[KEY_ALG_ECDSA_BRAINPOOL_R] = key_create_ecdsa_brainpool_r,
 	[KEY_ALG_ECDSA_BRAINPOOL_T] = key_create_ecdsa_brainpool_t,
+#endif
 #endif /* OPENSSL_NO_EC */
 };
 

diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index f10a768..14610ed 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c

@@ -85,8 +85,10 @@
 	[KEY_ALG_RSA] = "rsa",
 #ifndef OPENSSL_NO_EC
 	[KEY_ALG_ECDSA_NIST] = "ecdsa",
+#if OPENSSL_VERSION_NUMBER >= 0x10100000L
 	[KEY_ALG_ECDSA_BRAINPOOL_R] = "ecdsa-brainpool-regular",
 	[KEY_ALG_ECDSA_BRAINPOOL_T] = "ecdsa-brainpool-twisted",
+#endif
 #endif /* OPENSSL_NO_EC */
 };
 
@@ -269,8 +271,12 @@
 	},
 	{
 		{ "key-alg", required_argument, NULL, 'a' },
-		"Key algorithm: 'rsa' (default)- RSAPSS scheme as per PKCS#1 v2.1, " \
+		"Key algorithm: 'rsa' (default)- RSAPSS scheme as per PKCS#1 v2.1, "
+#if OPENSSL_VERSION_NUMBER >= 0x10100000L
 		"'ecdsa', 'ecdsa-brainpool-regular', 'ecdsa-brainpool-twisted'"
+#else
+		"'ecdsa'"
+#endif
 	},
 	{
 		{ "key-size", required_argument, NULL, 'b' },

diff --git a/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
index 903310b..792593f 100644
--- a/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
+++ b/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c

@@ -13,44 +13,44 @@
 
 toc_entry_t plat_def_toc_entries[] = {
 	{
-		.name = "RSS Firmware BL1_2 image",
-		.uuid = UUID_RSS_FIRMWARE_BL1_2,
-		.cmdline_name = "rss-bl1_2"
+		.name = "RSE Firmware BL1_2 image",
+		.uuid = UUID_RSE_FIRMWARE_BL1_2,
+		.cmdline_name = "rse-bl1_2"
 	},
 	{
-		.name = "RSS Firmware BL2 image",
-		.uuid = UUID_RSS_FIRMWARE_BL2,
-		.cmdline_name = "rss-bl2"
+		.name = "RSE Firmware BL2 image",
+		.uuid = UUID_RSE_FIRMWARE_BL2,
+		.cmdline_name = "rse-bl2"
 	},
 	{
-		.name = "RSS Firmware SCP BL1 image",
-		.uuid = UUID_RSS_FIRMWARE_SCP_BL1,
-		.cmdline_name = "rss-scp-bl1"
+		.name = "RSE Firmware SCP BL1 image",
+		.uuid = UUID_RSE_FIRMWARE_SCP_BL1,
+		.cmdline_name = "rse-scp-bl1"
 	},
 	{
-		.name = "RSS Firmware AP BL1 image",
-		.uuid = UUID_RSS_FIRMWARE_AP_BL1,
-		.cmdline_name = "rss-ap-bl1"
+		.name = "RSE Firmware AP BL1 image",
+		.uuid = UUID_RSE_FIRMWARE_AP_BL1,
+		.cmdline_name = "rse-ap-bl1"
 	},
 	{
-		.name = "RSS Firmware non-secure image",
-		.uuid = UUID_RSS_FIRMWARE_NS,
-		.cmdline_name = "rss-ns"
+		.name = "RSE Firmware non-secure image",
+		.uuid = UUID_RSE_FIRMWARE_NS,
+		.cmdline_name = "rse-ns"
 	},
 	{
-		.name = "RSS Firmware secure image",
-		.uuid = UUID_RSS_FIRMWARE_S,
-		.cmdline_name = "rss-s"
+		.name = "RSE Firmware secure image",
+		.uuid = UUID_RSE_FIRMWARE_S,
+		.cmdline_name = "rse-s"
 	},
 	{
-		.name = "RSS Firmware non-secure SIC tables",
-		.uuid = UUID_RSS_SIC_TABLES_NS,
-		.cmdline_name = "rss-sic-tables-ns"
+		.name = "RSE Firmware non-secure SIC tables",
+		.uuid = UUID_RSE_SIC_TABLES_NS,
+		.cmdline_name = "rse-sic-tables-ns"
 	},
 	{
-		.name = "RSS Firmware secure SIC tables",
-		.uuid = UUID_RSS_SIC_TABLES_S,
-		.cmdline_name = "rss-sic-tables-s"
+		.name = "RSE Firmware secure SIC tables",
+		.uuid = UUID_RSE_SIC_TABLES_S,
+		.cmdline_name = "rse-sic-tables-s"
 	},
 
 	{
commit	3465757b7f96990e9edb7274dec773b29d7cd9fb	[log] [tgz]
author	Joanna Farley <joanna.farley@arm.com>	Thu May 02 09:28:03 2024 +0200
committer	TrustedFirmware Code Review <review@review.trustedfirmware.org>	Thu May 02 09:28:03 2024 +0200
tree	e4d7d40470317469652b688cd5e0c03e0f5f1a04
parent	fa2c4000db45dc3b6503722bb22b5a860471a9f8 [diff]
parent	b8eca3b349578e40eb9675de1f395055cbdf07af [diff]