Merge "fix(cpus): workaround for Cortex-X4 erratum 2740089" into integration
diff --git a/Makefile b/Makefile
index 7058d57..6b1f47c 100644
--- a/Makefile
+++ b/Makefile
@@ -363,8 +363,8 @@
# Setup ARCH_MAJOR/MINOR before parsing arch_features.
################################################################################
ifeq (${ENABLE_RME},1)
- ARM_ARCH_MAJOR := 8
- ARM_ARCH_MINOR := 6
+ ARM_ARCH_MAJOR := 9
+ ARM_ARCH_MINOR := 2
endif
################################################################################
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index d25ec63..636aebe 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -116,6 +116,8 @@
ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
"BL1_RW_BASE address is not aligned on a page boundary.")
+ __RW_START__ = .;
+
DATA_SECTION >RAM AT>ROM
__DATA_RAM_START__ = __DATA_START__;
@@ -148,6 +150,8 @@
} >RAM
#endif /* USE_COHERENT_MEM */
+ __RW_END__ = .;
+
__BL1_RAM_START__ = ADDR(.data);
__BL1_RAM_END__ = .;
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index dbb646b..db0eafc 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -12,6 +12,7 @@
lib/cpus/${ARCH}/cpu_helpers.S \
lib/cpus/errata_report.c \
lib/el3_runtime/${ARCH}/context_mgmt.c \
+ lib/locks/exclusive/${ARCH}/spinlock.S \
plat/common/plat_bl1_common.c \
plat/common/${ARCH}/platform_up_stack.S \
${MBEDTLS_SOURCES}
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index d814104..a5fd1d6 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -68,6 +68,8 @@
+-----------------+---------------------------+------------------------------+
| v2.10 | 4th week of Nov '23 | 2nd week of Nov '23 |
+-----------------+---------------------------+------------------------------+
+| v2.11 | 4th week of May '24 | 2nd week of May '24 |
++-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
--------------------------------
@@ -99,6 +101,19 @@
| None at this time. | | | |
+--------------------------------+-------------+---------+---------------------------------------------------------+
+Build Options deprecated/removed
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Populated table provides details about build options that were removed or deprecated.
+
++-----------------------+--------------------------------+
+| Build Option | Deprecated from TF-A Version |
++=======================+================================+
+| CTX_INCLUDE_MTE_REGS | 2.11 |
++-----------------------+--------------------------------+
+| ENABLE_FEAT_MTE | 2.11 |
++-----------------------+--------------------------------+
+
--------------
*Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 5f0b5ab..5fbd7fd 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -53,7 +53,7 @@
consistency with the versioning schemes used in other parts of RMM.
This document specifies the 0.2 version of Boot Interface ABI and RMM-EL3
-services specification and the 0.2 version of the Boot Manifest.
+services specification and the 0.3 version of the Boot Manifest.
.. _rmm_el3_boot_interface:
@@ -182,17 +182,20 @@
This Boot Manifest is versioned independently of the Boot Interface, to help
evolve the former independent of the latter.
-The current version for the Boot Manifest is ``v0.2`` and the rules explained
+The current version for the Boot Manifest is ``v0.3`` and the rules explained
in :ref:`rmm_el3_ifc_versioning` apply on this version as well.
-The Boot Manifest v0.2 has the following fields:
+The Boot Manifest v0.3 has the following fields:
- - version : Version of the Manifest (v0.2)
+ - version : Version of the Manifest (v0.3)
- plat_data : Pointer to the platform specific data and not specified by this
document. These data are optional and can be NULL.
- plat_dram : Structure encoding the NS DRAM information on the platform. This
- field is also optional and platform can choose to zero out this structure if
+ field is optional and platform can choose to zero out this structure if
RMM does not need EL3 to send this information during the boot.
+ - plat_console : Structure encoding the list of consoles for RMM use on the
+ platform. This field is optional and platform can choose to not populate
+ the console list if this is not needed by the RMM for this platform.
For the current version of the Boot Manifest, the core manifest contains a pointer
to the platform data. EL3 must ensure that the whole Boot Manifest, including
@@ -533,23 +536,25 @@
RMM-EL3 Boot Manifest structure
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The RMM-EL3 Boot Manifest v0.2 structure contains platform boot information passed
-from EL3 to RMM. The size of the Boot Manifest is 40 bytes.
+The RMM-EL3 Boot Manifest v0.3 structure contains platform boot information passed
+from EL3 to RMM. The size of the Boot Manifest is 64 bytes.
The members of the RMM-EL3 Boot Manifest structure are shown in the following
table:
-+-----------+--------+----------------+----------------------------------------+
-| Name | Offset | Type | Description |
-+===========+========+================+========================================+
-| version | 0 | uint32_t | Boot Manifest version |
-+-----------+--------+----------------+----------------------------------------+
-| padding | 4 | uint32_t | Reserved, set to 0 |
-+-----------+--------+----------------+----------------------------------------+
-| plat_data | 8 | uintptr_t | Pointer to Platform Data section |
-+-----------+--------+----------------+----------------------------------------+
-| plat_dram | 16 | ns_dram_info | NS DRAM Layout Info structure |
-+-----------+--------+----------------+----------------------------------------+
++--------------+--------+----------------+----------------------------------------+
+| Name | Offset | Type | Description |
++==============+========+================+========================================+
+| version | 0 | uint32_t | Boot Manifest version |
++--------------+--------+----------------+----------------------------------------+
+| padding | 4 | uint32_t | Reserved, set to 0 |
++--------------+--------+----------------+----------------------------------------+
+| plat_data | 8 | uintptr_t | Pointer to Platform Data section |
++--------------+--------+----------------+----------------------------------------+
+| plat_dram | 16 | ns_dram_info | NS DRAM Layout Info structure |
++--------------+--------+----------------+----------------------------------------+
+| plat_console | 40 | console_list | List of consoles available to RMM |
++--------------+--------+----------------+----------------------------------------+
.. _ns_dram_info_struct:
@@ -587,5 +592,47 @@
| size | 8 | uint64_t | Size of bank in bytes |
+-----------+--------+----------------+----------------------------------------+
+.. _console_list_struct:
+
+Console List structure
+~~~~~~~~~~~~~~~~~~~~~~
+
+Console List structure contains information about the available consoles for RMM.
+The members of this structure are shown in the table below:
+
++--------------+--------+----------------+----------------------------------------+
+| Name | Offset | Type | Description |
++==============+========+================+========================================+
+| num_consoles | 0 | uint64_t | Number of consoles |
++--------------+--------+----------------+----------------------------------------+
+| consoles | 8 | console_info * | Pointer to 'console_info'[] array |
++--------------+--------+----------------+----------------------------------------+
+| checksum | 16 | uint64_t | Checksum |
++--------------+--------+----------------+----------------------------------------+
+
+Checksum is calculated as two's complement sum of 'num_consoles', 'consoles'
+pointer and the consoles array pointed by it.
+
+.. _console_info_struct:
+
+Console Info structure
+~~~~~~~~~~~~~~~~~~~~~~
+
+Console Info structure contains information about each Console available to RMM.
++-----------+--------+---------------+----------------------------------------+
+| Name | Offset | Type | Description |
++===========+========+===============+========================================+
+| base | 0 | uintptr_t | Console Base address |
++-----------+--------+---------------+----------------------------------------+
+| map_pages | 8 | uint64_t | Num of pages to map for console MMIO |
++-----------+--------+---------------+----------------------------------------+
+| name | 16 | char[] | Name of console |
++-----------+--------+---------------+----------------------------------------+
+| clk_in_hz | 24 | uint64_t | UART clock (in hz) for console |
++-----------+--------+---------------+----------------------------------------+
+| baud_rate | 32 | uint64_t | Baud rate |
++-----------+--------+---------------+----------------------------------------+
+| flags | 40 | uint64_t | Additional flags (RES0) |
++-----------+--------+---------------+----------------------------------------+
diff --git a/docs/components/romlib-design.rst b/docs/components/romlib-design.rst
index d34b3cc..62c173a 100644
--- a/docs/components/romlib-design.rst
+++ b/docs/components/romlib-design.rst
@@ -74,10 +74,10 @@
Script
~~~~~~
-There is a ``romlib_generate.py`` Python script that generates the necessary
+There is a ``romlib_generator.py`` Python script that generates the necessary
files for the "library at ROM" to work. It implements multiple functions:
-1. ``romlib_generate.py gentbl [args]`` - Generates the jump table by parsing
+1. ``romlib_generator.py gentbl [args]`` - Generates the jump table by parsing
the index file.
2. ``romlib_generator.py genvar [args]`` - Generates the jump table global
@@ -93,10 +93,10 @@
generate a dependency file of the included index files which can be directly
used in makefiles.
-Each ``romlib_generate.py`` function has its own manual which is accessible by
+Each ``romlib_generator.py`` function has its own manual which is accessible by
runing ``romlib_generator.py [function] --help``.
-``romlib_generate.py`` requires Python 3 environment.
+``romlib_generator.py`` requires Python 3 environment.
Patching of functions in library at ROM
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 9053e34..3498ac5 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -11,12 +11,11 @@
Build Host
----------
-|TF-A| can be built using either a Linux or a Windows machine as the build host.
+|TF-A| can be compiled on both Linux and Windows-based machines.
+However, we strongly recommend using a UNIX-compatible build environment.
-A relatively recent Linux distribution is recommended for building |TF-A|. We
-have performed tests using Ubuntu 22.04 LTS (64-bit) but other distributions
-should also work fine as a base, provided that the necessary tools and libraries
-can be installed.
+Testing is performed using Ubuntu 22.04 LTS (64-bit), but other distributions
+should also work, provided the necessary tools and libraries are installed.
.. _prerequisites_toolchain:
@@ -26,7 +25,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- TF-A has been tested with version 12.3.Rel1 (gcc 12.3) from the `Arm Developer website`_
+- TF-A has been tested with version 13.2.Rel1 (gcc 13.2) from the `Arm Developer website`_
You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for
AArch32 and AArch64 builds respectively.
@@ -43,10 +42,6 @@
reports are always welcome.
.. note::
- The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
- Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
-
-.. note::
For instructions on how to select the cross compiler refer to
:ref:`Performing an Initial Build`.
@@ -64,7 +59,7 @@
The following libraries must be available to build one or more components or
supporting tools:
-- OpenSSL >= 1.1.1 (v3.0.0 to v3.0.6 highly discouraged due to security issues)
+- OpenSSL >= 1.0.0 (1.0.x, v3.0.0 to v3.0.6 highly discouraged due to security issues)
Required to build the cert_create, encrypt_fw, and fiptool tools.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 35cc27d..12afa44 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -70,20 +70,10 @@
+----------------+----------------+--------------------+--------------------+
| Platform | Vendor | Deprecated version | Deleted version |
+================+================+====================+====================+
-| sgm775 | Arm | 2.5 | 2.7 |
-+----------------+----------------+--------------------+--------------------+
-| mt6795 | MTK | 2.5 | 2.7 |
-+----------------+----------------+--------------------+--------------------+
| sgi575 | Arm | 2.8 | TBD |
+----------------+----------------+--------------------+--------------------+
| rdn1edge | Arm | 2.8 | TBD |
+----------------+----------------+--------------------+--------------------+
-| tc0 | Arm | 2.8 | 2.10 |
-+----------------+----------------+--------------------+--------------------+
-| tc1 | Arm | 2.10 | TBD |
-+----------------+----------------+--------------------+--------------------+
-| rde1edge | Arm | 2.9 | 2.11 |
-+----------------+----------------+--------------------+--------------------+
--------------
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index ee86b7e..5508ebb 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -131,7 +131,6 @@
#define MPAMVPM6_EL2 S3_4_C10_C6_6
#define MPAMVPM7_EL2 S3_4_C10_C6_7
#define MPAMVPMV_EL2 S3_4_C10_C4_1
-#define TRFCR_EL2 S3_4_C1_C2_1
#define VNCR_EL2 S3_4_C2_C2_0
#define PMSCR_EL2 S3_4_C9_C9_0
#define TFSR_EL2 S3_4_C5_C6_0
@@ -1337,6 +1336,8 @@
#define GPTBR_EL3 S3_6_C2_C1_4
#define SCXTNUM_EL2 S3_4_C13_C0_7
+#define SCXTNUM_EL1 S3_0_C13_C0_7
+#define SCXTNUM_EL0 S3_3_C13_C0_7
/*******************************************************************************
* RAS system registers
@@ -1435,18 +1436,23 @@
#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)
/*******************************************************************************
- * FEAT_TCR2 - Extended Translation Control Register
+ * FEAT_TCR2 - Extended Translation Control Registers
******************************************************************************/
+#define TCR2_EL1 S3_0_C2_C0_3
#define TCR2_EL2 S3_4_C2_C0_3
/*******************************************************************************
- * Permission indirection and overlay
+ * Permission indirection and overlay Registers
******************************************************************************/
+#define PIRE0_EL1 S3_0_C10_C2_2
#define PIRE0_EL2 S3_4_C10_C2_2
+#define PIR_EL1 S3_0_C10_C2_3
#define PIR_EL2 S3_4_C10_C2_3
+#define POR_EL1 S3_0_C10_C2_4
#define POR_EL2 S3_4_C10_C2_4
#define S2PIR_EL2 S3_4_C10_C2_5
+#define S2POR_EL1 S3_0_C10_C2_5
/*******************************************************************************
* FEAT_GCS - Guarded Control Stack Registers
@@ -1454,10 +1460,19 @@
#define GCSCR_EL2 S3_4_C2_C5_0
#define GCSPR_EL2 S3_4_C2_C5_1
#define GCSCR_EL1 S3_0_C2_C5_0
+#define GCSCRE0_EL1 S3_0_C2_C5_2
+#define GCSPR_EL1 S3_0_C2_C5_1
+#define GCSPR_EL0 S3_3_C2_C5_1
#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6)
/*******************************************************************************
+ * FEAT_TRF - Trace Filter Control Registers
+ ******************************************************************************/
+#define TRFCR_EL2 S3_4_C1_C2_1
+#define TRFCR_EL1 S3_0_C1_C2_1
+
+/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/
#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 6356cab..57dbc06 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -284,6 +284,7 @@
DEFINE_SYSREG_RW_FUNCS(elr_el2)
DEFINE_SYSREG_RW_FUNCS(elr_el3)
DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
+DEFINE_SYSREG_RW_FUNCS(mdccint_el1)
DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
DEFINE_SYSREG_RW_FUNCS(sp_el1)
@@ -504,6 +505,7 @@
DEFINE_SYSREG_READ_FUNC(isr_el1)
+DEFINE_SYSREG_RW_FUNCS(mdscr_el1)
DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
DEFINE_SYSREG_RW_FUNCS(hstr_el2)
@@ -567,6 +569,8 @@
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
/* Armv8.1 VHE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
@@ -576,6 +580,7 @@
DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
/* Armv8.2 RAS Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2)
@@ -603,6 +608,7 @@
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
/* Armv8.5 MTE Registers */
@@ -634,20 +640,28 @@
DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
/* FEAT_TCR2 Register */
+DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
/* FEAT_SxPIE Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
/* FEAT_SxPOE Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1)
/* FEAT_GCS Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
@@ -704,16 +718,88 @@
}
/*
- * TLBIPAALLOS instruction
- * (TLB Inivalidate GPT Information by PA,
- * All Entries, Outer Shareable)
+ * TLBI PAALLOS instruction
+ * (TLB Invalidate GPT Information by PA, All Entries, Outer Shareable)
*/
static inline void tlbipaallos(void)
{
- __asm__("SYS #6,c8,c1,#4");
+ __asm__("sys #6, c8, c1, #4");
}
/*
+ * TLBI RPALOS instructions
+ * (TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable)
+ *
+ * command SIZE, bits [47:44] field:
+ * 0b0000 4KB
+ * 0b0001 16KB
+ * 0b0010 64KB
+ * 0b0011 2MB
+ * 0b0100 32MB
+ * 0b0101 512MB
+ * 0b0110 1GB
+ * 0b0111 16GB
+ * 0b1000 64GB
+ * 0b1001 512GB
+ */
+#define TLBI_SZ_4K 0UL
+#define TLBI_SZ_16K 1UL
+#define TLBI_SZ_64K 2UL
+#define TLBI_SZ_2M 3UL
+#define TLBI_SZ_32M 4UL
+#define TLBI_SZ_512M 5UL
+#define TLBI_SZ_1G 6UL
+#define TLBI_SZ_16G 7UL
+#define TLBI_SZ_64G 8UL
+#define TLBI_SZ_512G 9UL
+
+#define TLBI_ADDR_SHIFT U(12)
+#define TLBI_SIZE_SHIFT U(44)
+
+#define TLBIRPALOS(_addr, _size) \
+{ \
+ u_register_t arg = ((_addr) >> TLBI_ADDR_SHIFT) | \
+ ((_size) << TLBI_SIZE_SHIFT); \
+ __asm__("sys #6, c8, c4, #7, %0" : : "r" (arg)); \
+}
+
+/* Note: addr must be aligned to 4KB */
+static inline void tlbirpalos_4k(uintptr_t addr)
+{
+ TLBIRPALOS(addr, TLBI_SZ_4K);
+}
+
+/* Note: addr must be aligned to 16KB */
+static inline void tlbirpalos_16k(uintptr_t addr)
+{
+ TLBIRPALOS(addr, TLBI_SZ_16K);
+}
+
+/* Note: addr must be aligned to 64KB */
+static inline void tlbirpalos_64k(uintptr_t addr)
+{
+ TLBIRPALOS(addr, TLBI_SZ_64K);
+}
+
+/* Note: addr must be aligned to 2MB */
+static inline void tlbirpalos_2m(uintptr_t addr)
+{
+ TLBIRPALOS(addr, TLBI_SZ_2M);
+}
+
+/* Note: addr must be aligned to 32MB */
+static inline void tlbirpalos_32m(uintptr_t addr)
+{
+ TLBIRPALOS(addr, TLBI_SZ_32M);
+}
+
+/* Note: addr must be aligned to 512MB */
+static inline void tlbirpalos_512m(uintptr_t addr)
+{
+ TLBIRPALOS(addr, TLBI_SZ_512M);
+}
+
+/*
* Invalidate TLBs of GPT entries by Physical address, last level.
*
* @pa: the starting address for the range
@@ -722,7 +808,6 @@
*/
void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
-
/* Previously defined accessor functions with incomplete register names */
#define read_current_el() read_CurrentEl()
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index bebd9ce..c7c441d 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -51,7 +51,7 @@
#define SGIR_TGTLSTFLT_MASK U(0x3)
#define SGIR_TGTLST_SHIFT 16
#define SGIR_TGTLST_MASK U(0xff)
-#define SGIR_NSATT (U(0x1) << 16)
+#define SGIR_NSATT (U(0x1) << 15)
#define SGIR_INTID_MASK ULL(0xf)
#define SGIR_TGT_SPECIFIC U(0)
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index fbaa008..4f11ad2 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -109,21 +109,25 @@
#define CTX_AFSR1_EL1 U(0x98)
#define CTX_CONTEXTIDR_EL1 U(0xa0)
#define CTX_VBAR_EL1 U(0xa8)
+#define CTX_MDCCINT_EL1 U(0xb0)
+#define CTX_MDSCR_EL1 U(0xb8)
+
+#define CTX_AARCH64_END U(0xc0) /* Align to the next 16 byte boundary */
/*
* If the platform is AArch64-only, there is no need to save and restore these
* AArch32 registers.
*/
#if CTX_INCLUDE_AARCH32_REGS
-#define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */
-#define CTX_SPSR_UND U(0xb8)
-#define CTX_SPSR_IRQ U(0xc0)
-#define CTX_SPSR_FIQ U(0xc8)
-#define CTX_DACR32_EL2 U(0xd0)
-#define CTX_IFSR32_EL2 U(0xd8)
-#define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */
+#define CTX_SPSR_ABT (CTX_AARCH64_END + U(0x0))
+#define CTX_SPSR_UND (CTX_AARCH64_END + U(0x8))
+#define CTX_SPSR_IRQ (CTX_AARCH64_END + U(0x10))
+#define CTX_SPSR_FIQ (CTX_AARCH64_END + U(0x18))
+#define CTX_DACR32_EL2 (CTX_AARCH64_END + U(0x20))
+#define CTX_IFSR32_EL2 (CTX_AARCH64_END + U(0x28))
+#define CTX_AARCH32_END (CTX_AARCH64_END + U(0x30)) /* Align to the next 16 byte boundary */
#else
-#define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */
+#define CTX_AARCH32_END CTX_AARCH64_END
#endif /* CTX_INCLUDE_AARCH32_REGS */
/*
@@ -146,17 +150,76 @@
#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18))
-
-/* Align to the next 16 byte boundary */
-#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
+#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) /* Align to the next 16 byte boundary */
#else
#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
#endif /* ENABLE_FEAT_MTE2 */
+#if ENABLE_FEAT_RAS
+#define CTX_DISR_EL1 (CTX_MTE_REGS_END + U(0x0))
+#define CTX_RAS_REGS_END (CTX_MTE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_RAS_REGS_END CTX_MTE_REGS_END
+#endif /* ENABLE_FEAT_RAS */
+
+#if ENABLE_FEAT_S1PIE
+#define CTX_PIRE0_EL1 (CTX_RAS_REGS_END + U(0x0))
+#define CTX_PIR_EL1 (CTX_RAS_REGS_END + U(0x8))
+#define CTX_S1PIE_REGS_END (CTX_RAS_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_S1PIE_REGS_END CTX_RAS_REGS_END
+#endif /* ENABLE_FEAT_S1PIE */
+
+#if ENABLE_FEAT_S1POE
+#define CTX_POR_EL1 (CTX_S1PIE_REGS_END + U(0x0))
+#define CTX_S1POE_REGS_END (CTX_S1PIE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_S1POE_REGS_END CTX_S1PIE_REGS_END
+#endif /* ENABLE_FEAT_S1POE */
+
+#if ENABLE_FEAT_S2POE
+#define CTX_S2POR_EL1 (CTX_S1POE_REGS_END + U(0x0))
+#define CTX_S2POE_REGS_END (CTX_S1POE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_S2POE_REGS_END CTX_S1POE_REGS_END
+#endif /* ENABLE_FEAT_S2POE */
+
+#if ENABLE_FEAT_TCR2
+#define CTX_TCR2_EL1 (CTX_S2POE_REGS_END + U(0x0))
+#define CTX_TCR2_REGS_END (CTX_S2POE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_TCR2_REGS_END CTX_S2POE_REGS_END
+#endif /* ENABLE_FEAT_TCR2 */
+
+#if ENABLE_TRF_FOR_NS
+#define CTX_TRFCR_EL1 (CTX_TCR2_REGS_END + U(0x0))
+#define CTX_TRF_REGS_END (CTX_TCR2_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_TRF_REGS_END CTX_TCR2_REGS_END
+#endif /* ENABLE_TRF_FOR_NS */
+
+#if ENABLE_FEAT_CSV2_2
+#define CTX_SCXTNUM_EL0 (CTX_TRF_REGS_END + U(0x0))
+#define CTX_SCXTNUM_EL1 (CTX_TRF_REGS_END + U(0x8))
+#define CTX_CSV2_2_REGS_END (CTX_TRF_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_CSV2_2_REGS_END CTX_TRF_REGS_END
+#endif /* ENABLE_FEAT_CSV2_2 */
+
+#if ENABLE_FEAT_GCS
+#define CTX_GCSCR_EL1 (CTX_CSV2_2_REGS_END + U(0x0))
+#define CTX_GCSCRE0_EL1 (CTX_CSV2_2_REGS_END + U(0x8))
+#define CTX_GCSPR_EL1 (CTX_CSV2_2_REGS_END + U(0x10))
+#define CTX_GCSPR_EL0 (CTX_CSV2_2_REGS_END + U(0x18))
+#define CTX_GCS_REGS_END (CTX_CSV2_2_REGS_END + U(0x20)) /* Align to the next 16 byte boundary */
+#else
+#define CTX_GCS_REGS_END CTX_CSV2_2_REGS_END
+#endif /* ENABLE_FEAT_GCS */
+
/*
- * End of system registers.
+ * End of EL1 system registers.
*/
-#define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END
+#define CTX_EL1_SYSREGS_END CTX_GCS_REGS_END
/*******************************************************************************
* Constants that allow assembler code to access members of and the 'fp_regs'
diff --git a/include/lib/el3_runtime/context_el2.h b/include/lib/el3_runtime/context_el2.h
index 4ad9634..04f6587 100644
--- a/include/lib/el3_runtime/context_el2.h
+++ b/include/lib/el3_runtime/context_el2.h
@@ -49,9 +49,9 @@
uint64_t vttbr_el2;
} el2_common_regs_t;
-typedef struct el2_mte_regs {
+typedef struct el2_mte2_regs {
uint64_t tfsr_el2;
-} el2_mte_regs_t;
+} el2_mte2_regs_t;
typedef struct el2_fgt_regs {
uint64_t hdfgrtr_el2;
@@ -118,8 +118,8 @@
el2_common_regs_t common;
-#if ENABLE_FEAT_MTE
- el2_mte_regs_t mte;
+#if ENABLE_FEAT_MTE2
+ el2_mte2_regs_t mte2;
#endif
#if ENABLE_FEAT_FGT
@@ -185,14 +185,14 @@
#define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \
= (uint64_t) (val))
-#if ENABLE_FEAT_MTE
-#define read_el2_ctx_mte(ctx, reg) (((ctx)->mte).reg)
-#define write_el2_ctx_mte(ctx, reg, val) ((((ctx)->mte).reg) \
+#if ENABLE_FEAT_MTE2
+#define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg)
+#define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \
= (uint64_t) (val))
#else
-#define read_el2_ctx_mte(ctx, reg) ULL(0)
-#define write_el2_ctx_mte(ctx, reg, val)
-#endif /* ENABLE_FEAT_MTE */
+#define read_el2_ctx_mte2(ctx, reg) ULL(0)
+#define write_el2_ctx_mte2(ctx, reg, val)
+#endif /* ENABLE_FEAT_MTE2 */
#if ENABLE_FEAT_FGT
#define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg)
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index f631125..7451b85 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,12 +30,15 @@
void *cm_get_context(uint32_t security_state);
void cm_set_context(void *context, uint32_t security_state);
void cm_init_my_context(const struct entry_point_info *ep);
-void cm_init_context_by_index(unsigned int cpu_idx,
- const struct entry_point_info *ep);
void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
void cm_prepare_el3_exit(uint32_t security_state);
void cm_prepare_el3_exit_ns(void);
+#if !IMAGE_BL1
+void cm_init_context_by_index(unsigned int cpu_idx,
+ const struct entry_point_info *ep);
+#endif /* !IMAGE_BL1 */
+
#ifdef __aarch64__
#if IMAGE_BL31
void cm_manage_extensions_el3(void);
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 9fd3fc6..055a911 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,15 +15,21 @@
volatile uint32_t lock;
} spinlock_t;
+typedef struct bitlock {
+ volatile uint8_t lock;
+} bitlock_t;
+
void spin_lock(spinlock_t *lock);
void spin_unlock(spinlock_t *lock);
+void bit_lock(bitlock_t *lock, uint8_t mask);
+void bit_unlock(bitlock_t *lock, uint8_t mask);
+
#else
/* Spin lock definitions for use in assembly */
#define SPINLOCK_ASM_ALIGN 2
#define SPINLOCK_ASM_SIZE 4
-#endif
-
+#endif /* __ASSEMBLER__ */
#endif /* SPINLOCK_H */
diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
index 5ea5a41..c5df22b 100644
--- a/include/lib/transfer_list.h
+++ b/include/lib/transfer_list.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,6 +42,8 @@
TL_TAG_HOB_LIST = 3,
TL_TAG_ACPI_TABLE_AGGREGATE = 4,
TL_TAG_OPTEE_PAGABLE_PART = 0x100,
+ TL_TAG_DT_SPMC_MANIFEST = 0x101,
+ TL_TAG_EXEC_EP_INFO64 = 0x102,
};
enum transfer_list_ops {
@@ -73,9 +75,8 @@
*/
};
-struct transfer_list_entry {
- uint16_t tag_id;
- uint8_t reserved0; /* place holder */
+struct __attribute__((packed)) transfer_list_entry {
+ uint32_t tag_id : 24;
uint8_t hdr_size;
uint32_t data_size;
/*
@@ -89,6 +90,8 @@
*/
};
+CASSERT(sizeof(struct transfer_list_entry) == U(0x8), assert_transfer_list_entry_size);
+
void transfer_list_dump(struct transfer_list_header *tl);
entry_point_info_t *
transfer_list_set_handoff_args(struct transfer_list_header *tl,
@@ -113,12 +116,12 @@
struct transfer_list_entry *entry);
struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl,
- uint16_t tag_id,
+ uint32_t tag_id,
uint32_t data_size,
const void *data);
struct transfer_list_entry *
-transfer_list_add_with_align(struct transfer_list_header *tl, uint16_t tag_id,
+transfer_list_add_with_align(struct transfer_list_header *tl, uint32_t tag_id,
uint32_t data_size, const void *data,
uint8_t alignment);
@@ -127,7 +130,7 @@
struct transfer_list_entry *last);
struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl,
- uint16_t tag_id);
+ uint32_t tag_id);
#endif /*__ASSEMBLER__*/
#endif /*__TRANSFER_LIST_H*/
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index 1963bf0..3bb68ee 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -67,9 +67,6 @@
#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
-#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
-#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
-
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 828d43a..a43e13c 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -285,10 +285,14 @@
bool arm_io_is_toc_valid(void);
/* Utility functions for Dynamic Config */
-void arm_bl2_dyn_cfg_init(void);
+
void arm_bl1_set_mbedtls_heap(void);
int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
+#if IMAGE_BL2
+void arm_bl2_dyn_cfg_init(void);
+#endif /* IMAGE_BL2 */
+
#if MEASURED_BOOT
#if DICE_PROTECTION_ENVIRONMENT
int arm_set_nt_fw_info(int *ctx_handle);
diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h
index b89de9f..578bc14 100644
--- a/include/services/rmm_core_manifest.h
+++ b/include/services/rmm_core_manifest.h
@@ -14,7 +14,9 @@
#include <lib/cassert.h>
#define RMMD_MANIFEST_VERSION_MAJOR U(0)
-#define RMMD_MANIFEST_VERSION_MINOR U(2)
+#define RMMD_MANIFEST_VERSION_MINOR U(3)
+
+#define RMM_CONSOLE_MAX_NAME_LEN U(8)
/*
* Manifest version encoding:
@@ -60,12 +62,49 @@
CASSERT(offsetof(struct ns_dram_info, checksum) == 16UL,
rmm_manifest_checksum_unaligned);
+/* Console info structure */
+struct console_info {
+ uintptr_t base; /* Console base address */
+ uint64_t map_pages; /* Num of pages to be mapped in RMM for the console MMIO */
+ char name[RMM_CONSOLE_MAX_NAME_LEN]; /* Name of console */
+ uint64_t clk_in_hz; /* UART clock (in HZ) for the console */
+ uint64_t baud_rate; /* Baud rate */
+ uint64_t flags; /* Additional flags RES0 */
+};
+
+CASSERT(offsetof(struct console_info, base) == 0UL,
+ rmm_manifest_console_base_unaligned);
+CASSERT(offsetof(struct console_info, map_pages) == 8UL,
+ rmm_manifest_console_map_pages_unaligned);
+CASSERT(offsetof(struct console_info, name) == 16UL,
+ rmm_manifest_console_name_unaligned);
+CASSERT(offsetof(struct console_info, clk_in_hz) == 24UL,
+ rmm_manifest_console_clk_in_hz_unaligned);
+CASSERT(offsetof(struct console_info, baud_rate) == 32UL,
+ rmm_manifest_console_baud_rate_unaligned);
+CASSERT(offsetof(struct console_info, flags) == 40UL,
+ rmm_manifest_console_flags_unaligned);
+
-/* Boot manifest core structure as per v0.2 */
+struct console_list {
+ uint64_t num_consoles; /* Number of consoles */
+ struct console_info *consoles; /* Pointer to ns_dram_bank[] */
+ uint64_t checksum; /* Checksum of ns_dram_info data */
+};
+
+CASSERT(offsetof(struct console_list, num_consoles) == 0UL,
+ rmm_manifest_num_consoles);
+CASSERT(offsetof(struct console_list, consoles) == 8UL,
+ rmm_manifest_consoles);
+CASSERT(offsetof(struct console_list, checksum) == 16UL,
+ rmm_manifest_console_list_checksum);
+
+/* Boot manifest core structure as per v0.3 */
struct rmm_manifest {
- uint32_t version; /* Manifest version */
- uint32_t padding; /* RES0 */
- uintptr_t plat_data; /* Manifest platform data */
- struct ns_dram_info plat_dram; /* Platform NS DRAM data */
+ uint32_t version; /* Manifest version */
+ uint32_t padding; /* RES0 */
+ uintptr_t plat_data; /* Manifest platform data */
+ struct ns_dram_info plat_dram; /* Platform NS DRAM data (v0.2) */
+ struct console_list plat_console; /* Platform console list (v0.3) */
};
CASSERT(offsetof(struct rmm_manifest, version) == 0UL,
@@ -74,5 +113,7 @@
rmm_manifest_plat_data_unaligned);
CASSERT(offsetof(struct rmm_manifest, plat_dram) == 16UL,
rmm_manifest_plat_dram_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_console) == 40UL,
+ rmm_manifest_plat_console_unaligned);
#endif /* RMM_CORE_MANIFEST_H */
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index b60b8e0..301c60c 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -149,14 +149,13 @@
trf_init_el3();
}
- /*
- * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure
- * state execution. This does not affect lower NS ELs.
- */
- pmuv3_init_el3();
+ if (read_feat_pmuv3_id_field() >= 3U) {
+ pmuv3_init_el3();
+ }
#endif /* IMAGE_BL32 */
}
+#if !IMAGE_BL1
/*******************************************************************************
* The following function initializes the cpu_context for a CPU specified by
* its `cpu_idx` for first use, and sets the initial entrypoint state as
@@ -169,6 +168,7 @@
ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
cm_setup_context(ctx, ep);
}
+#endif /* !IMAGE_BL1 */
/*******************************************************************************
* The following function initializes the cpu_context for the current CPU
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 7a00e47..35c98f5 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -809,6 +809,7 @@
#endif /* IMAGE_BL31 */
}
+#if !IMAGE_BL1
/*******************************************************************************
* The following function initializes the cpu_context for a CPU specified by
* its `cpu_idx` for first use, and sets the initial entrypoint state as
@@ -821,6 +822,7 @@
ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
cm_setup_context(ctx, ep);
}
+#endif /* !IMAGE_BL1 */
/*******************************************************************************
* The following function initializes the cpu_context for the current CPU
@@ -1278,7 +1280,7 @@
el2_sysregs_context_save_gic(el2_sysregs_ctx);
if (is_feat_mte2_supported()) {
- write_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
+ write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
}
#if CTX_INCLUDE_MPAM_REGS
@@ -1342,8 +1344,8 @@
}
if (is_feat_gcs_supported()) {
- write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcspr_el2());
- write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcscr_el2());
+ write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2());
+ write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2());
}
}
@@ -1364,7 +1366,7 @@
el2_sysregs_context_restore_gic(el2_sysregs_ctx);
if (is_feat_mte2_supported()) {
- write_tfsr_el2(read_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2));
+ write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2));
}
#if CTX_INCLUDE_MPAM_REGS
@@ -1490,6 +1492,8 @@
write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1());
write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1());
write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1());
+ write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1());
+ write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1());
#if CTX_INCLUDE_AARCH32_REGS
write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt());
@@ -1515,6 +1519,58 @@
write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1());
#endif /* ENABLE_FEAT_MTE2 */
+#if ENABLE_FEAT_RAS
+ if (is_feat_ras_supported()) {
+ write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_S1PIE
+ if (is_feat_s1pie_supported()) {
+ write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1());
+ write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_S1POE
+ if (is_feat_s1poe_supported()) {
+ write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_S2POE
+ if (is_feat_s2poe_supported()) {
+ write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_TCR2
+ if (is_feat_tcr2_supported()) {
+ write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1());
+ }
+#endif
+
+#if ENABLE_TRF_FOR_NS
+ if (is_feat_trf_supported()) {
+ write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+ if (is_feat_csv2_2_supported()) {
+ write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0());
+ write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1());
+ }
+#endif
+
+#if ENABLE_FEAT_GCS
+ if (is_feat_gcs_supported()) {
+ write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1());
+ write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1());
+ write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1());
+ write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0());
+ }
+#endif
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@@ -1545,6 +1601,8 @@
write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1));
write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1));
write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1));
+ write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1));
+ write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1));
#if CTX_INCLUDE_AARCH32_REGS
write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT));
@@ -1570,6 +1628,58 @@
write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1));
#endif /* ENABLE_FEAT_MTE2 */
+#if ENABLE_FEAT_RAS
+ if (is_feat_ras_supported()) {
+ write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_S1PIE
+ if (is_feat_s1pie_supported()) {
+ write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1));
+ write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_S1POE
+ if (is_feat_s1poe_supported()) {
+ write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_S2POE
+ if (is_feat_s2poe_supported()) {
+ write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_TCR2
+ if (is_feat_tcr2_supported()) {
+ write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1));
+ }
+#endif
+
+#if ENABLE_TRF_FOR_NS
+ if (is_feat_trf_supported()) {
+ write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+ if (is_feat_csv2_2_supported()) {
+ write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0));
+ write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1));
+ }
+#endif
+
+#if ENABLE_FEAT_GCS
+ if (is_feat_gcs_supported()) {
+ write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1));
+ write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1));
+ write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1));
+ write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0));
+ }
+#endif
}
/*******************************************************************************
diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c
index effb7e0..456a48e 100644
--- a/lib/extensions/pmuv3/aarch32/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch32/pmuv3.c
@@ -25,10 +25,6 @@
return sdcr;
}
-/*
- * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and
- * to not clash with platforms which reuse the PMU name
- */
void pmuv3_init_el3(void)
{
u_register_t sdcr = read_sdcr();
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index 36f7a51..72e905e 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#if !ENABLE_RME
-#error "ENABLE_RME must be enabled to use the GPT library."
+#error "ENABLE_RME must be enabled to use the GPT library"
#endif
/*
@@ -58,7 +58,7 @@
static const gpt_p_val_e gpt_p_lookup[] = {PGS_4KB_P, PGS_64KB_P, PGS_16KB_P};
/*
- * This structure contains GPT configuration data.
+ * This structure contains GPT configuration data
*/
typedef struct {
uintptr_t plat_gpt_l0_base;
@@ -70,7 +70,7 @@
static gpt_config_t gpt_config;
-/* These variables are used during initialization of the L1 tables. */
+/* These variables are used during initialization of the L1 tables */
static unsigned int gpt_next_l1_tbl_idx;
static uintptr_t gpt_l1_tbl;
@@ -91,7 +91,7 @@
* Return
* true for a valid GPI, false for an invalid one.
*/
-static bool gpt_is_gpi_valid(unsigned int gpi)
+static bool is_gpi_valid(unsigned int gpi)
{
if ((gpi == GPT_GPI_NO_ACCESS) || (gpi == GPT_GPI_ANY) ||
((gpi >= GPT_GPI_SECURE) && (gpi <= GPT_GPI_REALM))) {
@@ -112,8 +112,8 @@
* Return
* True if PAS regions overlap, false if they do not.
*/
-static bool gpt_check_pas_overlap(uintptr_t base_1, size_t size_1,
- uintptr_t base_2, size_t size_2)
+static bool check_pas_overlap(uintptr_t base_1, size_t size_1,
+ uintptr_t base_2, size_t size_2)
{
if (((base_1 + size_1) > base_2) && ((base_2 + size_2) > base_1)) {
return true;
@@ -133,13 +133,13 @@
* Return
* True if a PAS region occupies the L0 region in question, false if not.
*/
-static bool gpt_does_previous_pas_exist_here(unsigned int l0_idx,
- pas_region_t *pas_regions,
- unsigned int pas_idx)
+static bool does_previous_pas_exist_here(unsigned int l0_idx,
+ pas_region_t *pas_regions,
+ unsigned int pas_idx)
{
- /* Iterate over PAS regions up to pas_idx. */
+ /* Iterate over PAS regions up to pas_idx */
for (unsigned int i = 0U; i < pas_idx; i++) {
- if (gpt_check_pas_overlap((GPT_L0GPTSZ_ACTUAL_SIZE * l0_idx),
+ if (check_pas_overlap((GPT_L0GPTSZ_ACTUAL_SIZE * l0_idx),
GPT_L0GPTSZ_ACTUAL_SIZE,
pas_regions[i].base_pa, pas_regions[i].size)) {
return true;
@@ -164,8 +164,8 @@
* Negative Linux error code in the event of a failure, number of L1 regions
* required when successful.
*/
-static int gpt_validate_pas_mappings(pas_region_t *pas_regions,
- unsigned int pas_region_cnt)
+static int validate_pas_mappings(pas_region_t *pas_regions,
+ unsigned int pas_region_cnt)
{
unsigned int idx;
unsigned int l1_cnt = 0U;
@@ -176,18 +176,18 @@
assert(pas_region_cnt != 0U);
for (idx = 0U; idx < pas_region_cnt; idx++) {
- /* Check for arithmetic overflow in region. */
+ /* Check for arithmetic overflow in region */
if ((ULONG_MAX - pas_regions[idx].base_pa) <
pas_regions[idx].size) {
- ERROR("[GPT] Address overflow in PAS[%u]!\n", idx);
+ ERROR("GPT: Address overflow in PAS[%u]!\n", idx);
return -EOVERFLOW;
}
- /* Initial checks for PAS validity. */
+ /* Initial checks for PAS validity */
if (((pas_regions[idx].base_pa + pas_regions[idx].size) >
GPT_PPS_ACTUAL_SIZE(gpt_config.t)) ||
- !gpt_is_gpi_valid(GPT_PAS_ATTR_GPI(pas_regions[idx].attrs))) {
- ERROR("[GPT] PAS[%u] is invalid!\n", idx);
+ !is_gpi_valid(GPT_PAS_ATTR_GPI(pas_regions[idx].attrs))) {
+ ERROR("GPT: PAS[%u] is invalid!\n", idx);
return -EFAULT;
}
@@ -196,12 +196,12 @@
* start from idx + 1 instead of 0 since prior PAS mappings will
* have already checked themselves against this one.
*/
- for (unsigned int i = idx + 1; i < pas_region_cnt; i++) {
- if (gpt_check_pas_overlap(pas_regions[idx].base_pa,
+ for (unsigned int i = idx + 1U; i < pas_region_cnt; i++) {
+ if (check_pas_overlap(pas_regions[idx].base_pa,
pas_regions[idx].size,
pas_regions[i].base_pa,
pas_regions[i].size)) {
- ERROR("[GPT] PAS[%u] overlaps with PAS[%u]\n",
+ ERROR("GPT: PAS[%u] overlaps with PAS[%u]\n",
i, idx);
return -EFAULT;
}
@@ -214,11 +214,12 @@
* initialized.
*/
for (unsigned int i = GPT_L0_IDX(pas_regions[idx].base_pa);
- i <= GPT_L0_IDX(pas_regions[idx].base_pa + pas_regions[idx].size - 1);
+ i <= GPT_L0_IDX(pas_regions[idx].base_pa +
+ pas_regions[idx].size - 1UL);
i++) {
if ((GPT_L0_TYPE(l0_desc[i]) == GPT_L0_TYPE_BLK_DESC) &&
(GPT_L0_BLKD_GPI(l0_desc[i]) == GPT_GPI_ANY)) {
- /* This descriptor is unused so continue. */
+ /* This descriptor is unused so continue */
continue;
}
@@ -226,18 +227,18 @@
* This descriptor has been initialized in a previous
* call to this function so cannot be initialized again.
*/
- ERROR("[GPT] PAS[%u] overlaps with previous L0[%d]!\n",
+ ERROR("GPT: PAS[%u] overlaps with previous L0[%d]!\n",
idx, i);
return -EFAULT;
}
- /* Check for block mapping (L0) type. */
+ /* Check for block mapping (L0) type */
if (GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs) ==
GPT_PAS_ATTR_MAP_TYPE_BLOCK) {
- /* Make sure base and size are block-aligned. */
+ /* Make sure base and size are block-aligned */
if (!GPT_IS_L0_ALIGNED(pas_regions[idx].base_pa) ||
!GPT_IS_L0_ALIGNED(pas_regions[idx].size)) {
- ERROR("[GPT] PAS[%u] is not block-aligned!\n",
+ ERROR("GPT: PAS[%u] is not block-aligned!\n",
idx);
return -EFAULT;
}
@@ -245,21 +246,21 @@
continue;
}
- /* Check for granule mapping (L1) type. */
+ /* Check for granule mapping (L1) type */
if (GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs) ==
GPT_PAS_ATTR_MAP_TYPE_GRANULE) {
- /* Make sure base and size are granule-aligned. */
+ /* Make sure base and size are granule-aligned */
if (!GPT_IS_L1_ALIGNED(gpt_config.p, pas_regions[idx].base_pa) ||
!GPT_IS_L1_ALIGNED(gpt_config.p, pas_regions[idx].size)) {
- ERROR("[GPT] PAS[%u] is not granule-aligned!\n",
+ ERROR("GPT: PAS[%u] is not granule-aligned!\n",
idx);
return -EFAULT;
}
- /* Find how many L1 tables this PAS occupies. */
+ /* Find how many L1 tables this PAS occupies */
pas_l1_cnt = (GPT_L0_IDX(pas_regions[idx].base_pa +
- pas_regions[idx].size - 1) -
- GPT_L0_IDX(pas_regions[idx].base_pa) + 1);
+ pas_regions[idx].size - 1UL) -
+ GPT_L0_IDX(pas_regions[idx].base_pa) + 1U);
/*
* This creates a situation where, if multiple PAS
@@ -277,26 +278,26 @@
* both for overlap against other PAS.
*/
if (pas_l1_cnt > 1) {
- if (gpt_does_previous_pas_exist_here(
+ if (does_previous_pas_exist_here(
GPT_L0_IDX(pas_regions[idx].base_pa +
- pas_regions[idx].size - 1),
+ pas_regions[idx].size - 1UL),
pas_regions, idx)) {
- pas_l1_cnt = pas_l1_cnt - 1;
+ pas_l1_cnt--;
}
}
- if (gpt_does_previous_pas_exist_here(
+ if (does_previous_pas_exist_here(
GPT_L0_IDX(pas_regions[idx].base_pa),
pas_regions, idx)) {
- pas_l1_cnt = pas_l1_cnt - 1;
+ pas_l1_cnt--;
}
l1_cnt += pas_l1_cnt;
continue;
}
- /* If execution reaches this point, mapping type is invalid. */
- ERROR("[GPT] PAS[%u] has invalid mapping type 0x%x.\n", idx,
+ /* If execution reaches this point, mapping type is invalid */
+ ERROR("GPT: PAS[%u] has invalid mapping type 0x%x.\n", idx,
GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs));
return -EINVAL;
}
@@ -314,8 +315,8 @@
* Return
* Negative Linux error code in the event of a failure, 0 for success.
*/
-static int gpt_validate_l0_params(gpccr_pps_e pps, uintptr_t l0_mem_base,
- size_t l0_mem_size)
+static int validate_l0_params(gpccr_pps_e pps, uintptr_t l0_mem_base,
+ size_t l0_mem_size)
{
size_t l0_alignment;
@@ -324,27 +325,29 @@
* to work.
*/
if (pps > GPT_PPS_MAX) {
- ERROR("[GPT] Invalid PPS: 0x%x\n", pps);
+ ERROR("GPT: Invalid PPS: 0x%x\n", pps);
return -EINVAL;
}
gpt_config.pps = pps;
gpt_config.t = gpt_t_lookup[pps];
- /* Alignment must be the greater of 4k or l0 table size. */
+ /* Alignment must be the greater of 4KB or l0 table size */
l0_alignment = PAGE_SIZE_4KB;
if (l0_alignment < GPT_L0_TABLE_SIZE(gpt_config.t)) {
l0_alignment = GPT_L0_TABLE_SIZE(gpt_config.t);
}
- /* Check base address. */
- if ((l0_mem_base == 0U) || ((l0_mem_base & (l0_alignment - 1)) != 0U)) {
- ERROR("[GPT] Invalid L0 base address: 0x%lx\n", l0_mem_base);
+ /* Check base address */
+ if ((l0_mem_base == 0UL) ||
+ ((l0_mem_base & (l0_alignment - 1UL)) != 0UL)) {
+ ERROR("GPT: Invalid L0 base address: 0x%lx\n", l0_mem_base);
return -EFAULT;
}
- /* Check size. */
+ /* Check size */
if (l0_mem_size < GPT_L0_TABLE_SIZE(gpt_config.t)) {
- ERROR("[GPT] Inadequate L0 memory: need 0x%lx, have 0x%lx)\n",
+ ERROR("%sL0%s\n", "GPT: Inadequate ", " memory\n");
+ ERROR(" Expected 0x%lx bytes, got 0x%lx bytes\n",
GPT_L0_TABLE_SIZE(gpt_config.t),
l0_mem_size);
return -ENOMEM;
@@ -365,8 +368,8 @@
* Return
* Negative Linux error code in the event of a failure, 0 for success.
*/
-static int gpt_validate_l1_params(uintptr_t l1_mem_base, size_t l1_mem_size,
- unsigned int l1_gpt_cnt)
+static int validate_l1_params(uintptr_t l1_mem_base, size_t l1_mem_size,
+ unsigned int l1_gpt_cnt)
{
size_t l1_gpt_mem_sz;
@@ -376,31 +379,31 @@
return -EPERM;
}
- /* Make sure L1 tables are aligned to their size. */
- if ((l1_mem_base & (GPT_L1_TABLE_SIZE(gpt_config.p) - 1)) != 0U) {
- ERROR("[GPT] Unaligned L1 GPT base address: 0x%lx\n",
+ /* Make sure L1 tables are aligned to their size */
+ if ((l1_mem_base & (GPT_L1_TABLE_SIZE(gpt_config.p) - 1UL)) != 0UL) {
+ ERROR("GPT: Unaligned L1 GPT base address: 0x%"PRIxPTR"\n",
l1_mem_base);
return -EFAULT;
}
- /* Get total memory needed for L1 tables. */
+ /* Get total memory needed for L1 tables */
l1_gpt_mem_sz = l1_gpt_cnt * GPT_L1_TABLE_SIZE(gpt_config.p);
- /* Check for overflow. */
+ /* Check for overflow */
if ((l1_gpt_mem_sz / GPT_L1_TABLE_SIZE(gpt_config.p)) != l1_gpt_cnt) {
- ERROR("[GPT] Overflow calculating L1 memory size.\n");
+ ERROR("GPT: Overflow calculating L1 memory size\n");
return -ENOMEM;
}
- /* Make sure enough space was supplied. */
+ /* Make sure enough space was supplied */
if (l1_mem_size < l1_gpt_mem_sz) {
- ERROR("[GPT] Inadequate memory for L1 GPTs. ");
- ERROR(" Expected 0x%lx bytes. Got 0x%lx bytes\n",
+ ERROR("%sL1 GPTs%s", "GPT: Inadequate ", " memory\n");
+ ERROR(" Expected 0x%lx bytes, got 0x%lx bytes\n",
l1_gpt_mem_sz, l1_mem_size);
return -ENOMEM;
}
- VERBOSE("[GPT] Requested 0x%lx bytes for L1 GPTs.\n", l1_gpt_mem_sz);
+ VERBOSE("GPT: Requested 0x%lx bytes for L1 GPTs\n", l1_gpt_mem_sz);
return 0;
}
@@ -412,7 +415,7 @@
* *pas Pointer to the structure defining the PAS region to
* initialize.
*/
-static void gpt_generate_l0_blk_desc(pas_region_t *pas)
+static void generate_l0_blk_desc(pas_region_t *pas)
{
uint64_t gpt_desc;
unsigned int end_idx;
@@ -424,7 +427,7 @@
/*
* Checking of PAS parameters has already been done in
- * gpt_validate_pas_mappings so no need to check the same things again.
+ * validate_pas_mappings so no need to check the same things again.
*/
l0_gpt_arr = (uint64_t *)gpt_config.plat_gpt_l0_base;
@@ -442,10 +445,10 @@
*/
end_idx = GPT_L0_IDX(pas->base_pa + pas->size);
- /* Generate the needed block descriptors. */
+ /* Generate the needed block descriptors */
for (; idx < end_idx; idx++) {
l0_gpt_arr[idx] = gpt_desc;
- VERBOSE("[GPT] L0 entry (BLOCK) index %u [%p]: GPI = 0x%" PRIx64 " (0x%" PRIx64 ")\n",
+ VERBOSE("GPT: L0 entry (BLOCK) index %u [%p]: GPI = 0x%"PRIx64" (0x%"PRIx64")\n",
idx, &l0_gpt_arr[idx],
(gpt_desc >> GPT_L0_BLK_DESC_GPI_SHIFT) &
GPT_L0_BLK_DESC_GPI_MASK, l0_gpt_arr[idx]);
@@ -465,7 +468,7 @@
* Return
* The PA of the end of the current range.
*/
-static uintptr_t gpt_get_l1_end_pa(uintptr_t cur_pa, uintptr_t end_pa)
+static uintptr_t get_l1_end_pa(uintptr_t cur_pa, uintptr_t end_pa)
{
uintptr_t cur_idx;
uintptr_t end_idx;
@@ -492,11 +495,11 @@
* first Address of first granule in range.
* last Address of last granule in range (inclusive).
*/
-static void gpt_fill_l1_tbl(uint64_t gpi, uint64_t *l1, uintptr_t first,
+static void fill_l1_tbl(uint64_t gpi, uint64_t *l1, uintptr_t first,
uintptr_t last)
{
uint64_t gpi_field = GPT_BUILD_L1_DESC(gpi);
- uint64_t gpi_mask = 0xFFFFFFFFFFFFFFFF;
+ uint64_t gpi_mask = ULONG_MAX;
assert(first <= last);
assert((first & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) == 0U);
@@ -504,25 +507,25 @@
assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
assert(l1 != NULL);
- /* Shift the mask if we're starting in the middle of an L1 entry. */
+ /* Shift the mask if we're starting in the middle of an L1 entry */
gpi_mask = gpi_mask << (GPT_L1_GPI_IDX(gpt_config.p, first) << 2);
- /* Fill out each L1 entry for this region. */
+ /* Fill out each L1 entry for this region */
for (unsigned int i = GPT_L1_IDX(gpt_config.p, first);
i <= GPT_L1_IDX(gpt_config.p, last); i++) {
- /* Account for stopping in the middle of an L1 entry. */
+ /* Account for stopping in the middle of an L1 entry */
if (i == GPT_L1_IDX(gpt_config.p, last)) {
- gpi_mask &= (gpi_mask >> ((15 -
+ gpi_mask &= (gpi_mask >> ((15U -
GPT_L1_GPI_IDX(gpt_config.p, last)) << 2));
}
- /* Write GPI values. */
+ /* Write GPI values */
assert((l1[i] & gpi_mask) ==
(GPT_BUILD_L1_DESC(GPT_GPI_ANY) & gpi_mask));
l1[i] = (l1[i] & ~gpi_mask) | (gpi_mask & gpi_field);
- /* Reset mask. */
- gpi_mask = 0xFFFFFFFFFFFFFFFF;
+ /* Reset mask */
+ gpi_mask = ULONG_MAX;
}
}
@@ -537,14 +540,14 @@
* Return
* Pointer to the next available L1 table.
*/
-static uint64_t *gpt_get_new_l1_tbl(void)
+static uint64_t *get_new_l1_tbl(void)
{
- /* Retrieve the next L1 table. */
+ /* Retrieve the next L1 table */
uint64_t *l1 = (uint64_t *)((uint64_t)(gpt_l1_tbl) +
(GPT_L1_TABLE_SIZE(gpt_config.p) *
gpt_next_l1_tbl_idx));
- /* Increment L1 counter. */
+ /* Increment L1 counter */
gpt_next_l1_tbl_idx++;
/* Initialize all GPIs to GPT_GPI_ANY */
@@ -563,7 +566,7 @@
* Parameters
* *pas Pointer to the structure defining the PAS region.
*/
-static void gpt_generate_l0_tbl_desc(pas_region_t *pas)
+static void generate_l0_tbl_desc(pas_region_t *pas)
{
uintptr_t end_pa;
uintptr_t cur_pa;
@@ -577,7 +580,7 @@
/*
* Checking of PAS parameters has already been done in
- * gpt_validate_pas_mappings so no need to check the same things again.
+ * validate_pas_mappings so no need to check the same things again.
*/
end_pa = pas->base_pa + pas->size;
@@ -586,7 +589,7 @@
/* We start working from the granule at base PA */
cur_pa = pas->base_pa;
- /* Iterate over each L0 region in this memory range. */
+ /* Iterate over each L0 region in this memory range */
for (l0_idx = GPT_L0_IDX(pas->base_pa);
l0_idx <= GPT_L0_IDX(end_pa - 1U);
l0_idx++) {
@@ -596,25 +599,23 @@
* need to create one.
*/
if (GPT_L0_TYPE(l0_gpt_base[l0_idx]) == GPT_L0_TYPE_TBL_DESC) {
- /* Get the L1 array from the L0 entry. */
+ /* Get the L1 array from the L0 entry */
l1_gpt_arr = GPT_L0_TBLD_ADDR(l0_gpt_base[l0_idx]);
} else {
- /* Get a new L1 table from the L1 memory space. */
- l1_gpt_arr = gpt_get_new_l1_tbl();
+ /* Get a new L1 table from the L1 memory space */
+ l1_gpt_arr = get_new_l1_tbl();
- /* Fill out the L0 descriptor and flush it. */
+ /* Fill out the L0 descriptor and flush it */
l0_gpt_base[l0_idx] = GPT_L0_TBL_DESC(l1_gpt_arr);
}
- VERBOSE("[GPT] L0 entry (TABLE) index %u [%p] ==> L1 Addr 0x%llx (0x%" PRIx64 ")\n",
- l0_idx, &l0_gpt_base[l0_idx],
- (unsigned long long)(l1_gpt_arr),
- l0_gpt_base[l0_idx]);
+ VERBOSE("GPT: L0 entry (TABLE) index %u [%p] ==> L1 Addr %p (0x%"PRIx64")\n",
+ l0_idx, &l0_gpt_base[l0_idx], l1_gpt_arr, l0_gpt_base[l0_idx]);
/*
* Determine the PA of the last granule in this L0 descriptor.
*/
- last_gran_pa = gpt_get_l1_end_pa(cur_pa, end_pa) -
+ last_gran_pa = get_l1_end_pa(cur_pa, end_pa) -
GPT_PGS_ACTUAL_SIZE(gpt_config.p);
/*
@@ -622,11 +623,11 @@
* function needs the addresses of the first granule and last
* granule in the range.
*/
- gpt_fill_l1_tbl(GPT_PAS_ATTR_GPI(pas->attrs), l1_gpt_arr,
+ fill_l1_tbl(GPT_PAS_ATTR_GPI(pas->attrs), l1_gpt_arr,
cur_pa, last_gran_pa);
- /* Advance cur_pa to first granule in next L0 region. */
- cur_pa = gpt_get_l1_end_pa(cur_pa, end_pa);
+ /* Advance cur_pa to first granule in next L0 region */
+ cur_pa = get_l1_end_pa(cur_pa, end_pa);
}
}
@@ -649,19 +650,19 @@
uint64_t *l0 = (uint64_t *)gpt_config.plat_gpt_l0_base;
assert(pas != NULL);
- assert(pas_count > 0);
+ assert(pas_count != 0U);
- /* Initial start and end values. */
+ /* Initial start and end values */
start_idx = GPT_L0_IDX(pas[0].base_pa);
- end_idx = GPT_L0_IDX(pas[0].base_pa + pas[0].size - 1);
+ end_idx = GPT_L0_IDX(pas[0].base_pa + pas[0].size - 1UL);
- /* Find lowest and highest L0 indices used in this PAS array. */
- for (idx = 1; idx < pas_count; idx++) {
+ /* Find lowest and highest L0 indices used in this PAS array */
+ for (idx = 1U; idx < pas_count; idx++) {
if (GPT_L0_IDX(pas[idx].base_pa) < start_idx) {
start_idx = GPT_L0_IDX(pas[idx].base_pa);
}
- if (GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1) > end_idx) {
- end_idx = GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1);
+ if (GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1UL) > end_idx) {
+ end_idx = GPT_L0_IDX(pas[idx].base_pa + pas[idx].size - 1UL);
}
}
@@ -670,7 +671,7 @@
* the end index value.
*/
flush_dcache_range((uintptr_t)&l0[start_idx],
- ((end_idx + 1) - start_idx) * sizeof(uint64_t));
+ ((end_idx + 1U) - start_idx) * sizeof(uint64_t));
}
/*
@@ -689,8 +690,8 @@
* Granule tables must be initialised before enabling
* granule protection.
*/
- if (gpt_config.plat_gpt_l0_base == 0U) {
- ERROR("[GPT] Tables have not been initialized!\n");
+ if (gpt_config.plat_gpt_l0_base == 0UL) {
+ ERROR("GPT: Tables have not been initialized!\n");
return -EPERM;
}
@@ -711,7 +712,7 @@
*/
gpccr_el3 |= SET_GPCCR_SH(GPCCR_SH_IS);
- /* Outer and Inner cacheability set to Normal memory, WB, RA, WA. */
+ /* Outer and Inner cacheability set to Normal memory, WB, RA, WA */
gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA);
gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA);
@@ -727,7 +728,7 @@
/* Enable GPT */
gpccr_el3 |= GPCCR_GPC_BIT;
- /* TODO: Configure GPCCR_EL3_GPCP for Fault control. */
+ /* TODO: Configure GPCCR_EL3_GPCP for Fault control */
write_gpccr_el3(gpccr_el3);
isb();
tlbipaallos();
@@ -769,16 +770,16 @@
int ret;
uint64_t gpt_desc;
- /* Ensure that MMU and Data caches are enabled. */
+ /* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
- /* Validate other parameters. */
- ret = gpt_validate_l0_params(pps, l0_mem_base, l0_mem_size);
+ /* Validate other parameters */
+ ret = validate_l0_params(pps, l0_mem_base, l0_mem_size);
if (ret != 0) {
return ret;
}
- /* Create the descriptor to initialize L0 entries with. */
+ /* Create the descriptor to initialize L0 entries with */
gpt_desc = GPT_L0_BLK_DESC(GPT_GPI_ANY);
/* Iterate through all L0 entries */
@@ -786,11 +787,11 @@
((uint64_t *)l0_mem_base)[i] = gpt_desc;
}
- /* Flush updated L0 tables to memory. */
+ /* Flush updated L0 tables to memory */
flush_dcache_range((uintptr_t)l0_mem_base,
(size_t)GPT_L0_TABLE_SIZE(gpt_config.t));
- /* Stash the L0 base address once initial setup is complete. */
+ /* Stash the L0 base address once initial setup is complete */
gpt_config.plat_gpt_l0_base = l0_mem_base;
return 0;
@@ -824,79 +825,79 @@
int ret;
int l1_gpt_cnt;
- /* Ensure that MMU and Data caches are enabled. */
+ /* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
- /* PGS is needed for gpt_validate_pas_mappings so check it now. */
+ /* PGS is needed for validate_pas_mappings so check it now */
if (pgs > GPT_PGS_MAX) {
- ERROR("[GPT] Invalid PGS: 0x%x\n", pgs);
+ ERROR("GPT: Invalid PGS: 0x%x\n", pgs);
return -EINVAL;
}
gpt_config.pgs = pgs;
gpt_config.p = gpt_p_lookup[pgs];
- /* Make sure L0 tables have been initialized. */
+ /* Make sure L0 tables have been initialized */
if (gpt_config.plat_gpt_l0_base == 0U) {
- ERROR("[GPT] L0 tables must be initialized first!\n");
+ ERROR("GPT: L0 tables must be initialized first!\n");
return -EPERM;
}
- /* Check if L1 GPTs are required and how many. */
- l1_gpt_cnt = gpt_validate_pas_mappings(pas_regions, pas_count);
+ /* Check if L1 GPTs are required and how many */
+ l1_gpt_cnt = validate_pas_mappings(pas_regions, pas_count);
if (l1_gpt_cnt < 0) {
return l1_gpt_cnt;
}
- VERBOSE("[GPT] %u L1 GPTs requested.\n", l1_gpt_cnt);
+ VERBOSE("GPT: %i L1 GPTs requested\n", l1_gpt_cnt);
- /* If L1 tables are needed then validate the L1 parameters. */
+ /* If L1 tables are needed then validate the L1 parameters */
if (l1_gpt_cnt > 0) {
- ret = gpt_validate_l1_params(l1_mem_base, l1_mem_size,
- l1_gpt_cnt);
+ ret = validate_l1_params(l1_mem_base, l1_mem_size,
+ (unsigned int)l1_gpt_cnt);
if (ret != 0) {
return ret;
}
- /* Set up parameters for L1 table generation. */
+ /* Set up parameters for L1 table generation */
gpt_l1_tbl = l1_mem_base;
gpt_next_l1_tbl_idx = 0U;
}
- INFO("[GPT] Boot Configuration\n");
+ INFO("GPT: Boot Configuration\n");
INFO(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t);
INFO(" PGS/P: 0x%x/%u\n", gpt_config.pgs, gpt_config.p);
INFO(" L0GPTSZ/S: 0x%x/%u\n", GPT_L0GPTSZ, GPT_S_VAL);
- INFO(" PAS count: 0x%x\n", pas_count);
- INFO(" L0 base: 0x%lx\n", gpt_config.plat_gpt_l0_base);
+ INFO(" PAS count: %u\n", pas_count);
+ INFO(" L0 base: 0x%"PRIxPTR"\n", gpt_config.plat_gpt_l0_base);
- /* Generate the tables in memory. */
+ /* Generate the tables in memory */
for (unsigned int idx = 0U; idx < pas_count; idx++) {
- INFO("[GPT] PAS[%u]: base 0x%lx, size 0x%lx, GPI 0x%x, type 0x%x\n",
- idx, pas_regions[idx].base_pa, pas_regions[idx].size,
- GPT_PAS_ATTR_GPI(pas_regions[idx].attrs),
- GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs));
+ VERBOSE("GPT: PAS[%u]: base 0x%"PRIxPTR"\tsize 0x%lx\tGPI 0x%x\ttype 0x%x\n",
+ idx, pas_regions[idx].base_pa, pas_regions[idx].size,
+ GPT_PAS_ATTR_GPI(pas_regions[idx].attrs),
+ GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs));
/* Check if a block or table descriptor is required */
if (GPT_PAS_ATTR_MAP_TYPE(pas_regions[idx].attrs) ==
GPT_PAS_ATTR_MAP_TYPE_BLOCK) {
- gpt_generate_l0_blk_desc(&pas_regions[idx]);
+ generate_l0_blk_desc(&pas_regions[idx]);
} else {
- gpt_generate_l0_tbl_desc(&pas_regions[idx]);
+ generate_l0_tbl_desc(&pas_regions[idx]);
}
}
- /* Flush modified L0 tables. */
+ /* Flush modified L0 tables */
flush_l0_for_pas_array(pas_regions, pas_count);
- /* Flush L1 tables if needed. */
+ /* Flush L1 tables if needed */
if (l1_gpt_cnt > 0) {
flush_dcache_range(l1_mem_base,
GPT_L1_TABLE_SIZE(gpt_config.p) *
l1_gpt_cnt);
}
- /* Make sure that all the entries are written to the memory. */
+ /* Make sure that all the entries are written to the memory */
dsbishst();
tlbipaallos();
dsb();
@@ -920,12 +921,12 @@
{
u_register_t reg;
- /* Ensure that MMU and Data caches are enabled. */
+ /* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
- /* Ensure GPC are already enabled. */
+ /* Ensure GPC are already enabled */
if ((read_gpccr_el3() & GPCCR_GPC_BIT) == 0U) {
- ERROR("[GPT] Granule protection checks are not enabled!\n");
+ ERROR("GPT: Granule protection checks are not enabled!\n");
return -EPERM;
}
@@ -938,18 +939,18 @@
GPTBR_BADDR_MASK) <<
GPTBR_BADDR_VAL_SHIFT;
- /* Read GPCCR to get PGS and PPS values. */
+ /* Read GPCCR to get PGS and PPS values */
reg = read_gpccr_el3();
gpt_config.pps = (reg >> GPCCR_PPS_SHIFT) & GPCCR_PPS_MASK;
gpt_config.t = gpt_t_lookup[gpt_config.pps];
gpt_config.pgs = (reg >> GPCCR_PGS_SHIFT) & GPCCR_PGS_MASK;
gpt_config.p = gpt_p_lookup[gpt_config.pgs];
- VERBOSE("[GPT] Runtime Configuration\n");
+ VERBOSE("GPT: Runtime Configuration\n");
VERBOSE(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t);
VERBOSE(" PGS/P: 0x%x/%u\n", gpt_config.pgs, gpt_config.p);
VERBOSE(" L0GPTSZ/S: 0x%x/%u\n", GPT_L0GPTSZ, GPT_S_VAL);
- VERBOSE(" L0 base: 0x%lx\n", gpt_config.plat_gpt_l0_base);
+ VERBOSE(" L0 base: 0x%"PRIxPTR"\n", gpt_config.plat_gpt_l0_base);
return 0;
}
@@ -963,7 +964,7 @@
/*
* A helper to write the value (target_pas << gpi_shift) to the index of
- * the gpt_l1_addr
+ * the gpt_l1_addr.
*/
static inline void write_gpt(uint64_t *gpt_l1_desc, uint64_t *gpt_l1_addr,
unsigned int gpi_shift, unsigned int idx,
@@ -976,7 +977,7 @@
/*
* Helper to retrieve the gpt_l1_* information from the base address
- * returned in gpi_info
+ * returned in gpi_info.
*/
static int get_gpi_params(uint64_t base, gpi_info_t *gpi_info)
{
@@ -985,12 +986,12 @@
gpt_l0_base = (uint64_t *)gpt_config.plat_gpt_l0_base;
gpt_l0_desc = gpt_l0_base[GPT_L0_IDX(base)];
if (GPT_L0_TYPE(gpt_l0_desc) != GPT_L0_TYPE_TBL_DESC) {
- VERBOSE("[GPT] Granule is not covered by a table descriptor!\n");
- VERBOSE(" Base=0x%" PRIx64 "\n", base);
+ VERBOSE("GPT: Granule is not covered by a table descriptor!\n");
+ VERBOSE(" Base=0x%"PRIx64"\n", base);
return -EINVAL;
}
- /* Get the table index and GPI shift from PA. */
+ /* Get the table index and GPI shift from PA */
gpi_info->gpt_l1_addr = GPT_L0_TBLD_ADDR(gpt_l0_desc);
gpi_info->idx = GPT_L1_IDX(gpt_config.p, base);
gpi_info->gpi_shift = GPT_L1_GPI_IDX(gpt_config.p, base) << 2;
@@ -1025,36 +1026,36 @@
int res;
unsigned int target_pas;
- /* Ensure that the tables have been set up before taking requests. */
+ /* Ensure that the tables have been set up before taking requests */
assert(gpt_config.plat_gpt_l0_base != 0UL);
- /* Ensure that caches are enabled. */
+ /* Ensure that caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
/* Delegate request can only come from REALM or SECURE */
assert(src_sec_state == SMC_FROM_REALM ||
src_sec_state == SMC_FROM_SECURE);
- /* See if this is a single or a range of granule transition. */
+ /* See if this is a single or a range of granule transition */
if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
return -EINVAL;
}
/* Check that base and size are valid */
if ((ULONG_MAX - base) < size) {
- VERBOSE("[GPT] Transition request address overflow!\n");
- VERBOSE(" Base=0x%" PRIx64 "\n", base);
+ VERBOSE("GPT: Transition request address overflow!\n");
+ VERBOSE(" Base=0x%"PRIx64"\n", base);
VERBOSE(" Size=0x%lx\n", size);
return -EINVAL;
}
- /* Make sure base and size are valid. */
- if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
- ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
+ /* Make sure base and size are valid */
+ if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
+ ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
(size == 0UL) ||
((base + size) >= GPT_PPS_ACTUAL_SIZE(gpt_config.t))) {
- VERBOSE("[GPT] Invalid granule transition address range!\n");
- VERBOSE(" Base=0x%" PRIx64 "\n", base);
+ VERBOSE("GPT: Invalid granule transition address range!\n");
+ VERBOSE(" Base=0x%"PRIx64"\n", base);
VERBOSE(" Size=0x%lx\n", size);
return -EINVAL;
}
@@ -1078,7 +1079,7 @@
/* Check that the current address is in NS state */
if (gpi_info.gpi != GPT_GPI_NS) {
- VERBOSE("[GPT] Only Granule in NS state can be delegated.\n");
+ VERBOSE("GPT: Only Granule in NS state can be delegated.\n");
VERBOSE(" Caller: %u, Current GPI: %u\n", src_sec_state,
gpi_info.gpi);
spin_unlock(&gpt_lock);
@@ -1094,7 +1095,7 @@
/*
* In order to maintain mutual distrust between Realm and Secure
* states, remove any data speculatively fetched into the target
- * physical address space. Issue DC CIPAPA over address range
+ * physical address space. Issue DC CIPAPA over address range.
*/
if (is_feat_mte2_supported()) {
flush_dcache_to_popa_range_mte2(nse | base,
@@ -1121,14 +1122,14 @@
GPT_PGS_ACTUAL_SIZE(gpt_config.p));
}
- /* Unlock access to the L1 tables. */
+ /* Unlock access to the L1 tables */
spin_unlock(&gpt_lock);
/*
* The isb() will be done as part of context
- * synchronization when returning to lower EL
+ * synchronization when returning to lower EL.
*/
- VERBOSE("[GPT] Granule 0x%" PRIx64 ", GPI 0x%x->0x%x\n",
+ VERBOSE("GPT: Granule 0x%"PRIx64" GPI 0x%x->0x%x\n",
base, gpi_info.gpi, target_pas);
return 0;
@@ -1157,36 +1158,36 @@
uint64_t nse;
int res;
- /* Ensure that the tables have been set up before taking requests. */
+ /* Ensure that the tables have been set up before taking requests */
assert(gpt_config.plat_gpt_l0_base != 0UL);
- /* Ensure that MMU and caches are enabled. */
+ /* Ensure that MMU and caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
/* Delegate request can only come from REALM or SECURE */
assert(src_sec_state == SMC_FROM_REALM ||
src_sec_state == SMC_FROM_SECURE);
- /* See if this is a single or a range of granule transition. */
+ /* See if this is a single or a range of granule transition */
if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
return -EINVAL;
}
/* Check that base and size are valid */
if ((ULONG_MAX - base) < size) {
- VERBOSE("[GPT] Transition request address overflow!\n");
- VERBOSE(" Base=0x%" PRIx64 "\n", base);
+ VERBOSE("GPT: Transition request address overflow!\n");
+ VERBOSE(" Base=0x%"PRIx64"\n", base);
VERBOSE(" Size=0x%lx\n", size);
return -EINVAL;
}
- /* Make sure base and size are valid. */
- if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
- ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) != 0UL) ||
+ /* Make sure base and size are valid */
+ if (((base & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
+ ((size & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) != 0UL) ||
(size == 0UL) ||
((base + size) >= GPT_PPS_ACTUAL_SIZE(gpt_config.t))) {
- VERBOSE("[GPT] Invalid granule transition address range!\n");
- VERBOSE(" Base=0x%" PRIx64 "\n", base);
+ VERBOSE("GPT: Invalid granule transition address range!\n");
+ VERBOSE(" Base=0x%"PRIx64"\n", base);
VERBOSE(" Size=0x%lx\n", size);
return -EINVAL;
}
@@ -1209,8 +1210,8 @@
gpi_info.gpi != GPT_GPI_REALM) ||
(src_sec_state == SMC_FROM_SECURE &&
gpi_info.gpi != GPT_GPI_SECURE)) {
- VERBOSE("[GPT] Only Granule in REALM or SECURE state can be undelegated.\n");
- VERBOSE(" Caller: %u, Current GPI: %u\n", src_sec_state,
+ VERBOSE("GPT: Only Granule in REALM or SECURE state can be undelegated.\n");
+ VERBOSE(" Caller: %u Current GPI: %u\n", src_sec_state,
gpi_info.gpi);
spin_unlock(&gpt_lock);
return -EPERM;
@@ -1272,9 +1273,9 @@
/*
* The isb() will be done as part of context
- * synchronization when returning to lower EL
+ * synchronization when returning to lower EL.
*/
- VERBOSE("[GPT] Granule 0x%" PRIx64 ", GPI 0x%x->0x%x\n",
+ VERBOSE("GPT: Granule 0x%"PRIx64" GPI 0x%x->0x%x\n",
base, gpi_info.gpi, GPT_GPI_NS);
return 0;
diff --git a/lib/gpt_rme/gpt_rme_private.h b/lib/gpt_rme/gpt_rme_private.h
index 3c817f3..b2a5dae 100644
--- a/lib/gpt_rme/gpt_rme_private.h
+++ b/lib/gpt_rme/gpt_rme_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,13 +15,13 @@
/* GPT descriptor definitions */
/******************************************************************************/
-/* GPT level 0 descriptor bit definitions. */
+/* GPT level 0 descriptor bit definitions */
#define GPT_L0_TYPE_MASK UL(0xF)
#define GPT_L0_TYPE_SHIFT U(0)
-/* For now, we don't support contiguous descriptors, only table and block. */
-#define GPT_L0_TYPE_TBL_DESC UL(0x3)
-#define GPT_L0_TYPE_BLK_DESC UL(0x1)
+/* For now, we don't support contiguous descriptors, only table and block */
+#define GPT_L0_TYPE_TBL_DESC UL(3)
+#define GPT_L0_TYPE_BLK_DESC UL(1)
#define GPT_L0_TBL_DESC_L1ADDR_MASK UL(0xFFFFFFFFFF)
#define GPT_L0_TBL_DESC_L1ADDR_SHIFT U(12)
@@ -57,7 +57,7 @@
/* GPT platform configuration */
/******************************************************************************/
-/* This value comes from GPCCR_EL3 so no externally supplied definition. */
+/* This value comes from GPCCR_EL3 so no externally supplied definition */
#define GPT_L0GPTSZ ((unsigned int)((read_gpccr_el3() >> \
GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK))
@@ -117,10 +117,10 @@
unsigned int gpi;
} gpi_info_t;
-/* Max valid value for PGS. */
+/* Max valid value for PGS */
#define GPT_PGS_MAX (2U)
-/* Max valid value for PPS. */
+/* Max valid value for PPS */
#define GPT_PPS_MAX (6U)
/******************************************************************************/
@@ -139,7 +139,7 @@
#define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \
((_t) - GPT_S_VAL) : (0U))
-/* Bit shift for the L0 index field in a PA. */
+/* Bit shift for the L0 index field in a PA */
#define GPT_L0_IDX_SHIFT (GPT_S_VAL)
/*
@@ -153,13 +153,13 @@
#define GPT_L0_IDX_MASK(_t) (0x3FFFFFUL >> (22U - \
(GPT_L0_IDX_WIDTH(_t))))
-/* Total number of L0 regions. */
+/* Total number of L0 regions */
#define GPT_L0_REGION_COUNT(_t) ((GPT_L0_IDX_MASK(_t)) + 1U)
-/* Total size of each GPT L0 region in bytes. */
+/* Total size of each GPT L0 region in bytes */
#define GPT_L0_REGION_SIZE (1UL << (GPT_L0_IDX_SHIFT))
-/* Total size in bytes of the whole L0 table. */
+/* Total size in bytes of the whole L0 table */
#define GPT_L0_TABLE_SIZE(_t) ((GPT_L0_REGION_COUNT(_t)) << 3U)
/******************************************************************************/
@@ -175,7 +175,7 @@
*/
#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U))
-/* Bit shift for the L1 index field. */
+/* Bit shift for the L1 index field */
#define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U)
/*
@@ -183,38 +183,38 @@
*
* The value 0x7FFFFF is 23 bits wide and is the maximum possible width of the
* L1 index within a physical address. It is calculated by
- * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512gb, the largest
+ * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512GB, the largest
* L0GPTSZ, and p_min is 12 for 4KB granules, the smallest PGS.
*/
#define GPT_L1_IDX_MASK(_p) (0x7FFFFFUL >> (23U - \
(GPT_L1_IDX_WIDTH(_p))))
-/* Bit shift for the index of the L1 GPI in a PA. */
+/* Bit shift for the index of the L1 GPI in a PA */
#define GPT_L1_GPI_IDX_SHIFT(_p) (_p)
-/* Mask for the index of the L1 GPI in a PA. */
+/* Mask for the index of the L1 GPI in a PA */
#define GPT_L1_GPI_IDX_MASK (0xF)
-/* Total number of entries in each L1 table. */
+/* Total number of entries in each L1 table */
#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U)
-/* Total size in bytes of each L1 table. */
+/* Total size in bytes of each L1 table */
#define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U)
/******************************************************************************/
/* General helper macros */
/******************************************************************************/
-/* Protected space actual size in bytes. */
+/* Protected space actual size in bytes */
#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t))
-/* Granule actual size in bytes. */
+/* Granule actual size in bytes */
#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p))
-/* L0 GPT region size in bytes. */
+/* L0 GPT region size in bytes */
#define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL)
-/* Get the index of the L0 entry from a physical address. */
+/* Get the index of the L0 entry from a physical address */
#define GPT_L0_IDX(_pa) ((_pa) >> GPT_L0_IDX_SHIFT)
/*
@@ -223,38 +223,38 @@
*/
#define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
-/* Get the type field from an L0 descriptor. */
+/* Get the type field from an L0 descriptor */
#define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \
GPT_L0_TYPE_MASK)
-/* Create an L0 block descriptor. */
+/* Create an L0 block descriptor */
#define GPT_L0_BLK_DESC(_gpi) (GPT_L0_TYPE_BLK_DESC | \
(((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \
GPT_L0_BLK_DESC_GPI_SHIFT))
-/* Create an L0 table descriptor with an L1 table address. */
+/* Create an L0 table descriptor with an L1 table address */
#define GPT_L0_TBL_DESC(_pa) (GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \
(GPT_L0_TBL_DESC_L1ADDR_MASK << \
GPT_L0_TBL_DESC_L1ADDR_SHIFT)))
-/* Get the GPI from an L0 block descriptor. */
+/* Get the GPI from an L0 block descriptor */
#define GPT_L0_BLKD_GPI(_desc) (((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \
GPT_L0_BLK_DESC_GPI_MASK)
-/* Get the L1 address from an L0 table descriptor. */
+/* Get the L1 address from an L0 table descriptor */
#define GPT_L0_TBLD_ADDR(_desc) ((uint64_t *)(((_desc) & \
(GPT_L0_TBL_DESC_L1ADDR_MASK << \
GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
-/* Get the index into the L1 table from a physical address. */
+/* Get the index into the L1 table from a physical address */
#define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
GPT_L1_IDX_MASK(_p))
-/* Get the index of the GPI within an L1 table entry from a physical address. */
+/* Get the index of the GPI within an L1 table entry from a physical address */
#define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
GPT_L1_GPI_IDX_MASK)
-/* Determine if an address is granule-aligned. */
+/* Determine if an address is granule-aligned */
#define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
== U(0))
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index 5144bf7..77bb7fe 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,8 @@
.globl spin_lock
.globl spin_unlock
+ .globl bit_lock
+ .globl bit_unlock
#if USE_SPINLOCK_CAS
#if !ARM_ARCH_AT_LEAST(8, 1)
@@ -73,3 +75,43 @@
stlr wzr, [x0]
ret
endfunc spin_unlock
+
+/*
+ * Atomic bit clear and set instructions require FEAT_LSE which is
+ * mandatory from Armv8.1.
+ */
+#if ARM_ARCH_AT_LEAST(8, 1)
+
+/*
+ * Acquire bitlock using atomic bit set on byte. If the original read value
+ * has the bit set, use load exclusive semantics to monitor the address and
+ * enter WFE.
+ *
+ * void bit_lock(bitlock_t *lock, uint8_t mask);
+ */
+func bit_lock
+1: ldsetab w1, w2, [x0]
+ tst w2, w1
+ b.eq 2f
+ ldxrb w2, [x0]
+ tst w2, w1
+ b.eq 1b
+ wfe
+ b 1b
+2:
+ ret
+endfunc bit_lock
+
+/*
+ * Use atomic bit clear store-release to unconditionally clear bitlock variable.
+ * Store operation generates an event to all cores waiting in WFE when address
+ * is monitored by the global monitor.
+ *
+ * void bit_unlock(bitlock_t *lock, uint8_t mask);
+ */
+func bit_unlock
+ stclrlb w1, [x0]
+ ret
+endfunc bit_unlock
+
+#endif /* ARM_ARCH_AT_LEAST(8, 1) */
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 41c7919..bd7a452 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -172,7 +172,8 @@
******************************************************************************/
static bool psci_is_last_cpu_to_idle_at_pwrlvl(unsigned int end_pwrlvl)
{
- unsigned int my_idx, lvl, parent_idx;
+ unsigned int my_idx, lvl;
+ unsigned int parent_idx = 0;
unsigned int cpu_start_idx, ncpus, cpu_idx;
plat_local_state_t local_state;
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index f11e577..62cbf3e 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -30,9 +30,10 @@
Q :=
endif
-LDFLAGS := --gc-sections -O1
+LDFLAGS := -Wl,--gc-sections -nostdlib
+
ifeq ($(DEBUG),1)
- LDFLAGS += -Map=$(MAPFILE)
+ LDFLAGS += -Wl,-Map=$(MAPFILE)
endif
ifeq (${ARM_ARCH_MINOR},0)
diff --git a/lib/transfer_list/transfer_list.c b/lib/transfer_list/transfer_list.c
index 63969e9..b7fedfa 100644
--- a/lib/transfer_list/transfer_list.c
+++ b/lib/transfer_list/transfer_list.c
@@ -366,7 +366,6 @@
/* create a dummy TE to fill up the gap */
dummy_te = (struct transfer_list_entry *)new_ev;
dummy_te->tag_id = TL_TAG_EMPTY;
- dummy_te->reserved0 = 0;
dummy_te->hdr_size = sizeof(*dummy_te);
dummy_te->data_size = gap - sizeof(*dummy_te);
}
@@ -388,7 +387,6 @@
return false;
}
te->tag_id = TL_TAG_EMPTY;
- te->reserved0 = 0;
transfer_list_update_checksum(tl);
return true;
}
@@ -399,7 +397,7 @@
* Return pointer to the added transfer entry or NULL on error
******************************************************************************/
struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl,
- uint16_t tag_id,
+ uint32_t tag_id,
uint32_t data_size,
const void *data)
{
@@ -428,7 +426,6 @@
te = (struct transfer_list_entry *)tl_ev;
te->tag_id = tag_id;
- te->reserved0 = 0;
te->hdr_size = sizeof(*te);
te->data_size = data_size;
tl->size += ev - tl_ev;
@@ -454,7 +451,7 @@
* Return pointer to the added transfer entry or NULL on error
******************************************************************************/
struct transfer_list_entry *
-transfer_list_add_with_align(struct transfer_list_header *tl, uint16_t tag_id,
+transfer_list_add_with_align(struct transfer_list_header *tl, uint32_t tag_id,
uint32_t data_size, const void *data,
uint8_t alignment)
{
@@ -501,13 +498,13 @@
* Return pointer to the found transfer entry or NULL on error
******************************************************************************/
struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl,
- uint16_t tag_id)
+ uint32_t tag_id)
{
struct transfer_list_entry *te = NULL;
do {
te = transfer_list_next(tl, te);
- } while (te && (te->tag_id != tag_id || te->reserved0 != 0));
+ } while (te && (te->tag_id != tag_id));
return te;
}
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index a99d516..36ac126 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -10,11 +10,6 @@
$(error This makefile only works with a Make program that supports $$(eval))
endif
-# Some utility macros for manipulating awkward (whitespace) characters.
-blank :=
-space :=${blank} ${blank}
-comma := ,
-
# A user defined function to recursively search for a filename below a directory
# $1 is the directory root of the recursive search (blank for current directory).
# $2 is the file name to search for.
diff --git a/make_helpers/toolchain.mk b/make_helpers/toolchain.mk
index 7255509..2f47647 100644
--- a/make_helpers/toolchain.mk
+++ b/make_helpers/toolchain.mk
@@ -60,6 +60,8 @@
endif
include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
+include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
+
include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
$(addsuffix .mk,$(toolchains)))
@@ -222,27 +224,27 @@
#
# Arm Compiler for Embedded
-guess-tool-arm-clang = $(shell $(1) --version 2>&1 | grep -o "Tool: armclang")
-guess-tool-arm-link = $(shell $(1) --help 2>&1 | grep -o "Tool: armlink")
-guess-tool-arm-fromelf = $(shell $(1) --help 2>&1 | grep -o "Tool: fromelf")
-guess-tool-arm-ar = $(shell $(1) --version 2>&1 | grep -o "Tool: armar")
+guess-tool-arm-clang = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
+guess-tool-arm-link = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
+guess-tool-arm-fromelf = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
+guess-tool-arm-ar = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Tool: armar")
# LLVM Project
-guess-tool-llvm-clang = $(shell $(1) -v 2>&1 | grep -o "clang version")
-guess-tool-llvm-lld = $(shell $(1) --help 2>&1 | grep -o "OVERVIEW: lld")
-guess-tool-llvm-objcopy = $(shell $(1) --help 2>&1 | grep -o "llvm-objcopy tool")
-guess-tool-llvm-objdump = $(shell $(1) --help 2>&1 | grep -o "llvm object file dumper")
-guess-tool-llvm-ar = $(shell $(1) --help 2>&1 | grep -o "LLVM Archiver")
+guess-tool-llvm-clang = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "clang version")
+guess-tool-llvm-lld = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
+guess-tool-llvm-objcopy = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
+guess-tool-llvm-objdump = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
+guess-tool-llvm-ar = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
# GNU Compiler Collection & GNU Binary Utilities
-guess-tool-gnu-gcc = $(shell $(1) -v 2>&1 | grep -o "gcc version")
-guess-tool-gnu-ld = $(shell $(1) -v 2>&1 | grep -o "GNU ld")
-guess-tool-gnu-objcopy = $(shell $(1) --version 2>&1 | grep -o "GNU objcopy")
-guess-tool-gnu-objdump = $(shell $(1) --version 2>&1 | grep -o "GNU objdump")
-guess-tool-gnu-ar = $(shell $(1) --version 2>&1 | grep -o "GNU ar")
+guess-tool-gnu-gcc = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "gcc version")
+guess-tool-gnu-ld = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "GNU ld")
+guess-tool-gnu-objcopy = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
+guess-tool-gnu-objdump = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU objdump")
+guess-tool-gnu-ar = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU ar")
# Other tools
-guess-tool-dtc = $(shell $(1) --version 2>&1 | grep -o "Version: DTC")
+guess-tool-dtc = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Version: DTC")
guess-tool = $(firstword $(foreach candidate,$(1), \
$(if $(call guess-tool-$(candidate),$(2)),$(candidate))))
@@ -271,34 +273,32 @@
# variable.
#
-guess-arm-clang-cpp = $(1) # Use the C compiler
-guess-arm-clang-as = $(1) # Use the C compiler
+guess-arm-clang-cpp = $(1)
+guess-arm-clang-as = $(1)
guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
-guess-llvm-clang-cpp = $(1) # Use the C compiler
-guess-llvm-clang-as = $(1) # Use the C compiler
-guess-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
-guess-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
-guess-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
-guess-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
+guess-llvm-clang-cpp = $(1)
+guess-llvm-clang-as = $(1)
+guess-llvm-clang-ld = $(shell $(call escape-shell,$(1)) --print-prog-name ld.lld 2>$(nul))
+guess-llvm-clang-oc = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-objcopy 2>$(nul))
+guess-llvm-clang-od = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-objdump 2>$(nul))
+guess-llvm-clang-ar = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-ar 2>$(nul))
-guess-gnu-gcc-cpp = $(1) # Use the C compiler
-guess-gnu-gcc-as = $(1) # Use the C compiler
-guess-gnu-gcc-ld = $(if $(filter 1,$(ENABLE_LTO)),$(1),$(shell $(1) --print-prog-name ld.bfd 2>$(nul)))
-guess-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
-guess-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
-guess-gnu-gcc-ar = $(patsubst %$(notdir $(1)),%$(subst gcc,gcc-ar,$(notdir $(1))),$(1))
+guess-gnu-gcc-cpp = $(1)
+guess-gnu-gcc-as = $(1)
+guess-gnu-gcc-ld = $(1)
+guess-gnu-gcc-oc = $(shell $(call escape-shell,$(1)) --print-prog-name objcopy 2>$(nul))
+guess-gnu-gcc-od = $(shell $(call escape-shell,$(1)) --print-prog-name objdump 2>$(nul))
+guess-gnu-gcc-ar = $(call which,$(call decompat-path,$(patsubst %$(call file-name,$(1)),%$(subst gcc,gcc-ar,$(call file-name,$(1))),$(call compat-path,$(1)))))
define locate-toolchain-tool-cc
$(eval toolchain := $(1))
- $(toolchain)-cc := $$(strip \
- $$(or $$($(toolchain)-cc),$$($(toolchain)-cc-default)))
- $(toolchain)-cc-id := $$(strip \
- $$(call guess-tool,$$(tools-cc),$$($(toolchain)-cc)))
+ $(toolchain)-cc := $$(or $$($(toolchain)-cc),$$($(toolchain)-cc-default))
+ $(toolchain)-cc-id := $$(call guess-tool,$$(tools-cc),$$($(toolchain)-cc))
endef
define locate-toolchain-tool
@@ -306,26 +306,24 @@
$(eval tool-class := $(2))
ifndef $(toolchain)-$(tool-class)
- $(toolchain)-$(tool-class) := $$(strip \
- $$(call guess-$$($(toolchain)-cc-id)-$(tool-class),$$($(toolchain)-cc)))
+ $(toolchain)-$(tool-class) := $$(call guess-$$($(toolchain)-cc-id)-$(tool-class),$$($(toolchain)-cc-path))
ifeq ($$($(toolchain)-$(tool-class)),)
- $(toolchain)-$(tool-class) := $$(strip \
- $$($(toolchain)-$(tool-class)-default))
+ $(toolchain)-$(tool-class) := $$($(toolchain)-$(tool-class)-default)
endif
endif
- $(toolchain)-$(tool-class)-id := $$(strip \
- $$(call guess-tool,$$(tools-$(tool-class)),$$($$(toolchain)-$(tool-class))))
+ $(toolchain)-$(tool-class)-id := $$(call guess-tool,$$(tools-$(tool-class)),$$($$(toolchain)-$(tool-class)))
endef
define canonicalize-toolchain-tool-path
$(eval toolchain := $(1))
$(eval tool-class := $(2))
- $(toolchain)-$(tool-class) := $$(strip $$(or \
- $$(call which,$$($(toolchain)-$(tool-class))), \
- $$($(toolchain)-$(tool-class))))
+ $(toolchain)-$(tool-class)-path := $$(call absolute-path,$$(call which,$$($(toolchain)-$(tool-class))))
+ $(toolchain)-$(tool-class)-path := $$(or $$($(toolchain)-$(tool-class)-path),$$($(toolchain)-$(tool-class)))
+
+ $(toolchain)-$(tool-class) := $(call escape-shell,$$($(toolchain)-$(tool-class)-path))
endef
define locate-toolchain
diff --git a/make_helpers/toolchains/aarch32.mk b/make_helpers/toolchains/aarch32.mk
index 226bc75..3475c91 100644
--- a/make_helpers/toolchains/aarch32.mk
+++ b/make_helpers/toolchains/aarch32.mk
@@ -7,7 +7,7 @@
aarch32-cc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
aarch32-cpp-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
aarch32-as-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-ld-default := $(or $(CROSS_COMPILE),arm-none-eabi-)ld.bfd
+aarch32-ld-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
aarch32-oc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objcopy
aarch32-od-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objdump
aarch32-ar-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc-ar
diff --git a/make_helpers/toolchains/aarch64.mk b/make_helpers/toolchains/aarch64.mk
index 15c5757..d83d918 100644
--- a/make_helpers/toolchains/aarch64.mk
+++ b/make_helpers/toolchains/aarch64.mk
@@ -7,7 +7,7 @@
aarch64-cc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
aarch64-cpp-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
aarch64-as-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-ld-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)ld.bfd
+aarch64-ld-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
aarch64-oc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objcopy
aarch64-od-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objdump
aarch64-ar-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc-ar
diff --git a/make_helpers/toolchains/rk3399-m0.mk b/make_helpers/toolchains/rk3399-m0.mk
index c61b6e8..f57d658 100644
--- a/make_helpers/toolchains/rk3399-m0.mk
+++ b/make_helpers/toolchains/rk3399-m0.mk
@@ -7,7 +7,7 @@
rk3399-m0-cc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
rk3399-m0-cpp-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
rk3399-m0-as-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-ld-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)ld.bfd
+rk3399-m0-ld-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
rk3399-m0-oc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objcopy
rk3399-m0-od-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objdump
rk3399-m0-ar-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc-ar
diff --git a/make_helpers/unix.mk b/make_helpers/unix.mk
index d285799..93e1fcc 100644
--- a/make_helpers/unix.mk
+++ b/make_helpers/unix.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -59,5 +59,5 @@
nul := /dev/null
- which = $(shell which $(1) 2>$(nul))
+ which = $(shell command -v $(call escape-shell,$(1)) 2>$(nul))
endif
diff --git a/make_helpers/utilities.mk b/make_helpers/utilities.mk
new file mode 100644
index 0000000..62769fb
--- /dev/null
+++ b/make_helpers/utilities.mk
@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+space :=
+space := $(space) $(space)
+comma := ,
+
+null := �
+
+compat-path = $(subst $(space),$(null),$(1))
+decompat-path = $(subst $(null), ,$(1))
+
+absolute-path = $(call decompat-path,$(abspath $(call compat-path,$(1))))
+real-path = $(call decompat-path,$(realpath $(call compat-path,$(1))))
+
+file-name = $(call decompat-path,$(notdir $(call compat-path,$(1))))
+directory-name = $(call decompat-path,$(dir $(call compat-path,$(1))))
+
+escape-shell = '$(subst ','\'',$(1))'
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk
index 7ed8e84..a75a740 100644
--- a/make_helpers/windows.mk
+++ b/make_helpers/windows.mk
@@ -70,7 +70,7 @@
nul := nul
- which = $(shell where $(1) 2>$(nul))
+ which = $(shell where "$(1)" 2>$(nul))
endif
# Because git is not available from CMD.EXE, we need to avoid
diff --git a/plat/arm/board/a5ds/fdts/a5ds_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_fw_config.dts
index b9ff8bf..5bf6a3f 100644
--- a/plat/arm/board/a5ds/fdts/a5ds_fw_config.dts
+++ b/plat/arm/board/a5ds/fdts/a5ds_fw_config.dts
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
+#include <platform_def.h>
/dts-v1/;
@@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x83000000>;
- max-size = <0x01000000>;
+ max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index 9f3df1e..b134911 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -208,6 +208,9 @@
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
+/* Define memory configuration for device tree files. */
+#define PLAT_ARM_HW_CONFIG_SIZE U(0x01000000)
+
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 4adf5d5..5d58731 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
+#include <platform_def.h>
/dts-v1/;
@@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x07f00000>;
- max-size = <0x00100000>;
+ max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
secondary-load-address = <0x0 0x82000000>;
};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index ee6c260..30f1760 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -96,6 +96,15 @@
<0x0 0x88000000 0x0 0x10000000>;
};
+ memory@2 {
+ device_type = "device-memory";
+ reg = <0x0 0x1c090000 0x0 0x40000>, /* UART */
+ <0x0 0x2bfe0000 0x0 0x20000>, /* SMMUv3TestEngine */
+ <0x0 0x2a490000 0x0 0x20000>, /* SP805 Trusted Watchdog */
+ <0x0 0x1c130000 0x0 0x10000>; /* Virtio block device */
+ };
+
+
#if MEASURED_BOOT
#include "event_log.dtsi"
#endif
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index 17a2fd1..d90544b 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -1,8 +1,9 @@
/*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
/dts-v1/;
#define AFF 00
@@ -15,7 +16,7 @@
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
- #size-cells = <1>;
+ #size-cells = <2>;
attribute {
spmc_id = <0x8000>;
@@ -59,6 +60,17 @@
memory@6000000 {
device_type = "memory";
- reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */
+ reg = <0x0 0x6000000 0x0 0x2000000>; /* Trusted DRAM */
+ };
+
+ memory@1 {
+ device_type = "ns-memory";
+ reg = <0x00008800 0x80000000 0x0 0x7f000000>,
+ <0x0 0x88000000 0x0 0x10000000>;
+ };
+
+ memory@0 {
+ device_type = "device-memory";
+ reg = <0x0 0x1c090000 0x0 0x40000>; /* UART */
};
};
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index beae242..8cbf10e 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -5,6 +5,7 @@
*/
#include <assert.h>
+#include <string.h>
#include <common/debug.h>
#include <drivers/arm/cci.h>
@@ -33,6 +34,14 @@
#define FVP_GICV2 1
#define FVP_GICV3 2
+/* Defines for RMM Console*/
+#define FVP_RMM_CONSOLE_BASE UL(0x1c0c0000)
+#define FVP_RMM_CONSOLE_BAUD UL(115200)
+#define FVP_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
+#define FVP_RMM_CONSOLE_NAME "pl011"
+
+#define FVP_RMM_CONSOLE_COUNT UL(1)
+
/*******************************************************************************
* arm_config holds the characteristics of the differences between the three FVP
* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
@@ -552,8 +561,9 @@
int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
{
- uint64_t checksum, num_banks;
+ uint64_t checksum, num_banks, num_consoles;
struct ns_dram_bank *bank_ptr;
+ struct console_info *console_ptr;
assert(manifest != NULL);
@@ -561,43 +571,74 @@
num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks);
assert(num_banks <= ARM_DRAM_NUM_BANKS);
+ /* Set number of consoles */
+ num_consoles = FVP_RMM_CONSOLE_COUNT;
+
manifest->version = RMMD_MANIFEST_VERSION;
manifest->padding = 0U; /* RES0 */
manifest->plat_data = (uintptr_t)NULL;
manifest->plat_dram.num_banks = num_banks;
+ manifest->plat_console.num_consoles = num_consoles;
/*
- * Array ns_dram_banks[] follows ns_dram_info structure:
+ * Boot Manifest structure illustration, with two dram banks and
+ * a single console.
*
- * +-----------------------------------+
- * | offset | field | comment |
- * +----------+-----------+------------+
- * | 0 | version | 0x00000002 |
- * +----------+-----------+------------+
- * | 4 | padding | 0x00000000 |
- * +----------+-----------+------------+
- * | 8 | plat_data | NULL |
- * +----------+-----------+------------+
- * | 16 | num_banks | |
- * +----------+-----------+ |
- * | 24 | banks | plat_dram |
- * +----------+-----------+ |
- * | 32 | checksum | |
- * +----------+-----------+------------+
- * | 40 | base 0 | |
- * +----------+-----------+ bank[0] |
- * | 48 | size 0 | |
- * +----------+-----------+------------+
- * | 56 | base 1 | |
- * +----------+-----------+ bank[1] |
- * | 64 | size 1 | |
- * +----------+-----------+------------+
+ * +----------------------------------------+
+ * | offset | field | comment |
+ * +--------+----------------+--------------+
+ * | 0 | version | 0x00000003 |
+ * +--------+----------------+--------------+
+ * | 4 | padding | 0x00000000 |
+ * +--------+----------------+--------------+
+ * | 8 | plat_data | NULL |
+ * +--------+----------------+--------------+
+ * | 16 | num_banks | |
+ * +--------+----------------+ |
+ * | 24 | banks | plat_dram |
+ * +--------+----------------+ |
+ * | 32 | checksum | |
+ * +--------+----------------+--------------+
+ * | 40 | num_consoles | |
+ * +--------+----------------+ |
+ * | 48 | consoles | plat_console |
+ * +--------+----------------+ |
+ * | 56 | checksum | |
+ * +--------+----------------+--------------+
+ * | 64 | base 0 | |
+ * +--------+----------------+ bank[0] |
+ * | 72 | size 0 | |
+ * +--------+----------------+--------------+
+ * | 80 | base 1 | |
+ * +--------+----------------+ bank[1] |
+ * | 88 | size 1 | |
+ * +--------+----------------+--------------+
+ * | 96 | base | |
+ * +--------+----------------+ |
+ * | 104 | map_pages | |
+ * +--------+----------------+ |
+ * | 112 | name | |
+ * +--------+----------------+ consoles[0] |
+ * | 120 | clk_in_hz | |
+ * +--------+----------------+ |
+ * | 128 | baud_rate | |
+ * +--------+----------------+ |
+ * | 136 | flags | |
+ * +--------+----------------+--------------+
*/
+
bank_ptr = (struct ns_dram_bank *)
- ((uintptr_t)&manifest->plat_dram.checksum +
- sizeof(manifest->plat_dram.checksum));
+ (((uintptr_t)manifest) + sizeof(*manifest));
+ console_ptr = (struct console_info *)
+ ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
manifest->plat_dram.banks = bank_ptr;
+ manifest->plat_console.consoles = console_ptr;
+
+ /* Ensure the manifest is not larger than the shared buffer */
+ assert((sizeof(struct rmm_manifest) +
+ (sizeof(struct console_info) * manifest->plat_console.num_consoles) +
+ (sizeof(struct ns_dram_bank) * manifest->plat_dram.num_banks)) <= ARM_EL3_RMM_SHARED_SIZE);
/* Calculate checksum of plat_dram structure */
checksum = num_banks + (uint64_t)bank_ptr;
@@ -617,6 +658,26 @@
/* Checksum must be 0 */
manifest->plat_dram.checksum = ~checksum + 1UL;
+ /* Calculate the checksum of the plat_consoles structure */
+ checksum = num_consoles + (uint64_t)console_ptr;
+
+ /* Zero out the console info struct */
+ memset((void *)console_ptr, '\0', sizeof(struct console_info) * num_consoles);
+
+ console_ptr[0].map_pages = 1;
+ console_ptr[0].base = FVP_RMM_CONSOLE_BASE;
+ console_ptr[0].clk_in_hz = FVP_RMM_CONSOLE_CLK_IN_HZ;
+ console_ptr[0].baud_rate = FVP_RMM_CONSOLE_BAUD;
+
+ strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME, RMM_CONSOLE_MAX_NAME_LEN-1UL);
+
+ /* Update checksum */
+ checksum += console_ptr[0].base + console_ptr[0].map_pages +
+ console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+
+ /* Checksum must be 0 */
+ manifest->plat_console.checksum = ~checksum + 1UL;
+
return 0;
}
#endif /* ENABLE_RME */
diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
index 971e35b..1db0502 100644
--- a/plat/arm/board/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,7 +36,7 @@
* fconf APIs are not supported for RESET_TO_SP_MIN, RESET_TO_BL31 and
* RESET_TO_BL2 systems.
*/
-#if RESET_TO_SP_MIN || RESET_TO_BL31 || RESET_TO_BL2
+#if RESET_TO_SP_MIN || RESET_TO_BL31 || RESET_TO_BL2 || IMAGE_BL1
cluster_count = FVP_CLUSTER_COUNT;
cpus_per_cluster = FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU;
#else
@@ -106,8 +106,10 @@
if (thread_id >= FVP_MAX_PE_PER_CPU)
return -1;
+#if !IMAGE_BL1
if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID)
return -1;
+#endif /* IMAGE_BL1 */
/*
* Core position calculation for FVP platform depends on the MT bit in
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index bf567a4..ab1b07f 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -110,6 +110,9 @@
#define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024
+/* Define memory configuration for device tree files. */
+#define PLAT_ARM_HW_CONFIG_SIZE U(0x4000)
+
#if SPMC_AT_EL3
/*
* Number of Secure Partitions supported.
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 6b995af..8fa01ff 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -237,6 +237,7 @@
plat/arm/board/fvp/fvp_bl1_setup.c \
plat/arm/board/fvp/fvp_err.c \
plat/arm/board/fvp/fvp_io_storage.c \
+ plat/arm/board/fvp/fvp_topology.c \
${FVP_CPU_LIBS} \
${FVP_INTERCONNECT_SOURCES}
diff --git a/plat/arm/board/fvp_r/include/platform_def.h b/plat/arm/board/fvp_r/include/platform_def.h
index ea3a258..548825c 100644
--- a/plat/arm/board/fvp_r/include/platform_def.h
+++ b/plat/arm/board/fvp_r/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -90,11 +90,11 @@
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
-#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
+#define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000)
#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
PLAT_HW_CONFIG_DTB_BASE, \
- PLAT_HW_CONFIG_DTB_SIZE, \
+ PLAT_ARM_HW_CONFIG_SIZE, \
MT_MEMORY | MT_RO | MT_NS)
#define V2M_FVP_R_SYSREGS_BASE UL(0x9c010000)
diff --git a/plat/arm/board/fvp_ve/fdts/fvp_ve_fw_config.dts b/plat/arm/board/fvp_ve/fdts/fvp_ve_fw_config.dts
index 6e5691b..422ef40 100644
--- a/plat/arm/board/fvp_ve/fdts/fvp_ve_fw_config.dts
+++ b/plat/arm/board/fvp_ve/fdts/fvp_ve_fw_config.dts
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
+#include <platform_def.h>
/dts-v1/;
@@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x82000000>;
- max-size = <0x01000000>;
+ max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index bd8ef6a..e09ea02 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -158,6 +158,9 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+/* Define memory configuration for device tree files. */
+#define PLAT_ARM_HW_CONFIG_SIZE U(0x01000000)
+
/*
* This macro defines the deepest retention state possible. A higher state
* id will represent an invalid or a power down state.
diff --git a/plat/arm/board/juno/fdts/juno_fw_config.dts b/plat/arm/board/juno/fdts/juno_fw_config.dts
index 2d79ac7..11e9574 100644
--- a/plat/arm/board/juno/fdts/juno_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_fw_config.dts
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
+#include <platform_def.h>
/dts-v1/;
@@ -20,7 +21,7 @@
hw-config {
load-address = <0x0 0x82000000>;
- max-size = <0x8000>;
+ max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index b276f7b..777729e 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -36,6 +36,9 @@
* Other platform porting definitions are provided by included headers
*/
+/* Define memory configuration for device tree files. */
+#define PLAT_ARM_HW_CONFIG_SIZE U(0x8000)
+
/*
* Required ARM standard platform porting definitions
*/
diff --git a/plat/arm/board/morello/fdts/morello_fw_config.dts b/plat/arm/board/morello/fdts/morello_fw_config.dts
index a63d7eb..a93d6c4 100644
--- a/plat/arm/board/morello/fdts/morello_fw_config.dts
+++ b/plat/arm/board/morello/fdts/morello_fw_config.dts
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
+#include <platform_def.h>
/dts-v1/;
/ {
@@ -25,7 +26,7 @@
hw-config {
load-address = <0x0 0xFEFF8000>;
- max-size = <0x8000>;
+ max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
};
diff --git a/plat/arm/board/morello/include/platform_def.h b/plat/arm/board/morello/include/platform_def.h
index 3cf723e..7ec89db 100644
--- a/plat/arm/board/morello/include/platform_def.h
+++ b/plat/arm/board/morello/include/platform_def.h
@@ -75,6 +75,9 @@
*/
#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
+/* Define memory configuration for device tree files. */
+#define PLAT_ARM_HW_CONFIG_SIZE U(0x8000)
+
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
*/
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index 82f1e7f..eb878ed 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -19,9 +19,6 @@
#define PLAT_ARM_RUN_UART_BASE 0x1C090000
#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
-#define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000
-#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000
-
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
diff --git a/plat/arm/board/tc/fdts/tc_fw_config.dts b/plat/arm/board/tc/fdts/tc_fw_config.dts
index b210e75..de446ea 100644
--- a/plat/arm/board/tc/fdts/tc_fw_config.dts
+++ b/plat/arm/board/tc/fdts/tc_fw_config.dts
@@ -27,11 +27,11 @@
hw-config {
load-address = <0x0 PLAT_HW_CONFIG_DTB_BASE>;
- max-size = <PLAT_HW_CONFIG_DTB_SIZE>;
+ max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
};
nt_fw-config {
- load-address = <0x0 (PLAT_HW_CONFIG_DTB_BASE + PLAT_HW_CONFIG_DTB_SIZE)>;
+ load-address = <0x0 (PLAT_HW_CONFIG_DTB_BASE + PLAT_ARM_HW_CONFIG_SIZE)>;
max-size = <0x1000>;
id = <NT_FW_CONFIG_ID>;
};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
index 3bc0cbb..e26e9b5 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
@@ -107,4 +107,9 @@
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
+
+ memory@2 {
+ device_type = "device-memory";
+ reg = <0x0 0x1c130000 0x0 0x10000>; /* Virtio block device */
+ };
};
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index f7a4807..3897096 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -88,11 +88,11 @@
MT_MEMORY | MT_RW | MT_SECURE)
#define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE
-#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
+#define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000)
#define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \
PLAT_HW_CONFIG_DTB_BASE, \
- PLAT_HW_CONFIG_DTB_SIZE, \
+ PLAT_ARM_HW_CONFIG_SIZE, \
MT_MEMORY | MT_RO | MT_NS)
/*
* Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to
@@ -391,8 +391,6 @@
*/
#undef PLAT_ARM_BOOT_UART_BASE
#undef PLAT_ARM_RUN_UART_BASE
-#undef PLAT_ARM_SP_MIN_RUN_UART_BASE
-#define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE
#undef PLAT_ARM_CRASH_UART_BASE
#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
@@ -413,7 +411,6 @@
#endif /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_RUN_UART_BASE TC_UART0
-#define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 99e2809..18ab5be 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -120,6 +120,7 @@
}
#endif /* CRYPTO_SUPPORT */
+#if IMAGE_BL2
/*
* BL2 utility function to initialize dynamic configuration specified by
* FW_CONFIG. Populate the bl_mem_params_node_t of other FW_CONFIGs if
@@ -229,3 +230,4 @@
panic();
}
}
+#endif /* IMAGE_BL2 */
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index 16187ef..ed95bc6 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -88,8 +88,8 @@
#
# We go v8.0 by default and will enable all features we want
-ARM_ARCH_MAJOR := 8
-ARM_ARCH_MINOR := 0
+ARM_ARCH_MAJOR ?= 8
+ARM_ARCH_MINOR ?= 0
# 8.0
ENABLE_FEAT_CSV2_2 := 2
@@ -106,6 +106,7 @@
# 8.4
ENABLE_FEAT_SEL2 := 2
ENABLE_FEAT_DIT := 2
+ENABLE_TRF_FOR_NS := 2
# 8.5
ENABLE_FEAT_RNG := 2
@@ -114,6 +115,7 @@
ENABLE_FEAT_SB := 0
# 8.6
+ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
# 8.7
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index a627ed7..0a70cc2 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -161,7 +161,7 @@
unsigned int plat_get_syscnt_freq2(void)
{
- return SYS_COUNTER_FREQ_IN_TICKS;
+ return read_cntfrq_el0();
}
/*******************************************************************************
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index cafee6f..068c69c 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -5,6 +5,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <string.h>
+
#include <platform_def.h>
#include <arch_helpers.h>
@@ -226,46 +228,76 @@
uint64_t checksum;
uintptr_t base;
uint64_t size;
+ size_t num_banks = 1;
+ size_t num_consoles = 1;
struct ns_dram_bank *bank_ptr;
+ struct console_info *console_ptr;
assert(manifest != NULL);
manifest->version = RMMD_MANIFEST_VERSION;
manifest->padding = 0U; /* RES0 */
manifest->plat_data = (uintptr_t)NULL;
- manifest->plat_dram.num_banks = 1;
+ manifest->plat_dram.num_banks = num_banks;
+ manifest->plat_console.num_consoles = num_consoles;
/*
- * Array ns_dram_banks[] follows ns_dram_info structure:
+ * Boot manifest structure illustration:
*
- * +-----------------------------------+
- * | offset | field | comment |
- * +----------+-----------+------------+
- * | 0 | version | 0x00000002 |
- * +----------+-----------+------------+
- * | 4 | padding | 0x00000000 |
- * +----------+-----------+------------+
- * | 8 | plat_data | NULL |
- * +----------+-----------+------------+
- * | 16 | num_banks | |
- * +----------+-----------+ |
- * | 24 | banks | plat_dram |
- * +----------+-----------+ |
- * | 32 | checksum | |
- * +----------+-----------+------------+
- * | 40 | base 0 | |
- * +----------+-----------+ bank[0] |
- * | 48 | size 0 | |
- * +----------+-----------+------------+
+ * +----------------------------------------+
+ * | offset | field | comment |
+ * +----------+--------------+--------------+
+ * | 0 | version | 0x00000003 |
+ * +----------+--------------+--------------+
+ * | 4 | padding | 0x00000000 |
+ * +----------+--------------+--------------+
+ * | 8 | plat_data | NULL |
+ * +----------+--------------+--------------+
+ * | 16 | num_banks | |
+ * +----------+--------------+ |
+ * | 24 | banks | plat_dram |
+ * +----------+--------------+ |
+ * | 32 | checksum | |
+ * +----------+--------------+--------------+
+ * | 40 | num_consoles | |
+ * +----------+--------------+ |
+ * | 48 | consoles | plat_console |
+ * +----------+--------------+ |
+ * | 56 | checksum | |
+ * +----------+--------------+--------------+
+ * | 64 | base 0 | |
+ * +----------+--------------+ bank[0] |
+ * | 72 | size 0 | |
+ * +----------+--------------+--------------+
+ * | 80 | base | |
+ * +----------+--------------+ |
+ * | 88 | map_pages | |
+ * +----------+--------------+ |
+ * | 96 | name | |
+ * +----------+--------------+ consoles[0] |
+ * | 104 | clk_in_hz | |
+ * +----------+--------------+ |
+ * | 112 | baud_rate | |
+ * +----------+--------------+ |
+ * | 120 | flags | |
+ * +----------+--------------+--------------+
*/
bank_ptr = (struct ns_dram_bank *)
- ((uintptr_t)&manifest->plat_dram.checksum +
- sizeof(manifest->plat_dram.checksum));
+ (((uintptr_t)manifest) + sizeof(*manifest));
+
+ console_ptr = (struct console_info *)
+ ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
manifest->plat_dram.banks = bank_ptr;
+ manifest->plat_console.consoles = console_ptr;
+
+ /* Ensure the manifest is not larger than the shared buffer */
+ assert((sizeof(struct rmm_manifest) +
+ (sizeof(struct console_info) * num_consoles) +
+ (sizeof(struct ns_dram_bank) * num_banks)) <= RMM_SHARED_SIZE);
/* Calculate checksum of plat_dram structure */
- checksum = 1 + (uint64_t)bank_ptr;
+ checksum = num_banks + (uint64_t)bank_ptr;
base = NS_DRAM0_BASE;
size = NS_DRAM0_SIZE;
@@ -276,6 +308,26 @@
/* Checksum must be 0 */
manifest->plat_dram.checksum = ~checksum + 1UL;
+ /* Calculate the checksum of the plat_consoles structure */
+ checksum = num_consoles + (uint64_t)console_ptr;
+
+ /* Zero out the console info struct */
+ memset((void *)console_ptr, 0, sizeof(struct console_info) * num_consoles);
+
+ console_ptr[0].map_pages = 1;
+ console_ptr[0].base = PLAT_QEMU_BOOT_UART_BASE;
+ console_ptr[0].clk_in_hz = PLAT_QEMU_BOOT_UART_CLK_IN_HZ;
+ console_ptr[0].baud_rate = PLAT_QEMU_CONSOLE_BAUDRATE;
+
+ strlcpy(console_ptr[0].name, "pl011", sizeof(console_ptr[0].name));
+
+ /* Update checksum */
+ checksum += console_ptr[0].base + console_ptr[0].map_pages +
+ console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+
+ /* Checksum must be 0 */
+ manifest->plat_console.checksum = ~checksum + 1UL;
+
return 0;
}
#endif /* ENABLE_RME */
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 4e0b50a..95620d3 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -302,11 +302,6 @@
#define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0
/*
- * System counter
- */
-#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
-
-/*
* Maximum size of Event Log buffer used in Measured Boot Event Log driver
*/
#define PLAT_EVENT_LOG_MAX_SIZE UL(0x400)
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index e8f0344..d230095 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -266,11 +266,6 @@
#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
#define PLAT_QEMU_DT_MAX_SIZE 0x100000
-/*
- * System counter
- */
-#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
-
#if SPM_MM
#define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE
#define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000)
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index b3b2a69..033e868 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -232,8 +232,10 @@
assert((shared_buf_size == SZ_4K) &&
((void *)shared_buf_base != NULL));
- /* Load the boot manifest at the beginning of the shared area */
+ /* Zero out and load the boot manifest at the beginning of the share area */
manifest = (struct rmm_manifest *)shared_buf_base;
+ (void)memset((void *)manifest, 0, sizeof(struct rmm_manifest));
+
rc = plat_rmmd_load_manifest(manifest);
if (rc != 0) {
ERROR("Error loading RMM Boot Manifest (%i)\n", rc);
diff --git a/services/std_svc/spmd/spmd_logical_sp.c b/services/std_svc/spmd/spmd_logical_sp.c
index d992187..64d506e 100644
--- a/services/std_svc/spmd/spmd_logical_sp.c
+++ b/services/std_svc/spmd/spmd_logical_sp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -528,9 +528,10 @@
}
/* Save the non-secure context before entering SPMC */
- cm_el1_sysregs_context_save(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_save(NON_SECURE);
+#else
+ cm_el1_sysregs_context_save(NON_SECURE);
#endif
spmd_build_ffa_info_get_regs(ctx, target_uuid, start_index, tag);
@@ -548,9 +549,10 @@
assert(is_ffa_error(retval) || is_ffa_success(retval));
- cm_el1_sysregs_context_restore(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_restore(NON_SECURE);
+#else
+ cm_el1_sysregs_context_restore(NON_SECURE);
#endif
cm_set_next_eret_context(NON_SECURE);
return true;
@@ -667,9 +669,10 @@
}
/* Save the non-secure context before entering SPMC */
- cm_el1_sysregs_context_save(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_save(NON_SECURE);
+#else
+ cm_el1_sysregs_context_save(NON_SECURE);
#endif
/*
@@ -707,9 +710,10 @@
ffa_endpoint_destination(x1)));
}
- cm_el1_sysregs_context_restore(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_restore(NON_SECURE);
+#else
+ cm_el1_sysregs_context_restore(NON_SECURE);
#endif
cm_set_next_eret_context(NON_SECURE);
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 7572adf..0715b13 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -227,9 +227,10 @@
assert(handle == cm_get_context(NON_SECURE));
/* Save the non-secure context before entering SPMC */
- cm_el1_sysregs_context_save(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_save(NON_SECURE);
+#else
+ cm_el1_sysregs_context_save(NON_SECURE);
#endif
/* Convey the event to the SPMC through the FFA_INTERRUPT interface. */
@@ -252,9 +253,10 @@
ctx->secure_interrupt_ongoing = false;
- cm_el1_sysregs_context_restore(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_restore(NON_SECURE);
+#else
+ cm_el1_sysregs_context_restore(NON_SECURE);
#endif
cm_set_next_eret_context(NON_SECURE);
@@ -593,14 +595,17 @@
*/
#if (EL3_EXCEPTION_HANDLING == 0)
/*
- * Register an interrupt handler routing Group0 interrupts to SPMD
- * while the NWd is running.
+ * If EL3 interrupts are supported by the platform, register an
+ * interrupt handler routing Group0 interrupts to SPMD while the NWd is
+ * running.
*/
- rc = register_interrupt_type_handler(INTR_TYPE_EL3,
- spmd_group0_interrupt_handler_nwd,
- flags);
- if (rc != 0) {
- panic();
+ if (plat_ic_has_interrupt_type(INTR_TYPE_EL3)) {
+ rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+ spmd_group0_interrupt_handler_nwd,
+ flags);
+ if (rc != 0) {
+ panic();
+ }
}
#endif
@@ -685,9 +690,6 @@
/* Save incoming security state */
#if SPMD_SPM_AT_SEL2
- if (secure_state_in == NON_SECURE) {
- cm_el1_sysregs_context_save(secure_state_in);
- }
cm_el2_sysregs_context_save(secure_state_in);
#else
cm_el1_sysregs_context_save(secure_state_in);
@@ -695,9 +697,6 @@
/* Restore outgoing security state */
#if SPMD_SPM_AT_SEL2
- if (secure_state_out == NON_SECURE) {
- cm_el1_sysregs_context_restore(secure_state_out);
- }
cm_el2_sysregs_context_restore(secure_state_out);
#else
cm_el1_sysregs_context_restore(secure_state_out);
@@ -948,9 +947,10 @@
break;
}
/* Save non-secure system registers context */
- cm_el1_sysregs_context_save(NON_SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_save(NON_SECURE);
+#else
+ cm_el1_sysregs_context_save(NON_SECURE);
#endif
/*
diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile
index baa6e7e..919c1de 100644
--- a/tools/renesas/rcar_layout_create/makefile
+++ b/tools/renesas/rcar_layout_create/makefile
@@ -89,19 +89,19 @@
# Linker
###################################################
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
- $(aarch64-ld) $(OBJ_FILE_SA0) \
+ $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib \
-T $(MEMORY_DEF_SA0) \
-o $(OUTPUT_FILE_SA0) \
- -Map $(FILE_NAME_SA0).map \
+ -Wl,-Map $(FILE_NAME_SA0).map \
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
- $(aarch64-ld) $(OBJ_FILE_SA6) \
+ $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib \
-T $(MEMORY_DEF_SA6) \
-o $(OUTPUT_FILE_SA6) \
- -Map $(FILE_NAME_SA6).map \
+ -Wl,-Map $(FILE_NAME_SA6).map \
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
diff --git a/tools/renesas/rzg_layout_create/makefile b/tools/renesas/rzg_layout_create/makefile
index 4cab5fb..e1c242d 100644
--- a/tools/renesas/rzg_layout_create/makefile
+++ b/tools/renesas/rzg_layout_create/makefile
@@ -86,19 +86,19 @@
# Linker
###################################################
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
- $(aarch64-ld) $(OBJ_FILE_SA0) \
+ $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib \
-T $(MEMORY_DEF_SA0) \
-o $(OUTPUT_FILE_SA0) \
- -Map $(FILE_NAME_SA0).map \
+ -Wl,-Map $(FILE_NAME_SA0).map \
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
- $(aarch64-ld) $(OBJ_FILE_SA6) \
+ $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib \
-T $(MEMORY_DEF_SA6) \
-o $(OUTPUT_FILE_SA6) \
- -Map $(FILE_NAME_SA6).map \
+ -Wl,-Map $(FILE_NAME_SA6).map \
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin