| commit | 2be03c06e08df475673ace8137ea2a630f52d7a3 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Mon Feb 13 09:14:48 2023 +0100 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Tue May 09 15:57:12 2023 +0100 |
| tree | 5085dd0af7deed3a5a52dbcd82a78aa5cd96e888 | |
| parent | 64b7cdcb4c2689a0907c7a063ca2d1369399290d [diff] [blame] |
fix(tree): correct some typos found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index cc1cb10..e0e38a9 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -376,7 +376,7 @@ /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */