fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c
index 32a35ef..71e0af1 100644
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -98,7 +98,7 @@
/* assert the pcg pcr bit of the core */
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
} else {
- /* disbale CORE WFI PDN & IRQ PUP */
+ /* disable CORE WFI PDN & IRQ PUP */
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
COREx_IRQ_WUP(core_id));
/* deassert the pcg pcr bit of the core */
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c
index cc1cb10..e0e38a9 100644
--- a/plat/imx/imx8m/imx8mm/gpc.c
+++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -376,7 +376,7 @@
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
- * the CPU CORE and SCU power up timming counter
+ * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c
index 4e05297..20c9a55 100644
--- a/plat/imx/imx8m/imx8mn/gpc.c
+++ b/plat/imx/imx8m/imx8mn/gpc.c
@@ -170,7 +170,7 @@
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
- * the CPU CORE and SCU power up timming counter
+ * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index 452e788..956b508 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -337,7 +337,7 @@
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
- * the CPU CORE and SCU power up timming counter
+ * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c
index 0a029d6..ebf92f7 100644
--- a/plat/imx/imx8m/imx8mq/gpc.c
+++ b/plat/imx/imx8m/imx8mq/gpc.c
@@ -417,7 +417,7 @@
/* set all mix/PU in A53 domain */
mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
- /* set SCU timming */
+ /* set SCU timing */
mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
(0x59 << 10) | 0x5B | (0x2 << 20));