| /* |
| * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ |
| #define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ |
| |
| /* CRU */ |
| #define CRU_DPLL_CON0 0x40 |
| #define CRU_DPLL_CON1 0x44 |
| #define CRU_DPLL_CON2 0x48 |
| #define CRU_DPLL_CON3 0x4c |
| #define CRU_DPLL_CON4 0x50 |
| #define CRU_DPLL_CON5 0x54 |
| |
| /* CRU_PLL_CON3 */ |
| #define PLL_SLOW_MODE 0 |
| #define PLL_NORMAL_MODE 1 |
| #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) |
| #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) |
| |
| /* PMU CRU */ |
| #define PMU_CRU_GATEDIS_CON0 0x130 |
| |
| #endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */ |